A capacitor voltage conversion device

Abstract

This disclosure provides a capacitor-to-voltage conversion device, comprising: a charge integration module including a first operational amplifier, a feedback capacitor, and a third switch; a sample-and-hold module including a third capacitor, a fourth capacitor, a fifth capacitor, a second operational amplifier, and multiple switches; one end of the fifth capacitor is connected to the other end of the third capacitor, and the other end of the fifth capacitor is connected to the output terminal and the non-inverting input terminal of the second operational amplifier respectively through two switches; the fourth capacitor is connected across the output terminal and the inverting input terminal of the second operational amplifier; the non-inverting input terminal of the second operational amplifier is also connected to a reference voltage input terminal; at least one adjustable capacitor compensation module, each adjustable capacitor compensation module including multiple parallel capacitor branches, each capacitor branch including a compensation capacitor and an adjustment switch; wherein, one or more of the detection capacitor and feedback capacitor of the detection sensor are adjustable capacitor compensation modules.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a capacitor voltage conversion device. Background Technology

[0002] Capacitive sensors are widely used, such as pressure sensors, accelerometers, and gyroscopes. In recent years, MEMS (Micro-Electro-Mechanical Systems) have developed rapidly, and with the popularization of MEMS technology, MEMS sensors have emerged. MEMS sensors have advantages such as small size, light weight, low cost, and easy integration with CMOS readout circuit systems. However, due to their small size, the capacitance value of the sensor is generally on the order of pF, and the change in output capacitance is very weak, often only a few or tens of fF. If it is connected to an external circuit, parasitic capacitance and distributed parameters will have a significant impact on the useful signal. Therefore, a detection circuit is needed to detect the minute changes in capacitance to improve the sensor's detection accuracy.

[0003] Common detection circuits include continuous-time current readout, continuous-time voltage readout, and switched-capacitor charge integration. In continuous-time current readout, the alternating current generated by charge transfer in the circuit is detected through a transimpedance amplifier (TIA). However, the noise performance of this method is inferior to other capacitor readout structures because the thermal noise of the TIA is amplified at high frequencies due to its high-pass frequency response. Continuous-time voltage readout circuits require a large resistor to provide DC bias. This large resistor not only consumes area but also generates very large parasitic capacitance, leading to reduced detection accuracy. Both continuous-time current and continuous-time voltage readout require a very high-impedance resistor to provide DC bias. However, in CMOS integrated circuit technology, large resistors occupy a considerable area and generate large integrated capacitance, further reducing detection accuracy. Switched-capacitor charge integration is a widely used capacitor detection circuit. The circuit first charges the sensor capacitor and then uses charge transfer and redistribution principles to transfer the charge to a charge integrator, converting it into a voltage output proportional to the capacitance change. While switched-capacitor detection circuits are relatively simple, practical applications suffer from issues such as clock feedthrough, charge injection, switching noise, and parasitic parameters, limiting the accuracy of capacitance detection and conversion. Furthermore, most current capacitive sensor detection circuits are specifically designed for particular sensors and cannot be applied to other sensors of the same type, resulting in high design costs. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] This disclosure provides a capacitor voltage conversion device that at least solves the above-mentioned technical problems.

[0006] (II) Technical Solution

[0007] A capacitor-to-voltage conversion device includes: a charge integration module comprising a first operational amplifier, a feedback capacitor, and a third switch, wherein the feedback capacitor and the third switch are connected in parallel and are both connected across the inverting input and output of the first operational amplifier, and the inverting input of the first operational amplifier is also connected to the output of a detection sensor; a sample-and-hold module comprising a third capacitor, a fourth capacitor, a fifth capacitor, a second operational amplifier, and multiple switches, wherein one end of the third capacitor is connected to the output of the first operational amplifier, and the other end is connected to the inverting input and non-inverting input of the second operational amplifier via two switches respectively; one end of the fifth capacitor is connected to the other end of the third capacitor, and the other end is connected to the output and non-inverting input of the second operational amplifier via two switches respectively; the fourth capacitor is connected across the output and inverting input of the second operational amplifier; the non-inverting input of the second operational amplifier is also connected to a reference voltage input; and at least one adjustable capacitor compensation module, each adjustable capacitor compensation module comprising multiple parallel capacitor branches, each capacitor branch comprising a compensation capacitor and an adjustment switch; wherein one or more of the detection capacitor and feedback capacitor of the detection sensor constitute an adjustable capacitor compensation module.

[0008] Optionally, each adjustable capacitor compensation module includes n+1 capacitor branches, and the capacitance values ​​of the n+1 capacitor branches are respectively 2 times that of the unit capacitance. x The value X is multiplied by 1, starting from 0 and increasing in increments of 1 to the preset value n.

[0009] Optionally, the number of capacitor branches included in each of the at least one adjustable capacitor compensation modules is not equal.

[0010] Optionally, the adjustment switch includes a first MOSFET and a second MOSFET, wherein the first MOSFET and the compensation capacitor are connected in series between the two common connection points of the adjustable capacitor compensation module, and its drain is connected to the compensation capacitor; the drain of the second MOSFET is connected to the connection point of the first MOSFET and the compensation capacitor, and the source of the second MOSFET is grounded.

[0011] Optionally, the charge integration module further includes a virtual switch, which is an NMOS transistor with its source and drain connected. The connection point between the source and drain is the first connection terminal, and the gate is the second connection terminal. The gate receives a clock that is opposite to the clock provided to the NMOS switch. The input or output terminal of the third switch is connected to the first connection terminal, and the second connection terminal is the inverted signal input terminal of the third switch.

[0012] Optionally, in the sample-and-hold module, the switch connecting the third capacitor to the inverting input of the second operational amplifier adopts a virtual switch or a transmission gate structure.

[0013] Optionally, in the sample-and-hold module, the switch connecting the fifth capacitor to the output of the second operational amplifier adopts a virtual switch or a transmission gate structure.

[0014] Optionally, the capacitor voltage conversion device further includes a low-pass filter module, which is connected to the output of the second operational amplifier of the sample-and-hold module.

[0015] Optionally, the low-pass filter module includes at least one capacitor, which is an adjustable capacitor compensation module.

[0016] Optionally, the switching on and off of the switches in the charge integration module, sample and hold module, adjustable capacitor compensation module, and low-pass filter module are controlled by digital circuits.

[0017] (III) Beneficial Effects

[0018] This disclosure provides a capacitor voltage conversion device, which has at least the following advantages:

[0019] The adjustable capacitor compensation module used in this application eliminates the influence of input parasitic capacitance, and the adjustable feedback capacitor makes the voltage range of the amplified output adjustable to adapt to different input capacitance ranges and resolution requirements.

[0020] A hold module and a low-pass filter module are used to demodulate the high-frequency modulated signal output by the charge integrator and filter out high-frequency noise.

[0021] The low-pass filter module can also be designed with an adjustable capacitor compensation module, which can be adjusted to configure the bandwidth to meet the requirements of different sensors;

[0022] To mitigate the effects of charge injection and clock feedthrough caused by switching in a circuit, virtual switches and transmission gates can be used at high-impedance nodes in the circuit. Attached Figure Description

[0023] Figure 1 A circuit diagram of a capacitor voltage conversion device according to an embodiment of the present disclosure is shown schematically;

[0024] Figure 2a A schematic diagram of a capacitive sensor according to an embodiment of the present disclosure is shown.

[0025] Figure 2b This schematic diagram illustrates the state of a capacitive sensor subjected to an upward force according to an embodiment of the present disclosure;

[0026] Figure 2c A schematic diagram illustrating the detection principle of a capacitive sensor according to an embodiment of the present disclosure is shown.

[0027] Figure 3 A timing diagram of some switches according to an embodiment of the present disclosure is shown schematically;

[0028] Figure 4 A schematic diagram of the structure of a virtual switch according to an embodiment of the present disclosure is shown.

[0029] Figure 5 A schematic diagram of a sample-and-hold circuit according to an embodiment of the present disclosure is shown.

[0030] Figure 6 A timing diagram of a sample-and-hold module according to an embodiment of the present disclosure is illustrated schematically;

[0031] Figure 7 A schematic diagram of the structure of an adjustable capacitor compensation module according to an embodiment of the present disclosure is shown.

[0032] In the accompanying drawings of this invention, overlined symbols represent inversion, for example... This represents the inverted signal of n. Detailed Implementation

[0033] To address the issues that current continuous-time current and voltage readout methods require a very high-impedance resistor to provide DC bias for the circuit, resulting in a large area occupied by the resistor and a large integrated capacitance, thus reducing the detection accuracy of the circuit; and that switched-capacitor detection structures suffer from problems such as clock feedthrough, charge injection, switching noise, and parasitic parameters in practical applications, limiting the accuracy of capacitance detection and conversion; furthermore, most current capacitive sensor detection circuits are specifically designed for specific sensors and cannot be applied to other sensors of the same type, leading to high design costs, this disclosure provides a capacitor-voltage conversion device to overcome the above technical problems.

[0034] The capacitor-to-voltage conversion device provided in this disclosure includes a charge integration module, a sample-and-hold module, and at least one adjustable capacitor compensation module, wherein:

[0035] The charge integration module includes a first operational amplifier, a feedback capacitor, and a third switch. The feedback capacitor and the third switch are connected in parallel and are both connected across the inverting input and output of the first operational amplifier. The inverting input of the first operational amplifier is also connected to the output of the detection sensor.

[0036] The sample-and-hold module includes a third capacitor, a fourth capacitor, a fifth capacitor, a second operational amplifier, and multiple switches. One end of the third capacitor is connected to the output of the first operational amplifier, and the other end is connected to the inverting input and non-inverting input of the second operational amplifier via two switches. One end of the fifth capacitor is connected to the other end of the third capacitor, and the other end is connected to the output and non-inverting input of the second operational amplifier via two switches. The fourth capacitor is connected across the output and inverting input of the second operational amplifier. The non-inverting input of the second operational amplifier is also connected to a reference voltage input.

[0037] At least one adjustable capacitor compensation module, each adjustable capacitor compensation module includes multiple parallel capacitor branches, each capacitor branch includes a compensation capacitor and an adjustment switch.

[0038] Among them, one or more of the detection capacitor and feedback capacitor of the detection sensor are connected in parallel with an adjustable capacitor compensation module.

[0039] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0040] like Figure 1 As shown, the charge integration module includes a first operational amplifier AMP1 and a feedback capacitor C. F And the third switch K3, wherein the feedback capacitor C F The third switch K3 is connected in parallel and is connected across the inverting input and output of the first operational amplifier AMP1. The inverting input of the first operational amplifier AMP1 is also connected to the output of the detection sensor.

[0041] The detection sensor is used to receive external forces, etc., and detects the changes in its internal capacitance caused by the force. In this embodiment, the detection sensor is a MEMS capacitive sensor, which works by measuring the difference between two sensing capacitors or the difference between the sensor and a reference capacitor to detect external physical quantities. Specifically, taking a MEMS capacitive accelerometer as an example, due to manufacturing process deviations and storage variations, deviations in the sensor's sensitive structure cause changes in the DC component of the signal, resulting in zero bias in the circuit and affecting the overall circuit accuracy. To adjust the bias caused by the asymmetry of the input capacitors, this application designs a pair of adjustable capacitor compensation modules C1 and C2 to achieve compensation for different capacitance values.

[0042] The structure and capacitance detection principle of this MEMS capacitive accelerometer are as follows: Figures 2a-2cAs shown, when the MEMS capacitive accelerometer receives a force, such as an upward force in this embodiment, the sensitive mass block generates an upward displacement Δx, causing a change in the equivalent capacitance value between the upper electrode 201, the lower electrode 203, and the sensitive mass block 202. The change is ΔC. ε , Where x0 represents the initial distance between the upper electrode 201 and the sensitive mass block 202, and between the lower electrode 203 and the sensitive mass block 202. The equivalent capacitance between the upper electrode 201, the lower electrode 203, and the sensitive mass block 202 can be represented by two variable capacitors C. 1in and C 2in express.

[0043] This MEMS capacitive accelerometer includes two variable capacitors C. 1in and C 2in Two adjustable capacitor compensation modules, C1 and C2, have different numbers of capacitor branches. Specifically, C1... 1in Connected in series with C1, C 2in Connected in series with C2, C 1in and C1 and C 2in It is connected in parallel with C2, and its common connection terminal is connected to the inverting input terminal of the first operational amplifier AMP1. 1in C1 is connected to the reference voltage V via a switch K1. REF The connection is grounded via a switch K2; similarly, C 2in C2 is connected to the reference voltage V via a switch K1. REF The connection is made to ground via a switch K2.

[0044] In another embodiment of this disclosure, the feedback capacitor C F The timing diagrams for switches K1, K2, and K3 are as follows for the adjustable capacitor compensation module. Figure 3 As shown, through the feedback capacitor C F This allows the capacitor-to-voltage conversion circuit to adapt to different ranges of input capacitance values. The first operational amplifier, AMP1, employs a folded common-gate structure to increase gain and improve output swing. The charge integration module achieves capacitor-to-voltage conversion through capacitor switching. First, the capacitor in the detection sensor is charged, then the charge is transferred to the charge integrator using charge transfer and redistribution principles, ultimately converting it into a voltage output proportional to the capacitance change. For example... Figure 3 As shown, during stage t1, K1 is closed, while K2 and K3 are open, and C... F Initialization: The reference voltage charges C1, at which point capacitor C... 1in The charge Q1 on C1 = (C in -C1)×V REF C 2inThe charge on C2 is Q2 = 0; during stage t2, K1 is closed, K2 is open, and K3 is closed, and the charge on each capacitor remains unchanged; during stage t3, C 2in Charge with C2, C 1in Discharge occurs between C1 and C2, with charge flowing towards C2. F The transfer, according to the law of conservation of charge, is denoted as ΔC = (C 2in +C2)-(C 1in +C1), then the output voltage V OUT ,

[0045] Switching can lead to charge injection and clock feedthrough. To address this issue, a virtual switch or transmission gate, such as [missing information], can be used at the high-impedance node K3. Figure 4 The virtual switch is an NMOS transistor with its source and drain connected. The connection point between the source and drain is the first connection terminal, and the gate is the second connection terminal. The gate receives a clock signal that is opposite to the clock signal supplied to the NMOS switch. The input or output terminal of the third switch is connected to the first connection terminal, and the second connection terminal is the inverting signal input terminal of the third switch K3. Because the charge generated by the clock feedthrough through the pseudo-switch capacitor is opposite to the charge injected into the NMOS switch, the effects of charge injection and clock feedthrough on the switch are reduced.

[0046] The voltage output by the charge integration module is a periodic high-frequency modulated signal, which needs to be demodulated by the sample-and-hold module. Figure 5 This is a simple sample-and-hold circuit where the voltage is held by a capacitor and output through a unity-gain operational amplifier. However, this circuit introduces an error at the output due to charge injection from the switch when it is open. Furthermore, it lacks the capability to shape and further amplify the held signal. Therefore, this application provides an improved sample-and-hold module, such as... Figure 1 As shown.

[0047] The sample-and-hold module in this application includes a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a second operational amplifier AMP2, and multiple switches K4, K5, and K6. One end of the third capacitor is connected to the output of the first operational amplifier, and its other end is connected to the inverting input and non-inverting input of the second operational amplifier via two switches. One end of the fifth capacitor is connected to the other end of the third capacitor, and its other end is connected to the output and non-inverting input of the second operational amplifier via two switches. The fourth capacitor is connected across the output and inverting input of the second operational amplifier. The non-inverting input of the second operational amplifier is also connected to a reference voltage input. Specifically, the inverting input of operational amplifier AMP2 is connected to one end of switch K6 and one end of capacitor C4, and the non-inverting input of AMP2 is connected to the reference voltage V. ERFOne end of switch K5 and one end of switch K4 are connected. The output of AMP2 is connected to one end of switch K6 and the other end of capacitor C4, and then connected to the subsequent low-pass filter module. One end of capacitor C3 is connected to the charge integration module, and the other end is connected to the other ends of switches K5 and K6 and one end of capacitor C5. The other end of capacitor C5 is connected to the other ends of switches K4 and K6. Since the signal output by the charge integration module is a modulated signal, it needs to be demodulated. The timing of the control switches is as follows: Figure 6 As shown. During stage t1, K4 and K5 are turned on, and K6 is turned off. At this time, the charge integration module has been initialized and sampling is performed. V in The current input voltage value, V out(n-1) Given the output voltage value of the previous cycle, the charge on C3 is Q3 = [V]. in -V REF The charge Q4 on C3 and C4 is -[V] out(n-1) -V REF The charge Q5 on C4 and C5 is 0; during stage t2, K4 and K5 are closed, and the stored charge in each capacitor remains unchanged; during stage t3, K6 is turned on, and the charge at V... in Decrease to V REF Afterwards, remember v in =V in -V REF According to the law of conservation of charge: The amplitude of the output signal can be varied by adjusting the values ​​of C3, C4, and C5. After passing through the sample-and-hold module, the output is a continuous voltage signal proportional to the difference in input capacitance.

[0048] To reduce the effects of charge injection and clock feedthrough on the switches, the switch K6 connected to the inverting input of the second operational amplifier and the third capacitor adopts a virtual switch or transmission gate structure, as does the switch K6 connected to the output of the second operational amplifier and the fifth capacitor.

[0049] At least one adjustable capacitor compensation module, each adjustable capacitor compensation module including multiple parallel capacitor branches, each capacitor branch including a compensation capacitor and an adjustment switch, such as Figure 7 As shown, the adjustable capacitor compensation module includes a preset number (n+1) parallel capacitor branches. Each capacitor branch includes a compensation capacitor and an adjustment switch. The adjustment switch includes a first MOSFET and a second MOSFET. The first MOSFET and the compensation capacitor are connected in series between the two common connection points of the adjustable capacitor compensation module, and its drain is connected to the compensation capacitor. The drain of the second MOSFET is connected to the connection point of the first MOSFET and the compensation capacitor, and the source of the second MOSFET is grounded. The capacitance values ​​of the n+1 capacitor branches are 2 times the capacitance of the unit capacitor. xThe value X increases from 0 in increments of 1 to a preset value n. For example, if C is the unit capacitance, then the capacitance values ​​of each branch are C, C×2, and so on. 1 , …C×2 n Each adjustable capacitor compensation module can use a different n value. The capacitance value of the adjustable capacitor compensation module can be adjusted by an n-bit external signal to suppress zero-point drift and improve the linearity of the conversion circuit.

[0050] Among them, one or more of the detection capacitor and feedback capacitor of the detection sensor can be the aforementioned adjustable capacitor compensation module or connected in series.

[0051] The capacitor-to-voltage conversion device also includes a low-pass filter module connected to the output of the second operational amplifier of the sample-and-hold module. The low-pass filter module includes at least one capacitor, which is an adjustable capacitor compensation module connected in series.

[0052] The switching on and off of the switches in the aforementioned charge integration module, sample and hold module, adjustable capacitor compensation module, and low-pass filter module are controlled by digital circuits, and the reference voltage can be provided by a bandgap reference.

[0053] In summary, the adjustable capacitor compensation module used in this application eliminates the influence of input parasitic capacitance. Furthermore, the adjustable feedback capacitor design allows for adjustable output voltage range to accommodate different input capacitance ranges and resolution requirements. This capacitor-to-voltage conversion device also includes a hold module and a low-pass filter module for demodulating the high-frequency modulation signal output from the charge integrator and filtering out high-frequency noise. The low-pass filter module can also be designed with an adjustable capacitor compensation module, allowing for bandwidth configuration to meet the requirements of different sensors. To mitigate charge injection and clock feedthrough that may occur due to switching in the circuit, virtual switches and transmission gates are used at high-impedance nodes to reduce their impact.

[0054] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A capacitor-to-voltage conversion device, comprising: The charge integration module includes a first operational amplifier, a feedback capacitor, and a third switch. The feedback capacitor and the third switch are connected in parallel and are both connected across the inverting input and output of the first operational amplifier. The inverting input of the first operational amplifier is also connected to the output of the detection sensor. The sample-and-hold module includes a third capacitor, a fourth capacitor, a fifth capacitor, a second operational amplifier, and multiple switches. One end of the third capacitor is connected to the output of the first operational amplifier, and its other end is connected to the inverting input and non-inverting input of the second operational amplifier via two switches. One end of the fifth capacitor is connected to the other end of the third capacitor, and its other end is connected to the output and non-inverting input of the second operational amplifier via two switches. The fourth capacitor is connected across the output and inverting input of the second operational amplifier. The non-inverting input of the second operational amplifier is also connected to a reference voltage input. At least one adjustable capacitor compensation module is provided, each of which includes n+1 parallel capacitor branches. Each capacitor branch includes a compensation capacitor and an adjustment switch. The capacitance values ​​of the n+1 capacitor branches are respectively 2 times that of the unit capacitance. x The number of capacitor branches contained in each of the at least one adjustable capacitor compensation modules is not equal. Among them, one or more of the detection capacitor and feedback capacitor of the detection sensor are the adjustable capacitor compensation module.

2. The device according to claim 1, wherein the adjusting switch comprises a first MOSFET and a second MOSFET, wherein, The first MOS transistor and the compensation capacitor are connected in series between the two common connection points of the adjustable capacitor compensation module, and its drain is connected to the compensation capacitor; the drain of the second MOS transistor is connected to the connection point of the first MOS transistor and the compensation capacitor, and the source of the second MOS transistor is grounded.

3. The apparatus according to claim 1, wherein the charge integration module further comprises a virtual switch, the virtual switch being an NMOS transistor with its source and drain connected, wherein, The connection point between the source and drain is the first connection terminal, and the gate is the second connection terminal. The gate receives a clock that is opposite to the clock provided to the NMOS switch. The input or output terminal of the third switch is connected to the first connection terminal, and the second connection terminal is the inverted signal input terminal of the third switch.

4. In the apparatus according to claim 1, in the sample-and-hold module, the switch connecting the third capacitor to the inverting input terminal of the second operational amplifier is a virtual switch or a transmission gate structure.

5. In the apparatus according to claim 1, in the sample-and-hold module, the switch connecting the fifth capacitor to the output terminal of the second operational amplifier adopts a virtual switch or a transmission gate structure.

6. The apparatus according to claim 1 further includes a low-pass filter module connected to the output of the second operational amplifier of the sample-and-hold module.

7. The apparatus according to claim 6, wherein the low-pass filter module includes at least one capacitor, the capacitor being the adjustable capacitor compensation module.

8. In the apparatus according to claim 7, the switching on and off of the switches in the charge integration module, sample and hold module, adjustable capacitor compensation module, and low-pass filter module is controlled by digital circuitry.

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