Variable resistance memory device and manufacturing method thereof

Abstract

Disclosed are a variable resistance memory device and a method for manufacturing the same. The variable resistance memory device may include: a plurality of memory cells, each including a variable resistance pattern and a switch pattern; a plurality of wires to which the memory cells are connected; a bottom electrode, connecting at least one of the wires to the variable resistance pattern; and a spacer pattern formed on the bottom electrode to contact the variable resistance pattern. The spacer pattern includes a dielectric material doped with impurities.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0002372 filed on January 8, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Example embodiments of the inventive concepts relate to a semiconductor memory and a method of manufacturing the same, and more particularly, to a variable resistance memory device and a method of manufacturing the same. Background Art

[0003] According to the demand for memory devices with high capacitance and low power consumption, research is being conducted on next-generation memories that are nonvolatile and do not require refresh operations. The next-generation memory devices are required to have the high integration characteristics of DRAM (dynamic random access memory), the non-volatile characteristics of flash memory, and / or the high speed of SRAM (static RAM).

[0004] Recently, next-generation semiconductor memory devices (e.g., ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and phase change random access memory (PRAM)) are being developed to meet the trend of high performance and low power consumption of semiconductor memory devices. The next-generation semiconductor memory device is formed of a material having a characteristic that its resistance becomes different according to an applied current or voltage and that its resistance is maintained even when the current or voltage supply is interrupted. Summary of the invention

[0005] Example embodiments of the inventive concepts provide a variable resistance memory device and a method of manufacturing the same, which can improve electrical characteristics of the variable resistance memory device and achieve process simplification.

[0006] The objects of the inventive concept are not limited to the above-mentioned contents, and other objects not mentioned above will be clearly understood by those skilled in the art through the following description.

[0007] According to example embodiments, there is provided a variable resistance memory device, which may include: a plurality of memory cells each including a variable resistance pattern and a switch pattern; a plurality of wires to which the memory cells are connected; a bottom electrode connecting at least one of the plurality of wires to the variable resistance pattern; and a spacer pattern formed on the bottom electrode to contact the variable resistance pattern. The spacer pattern may include a dielectric material doped with impurities.

[0008] According to example embodiments, there is provided a variable resistance memory device, which may include: a first conductive line extending in a first direction; a molded dielectric pattern formed on the first conductive line; a second conductive line formed on the molded dielectric pattern and extending in a second direction different from the first direction; a bottom electrode formed in the molded dielectric pattern, the bottom electrode including a bottom portion connected to the first conductive line and a sidewall portion vertically protruding from the bottom portion; a buried dielectric pattern covering the bottom portion and the sidewall portion of the bottom electrode; a spacer pattern formed between the buried dielectric pattern and the bottom electrode, the spacer pattern including a dielectric material doped with impurities; and a variable resistance pattern formed between the bottom electrode and the second conductive line, the variable resistance pattern contacting the sidewall portion of the bottom electrode.

[0009] According to example embodiments, a method for manufacturing a variable resistance memory device is provided, the method may include: forming a first conductive line extending in a first direction on a substrate; forming a groove in a molded dielectric layer covering the first conductive line; sequentially forming an initial electrode pattern and an initial spacer pattern in the groove; forming a mask dielectric pattern in the groove in which the initial electrode pattern and the initial spacer pattern are formed; performing a first etching process to recess a top surface of the initial electrode pattern and a top surface of the spacer pattern; performing a second etching process on the molded dielectric layer and the buried dielectric pattern to form an expanded recessed area between the molded dielectric layer and the buried dielectric pattern; and forming a variable resistance pattern in the expanded recessed area. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A conceptual diagram illustrating a variable resistance memory device according to example embodiments is shown.

[0011] Figure 2 A simplified circuit diagram illustrating a cell array block of a variable resistance memory device according to example embodiments is shown.

[0012] Figure 3 A perspective view showing a single memory cell stack is shown.

[0013] Figure 4 A plan view illustrating a variable resistance memory device according to example embodiments is shown.

[0014] Figure 5 Shown along Figure 4 2 , cross-sectional views taken along line II′, line II-II′, and line III-III′ illustrate a variable resistance memory device according to example embodiments.

[0015] Fig. 6A , Figure 6B and Figure 6C Shows Shows Figure 5 An enlarged view of part A of FIG.

[0016] Figure 7 Shown along Figure 4 2 , cross-sectional views taken along line II′, line II-II′, and line III-III′ illustrate a variable resistance memory device according to example embodiments.

[0017] Figure 8 Shown Shown Figure 7 An enlarged view of part B.

[0018] Fig. 9 A flowchart illustrating a method of manufacturing a variable resistance memory device according to example embodiments is shown.

[0019] Fig. 10A , Fig.11A and Fig. 12A A plan view illustrating a method of manufacturing a variable resistance memory device according to example embodiments is shown.

[0020] Fig. 10B , Fig. 11B and Fig. 12B Shown along Fig. 10A , Fig.11A and Fig. 12A 1 and 2 , cross-sectional views taken along line II′, line II-II′, and line III-III′ illustrate a method of manufacturing a variable resistance memory device according to example embodiments.

[0021] Fig.13 , Fig.15 and Fig.17 A cross-sectional view illustrating a method of manufacturing a variable resistance memory device according to example embodiments is shown.

[0022] Fig.14 Shows Shows Fig.13 An enlarged view of portion C of FIG.

[0023] Fig.16 Shows Shows Fig.15 An enlarged view of portion D of FIG. DETAILED DESCRIPTION

[0024] A variable resistance memory device and a method of manufacturing the same according to example embodiments will now be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 A conceptual diagram illustrating a variable resistance memory device according to example embodiments is shown.

[0026] Reference Figure 1, a variable resistance memory device according to example embodiments may include a plurality of memory cell stacks MCA sequentially stacked on a substrate 100. Each of the plurality of memory cell stacks MCA may include a plurality of variable resistance memory cells arranged two-dimensionally. The variable resistance memory device may include a plurality of conductive lines disposed between the plurality of memory cell stacks MCA to write, read, and erase the memory cells. Figure 1 Five memory cell stacks MCA are shown, but the inventive concept is not limited thereto.

[0027] Figure 2 A simplified circuit diagram illustrating a cell array block of a variable resistance memory device according to example embodiments is shown.

[0028] Reference Figure 2 , the first to fourth memory cell stacks MCA1 to MCA4 may be stacked along the third direction D3 on a plane extending along the first and second directions D1 and D2 intersecting each other.

[0029] Each of the first to fourth memory cell stacks MCA1 to MCA4 may include a first conductive line CL1, a second conductive line CL2, and a memory cell MC at a corresponding intersection of the first conductive line CL1 and the second conductive line CL2. For example, in the first to fourth memory cell stacks MCA1 to MCA4, the memory cells MC may be two-dimensionally arranged along a first direction D1 and a second direction D2.

[0030] Memory cells MC adjacent to each other in the third direction D3 may share a first conductive line CL1 or a second conductive line CL2 disposed therebetween.

[0031] Figure 3 A perspective view showing a single memory cell stack is shown.

[0032] Reference Figure 3 , the memory cells MC may be disposed at corresponding intersections of the first conductive line CL1 and the second conductive line CL2.

[0033] Each of the memory cells MC may include a switching element SW and a variable resistance structure VR. The memory cells MC may be spaced apart from each other in the first direction D1 and the second direction D2.

[0034] The variable resistance structure VR may be correspondingly disposed at the intersection of the first conductive line CL1 and the second conductive line CL2 , and the switch element SW may be correspondingly disposed between the variable resistance structure VR and the second conductive line CL2 .

[0035] although Figure 3It is shown that the switch element SW is disposed between the variable resistance structure VR and the second conductive line CL2 , but the switch element SW may be disposed between the variable resistance structure VR and the first conductive line CL1 .

[0036] Figure 4 A plan view illustrating a variable resistance memory device according to example embodiments is shown. Figure 5 Shown along Figure 4 2 , cross-sectional views taken along line II′, line II-II′, and line III-III′ illustrate a variable resistance memory device according to example embodiments. Fig. 6A , Figure 6B and Figure 6C FIG. 1 shows a diagram illustrating a method according to an example embodiment Figure 5 An enlarged view of part A of FIG.

[0037] Reference Figure 4 and Figure 5 , a first conductive line CL1 is disposed on the substrate 100 , and a lower interlayer dielectric layer 110 surrounds the first conductive line CL1 on the substrate 100 .

[0038] The substrate 100 may be a semiconductor substrate formed of one or more of silicon, germanium, and silicon-germanium. The substrate 100 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial layer substrate obtained by performing selective epitaxial growth (SEG).

[0039] The first conductive lines CL1 may extend in a first direction D1 and be spaced apart from each other in a second direction D2. The first direction D1 and the second direction D2 may intersect each other and be parallel to the top surface of the substrate 100. The lower interlayer dielectric layer 110 may be disposed around the first conductive lines CL1 and may expose the top surface of the first conductive lines CL1.

[0040] The first conductive line CL1 may include one or more of metal (eg, copper, tungsten, or aluminum) and metal nitride (eg, tantalum nitride, titanium nitride, or tungsten nitride). The lower interlayer dielectric layer 110 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0041] The second conductive line CL2 may be disposed across the first conductive line CL1. The second conductive lines CL2 may extend in the second direction D2 and be spaced apart from each other in the first direction D1. The second conductive line CL2 may be spaced apart from the first conductive line CL1 in a direction perpendicular to the top surface of the substrate 100. The second conductive line CL2 may include one or more of a metal (e.g., copper, tungsten, or aluminum) and a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride).

[0042] As discussed above, the memory cell (see Figure 3The memory cell (see Figure 3 Each of the memory cells MC may include a variable resistance pattern VRP and a switching element SW. Each of the memory cells may include an intermediate electrode ME between the variable resistance pattern VRP and the switching element SW.

[0043] The variable resistance pattern VRP may be disposed between the switching element SW and the first conductive line CL1. Alternatively, the variable resistance pattern VRP may be disposed between the switching element SW and the second conductive line CL2.

[0044] The variable resistance pattern VRP may be disposed in a mold structure ML located between the switch element SW and the first conductive line CL1. The mold structure ML may include a mold dielectric pattern 121, a first buried dielectric pattern 151, and a second buried dielectric pattern 161. The mold dielectric pattern 121 and the first buried dielectric pattern 151 may be alternately disposed on each of the first conductive lines CL1 along the first direction D1. The second buried dielectric pattern 161 may extend in the first direction D1 between the first conductive lines CL1. In a particular embodiment, the mold dielectric pattern 121 and the first buried dielectric pattern 151 and the second buried dielectric pattern 161 may include the same dielectric material. For example, the mold dielectric pattern 121 and the first buried dielectric pattern 151 and the second buried dielectric pattern 161 may include silicon nitride or silicon oxynitride.

[0045] The mold structure ML may provide recessed regions ER arranged two-dimensionally spaced apart from each other along the first direction D1 and the second direction D2 . Each of the recessed regions ER may be defined by the mold dielectric pattern 121 and the first and second buried dielectric patterns 151 and 161 .

[0046] The variable resistance pattern VRP may be formed in the recessed region ER. In an example embodiment, the variable resistance pattern VPR may be disposed at corresponding intersections of the first conductive line CL1 and the second conductive line CL2, thereby forming a two-dimensional arrangement. In another example embodiment, the variable resistance pattern VRP may have a plurality of linear shapes extending along the first direction D1 or the second direction D2.

[0047] The variable resistance pattern VRP may be formed of at least one of the materials having physical properties capable of storing data. In the case of adopting a phase change memory device as the variable resistance memory device according to the example embodiment, the variable resistance pattern VRP may include a material whose phase changes between a crystalline state and an amorphous state based on temperature. For example, the variable resistance pattern VRP may have a phase change temperature of about 250° C. to 350° C. between a crystalline state and an amorphous state. The variable resistance pattern VRP may be formed of a compound in which one or more of Te and Se as chalcogenide elements are combined with one or more of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C. For example, the variable resistance pattern VRP may include one or more of GeTeSe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe. For another example, the variable resistance pattern VRP may include a superlattice structure in which a Ge-containing layer and a Ge-free layer are repeatedly stacked. For another example, the variable resistance pattern VRP may include a structure in which a GeTe layer and a SbTe layer are repeatedly stacked.

[0048] In other example embodiments, the variable resistance pattern VRP may include one or more of a perovskite compound and a conductive metal oxide. For example, the variable resistance pattern VRP may include niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr, Ca) MnO 3 ), one or more of strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide, barium-zirconium oxide, and barium-strontium-zirconium oxide. When the variable resistance pattern VRP includes a transition metal oxide, the variable resistance pattern VRP may have a dielectric constant greater than that of the silicon oxide layer. In other example embodiments, the variable resistance pattern VRP may have a double-layer structure having a conductive metal oxide layer and a tunnel dielectric layer or a triple-layer structure having a first conductive metal oxide layer, a tunnel dielectric layer, and a second conductive metal oxide layer. The tunnel dielectric layer may include aluminum oxide, hafnium oxide, or silicon oxide.

[0049] The bottom electrode pattern 133 may be disposed between the first conductor CL1 and the variable resistance pattern VRP. Each of the bottom electrode patterns 133 may connect a pair of variable resistance patterns VRP adjacent in the first direction D1 to the first conductor CL1. For example, each of the bottom electrode patterns 133 may include a bottom portion 133a connected to the first conductor CL1, and may also include a pair of sidewall portions 133b extending from opposite ends of the bottom portion 133a toward a pair of variable resistance patterns VRP. For another example, the bottom electrode pattern 133 may be arranged two-dimensionally at the intersection of the first conductor CL1 and the second conductor CL2. Each of the bottom electrode patterns 133 may have a uniform thickness and a U-shaped cross-section in the first direction D1. Each of the bottom electrode patterns 133 may have an uneven top surface and a width smaller than the width of the variable resistance pattern VRP.

[0050] The sidewall portion 133b of the bottom electrode pattern 133 may be in direct contact with the corresponding variable resistance pattern VRP. The bottom electrode pattern 133 may be an electrode that heats the variable resistance pattern VRP and causes the variable resistance pattern VRP to change phase. The bottom electrode pattern 133 may be formed of a material having a resistivity greater than that of the first conductive line CL1. For example, the bottom electrode pattern 133 may include one or more of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, and TiO.

[0051] The spacer pattern 143 may be disposed between the first buried dielectric pattern 151 and each bottom electrode pattern 133. The spacer pattern 143 may extend along a bottom portion 133a and a sidewall portion 133b of the bottom electrode pattern 133. The spacer pattern 143 may have a uniform thickness on the bottom electrode pattern 133. The thickness of the spacer pattern 143 may be substantially equal to or greater than the thickness of the bottom electrode pattern 133. The spacer pattern 143 may include a first segment 143a covering a bottom portion 133a of the bottom electrode pattern 133 and a second segment 143b covering a sidewall portion 133b of the bottom electrode pattern 133. For example, the spacer pattern 143 may have a U-shaped cross-section in the first direction D1.

[0052] In certain embodiments, the spacer pattern 143 may be formed of a dielectric material doped with impurities. The dielectric material doped with impurities may be different from the dielectric materials of the mold dielectric pattern 121 , the first buried dielectric pattern 151 , and the second buried dielectric pattern 161 .

[0053] Impurities doped in the spacer pattern 143 may include one or more of germanium (Ge), tin (Sn), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), and cobalt (Co).

[0054] The spacer pattern 143 may include a metal element, a silicon element, and an oxygen element. For example, the impurities doped in the spacer pattern 143 may include the same metal element as the metal element of the bottom electrode pattern 133. When the bottom electrode pattern 133 and the spacer pattern 143 include the same metal element, the concentration of the metal element in the spacer pattern 143 may be lower than the concentration of the metal element in the bottom electrode pattern 133.

[0055] The dielectric material of the spacer pattern 143 may include a first semiconductor element, and the impurities doped in the dielectric material of the spacer pattern 143 may include a second semiconductor element different from the first semiconductor element. For example, the spacer pattern 143 may include silicon oxide doped with titanium (Ti). For another example, the spacer pattern 143 may include silicon oxide doped with germanium (Ge) or carbon (C).

[0056] The spacer pattern 143 may have an inner wall directly contacting the first buried dielectric pattern 151. The bottom electrode pattern 133 and the spacer pattern 143 may have their top surfaces at a level lower than that of the mold dielectric pattern 121, the first buried dielectric pattern 151, and the second buried dielectric pattern 161.

[0057] In certain embodiments, the first buried dielectric pattern 151 may have a discontinuous interface IS therein. In this specification, the term "discontinuous interface IS" may refer to the presence of a material that can be detected by a composition difference of the material, a grain change of the material, a gap, a void, or an analytical device such as a transmission electron microscope (TEM) or a scanning electron microscope (SEM).

[0058] The discontinuous interface IS in the first buried dielectric pattern 151 may exist between the sidewall portions 133b of the bottom electrode pattern 133. Fig. 6A and Figure 6B As shown in , the discontinuous interface IS may be a gap in the first buried dielectric pattern 151. Alternatively, as Figure 6C As shown in , the discontinuous interface IS may be a void formed inside the first buried dielectric pattern 151 .

[0059] Reference Fig. 6A , each variable resistance pattern VRP may have a width in the first direction D1 that is greater than the sum of a width of a sidewall portion 133b of the bottom electrode pattern 133 and a width of a second segment 143b of the spacer pattern 143. The width of the variable resistance pattern VRP may correspond to a distance between a sidewall of the mold dielectric pattern 121 and a sidewall of the first buried dielectric pattern 151, with which the sidewalls of the mold dielectric pattern 121 and the first buried dielectric pattern 151 are in contact.

[0060] Reference Figure 6B , a width of each variable resistance pattern VRP in the first direction D1 may be substantially equal to a sum of a width of a sidewall portion 133 b of the bottom electrode pattern 133 and a width of a second segment 143 b of the spacer pattern 143 .

[0061] The intermediate electrode ME may be disposed on the corresponding variable resistance pattern VRP. The intermediate electrode ME may electrically connect the variable resistance pattern VRP to the switching element SW, and may prevent direct contact between the variable resistance pattern VRP and the switching element SW. The intermediate electrode ME may include one or more of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0062] The intermediate electrode ME may be disposed on an upper portion of the recessed region ER. For example, the intermediate electrode ME may have a top surface substantially coplanar with a top surface of the mold dielectric pattern 121 and top surfaces of the first and second buried dielectric patterns 151 and 161.

[0063] The switching element SW may be disposed on the corresponding middle electrode ME. Each of the switching elements ME may have a width equal to or greater than the width of the variable resistance pattern VRP in the first direction D1. The switching element SW may be an OTS (bidirectional threshold switch) device exhibiting bidirectional characteristics. For example, the switching element SW may be a device based on a threshold switching phenomenon exhibiting a nonlinear IV curve (e.g., an S-type IV curve). The switching element SW may have a phase transition temperature greater than the phase transition temperature of the variable resistance pattern VRP, at which the phase state of the material forming the switching element SW transitions between a crystalline state and an amorphous state. For example, the switching element SW may have a phase transition temperature of about 350°C to about 450°C. Therefore, when operating the variable resistance memory device according to the example embodiment, the variable resistance pattern VRP may be configured to change its phase state between a crystalline state and an amorphous state, while the switching element SW may maintain its substantially amorphous state without phase change. In this specification, the phrase "substantially amorphous state" may not exclude the presence of a local crystallized grain boundary or a local crystallized portion in the object.

[0064] The switching element SW may be formed of a compound in which one or more of Te and Se as chalcogenide elements are combined with one or more of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. The switching element SW may further include a thermally stable element other than the compound. The thermally stable element may be one or more of C, N, and O. For example, the switching element SW may include AsTe, AsSe, GeTe, SnTe, GeSe, SnTe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsTeGeSe, AsSeGeSi, AsSeGeC, AsTeGeSi, AsTeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSb, AsTeGeSeSi, AsTeGeSiSeNS, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, and GeAsBiSe.

[0065] The top electrode TE may be disposed between the switching element SW and the second conductive line CL2. The top electrodes TE may be arranged on the corresponding switching elements SW two-dimensionally spaced apart from each other. Alternatively, each of the top electrodes TE may be commonly connected to the switching elements SW arranged along the second direction D2.

[0066] The upper interlayer dielectric layer 170 may be disposed on the mold dielectric layer 121 and the first buried dielectric layer 151 and the second buried dielectric layer 161. The upper interlayer dielectric layer 170 may fill the space between the switching elements SW. The upper interlayer dielectric layer 170 may be formed of a low-k dielectric material. The upper interlayer dielectric layer 170 may have a top surface coplanar with the top surface of the top electrode TE.

[0067] The second conductive lines CL2 may be disposed on the top electrode TE. The second conductive lines CL2 may extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0068] Figure 7 Shown along Figure 4 2 , cross-sectional views taken along line II′, line II-II′, and line III-III′ illustrate a variable resistance memory device according to example embodiments. Figure 8 Shows Shows Figure 7 An enlarged view of part B of FIG. For the sake of brevity, descriptions of repeated components may be omitted.

[0069] Reference Figure 7 and Figure 8, the variable resistance pattern VRP may have its top surface at substantially the same level as that of the top surface of the mold structure ML. For example, the top surface of the variable resistance pattern VRP may be coplanar with the top surface of the mold dielectric pattern 121 and the top surfaces of the first buried dielectric pattern 151 and the second buried dielectric pattern 161.

[0070] The intermediate electrode ME may be disposed on the mold dielectric pattern 121 and the first and second buried dielectric patterns 151 and 161. The intermediate electrode ME may have a sidewall vertically aligned with a sidewall of the switching element SW.

[0071] <Manufacturing method>

[0072] Fig. 9 A flowchart illustrating a method of manufacturing a variable resistance memory device according to example embodiments is shown.

[0073] Fig. 10A , Fig.11A and Fig. 12A A plan view illustrating a method of manufacturing a variable resistance memory device according to example embodiments is shown. Fig. 10B , Fig. 11B and Fig. 12B Shown along Fig. 10A , Fig.11A and Fig. 12A 1 and 2 , cross-sectional views taken along line II′, line II-II′, and line III-III′ illustrate a method of manufacturing a variable resistance memory device according to example embodiments. Fig.13 , Fig.15 and Fig.17 A cross-sectional view illustrating a method of manufacturing a variable resistance memory device according to example embodiments is shown. Fig.14 Shows Shows Fig.13 An enlarged view of portion C of FIG. Fig.16 Shows Shows Fig.15 An enlarged view of portion D of FIG.

[0074] Reference Fig. 9 , Fig. 10A and Fig. 10B , first conductive lines CL1 may be formed on the substrate 100 to extend in the first direction D1 and to be spaced apart from each other in the second direction D2 ( S10 ).

[0075] The first conductive line CL1 may be formed by depositing a conductive layer on the substrate 100 and patterning the conductive layer. After forming the first conductive line CL1, a lower interlayer dielectric layer 110 may be formed to fill the space between the first conductive lines CL1. The step of forming the first conductive line CL1 by patterning the conductive layer may be performed when patterning the bottom electrode layer 130 (which will be discussed below).

[0076] The first conductive line CL1 may include one or more of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, aluminum, titanium, and / or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride), and a metal-semiconductor compound (e.g., metal silicide). The bottom electrode layer 130, which will be discussed below, may include one or more of W, Ti, Ta, Al, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0077] Also refer to Fig. 9 , Fig. 10A and Fig. 10B , a mold dielectric layer 120 having a trench T extending in the first direction D1 or in the second direction D2 may be formed on the first conductive line CL1 ( S20 ).

[0078] The mold dielectric layer 120 may cover the top surface of the first conductive line CL1. The mold dielectric layer 120 may include silicon nitride or silicon oxynitride. The mold dielectric layer 120 may be formed by using a deposition process performed at a relatively low temperature (eg, equal to or lower than about 400° C.).

[0079] A linear mask pattern (not shown) may be formed on the mold dielectric layer 120 and then used to etch the mold dielectric layer 120 to expose the top surface of the first conductive line CL1, and as a result, a trench T may be formed. The trenches T may extend in the second direction D2 to cross the first conductive line CL1, and may be spaced apart from each other in the first direction D1. Each trench T may be formed between a pair of first conductive lines CL1. When the mold dielectric layer 120 is anisotropically etched to form the trenches T, each trench T may have inclined, opposing sidewalls.

[0080] The mold dielectric layer 120 may be formed on the first conductive line CL1 , but the inventive concept is not limited thereto. The mold dielectric layer 120 having the trench T may be formed on the conductive layer covering the entire surface of the substrate 100 .

[0081] Reference Fig. 9 , Fig.11A and Fig. 11B , a bottom electrode layer 130 and a spacer layer 140 may be sequentially formed on the mold dielectric layer 120 having the trench T formed therein ( S30 ).

[0082] The bottom electrode layer 130 and the spacer layer 140 may be formed using a layer formation technique having excellent step coverage or excellent film conformality, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0083] The bottom electrode layer 130 may conformally cover the inner wall of the trench T. The bottom electrode layer 130 may be formed using one of atomic layer deposition (ALD), metal organic chemical vapor deposition (MO-CVD), thermal CVD, plasma CVD, and electron cyclotron resonance chemical vapor deposition (ECR-CVD). The bottom electrode layer 130 may have a deposition thickness of about 0.1 nm to about 10 nm. The bottom electrode layer 130 may be made of a nitride containing a metal element, a nitride containing a metal element, carbon (C), titanium (Ti), tantalum (Ta), aluminum titanium (AlTi), zirconium (Zr), hafnium (Hf), molybdenum (Mo), aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), copper (Cu), tungsten (W), titanium tungsten (TiW), and tungsten silicide (WSi x ). The nitride containing metal elements may include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN or TaAlN, and the oxynitride containing metal elements may include TiON, TiAlON, WON or TaON.

[0084] The spacer layer 140 may be formed of a dielectric material different from the dielectric material of the mold dielectric layer 120. The spacer layer 140 may be formed of a dielectric material having a high etching selectivity with respect to the mold dielectric layer 120 but a low etching selectivity with respect to the bottom electrode layer 130. In a specific embodiment, the spacer layer 140 may be formed of a dielectric material doped with impurities. The impurities may include one or more of germanium (Ge), tin (Sn), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), and cobalt (Co).

[0085] The spacer layer 140 may include a metal element, a silicon element, and an oxygen element. The spacer layer 140 may be a silicon oxide layer doped with a metal element. The metal element may include one or more of tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), and cobalt (Co). Alternatively, the spacer layer 140 may be a silicon oxide layer doped with germanium (Ge).

[0086] In certain embodiments, the impurities in the spacer layer 140 may include the same metal element as the metal element of the bottom electrode layer 130. For example, the bottom electrode layer 130 and the spacer layer 140 may include titanium (Ti), and the spacer layer 140 has a titanium (Ti) concentration lower than that of the bottom electrode layer 130.

[0087] The spacer layer 140 may be formed using atomic layer deposition (ALD), metal organic chemical vapor deposition (MO-CVD), thermal CVD, plasma CVD, and electron cyclotron resonance chemical vapor deposition (ECR-CVD). Impurities may be doped into the spacer layer 140 during the deposition of the spacer layer 140, and the doping amount of the impurities may affect the etching rate in the first etching process to be discussed below. For example, the spacer layer 140 may be formed by in-situ doping with impurities while the silicon oxide layer is formed using atomic layer deposition.

[0088] The spacer layer 140 may be deposited to have a uniform thickness on the bottom electrode layer 130. The spacer layer 140 may have a deposition thickness substantially equal to or greater than that of the bottom electrode layer 130. For example, the deposition thickness of the spacer layer 140 may be, for example, about 1 nm to 10 nm.

[0089] The sum of the thicknesses of the bottom electrode layer 130 and the spacer layer 140 is smaller than half the width of the trench T. The bottom electrode layer 130 and the spacer layer 140 may thus define an empty space in the trench T.

[0090] The first buried dielectric layer 150 may be formed to fill the trench T in which the bottom electrode layer 130 and the spacer layer 140 are formed. The first buried dielectric layer 150 may be formed of a dielectric material different from the dielectric material of the spacer layer 140. For example, the first buried dielectric layer 150 may include silicon oxide or silicon oxynitride. The first buried dielectric layer 150 may be formed using a deposition process performed at a relatively low temperature (e.g., equal to or lower than about 400° C.). The first buried dielectric layer 150 may be formed by, for example, plasma enhanced atomic layer deposition.

[0091] When the first buried dielectric layer 150 is deposited to fill the empty space defined by the bottom electrode layer 130 and the spacer layer 140, as shown in FIG. Fig. 6A , Figure 6B and Figure 6C As discussed, a discontinuous interface (eg, a seam or a void) may be formed in the first buried dielectric layer 150. The discontinuous interface (eg, a seam or a void) may extend along the second direction D2.

[0092] Reference Fig. 9 , Fig. 12A and Fig. 12B , preliminary electrode patterns 131 and preliminary spacer patterns 141 spaced apart from each other in the first direction D1 and the second direction D2 may be formed ( S40 ).

[0093] For example, after forming the first buried dielectric layer 150, a planarization process may be performed to expose the mold dielectric layer 120. After the planarization process, the bottom electrode layer 130, the spacer layer 140, and the first buried dielectric layer 150 may extend in the trench T along the second direction D2.

[0094] When the planarization process is completed, a mask pattern (not shown) may be formed across the bottom electrode layer 130, the spacer layer 140, and the mold dielectric layer 120 along the first direction D1. The mold dielectric layer 120, the first buried dielectric layer 150, the bottom electrode layer 130, and the spacer layer 140 may be anisotropically etched using the mask pattern to respectively form a mold dielectric pattern 121, a first buried dielectric pattern 151, a preliminary electrode pattern 131, and a preliminary spacer pattern 141. A plurality of linear openings extending in the first direction D1 may be formed between the preliminary electrode patterns 131 adjacent along the second direction D2.

[0095] Each of the preliminary electrode patterns 131 may include a bottom portion 131a in contact with the first conductive line CL1 and a sidewall portion 131b vertically protruding from opposite ends of the bottom portion 131a (i.e., protruding perpendicularly to the opposite ends of the bottom portion 131a). Each of the preliminary spacer patterns 141 may include a first segment 141a and a second segment 141b vertically protruding from opposite ends of the first segment 141a. The sidewall portion 131b of the preliminary electrode pattern 131 may have a top surface substantially coplanar with a top surface of the second segment 141b of the preliminary spacer pattern 141.

[0096] In certain embodiments, when the first conductive line is not formed under the mold dielectric layer 120 , the first conductive line may also be formed during the anisotropic etching process performed to form the preliminary electrode pattern 131 and the preliminary spacer pattern 141 .

[0097] The second buried dielectric pattern 161 may fill a space between the preliminary electrode pattern 131 and the preliminary spacer pattern 141 adjacent to each other in the second direction D2. For example, the second buried dielectric pattern 161 may fill an opening. The second buried dielectric pattern 161 may be formed of the same material as the mold dielectric pattern 121 and the first buried dielectric pattern 151, and may cover the sidewalls of the preliminary electrode pattern 131 and the sidewalls of the preliminary spacer pattern 141.

[0098] The second buried dielectric pattern 161 may be formed by depositing a second buried dielectric layer (not shown) on the substrate 100 on which the preliminary electrode pattern 131 and the preliminary spacer pattern 141 are formed and then performing a planarization process. The second buried dielectric layer may be formed using a deposition process performed at a relatively low temperature (e.g., equal to or lower than 400° C.). The second buried dielectric pattern 161 may include a discontinuous interface (e.g., a gap or a void) that may be formed along the first direction D1.

[0099] Reference Fig. 9 , Fig.13 and Fig.14 , a first etching process may be performed to simultaneously recess top surfaces of the preliminary electrode pattern 131 and the preliminary spacer pattern 141 ( S50 ).

[0100] The first etching process may be an isotropic wet etching process using a first etchant having an etching selectivity with respect to the mold dielectric layer 120 and the first buried dielectric layer 151 and the second buried dielectric layer 161. In the first etching process, an etching rate of the preliminary spacer pattern 141 may depend on a concentration of impurities doped in the preliminary spacer pattern 141. The preliminary electrode pattern 131 and the preliminary spacer pattern 141 may be simultaneously etched in the first etching process using the first etchant. In the first etching process using the etchant, the preliminary electrode pattern 131 and the preliminary spacer pattern 141 may be etched at an etching selectivity ratio of about 1:1 or about 1.5:1.

[0101] When the preliminary electrode pattern 131 is formed of a nitride containing a metal element and the preliminary spacer pattern is formed of silicon oxide doped with a metal element, the first etchant may include ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and deionized water.

[0102] The first etching process may form an initial recessed region RS that partially exposes the sidewalls of the mold dielectric pattern 121, the sidewalls of the first buried dielectric pattern 151, and the sidewalls of the second buried dielectric pattern 161, and may also form the bottom electrode pattern 133 and the spacer pattern 143. As discussed above, the bottom electrode pattern 133 may include a bottom portion 133a connected to the first conductive line CL1 and a pair of sidewall portions 133b vertically protruding from opposite ends of the bottom portion 133a. As discussed above, the spacer pattern 143 may include a first segment 143a covering the bottom portion 133a of the bottom electrode pattern 133 and a second segment 143b covering the sidewall portion 133b of the bottom electrode pattern 133.

[0103] like Fig.14, the preliminary recessed region RS may have a first width W1 in the first direction D1 corresponding to the sum of the thicknesses of the bottom electrode pattern 133 and the spacer pattern 143. When the isotropic wet etching process is performed to form the preliminary recessed region RS, the bottom electrode pattern 133 and the spacer pattern 143 may each have a rounded top surface.

[0104] In certain embodiments, since top surfaces of the preliminary electrode pattern 131 and the preliminary spacer pattern 141 made of different materials are simultaneously recessed, a method of manufacturing a variable resistance memory device may be simplified.

[0105] Because the first etching process uses an etching recipe having an etching selectivity with respect to the mold dielectric pattern 121, the first buried dielectric pattern 151, and the second buried dielectric pattern 161, the mold dielectric pattern 121, the first buried dielectric pattern 151, and the second buried dielectric pattern 161 may be prevented from being damaged while forming the initial recessed region RS.

[0106] Reference Fig. 9 , Fig.15 and Fig.16 , a second etching process may be performed to form an expanded recessed region ER having a width greater than that of the initial etched region RS ( S60 ).

[0107] The second etching process may be an isotropic wet etching process. The second etching process may use a second etchant having an etching selectivity with respect to the bottom electrode pattern 133 and the spacer pattern 143. The second etching process may partially etch the sidewalls of the mold dielectric pattern 121, the first buried dielectric pattern 151, and the second buried dielectric pattern 161.

[0108] When the mold dielectric pattern 121 , the first dielectric pattern 151 , and the second dielectric pattern 161 are formed of silicon nitride or silicon oxynitride, the second etchant may include phosphoric acid.

[0109] like Fig.16 As shown in , the expanded recessed region ER may have a second width W2 greater than the first width W1 of the initial recessed region RS. Since the second etching process causes the expanded recessed region ER to have an increased width, the expanded recessed region ER may be easily filled with a variable resistance pattern VRP to be discussed below.

[0110] Reference Fig. 9 and Fig.17 , a variable resistance pattern VRP may be formed in the expanded recessed region ER ( S70 ).

[0111] For example, a variable resistance layer may be formed to fill the enlarged recessed region ER, and then an upper portion of the variable resistance layer may be etched to form a variable resistance pattern VRP. The variable resistance layer may include one or more of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe. The variable resistance layer may be formed by physical vapor deposition or chemical vapor deposition.

[0112] The variable resistance pattern VRP may completely or partially fill the expanded recessed region ER. When the variable resistance pattern VRP completely fills the expanded recessed region ER, a planarization process may be performed to allow the variable resistance pattern VRP to have a top surface coplanar with the top surfaces of the mold dielectric pattern 121, the first buried pattern 151, and the second buried pattern 161.

[0113] When the variable resistance pattern VRP partially fills the expanded recessed region ER, an intermediate electrode may be formed on an upper portion of the expanded recessed region ER (see Figure 5 The intermediate electrode ME may be formed by forming an electrode layer on the substrate 100 on which the variable resistance pattern VRP is formed, and then performing a planarization process on the electrode layer. The intermediate electrode ME may include one or more of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0114] Return to reference Figure 4 , Figure 5 and Fig. 9 , a switching element SW and a top electrode TE may be formed on the corresponding variable resistance pattern VRP ( S80 ).

[0115] For example, a switch layer and an electrode layer may be sequentially stacked on the top surface of the variable resistance pattern VRP. A mask pattern may be formed on the top electrode layer, and then may be used as an etching mask to sequentially etch the top electrode layer and the switch layer. As a result, the switch element SW and the top electrode TE may be two-dimensionally separated from each other along the first direction D1 and the second direction D2.

[0116] The switching layer may be formed of a compound in which one or more of Te and Se as chalcogenide elements are combined with one or more of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. The switching layer may further include a thermally stable element other than the compound.

[0117] The top electrode layer may be formed of one or more of W, Ti, Ta, Al, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0118] An upper interlayer dielectric layer 170 may be formed between the switching elements SW. The upper interlayer dielectric layer 170 may include carbon. For example, the upper interlayer dielectric layer 170 may include one or more of silicon oxycarbide, silicon oxycarbon nitride, and silicon oxynitride. After the formation of the upper interlayer dielectric layer 170 is completed, a planarization process may be performed to expose the top surface of the top electrode TE.

[0119] Refer again Figure 4 , Figure 5 and Fig. 9 , a second conductive line CL2 may be formed on the top electrode TE ( S90 ).

[0120] The formation of the second conductive line CL2 may include forming a conductive layer on the top electrode TE and then etching the conductive layer by using a mask pattern (not shown) extending in the second direction D2.

[0121] According to example embodiments, the spacer pattern may be formed of a dielectric material doped with impurities, and a first etching process may be performed to simultaneously recess a top surface of the preliminary spacer pattern and a top surface of the preliminary electrode pattern. Thus, a method of manufacturing a variable resistance memory device may be simplified.

[0122] In addition, the first etching process can use an etching recipe having an etching selectivity with respect to the mold dielectric pattern and the first buried dielectric pattern and the second buried dielectric pattern, so that the mold dielectric pattern, the first buried dielectric pattern and the second buried dielectric pattern can be prevented from being damaged while forming the recessed area. Therefore, the variable resistance memory device can be improved in terms of electrical reliability.

[0123] Although the present invention has been described in conjunction with the exemplary embodiments of the inventive concept shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential features of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the inventive concept.

Claims

1. A variable resistance memory device, the variable resistance memory device comprising: a plurality of memory cells, each comprising a variable resistance pattern and a switch pattern; a plurality of conductive lines to which the memory cells are connected; a bottom electrode connecting at least one of the plurality of conductive lines to the variable resistance pattern; as well as a spacer pattern formed on the bottom electrode to contact the variable resistance pattern, wherein the spacer pattern comprises a dielectric material doped with impurities, wherein the impurities doped in the dielectric material of the spacer pattern include the same metal element as the metal element of the bottom electrode, so that the top surface of the bottom electrode and the top surface of the spacer pattern are simultaneously recessed in the etching process, The variable resistance memory device further comprises a mold structure, in which the bottom electrode and the spacer pattern are formed. The dielectric material of the spacer pattern has a high etching selectivity with respect to a material forming the mold structure and has a low etching selectivity with respect to a material forming the bottom electrode.

2. The variable resistance memory device according to claim 1, wherein: The concentration of the metal element in the spacer pattern is lower than the concentration of the metal element in the bottom electrode.

3. The variable resistance memory device according to claim 1, wherein: The spacer pattern includes silicon elements, metal elements, and oxygen elements.

4. The variable resistance memory device according to claim 1, wherein: Impurities doped in the dielectric material of the spacer pattern include one or more of germanium, tin, tungsten, titanium, tantalum, aluminum, zirconium, hafnium, nickel, and cobalt.

5. The variable resistance memory device according to claim 1, wherein: The molding structure includes a dielectric material different from the dielectric material of the spacer pattern.

6. The variable resistance memory device according to claim 1, wherein: The dielectric material is silicon oxide doped with impurities including one or more of germanium, tin, tungsten, titanium, tantalum, aluminum, zirconium, hafnium, nickel, and cobalt.

7. A variable resistance memory device, the variable resistance memory device comprising: A first conductive line extending in a first direction; molding a dielectric pattern formed on the first conductive line; a second conductive line formed on the molded dielectric pattern and extending in a second direction different from the first direction; a bottom electrode formed in the molded dielectric pattern, the bottom electrode including a bottom portion connected to the first conductive line and a sidewall portion vertically protruding from the bottom portion; a buried dielectric pattern covering a bottom portion and a sidewall portion of the bottom electrode; a spacer pattern formed between the buried dielectric pattern and the bottom electrode, the spacer pattern comprising a dielectric material doped with impurities; as well as a variable resistance pattern formed between the bottom electrode and the second conductive line, the variable resistance pattern being in contact with a sidewall portion of the bottom electrode, Wherein, the impurities doped in the dielectric material of the spacer pattern include a first metal element, wherein the bottom electrode comprises a conductive material, the conductive material comprising a second metal element that is the same as the first metal element, so that a top surface of the bottom electrode and a top surface of the spacer pattern are simultaneously recessed during an etching process, The dielectric material of the spacer pattern has a high etching selectivity with respect to a material forming the mold dielectric pattern and the buried dielectric pattern, and has a low etching selectivity with respect to a material forming the bottom electrode.

8. The variable resistance memory device according to claim 7, wherein: The spacer pattern includes silicon elements, metal elements, and oxygen elements.

9. The variable resistance memory device according to claim 7, wherein: The dielectric material of the spacer pattern includes a first semiconductor element, and The impurities doped into the dielectric material of the spacer pattern include a second semiconductor element different from the first semiconductor element.

10. The variable resistance memory device according to claim 7, wherein: The variable resistance pattern has a rounded bottom surface contacting a top surface of the spacer pattern and a top surface of the bottom electrode.

11. The variable resistance memory device according to claim 7, wherein: Spacer patterns include: a first segment formed on a bottom portion of the bottom electrode; and The second section is formed on the sidewall portion of the bottom electrode, The second section of the spacer pattern contacts the variable resistor pattern.

12. The variable resistance memory device according to claim 7, wherein: On the first conductive line, a thickness of the bottom electrode is smaller than a thickness of the spacer pattern.

13. The variable resistance memory device according to claim 7, wherein: The molded dielectric pattern and the buried dielectric pattern include a dielectric material different from a dielectric material of the spacer pattern.

14. The variable resistance memory device according to claim 7, wherein: The sidewall portion of the bottom electrode includes a pair of sidewall portions extending from opposite ends of the bottom portion, and The buried dielectric pattern includes a gap or a void between the pair of sidewall portions of the bottom electrode.

15. The variable resistance memory device according to claim 7, further comprising a switching element formed between the variable resistance pattern and the second conductive line, in, The switching element includes a chalcogenide material.

16. A method of manufacturing a variable resistance memory device, the method comprising: forming a first conductive line extending in a first direction on the substrate; forming a trench in a molded dielectric layer covering the first conductive line; sequentially forming a preliminary electrode pattern and a preliminary spacer pattern in the trench; forming a buried dielectric pattern in the trench formed with the preliminary electrode pattern and the preliminary spacer pattern; performing a first etching process to simultaneously recess a top surface of the preliminary electrode pattern and a top surface of the preliminary spacer pattern; performing a second etching process on the mold dielectric layer and the buried dielectric pattern to form an enlarged recessed region between the mold dielectric layer and the buried dielectric pattern; forming a variable resistance pattern in the enlarged recessed area, wherein the preliminary spacer pattern includes a dielectric material doped with a metal element that is the same as a metal element included in the preliminary electrode pattern, so that a top surface of the preliminary electrode pattern and a top surface of the preliminary spacer pattern are simultaneously recessed in the first etching process, The first etching process includes an isotropic etching process using a first etchant, and the first etchant has an etching selectivity with respect to the mold dielectric layer and the buried dielectric pattern.

17. The method according to claim 16, wherein: The preliminary spacer pattern includes silicon oxide doped with impurities.

18. The method according to claim 17, wherein: The impurities doped in the silicon oxide of the preliminary spacer pattern include one or more of germanium, tin, tungsten, titanium, tantalum, aluminum, zirconium, hafnium, nickel, and cobalt.

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