Quad-core RF coil circuit

Abstract

The embodiment of the present invention discloses a quad-core radio frequency coil circuit, comprising: a coil module, the coil module is used to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal; a front-end module, the front-end module is connected to the coil module, and is used to generate the nuclear magnetic test signal and collect the induction signal. The quad-core radio frequency coil circuit disclosed in the embodiment of the present invention, through a double-layer nested structure combination design, can emit multiple nuclide signals simultaneously or at different times for nuclear magnetic resonance imaging on the basis of a high degree of coordination with multi-frequency multi-channel electronics and timing control systems, solves the problems of interaction between different nuclides and electromagnetic interference, and realizes multi-channel multi-frequency high-uniformity radio frequency excitation and high-sensitivity signal acquisition.

Description

Technical Field

[0001] The embodiments of the present invention relate to nuclear magnetic resonance technology, and in particular to a quad-core radio frequency coil circuit. Background Art

[0002] At present, hydrogen atom magnetic resonance imaging is relatively mature, but only hydrogen atom imaging can no longer meet the needs of human diagnosis of various diseases. Since multi-nuclear magnetic resonance imaging technology can be used to obtain morphological and metabolic information in biological systems, it has been rapidly developed. In addition to 1H, there are also studies on nuclides such as 13C, 19F, 23Na, and 31P. With the development of magnetic resonance technology, a three-tuned magnetic resonance radio frequency probe or coil has been proposed to meet the needs of detecting three different MR sensitive nuclides. The design was demonstrated in a small coil using lumped element technology and showed its feasibility in three-frequency operation for small sample MR applications. However, due to the complex structure of the multi-tuned coil, the difficulty of its design, production and debugging is greatly increased. At present, there is no multi-channel radio frequency coil system that can achieve synchronous excitation and acquisition of four nuclide signals in high and ultra-high fields. In large sample imaging applications with high magnetic fields, multi-channel four-core RF coils may encounter technical challenges. The interaction between different nuclear channels, the mutual coupling between channels, and the complex electromagnetic wave behavior in high-intensity electromagnetic fields, dielectric and conductive biological samples, etc. will seriously reduce the transmission efficiency and receiving sensitivity of the coil. In radio frequency technology, in order to have a uniform excitation when exciting the signal and a high sensitivity when receiving the signal, the phase of the excitation source of different channels can be changed to achieve orthogonal excitation of the multi-channel coils of each nuclide to generate a circularly polarized transmission field. Only when a high-sensitivity receiving field is formed in the receiving mode can there be sufficient coverage to improve the signal-to-noise ratio of weak nuclides.

[0003] In dual-core RF coils of various configurations for observing signals from nuclei other than protons, such as 19F and 31P. A dual-tuned coil design can be achieved using a common-mode differential mode approach or using two geometrically isolated coils (the B1 fields are perpendicular to each other). This approach is often used for single-core orthogonal coil designs to improve SNR, but the coil can also be used as a dual-resonance mode without using an orthogonal configuration. For example, one coil can be a loop tuned to 1H, and the other can be a butterfly, dual loop, monopole antenna, or microstrip transmission line tuned to the other core. A dual-resonance unit can also be formed by nesting two independent coil loops; a dual-core resonant coil unit sharing one coil loop is achieved by inserting a resonant network at the coil port. Most current multi-nuclear MRI experiments are performed by performing single-nuclear acquisitions separately and then registering the images acquired from each nucleus. This is not only time-consuming, but also difficult to successfully complete image registration due to the different coil settings and image resolutions for each single-nuclear acquisition. One solution is to use a multi-tuned coil array to detect multi-nuclear signals simultaneously. However, the design of this type of coil is complex and interactions and crosstalk between each individually tuned coil element must be suppressed. Summary of the invention

[0004] The present invention provides a quad-core radio frequency coil circuit to achieve multi-channel, multi-frequency, high-uniformity radio frequency excitation and high-sensitivity signal acquisition, including:

[0005] A coil module, the coil module is used to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal;

[0006] A front-end module is connected to the coil module and is used to generate the nuclear magnetic test signal and collect the induction signal.

[0007] Optionally, the coil module includes a first coil array and a second coil array, and the center positions of the first coil array coincide with those of the second coil array.

[0008] Optionally, the first coil array includes a plurality of first coil units, which are arranged in a superimposed manner based on a first preset phase difference, and the second coil array includes a plurality of second coil units, which are arranged in a superimposed manner based on a second preset phase difference.

[0009] Optionally, the first coil unit includes: a first interface circuit and a first detuning circuit, the first detuning circuit is connected to the first interface circuit, and the first interface circuit is connected to the front-end module.

[0010] Optionally, the first interface circuit includes: an input terminal IN1, an input terminal IN2, a capacitor C1, a capacitor C2 and an inductor L1, the input terminal IN1 is connected to the first end of the capacitor C1, the second end of the capacitor C1 is connected to the first end of the capacitor C2, the second end of the capacitor C2 is connected to the first end of the inductor L1, the second end of the inductor L1 is connected to the first end of the capacitor C2, and the input terminal IN2 is connected to the second end of the capacitor C1.

[0011] Optionally, the first detuning circuit includes: an inductor L2, an inductor L3, an inductor L4, a capacitor C3, a capacitor C4, a capacitor C5, a diode D1, a diode D2 and a diode D3, wherein a first end of the inductor L2 is connected to a first end of the capacitor C3, a second end of the inductor L2 is connected to a cathode of the diode D1, an anode of the diode D2 is connected to a second end of the capacitor C3, a second end of the capacitor C4 is connected to a first end of the capacitor C3, an anode of the diode D2 is connected to a second end of the capacitor C4, a cathode of the diode D2 is connected to a second end of the inductor L3, a first end of the inductor L3 is connected to a first end of the capacitor C4, a second end of the capacitor C5 is connected to a first end of the capacitor C4, an anode of the diode D3 is connected to a second end of the capacitor C5, a cathode of the diode D3 is connected to a second end of the inductor L4, and a first end of the inductor L4 is connected to a first end of the capacitor C5.

[0012] Optionally, the second coil unit includes: a second interface circuit and a second detuning circuit, the second detuning circuit is connected to the second interface circuit, and the second interface module is connected to the front-end module.

[0013] Optionally, the second interface circuit includes: an input terminal IN1, an input terminal IN2, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a variable capacitor B1, a variable capacitor B2, an inductor L5, an inductor L6 and an inductor L7, wherein the input terminal IN1 is connected to a first end of the capacitor C6, a second end of the capacitor C6 is connected to a first end of the capacitor C7, a first end of the inductor L5 is connected to a second end of the capacitor C7, a second end of the inductor L5 is connected to a first end of the capacitor C6, a first end of the capacitor C8 is connected to a second end of the capacitor C7, a second end of the capacitor C8 is connected to a first end of the capacitor C9, and a second end of the capacitor C9 is connected to a first end of the capacitor C6. The first end of the inductor L2 is connected to the second end of the capacitor C6, the second end of the inductor L2 is connected to the second end of the capacitor C10, the first end of the inductor L3 is connected to the first end of the capacitor C9, the second end of the inductor L3 is connected to the second end of the capacitor C10, the first end of the variable capacitor B1 is connected to the first end of the capacitor C8, the second end of the variable capacitor B1 is connected to the second end of the capacitor C8, the first end of the variable capacitor B2 is connected to the first end of the capacitor C8, and the second end of the variable capacitor B2 is connected to the second end of the capacitor C8.

[0014] Optionally, the second detuning circuit includes: a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, an inductor L8, an inductor L9, an inductor L10, a diode D4, a diode D5 and a diode D6, wherein a first end of the inductor L8 is connected to a first end of the capacitor C11, a second end of the inductor L8 is connected to a cathode of the diode D4, an anode of the diode D5 is connected to a second end of the capacitor C11, a second end of the capacitor C12 is connected to a first end of the capacitor C11, and a first end of the capacitor C12 is connected to a cathode of the diode D4. The second end of the capacitor C13, the anode of the diode D5 is connected to the second end of the capacitor C12, the cathode of the diode D5 is connected to the second end of the inductor L9, the first end of the inductor L9 is connected to the first end of the capacitor C13, the second end of the capacitor C14 is connected to the first end of the capacitor C12, the anode of the diode D6 is connected to the second end of the capacitor C14, the cathode of the diode D6 is connected to the second end of the inductor L10, and the first end of the inductor L10 is connected to the first end of the capacitor C14.

[0015] Optionally, the front-end module includes: a power division module and a signal driving module, the power division module is connected to the signal driving module, the signal driving module is connected to the coil module, the power division module is used to split the nuclear magnetic resonance test signal into multiple test signals, and the signal driving module is used to input the multiple test signals into the coil module.

[0016] The embodiment of the present invention discloses a quad-core radio frequency coil circuit, comprising: a coil module, the coil module is used to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal; a front-end module, the front-end module is connected to the coil module, and is used to generate the nuclear magnetic test signal and collect the induction signal. The quad-core radio frequency coil circuit disclosed in the embodiment of the present invention, through a double-layer nested structure combination design, can emit multiple nuclide signals simultaneously or at different times for nuclear magnetic resonance imaging on the basis of a high degree of coordination with multi-frequency multi-channel electronics and timing control systems, solves the problems of interaction between different nuclides and electromagnetic interference, and realizes multi-channel multi-frequency high-uniformity radio frequency excitation and high-sensitivity signal acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A module connection diagram of a quad-core radio frequency coil circuit provided in Embodiment 1 of the present invention;

[0018] Figure 2 It is a top view of the structure of the quad-core radio frequency coil circuit in the first embodiment of the present invention;

[0019] Figure 3 is a circuit diagram of the first coil array in the first embodiment of the present invention;

[0020] Figure 4 is a circuit diagram of the coil Na1 in the first embodiment of the present invention;

[0021] Figure 5 is a circuit diagram of the coil P1 in the first embodiment of the present invention;

[0022] Figure 6 is a circuit diagram of coil Na2 in Embodiment 1 of the present invention;

[0023] Figure 7 is a circuit diagram of the coil P2 in the first embodiment of the present invention;

[0024] Figure 8 is a schematic diagram of the arrangement of the first coil array in an alternative embodiment;

[0025] Fig. 9 is a circuit diagram of the second coil array in the first embodiment of the present invention;

[0026] Fig.10 is a circuit diagram of the coil H1 in the first embodiment of the present invention;

[0027] Fig.11 is a circuit diagram of the coil F1 in the first embodiment of the present invention;

[0028] Fig.12 is a circuit diagram of coil H2 in Embodiment 1 of the present invention;

[0029] Fig.13 is a circuit diagram of coil F2 in Embodiment 1 of the present invention;

[0030] Fig.14 is a circuit diagram of a front-end module in Embodiment 2 of the present invention;

[0031] Fig.15 This is a circuit diagram of a quad-core radio frequency coil circuit in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0033] It should be mentioned before discussing the exemplary embodiments in more detail that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0034] In addition, the terms "first", "second", etc. may be used herein to describe various directions, actions, steps or elements, etc., but these directions, actions, steps or elements are not limited by these terms. These terms are only used to distinguish a first direction, action, step or element from another direction, action, step or element. For example, without departing from the scope of the present application, the first coil array may be referred to as the first coil array, and similarly, the second coil array may be referred to as the first coil array. Both the first coil array and the second coil array are first coil arrays, but they are not the same first coil array. The terms "first", "second", etc. should not be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0035] Embodiment 1

[0036] Figure 1 This is a module connection diagram of a quad-core radio frequency coil circuit provided in Embodiment 1 of the present invention. This embodiment is applicable to the case where nuclear magnetic resonance is performed using multiple radionuclide signals. Specifically, the quad-core radio frequency coil circuit provided in this embodiment includes: a coil module 1 and a front-end module 2.

[0037] The coil module 1 is used to receive the nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal. In this embodiment, the nuclear magnetic test signal is generated by an instrument such as a signal generator for nuclear magnetic resonance imaging. Common nuclides include 1H (hydrogen), 13C (carbon), 19F (fluorine), 23Na (sodium) and 31P (phosphorus), etc. The four-nuclear radio frequency coil circuit provided in this embodiment is illustrated by taking H, F, Na and P as examples. The induction signal is the induction signal fed back by the user according to the nuclear magnetic test signal. After the coil module 1 collects the induction signal from the user, it can be transmitted to an instrument such as an oscilloscope for imaging.

[0038] See also Figure 2 The coil module 1 includes a first coil array 11 and a second coil array 12 , and the center positions of the first coil array 11 and the second coil array 12 coincide with each other. Figure 2 This is a top view of the structure of the quad-core RF coil circuit in this embodiment. The first coil array 11 and the second coil array 12 are designed with a double-layer nested structure combination. The first coil array 11 includes 4 Na coils and 4 P coils, and the 4 Na coils and the 4 P coils form a circular structure. The second coil array includes 2 H coils and 2 F coils, and the 2 H coils and the 2 F coils also form a circular structure, and the center of the circular structure coincides with the center of the circular structure of the 2 Na coils and the 2 P coils. Specifically, the center line of the P coil perpendicular to the plane where the P coil is located (ignoring the coil curvature) coincides with the center line of the H coil perpendicular to the plane where the H coil is located, for example, coincides with the axis Z1 passing through the center of the circle. The center line Z2 of the Na coil perpendicular to the plane where the Na coil is located (ignoring the coil curvature) is 45° different from the center line Z3 of the F coil perpendicular to the plane where the F coil is located (ignoring the coil curvature). The problem of interference between the inner and outer coil arrays is solved by offsetting the position of the Na coil relative to the F coil by 45°.

[0039] See also Figure 3 , Figure 3: is a circuit diagram of the first coil array 11. In the present embodiment, the first coil array 11 is illustrated by taking two Na coils and two P coils as an example. The first coil array 11 includes a plurality of first coil units (coil Na1, coil P1, coil Na2 and coil P2). The plurality of first coil units are arranged in a superimposed manner based on a first preset phase difference. Specifically, coil Na1 and coil Na2 are Na coils, coil P1 and coil P2 are P coils, wires X2 and X3 of coil Na1 and wires X5 and X8 of coil P1 form an overlapping region with an area of ​​M1, wires X6 and X7 of coil P1 and wires X9 and X12 of coil C11 form an overlapping region with an area of ​​M2, wires X10 and X11 of coil Na2 and wires X13 and X16 of coil P2 form an overlapping region with an area of ​​M3. By superimposing and arranging a plurality of regions in the first coil array 11, the effect of decoupling adjacent coil channels is achieved, and interference between Na coils and P coils is reduced.

[0040] See also Figure 4 The coil NA1 in the first coil unit includes: a first interface circuit 111A and a first detuning circuit 112A, the first detuning circuit 112A is connected to the first interface circuit 111A, and the first interface circuit 111A is connected to the front-end module 2. The wires X1, X2, X3 and X4 of the coil NA1 form a rectangular and raised structure, the wires X1, X3 and X4 are L-shaped wires, the wire X2 includes a Z-shaped wire and an L-shaped wire, a raised structure is formed between the Z-shaped wire and the L-shaped wire for connecting the inductor L5A, a secondary detuning circuit consisting of an inductor L2A, a diode D1A and a capacitor C3A is connected between the wire X1 and the wire X4, a secondary detuning circuit consisting of an inductor L3A, a diode D2A and a capacitor C4A is connected between the wire X1 and the wire X2, a secondary detuning circuit consisting of an inductor L4A, a diode D3A and a capacitor C5A is connected between the wire X2 and the wire X3, and a first interface circuit 111A is connected between the wire X4 and the wire X3. Figure 4: is a circuit diagram of the coil 11A, the first interface circuit 111A includes: an input terminal IN1A, an input terminal IN2A, a capacitor C1A, a capacitor C2A and an inductor L1A, the input terminal IN1A is connected to the first end of the capacitor C1A, the second end of the capacitor C1A is connected to the first end of the capacitor C2A, the second end of the capacitor C2A is connected to the first end of the inductor L1A, the second end of the inductor L1A is connected to the first end of the capacitor C2A, and the input terminal IN2A is connected to the second end of the capacitor C1A. The first detuning circuit 112A includes: an inductor L2A, an inductor L3A, an inductor L4A, an inductor L5A, a capacitor C3A, a capacitor C4A, a capacitor C5A, a diode D1A, a diode D2A and a diode D3A, wherein a first end of the inductor L2A is connected to a first end of the capacitor C3A, a second end of the inductor L2A is connected to a cathode of the diode D1A, an anode of the diode D2A is connected to a second end of the capacitor C3A, a second end of the capacitor C4A is connected to a first end of the capacitor C3A, an anode of the diode D2A is connected to a second end of the capacitor C4A, a cathode of the diode D2A is connected to a second end of the inductor L3A, a first end of the inductor L3A is connected to a first end of the capacitor C4A, an anode of the diode D3A is connected to a second end of the capacitor C5A, a cathode of the diode D3A is connected to a second end of the inductor L4A, a first end of the inductor L4A is connected to a first end of the capacitor C5A, a first end of the capacitor L5A is connected to a second end of the capacitor C5A, and a second end of the inductor L5A is connected to a second end of the capacitor C4A.

[0041] See also Figure 5 , Figure 5For the specific circuit of coil P1, the wire X5, wire X6, wire X7 and wire X8 of coil P1 form a rectangular plus a raised structure, wire X5, wire X7 and wire X8 are L-shaped wires, wire X6 includes a Z-shaped wire and an L-shaped wire, a raised structure is formed between the Z-shaped wire and the L-shaped wire for connecting the inductor L5B, a secondary detuning circuit consisting of an inductor L2B, a diode D1B and a capacitor C3B is connected between wire X5 and wire X8, a secondary detuning circuit consisting of an inductor L3B, a diode D2B and a capacitor C4B is connected between wire X5 and wire X6, a secondary detuning circuit consisting of an inductor L4B, a diode D3B and a capacitor C5B is connected between wire X6 and wire X7, and a first interface circuit 111B is connected between wire X8 and wire X7. The first interface circuit 111B includes: an input terminal IN1B, an input terminal IN2B, a capacitor C1B, a capacitor C2B and an inductor L1B, the input terminal IN1B is connected to the first end of the capacitor C1B, the second end of the capacitor C1B is connected to the first end of the capacitor C2B, the second end of the capacitor C2B is connected to the first end of the inductor L1B, the second end of the inductor L1B is connected to the first end of the capacitor C2B, and the input terminal IN2B is connected to the second end of the capacitor C1B. The first detuning circuit 112B includes: an inductor L2B, an inductor L3B, an inductor L4B, an inductor L5B, a capacitor C3B, a capacitor C4B, a capacitor C5B, a diode D1B, a diode D2B and a diode D3B, wherein a first end of the inductor L2B is connected to a first end of the capacitor C3B, a second end of the inductor L2B is connected to a cathode of the diode D1B, an anode of the diode D2B is connected to a second end of the capacitor C3B, a second end of the capacitor C4B is connected to a first end of the capacitor C3B, an anode of the diode D2B is connected to a second end of the capacitor C4B, a cathode of the diode D2B is connected to a second end of the inductor L3B, a first end of the inductor L3B is connected to a first end of the capacitor C4B, an anode of the diode D3B is connected to a second end of the capacitor C5B, a cathode of the diode D3B is connected to a second end of the inductor L4B, a first end of the inductor L4B is connected to a first end of the capacitor C5B, a first end of the capacitor L5B is connected to a second end of the capacitor C5B, and a second end of the inductor L5B is connected to a second end of the capacitor C4B.

[0042] See also Figure 6 , Figure 6For the specific circuit of coil NA2, the wire X9, wire X10, wire X11 and wire X12 of coil NA2 form a rectangular plus a raised structure, the wire X10, wire X11 and wire X12 are L-shaped wires, the wire X9 includes a Z-shaped wire and an L-shaped wire, a raised structure is formed between the Z-shaped wire and the L-shaped wire for connecting the inductor L5C, a secondary detuning circuit consisting of an inductor L2C, a diode D1C and a capacitor C3C is connected between the wire X10 and the wire X11, a secondary detuning circuit consisting of an inductor L3C, a diode D2C and a capacitor C4C is connected between the wire X9 and the wire X10, a secondary detuning circuit consisting of an inductor L4C, a diode D3C and a capacitor C5C is connected between the wire X9 and the wire X12, and a first interface circuit 111C is connected between the wire X11 and the wire X12. In this embodiment, the inductance L5A of the coil Na1 and the inductance L5C of the coil Na2 are arranged adjacent to each other and correspondingly, and are used for decoupling between the coil Na1 and the coil Na2. Specifically, decoupling is achieved by adaptively adjusting the overlapping area of ​​the inductance coils between the inductance L5A and the inductance L5C. The first interface circuit 111C includes: an input terminal IN1C, an input terminal IN2C, a capacitor C1C, a capacitor C2C and an inductance L1C, the input terminal IN1C is connected to the first end of the capacitor C1C, the second end of the capacitor C1C is connected to the first end of the capacitor C2C, the second end of the capacitor C2C is connected to the first end of the inductance L1C, the second end of the inductance L1C is connected to the first end of the capacitor C2C, and the input terminal IN2C is connected to the second end of the capacitor C1C. The first detuning circuit 112C includes: an inductor L2C, an inductor L3C, an inductor L4C, an inductor L5C, a capacitor C3C, a capacitor C4C, a capacitor C5C, a diode D1C, a diode D2C and a diode D3C, wherein a first end of the inductor L2C is connected to a first end of the capacitor C3C, a second end of the inductor L2C is connected to a cathode of the diode D1C, an anode of the diode D2C is connected to a second end of the capacitor C3C, a second end of the capacitor C4C is connected to a first end of the capacitor C3C, an anode of the diode D2C is connected to a second end of the capacitor C4C, a cathode of the diode D2C is connected to a second end of the inductor L3C, a first end of the inductor L3C is connected to a first end of the capacitor C4C, an anode of the diode D3C is connected to a second end of the capacitor C5C, a cathode of the diode D3C is connected to a second end of the inductor L4C, a first end of the inductor L4C is connected to a first end of the capacitor C5C, a first end of the capacitor L5C is connected to a second end of the capacitor C5C, and a second end of the inductor L5C is connected to a second end of the capacitor C4C.

[0043] See also Figure 7 , Figure 7It is a specific circuit of coil P2, wherein the wires X13, X14, X15 and X16 of coil P2 form a rectangular and raised structure, wherein the wires X14, X15 and X16 are L-shaped wires, and the wire X13 includes a Z-shaped wire and an L-shaped wire, wherein a raised structure is formed between the Z-shaped wire and the L-shaped wire for connecting the inductor L5D, and a secondary detuning circuit consisting of an inductor L2D, a diode D1D and a capacitor C3D is connected between the wires X14 and X15, and a secondary detuning circuit consisting of an inductor L3D, a diode D2D and a capacitor C4D is connected between the wires X13 and X14, and a secondary detuning circuit consisting of an inductor L4D, a diode D3D and a capacitor C5D is connected between the wires X13 and X16, and a first interface circuit 111D is connected between the wires X15 and X16. In this embodiment, the inductor L5B of the coil P1 and the inductor L5D of the coil P2 are arranged adjacent to each other and correspondingly, and are used for decoupling between the coils P1 and P2. Specifically, decoupling is achieved by adaptively adjusting the overlapping area of ​​the inductor coils between the inductor L5B and the inductor L5D. The first interface circuit 111D includes: an input terminal IN1D, an input terminal IN2D, a capacitor C1D, a capacitor C2D, and an inductor L1D. The input terminal IN1D is connected to a first end of the capacitor C1D, a second end of the capacitor C1D is connected to a first end of the capacitor C2D, a second end of the capacitor C2D is connected to a first end of the inductor L1D, a second end of the inductor L1D is connected to a first end of the capacitor C2D, and the input terminal IN2D is connected to a second end of the capacitor C1D. The first detuning circuit 112D includes: an inductor L2D, an inductor L3D, an inductor L4D, an inductor L5D, a capacitor C3D, a capacitor C4D, a capacitor C5D, a diode D1D, a diode D2D and a diode D3D. A first end of the inductor L2D is connected to a first end of the capacitor C3D, a second end of the inductor L2D is connected to a cathode of the diode D1D, an anode of the diode D2D is connected to a second end of the capacitor C3D, a second end of the capacitor C4D is connected to a first end of the capacitor C3D, an anode of the diode D2D is connected to a second end of the capacitor C4D, a cathode of the diode D2D is connected to a second end of the inductor L3D, a first end of the inductor L3D is connected to a first end of the capacitor C4D, an anode of the diode D3D is connected to a second end of the capacitor C5D, a cathode of the diode D3D is connected to a second end of the inductor L4D, a first end of the inductor L4D is connected to a first end of the capacitor C5D, a first end of the capacitor L5D is connected to a second end of the capacitor C5D, and a second end of the inductor L5D is connected to a second end of the capacitor C4D.

[0044] In an alternative embodiment, the first coil array 11 includes 4 Na coils and 4 P coils, see Figure 8 , Figure 8As an alternative to the arrangement diagram of the first coil array 11 in the embodiment, the four Na coils (coil Na1, coil Na2, coil Na3, coil Na4) are decoupled from each other through the inductance of the rectangular outer protruding part, and the four P coils (coil P1, coil P2, coil P3, coil P4) are also decoupled from each other through the inductance of the rectangular outer protruding part. Adjacent coils, such as coil Na1 and coil Na2, are decoupled through the overlapping area.

[0045] In this embodiment, the nuclear magnetic test signal is input into the first interface module through the input terminal IN1 and the input terminal IN2, and the working states of the Na coil and the P coil are respectively controlled through the first detuning circuit 112 to reduce the residual interference and shielding effect caused by the copper components in other array loops, allowing simultaneous imaging of Na and P, adding a resonant circuit to the coil unit port to achieve single coil dual-frequency resonance, and generating two resonant frequencies at the same time, solving the problem of electromagnetic interference between the two nuclides of Na and P. In this embodiment, the value of each element in each coil can be adjusted according to actual conditions, and is not limited in this embodiment.

[0046] See also Fig. 9 , Fig. 9 is a circuit diagram of the second coil array 12. In this embodiment, both the H coil and the F coil can transmit the radio frequency signal of the nuclide H or the nuclide F, and the H coil and the F coil have the same structure. Therefore, the H coil can also be used as the F coil, and the F coil can also be used as the H coil. The specific usage can be selected according to actual needs. In this embodiment, two H coils and two F coils are taken as an example for description. The second coil array 12 includes multiple second coil units (coil H1, coil F1, coil H2 and coil F2), and the multiple second coil units are arranged in a superimposed manner based on a second preset phase difference. Specifically, coil H1 and coil H2 are P coils, coil F1 and coil F2 are Na coils, and the wires X18 and X19 of coil H1 and the wires X21 and X24 of coil F1 form an overlapping area with an area of ​​M4, the wires X22 and X23 of coil F1 and the wires X25 and X28 of coil C12 form an overlapping area with an area of ​​M5, and the wires X26 and X27 of coil H2 and the wires X29 and X32 of coil F2 form an overlapping area with an area of ​​M6. By superimposing and arranging multiple areas in the first coil array 12, the effect of decoupling adjacent coil channels is achieved.

[0047] The coil H1 in the second coil unit includes: a second interface circuit 121A and a second detuning circuit 122A, the second detuning circuit 122A is connected to the second interface circuit 121A, and the second interface module is connected to the front-end module 2. Fig.10 , Fig.10: is a circuit diagram of the coil H1 in this embodiment, wherein the wires X17, X18, X19 and X20 of the coil H1 form a rectangular structure with a protrusion, the wires X17, X19 and X20 are L-shaped wires, the wire X18 includes a Z-shaped wire and an L-shaped wire, a protrusion structure is formed between the Z-shaped wire and the L-shaped wire for connecting the inductor L12A, a secondary detuning circuit consisting of an inductor L11A, a diode D4A and a capacitor C11A is connected between the wire X17 and the wire X20, a secondary detuning circuit consisting of an inductor L9A, a diode D5A, a capacitor C12A and a capacitor C13A is connected between the wire X17 and the wire X18, a secondary detuning circuit consisting of an inductor L10A, a diode D6A and a capacitor C14A is connected between the wire X18 and the wire X19, and a second interface circuit 121A is connected between the wire X20 and the wire X19. The second interface circuit 121 includes: an input terminal IN1, an input terminal IN2, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a variable capacitor B1, a variable capacitor B2, an inductor L6, an inductor L7 and an inductor L8, wherein the input terminal IN1 is connected to a first end of the capacitor C6, a second end of the capacitor C6 is connected to a first end of the capacitor C7, a first end of the inductor L8 is connected to a second end of the capacitor C7, a second end of the inductor L8 is connected to a first end of the capacitor C6, a first end of the capacitor C8 is connected to a second end of the capacitor C7, a second end of the capacitor C8 is connected to a first end of the capacitor C9, and the capacitor C The second end of inductor L9 is connected to the first end of capacitor C10, the second end of capacitor C10 is connected to input terminal IN2, the first end of inductor L2 is connected to the second end of capacitor C6, the second end of inductor L2 is connected to the second end of capacitor C10, the first end of inductor L3 is connected to the first end of capacitor C9, the second end of inductor L3 is connected to the second end of capacitor C10, the first end of variable capacitor B1 is connected to the first end of capacitor C8, the second end of variable capacitor B1 is connected to the second end of capacitor C8, the first end of variable capacitor B2 is connected to the first end of capacitor C8, and the second end of variable capacitor B2 is connected to the second end of capacitor C8.The second detuning circuit 122 includes: a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, an inductor L9, an inductor L10, an inductor L11, an inductor L12, a diode D4, a diode D5 and a diode D6, wherein a first end of the inductor L11 is connected to a first end of the capacitor C11, a second end of the inductor L11 is connected to a cathode of the diode D4, an anode of the diode D5 is connected to a second end of the capacitor C11, a second end of the capacitor C12 is connected to a first end of the capacitor C11, a first end of the capacitor C12 is connected to a second end of the capacitor C13, and a diode D6. The positive electrode of D5 is connected to the second end of capacitor C12, the negative electrode of diode D5 is connected to the second end of inductor L9, the first end of inductor L9 is connected to the first end of capacitor C13, the second end of capacitor C14 is connected to the first end of capacitor C12, the positive electrode of diode D6 is connected to the second end of capacitor C14, the negative electrode of diode D6 is connected to the second end of inductor L10, the first end of inductor L10 is connected to the first end of capacitor C14, the first end of inductor L12 is connected to the second end of capacitor C13, and the second end of inductor L12 is connected to the first end of capacitor C14.

[0048] See also Fig.11 , Fig.11: is a circuit diagram of the coil F1 in this embodiment, wherein the wire X21, the wire X22, the wire X23 and the wire X24 of the coil F1 form a rectangular plus a raised structure, the wire X21, the wire X23 and the wire X24 are L-shaped wires, the wire X22 includes a Z-shaped wire and an L-shaped wire, a raised structure is formed between the Z-shaped wire and the L-shaped wire for connecting the inductor L12B, a secondary detuning circuit consisting of an inductor L11B, a diode D4B and a capacitor C11B is connected between the wire X21 and the wire X24, a secondary detuning circuit consisting of an inductor L9B, a diode D5B, a capacitor C12B and a capacitor C13B is connected between the wire X21 and the wire X22, a secondary detuning circuit consisting of an inductor L10B, a diode D6B and a capacitor C14B is connected between the wire X22 and the wire X23, and a second interface circuit 121B is connected between the wire X23 and the wire X24. The second interface circuit 121B includes: an input terminal IN1B, an input terminal IN2B, a capacitor C6B, a capacitor C7B, a capacitor C8B, a capacitor C9B, a capacitor C10B, a variable capacitor B1B, a variable capacitor B2B, an inductor L6B, an inductor L7B and an inductor L8B, the input terminal IN1B is connected to a first end of the capacitor C6B, the second end of the capacitor C6B is connected to a first end of the capacitor C7B, the first end of the inductor L8B is connected to a second end of the capacitor C7B, the second end of the inductor L8B is connected to a first end of the capacitor C6B, the first end of the capacitor C8B is connected to a second end of the capacitor C7B, and the second end of the capacitor C8B is connected to a first end of the capacitor C9B. The second end of capacitor C9B is connected to the first end of capacitor C10B, the second end of capacitor C10B is connected to input terminal IN2B, the first end of inductor L2B is connected to the second end of capacitor C6B, the second end of inductor L2B is connected to the second end of capacitor C10B, the first end of inductor L3B is connected to the first end of capacitor C9B, the second end of inductor L3B is connected to the second end of capacitor C10B, the first end of variable capacitor B1B is connected to the first end of capacitor C8B, the second end of variable capacitor B1B is connected to the second end of capacitor C8B, the first end of variable capacitor B2B is connected to the first end of capacitor C8B, and the second end of variable capacitor B2B is connected to the second end of capacitor C8B.The second detuning circuit 122B includes: a capacitor C11B, a capacitor C12B, a capacitor C13B, a capacitor C14B, an inductor L9B, an inductor L10B, an inductor L11B, an inductor L12B, a diode D4B, a diode D5B and a diode D6B, wherein a first end of the inductor L11B is connected to a first end of the capacitor C11B, a second end of the inductor L11B is connected to a cathode of the diode D4B, an anode of the diode D5B is connected to a second end of the capacitor C11B, a second end of the capacitor C12B is connected to a first end of the capacitor C11B, a first end of the capacitor C12B is connected to a second end of the capacitor C13B, and the diodes D6B are connected to the cathode of the diode D5B. The anode of diode D5B is connected to the second end of capacitor C12B, the cathode of diode D5B is connected to the second end of inductor L9B, the first end of inductor L9B is connected to the first end of capacitor C13B, the second end of capacitor C14B is connected to the first end of capacitor C12B, the anode of diode D6B is connected to the second end of capacitor C14B, the cathode of diode D6B is connected to the second end of inductor L10B, the first end of inductor L10B is connected to the first end of capacitor C14B, the first end of inductor L12B is connected to the second end of capacitor C13B, and the second end of inductor L12B is connected to the first end of capacitor C14B.

[0049] See also Fig.12 , Fig.12: is a circuit diagram of the coil H2 in this embodiment, wherein the wires X25, X26, X27 and X28 of the coil H2 form a rectangular and raised structure, the wires X26, X27 and X28 are L-shaped wires, the wire X25 includes a Z-shaped wire and an L-shaped wire, a raised structure is formed between the Z-shaped wire and the L-shaped wire for connecting the inductor L12C, a secondary detuning circuit consisting of an inductor L11C, a diode D4C and a capacitor C11C is connected between the wire X26 and the wire X27, a secondary detuning circuit consisting of an inductor L9C, a diode D5C, a capacitor C12C and a capacitor C13C is connected between the wire X25 and the wire X26, a secondary detuning circuit consisting of an inductor L10C, a diode D6C and a capacitor C14C is connected between the wire X25 and the wire X28, and a first interface circuit 111C is connected between the wire X27 and the wire X28. In this embodiment, the inductance L12A of the coil H1 and the inductance L12C of the coil H2 are arranged adjacent to each other and correspondingly, and are used for decoupling between the coil H1 and the coil H2. Specifically, decoupling is achieved by adaptively adjusting the overlapping area of ​​the inductance coils between the inductance L12A and the inductance L12C. The second interface circuit 121C includes: an input terminal IN1C, an input terminal IN2C, a capacitor C6C, a capacitor C7C, a capacitor C8C, a capacitor C9C, a capacitor C10C, a variable capacitor C1C, a variable capacitor C2C, an inductance L6C, an inductance L7C, and an inductance L8C. The input terminal IN1C is connected to a first end of the capacitor C6C, a second end of the capacitor C6C is connected to a first end of the capacitor C7C, a first end of the inductance L8C is connected to a second end of the capacitor C7C, a second end of the inductance L8C is connected to a first end of the capacitor C6C, a first end of the capacitor C8C is connected to a second end of the capacitor C7C, and a second end of the capacitor C8C is connected to a first end of the capacitor C9C. The second end of capacitor C9C is connected to the first end of capacitor C10C, the second end of capacitor C10C is connected to input terminal IN2C, the first end of inductor L2C is connected to the second end of capacitor C6C, the second end of inductor L2C is connected to the second end of capacitor C10C, the first end of inductor L3C is connected to the first end of capacitor C9C, the second end of inductor L3C is connected to the second end of capacitor C10C, the first end of variable capacitor C1C is connected to the first end of capacitor C8C, the second end of variable capacitor C1C is connected to the second end of capacitor C8C, the first end of variable capacitor C2C is connected to the first end of capacitor C8C, and the second end of variable capacitor C2C is connected to the second end of capacitor C8C.The second detuning circuit 122C includes: a capacitor C11C, a capacitor C12C, a capacitor C13C, a capacitor C14C, an inductor L9C, an inductor L10C, an inductor L11C, an inductor L12C, a diode D4C, a diode D5C and a diode D6C, wherein a first end of the inductor L11C is connected to a first end of the capacitor C11C, a second end of the inductor L11C is connected to a cathode of the diode D4C, an anode of the diode D5C is connected to a second end of the capacitor C11C, a second end of the capacitor C12C is connected to a first end of the capacitor C11C, a first end of the capacitor C12C is connected to a second end of the capacitor C13C, and the diodes D6C and D7C are connected to each other. The positive electrode of diode D5C is connected to the second end of capacitor C12C, the negative electrode of diode D5C is connected to the second end of inductor L9C, the first end of inductor L9C is connected to the first end of capacitor C13C, the second end of capacitor C14C is connected to the first end of capacitor C12C, the positive electrode of diode D6C is connected to the second end of capacitor C14C, the negative electrode of diode D6C is connected to the second end of inductor L10C, the first end of inductor L10C is connected to the first end of capacitor C14C, the first end of inductor L12C is connected to the second end of capacitor C13C, and the second end of inductor L12C is connected to the first end of capacitor C14C.

[0050] See also Fig.13 , Fig.13: is a circuit diagram of the coil F2 in this embodiment, wherein the wire X29, wire X30, wire X31 and wire X32 of the coil F2 form a rectangular plus a raised structure, the wire X30, wire X31 and wire X32 are L-shaped wires, the wire X29 includes a Z-shaped wire and an L-shaped wire, a raised structure is formed between the Z-shaped wire and the L-shaped wire for connecting the inductor L12D, a secondary detuning circuit consisting of an inductor L11D, a diode D4D and a capacitor C11D is connected between the wire X30 and the wire X31, a secondary detuning circuit consisting of an inductor L9D, a diode D5D, a capacitor C12D and a capacitor C13D is connected between the wire X29 and the wire X30, a secondary detuning circuit consisting of an inductor L10D, a diode D6D and a capacitor C14D is connected between the wire X29 and the wire X32, and a first interface circuit 111D is connected between the wire X31 and the wire X32. In this embodiment, the inductance L12B of the coil F1 and the inductance L12D of the coil F2 are arranged adjacent to each other and correspondingly, and are used for decoupling between the coils F1 and F2. Specifically, decoupling is achieved by adaptively adjusting the overlapping area of ​​the inductance coils between the inductance L12B and the inductance L12C. The second interface circuit 121D includes: an input terminal IN1D, an input terminal IN2D, a capacitor C6D, a capacitor C7D, a capacitor C8D, a capacitor C9D, a capacitor C10D, a variable capacitor C1D, a variable capacitor C2D, an inductance L6D, an inductance L7D, and an inductance L8D. The input terminal IN1D is connected to a first end of the capacitor C6D, a second end of the capacitor C6D is connected to a first end of the capacitor C7D, a first end of the inductance L8D is connected to a second end of the capacitor C7D, a second end of the inductance L8D is connected to a first end of the capacitor C6D, a first end of the capacitor C8D is connected to a second end of the capacitor C7D, and a second end of the capacitor C8D is connected to a first end of the capacitor C9D. The second end of capacitor C9D is connected to the first end of capacitor C10D, the second end of capacitor C10D is connected to input terminal IN2D, the first end of inductor L2D is connected to the second end of capacitor C6D, the second end of inductor L2D is connected to the second end of capacitor C10D, the first end of inductor L3D is connected to the first end of capacitor C9D, the second end of inductor L3D is connected to the second end of capacitor C10D, the first end of variable capacitor C1D is connected to the first end of capacitor C8D, the second end of variable capacitor C1D is connected to the second end of capacitor C8D, the first end of variable capacitor C2D is connected to the first end of capacitor C8D, and the second end of variable capacitor C2D is connected to the second end of capacitor C8D.The second detuning circuit 122D includes: a capacitor C11D, a capacitor C12D, a capacitor C13D, a capacitor C14D, an inductor L9D, an inductor L10D, an inductor L11D, an inductor L12D, a diode D4D, a diode D5D and a diode D6D, wherein a first end of the inductor L11D is connected to a first end of the capacitor C11D, a second end of the inductor L11D is connected to a cathode of the diode D4D, an anode of the diode D5D is connected to a second end of the capacitor C11D, a second end of the capacitor C12D is connected to a first end of the capacitor C11D, a first end of the capacitor C12D is connected to a second end of the capacitor C13D, and the diodes D6D and D7D are connected to each other. The anode of diode D5D is connected to the second end of capacitor C12D, the cathode of diode D5D is connected to the second end of inductor L9D, the first end of inductor L9D is connected to the first end of capacitor C13D, the second end of capacitor C14D is connected to the first end of capacitor C12D, the anode of diode D6D is connected to the second end of capacitor C14D, the cathode of diode D6D is connected to the second end of inductor L10D, the first end of inductor L10D is connected to the first end of capacitor C14D, the first end of inductor L12D is connected to the second end of capacitor C13D, and the second end of inductor L12D is connected to the first end of capacitor C14D.

[0051] In this embodiment, the nuclear magnetic test signal is input into the second interface module through the input terminal IN1 and the input terminal IN2, and the working state of the H and F coils is controlled respectively through the first detuning circuit 112 to reduce the residual interference and shielding effect caused by the copper components in other array loops. By designing multiple independent detuning circuits to control the working state of each nuclide coil respectively, the interference between the nuclides of the inner and outer coils is reduced. When the Na array and the H / F double-tuned array work at the same time, the P array is detuned. When the P array works, the Na array and the H / F double-tuned array are detuned to reduce the electromagnetic interference between the P and H / F / N arrays. And in order to decouple the P and H / F / Na arrays, three active detuning circuits are inserted in each loop of the array to reduce the residual interference and shielding effect caused by the copper components in other array loops. In this embodiment, the value of each element in each coil can be adjusted according to the actual situation, and is not limited in this embodiment.

[0052] The front-end module 2 is connected to the coil module 1 and is used to generate nuclear magnetic test signals and collect induction signals.

[0053] In this embodiment, the front-end module 2 is connected to an external RF signal generator, and by inputting a nuclear magnetic resonance test signal and using, for example, an orthogonal coupler to phase-device the nuclear magnetic resonance test signal, the nuclear magnetic resonance test signal is split into multiple RF signals with different phases, and multiple radionuclide signals can be emitted simultaneously or at different times to achieve the effect of nuclear magnetic resonance imaging.

[0054] The present embodiment discloses a quad-core radio frequency coil circuit, comprising: a coil module, the coil module is used to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal; a front-end module, the front-end module is connected to the coil module, and is used to generate the nuclear magnetic test signal and collect the induction signal. A quad-core radio frequency coil circuit disclosed in an embodiment of the present invention, through a double-layer nested structure combination design, can emit multiple nuclide signals simultaneously or at different times for nuclear magnetic resonance imaging on the basis of a high degree of coordination with multi-frequency multi-channel electronics and timing control systems, solves the problems of interaction between different nuclides and electromagnetic interference, and realizes multi-channel multi-frequency high-uniformity radio frequency excitation and high-sensitivity signal acquisition.

[0055] Embodiment 2

[0056] This embodiment describes the structure of the front-end module in detail based on the first embodiment. Fig.14 2 is a circuit diagram of a front-end module in the second embodiment. The front-end module 2 includes a power division module 21 and a signal driving module 22 .

[0057] The power division module 21 is connected to the signal driving module 22 , and the power division module 21 is used to split the nuclear magnetic test signal into multiple test signals.

[0058] In this embodiment, the power division module 21 includes three 1:2 power dividers 211, 212 and 213. The input end of the power division module 21 is used to connect an external signal generator, and the external input high-power output signal is divided into 4 signals by three 1:2 distributors, and each signal corresponds to a different coil unit in the coil module 1. The power division module 21 cooperates to realize the amplitude and phase control of each channel excitation source, and separates the 4 signals to finally realize the amplitude change and phase modulation of each channel excitation source.

[0059] The signal driving module 22 is connected to the coil module 1 , and is used to input multi-channel test signals into the coil module 1 .

[0060] In this embodiment, four signal driving modules 22 are connected to four signals generated by the power division module 21, and three radio frequency traps (radio frequency trap 221, radio frequency trap 222 and radio frequency trap 223) of different frequencies are connected to the coaxial cable of each coil. The radio frequency trap corresponding to the working frequency of the coil is connected at a position close to the coil direction, and the other two are connected after the radio frequency trap. The test signal is input into the coil module 1 through the output terminal 1, and the weak magnetic resonance voltage signal received from the coil is amplified by the amplifier 224, and the signal is divided into two paths through the bridge 225, and transmitted to the spectrometer through the bed to complete the image reconstruction and display the nuclear magnetic resonance imaging results.

[0061] See also Fig.15 , Fig.15 The circuit diagram of a quad-core radio frequency coil circuit in this embodiment is shown in FIG. 1 . The first coil array 11 is connected to four signal driving modules 22A, 22B, 22C and 22D, and the four signal driving modules 22A, 22B, 22C and 22D are connected to the power division module 21E, and the power division module 21E is connected to the external signal input terminal. The first coil array 12 is connected to four signal driving modules 22F, 22G, 22H and 22I, and the four signal driving modules 22F, 22G, 22H and 22I are connected to the power division module 21J, and the power division module 21J is connected to the external signal input terminal. The signal input terminal is divided into a plurality of signals with different phase differences by inputting a preset nuclear magnetic signal through the power division module and inputted into the first coil array 11 and the second coil array 12. The signal is inputted into an external display device through the detected feedback signal, and the nuclear magnetic detection result can be observed. In an alternative embodiment, the first coil array and the second coil array may not be connected to the same signal input terminal, and can be selected according to the actual application.

[0062] The present embodiment discloses a quad-core radio frequency coil circuit, comprising: a coil module, the coil module is used to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal; a front-end module, the front-end module is connected to the coil module, and is used to generate the nuclear magnetic test signal and collect the induction signal. A quad-core radio frequency coil circuit disclosed in an embodiment of the present invention, through a double-layer nested structure combination design, can emit multiple nuclide signals simultaneously or at different times for nuclear magnetic resonance imaging on the basis of a high degree of coordination with multi-frequency multi-channel electronics and timing control systems, solves the problems of interaction between different nuclides and electromagnetic interference, and realizes multi-channel multi-frequency high-uniformity radio frequency excitation and high-sensitivity signal acquisition.

[0063] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A quad-core radio frequency coil circuit, characterized in that: include: A coil module, the coil module is used to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal; A front-end module, which is connected to the coil module and is used to generate the nuclear magnetic test signal and collect the induction signal; The coil module comprises a first coil array and a second coil array, wherein the center positions of the first coil array and the second coil array coincide with each other; The first coil array includes a plurality of first coil units, which are arranged in a superimposed manner based on a first preset phase difference, and the second coil array includes a plurality of second coil units, which are arranged in a superimposed manner based on a second preset phase difference; The first coil unit includes a Na coil and a P coil; the second coil unit includes an H coil and an F coil; the center line of the Na coil perpendicular to the plane where the Na coil is located is 45° away from the center line of the F coil perpendicular to the plane where the F coil is located; The first coil unit comprises: a first interface circuit and a first detuning circuit, the first detuning circuit is connected to the first interface circuit, and the first interface circuit is connected to the front-end module; The first detuning circuit includes: an inductor L2, an inductor L3, an inductor L4, an inductor L5, a capacitor C3, a capacitor C4, a capacitor C5, a diode D1, a diode D2 and a diode D3, wherein a first end of the inductor L2 is connected to a first end of the capacitor C3, a second end of the inductor L2 is connected to a cathode of the diode D1, an anode of the diode D2 is connected to a second end of the capacitor C3, a second end of the capacitor C4 is connected to a first end of the capacitor C3, an anode of the diode D2 is connected to a second end of the capacitor C4, a cathode of the diode D2 is connected to a second end of the inductor L3, a first end of the inductor L3 is connected to a first end of the capacitor C4, an anode of the diode D3 is connected to a second end of the capacitor C5, a cathode of the diode D3 is connected to a second end of the inductor L4, a first end of the inductor L4 is connected to a first end of the capacitor C5, a first end of the capacitor L5 is connected to a second end of the capacitor C5, and a second end of the inductor L5 is connected to a second end of the capacitor C4.

2. A quad-core radio frequency coil circuit according to claim 1, characterized in that: The first interface circuit includes: an input terminal IN1, an input terminal IN2, a capacitor C1, a capacitor C2 and an inductor L1, the input terminal IN1 is connected to the first end of the capacitor C1, the second end of the capacitor C1 is connected to the first end of the capacitor C2, the second end of the capacitor C2 is connected to the first end of the inductor L1, the second end of the inductor L1 is connected to the first end of the capacitor C2, and the input terminal IN2 is connected to the second end of the capacitor C1.

3. A quad-core radio frequency coil circuit according to claim 1, characterized in that: The second coil unit includes: a second interface circuit and a second detuning circuit, the second detuning circuit is connected to the second interface circuit, and the second interface circuit is connected to the front-end module.

4. A quad-core radio frequency coil circuit according to claim 3, characterized in that: The second interface circuit includes: an input terminal IN1, an input terminal IN2, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a variable capacitor B1, a variable capacitor B2, an inductor L6, an inductor L7 and an inductor L8, wherein the input terminal IN1 is connected to a first end of the capacitor C6, a second end of the capacitor C6 is connected to a first end of the capacitor C7, a first end of the inductor L8 is connected to a second end of the capacitor C7, a second end of the inductor L8 is connected to a first end of the capacitor C6, a first end of the capacitor C8 is connected to a second end of the capacitor C7, a second end of the capacitor C8 is connected to a first end of the capacitor C9, and a second end of the capacitor C9 is connected to a connected to the first end of the capacitor C10, the second end of the capacitor C10 is connected to the input terminal IN2, the first end of the inductor L7 is connected to the second end of the capacitor C6, the second end of the inductor L2 is connected to the second end of the capacitor C10, the first end of the inductor L6 is connected to the first end of the capacitor C9, the second end of the inductor L6 is connected to the second end of the capacitor C10, the first end of the variable capacitor B1 is connected to the first end of the capacitor C8, the second end of the variable capacitor B1 is connected to the second end of the capacitor C8, the first end of the variable capacitor B2 is connected to the first end of the capacitor C8, and the second end of the variable capacitor B2 is connected to the second end of the capacitor C8.

5. A quad-core radio frequency coil circuit according to claim 3, characterized in that: The second detuning circuit includes: a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, an inductor L9, an inductor L10, an inductor L11, an inductor L12, a diode D4, a diode D5 and a diode D6, wherein a first end of the inductor L11 is connected to a first end of the capacitor C11, a second end of the inductor L11 is connected to a cathode of the diode D4, an anode of the diode D5 is connected to a second end of the capacitor C11, a second end of the capacitor C12 is connected to a first end of the capacitor C11, a first end of the capacitor C12 is connected to a second end of the capacitor C13, and an anode of the diode D5 is connected to to the second end of the capacitor C12, the cathode of the diode D5 is connected to the second end of the inductor L9, the first end of the inductor L9 is connected to the first end of the capacitor C13, the second end of the capacitor C14 is connected to the first end of the capacitor C12, the anode of the diode D6 is connected to the second end of the capacitor C14, the cathode of the diode D6 is connected to the second end of the inductor L10, the first end of the inductor L10 is connected to the first end of the capacitor C14, the first end of the inductor L12 is connected to the second end of the capacitor C13, and the second end of the inductor L12 is connected to the first end of the capacitor C14.

6. The quad-core radio frequency coil circuit according to claim 1, characterized in that: The front-end module includes: a power division module and a signal driving module, the power division module is connected to the signal driving module, the signal driving module is connected to the coil module, the power division module is used to split the nuclear magnetic resonance test signal into multiple test signals, and the signal driving module is used to input the multiple test signals into the coil module.

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