Device comprising an electronic circuit for controlling signal gain

Abstract

The present disclosure relates to a device including an electronic circuit for controlling a gain of a signal, the device including: a path unit configured to form a first impedance for controlling the gain of an input signal. The device also includes a shunt unit configured to form a second impedance for attenuation between the path unit and ground, wherein the path unit uses an on-resistance of at least one transistor to form the first impedance.

Description

Technical Field

[0001] The present disclosure relates to electronic circuits, and more particularly to an apparatus including an electronic circuit for controlling the gain of a signal. Background Art

[0002] In various electronic circuits that process radio frequency (RF), it is necessary to control the gain of a signal for various purposes. For example, a device that performs communication may need to control the gain in order to perform efficient signal processing in the device or to efficiently transmit a signal to the outside.

[0003] A circuit that controls the gain of a signal is called an attenuator. Depending on the detailed circuit design, an attenuator can have a gain control range and can have limited linearity. Since an attenuator has a large gain range and high linearity, its utilization can be increased.

[0004] The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with respect to the present disclosure. Summary of the invention

[0005] An aspect of the present disclosure is to provide an apparatus including an electronic circuit configured to effectively control a gain of a signal.

[0006] An aspect of the present disclosure is to provide a device including an electronic circuit implementing an attenuator having a wide gain control range and high linearity.

[0007] According to one aspect of the present disclosure, a device including an electronic circuit may include: a path unit, which is configured to form a first impedance for controlling the gain of an input signal; and a shunt unit, which is configured to form a second impedance to attenuate between the path unit and ground, and the path unit may use the on-resistance of at least one transistor to form the first impedance.

[0008] According to an aspect of the present disclosure, the device may include an attenuation enabling unit, which is configured to turn on or off the path between the path unit and the shunt unit, and if the electronic circuit attenuates the gain of the input signal, the attenuation enabling unit may turn on the path.

[0009] According to an aspect of the present disclosure, the path unit may include a plurality of paths forming different impedance values, and each of the plurality of paths may include at least one transistor serving as a switch.

[0010] According to an aspect of the present disclosure, at least one transistor included in a first path among the multiple paths corresponding to a gain change of the input signal is turned on, and at least one transistor included in at least one path remaining after excluding the first path from the multiple paths is turned off.

[0011] According to an aspect of the present disclosure, the plurality of paths may include a through path providing minimal gain variation, and the through path may include a transistor and an inductor connected in parallel.

[0012] According to an aspect of the present disclosure, at least one path among the plurality of paths may include a plurality of transistors connected in a stack structure.

[0013] According to an aspect of the present disclosure, the device may further include: an input matching unit connected to an input end of the input signal; and the input matching unit may include at least one inductor for performing compensation related to parasitic capacitance of the at least one transistor.

[0014] According to an aspect of the present disclosure, the at least one transistor may be controlled to be in a reverse biased state.

[0015] According to the apparatus of various embodiments, an attenuator is implemented using the on-resistance of a transistor, and a small circuit size and a low voltage volume temperature (PVT) variation can be ensured.

[0016] Effects obtainable by the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

[0017] Before proceeding to the following detailed description, it may be helpful to set forth the definitions of certain words and phrases used throughout the patent document: the terms "include" and "comprising" and their derivatives are intended to include without limitation; the term "or" is inclusive, meaning and / or; the phrases "associated with" and "associated with" and their derivatives may mean including, included therein, interconnected therewith, containing, contained therein, connected therewith, coupled therewith, communicable therewith, cooperating with, intertwined, juxtaposed, adjacent to, constrained or bound therewith, having, having the property of, etc.; the term "controller" refers to any device, system, or part thereof that controls at least one operation, such device may be implemented in hardware, firmware, or software, or some combination of at least two of them. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether local or remote.

[0018] In addition, the various functions described below can be implemented or supported by one or more computer programs, each of which is formed by a computer-readable program code and embedded in a computer-readable medium. The terms "application" and "program" refer to one or more computer programs, software components, instruction sets, processes, functions, objects, classes, instances, related data or a part thereof, which are suitable for implementation in a suitable computer-readable program code. The phrase "computer-readable program code" includes any type of computer code, including source code, object code and executable code. The phrase "computer-readable medium" includes any type of medium that can be accessed by a computer, such as a read-only memory (ROM), a random access memory (RAM), a hard drive, a compact disc (CD), a digital video disc (DVD) or any other type of memory. "Non-transitory" computer-readable media does not include wired, wireless, optical or other communication links that transmit instantaneous electrical signals or other signals. Non-transitory computer-readable media include media that can permanently store data and media that can store data and overwrite data later, such as rewritable optical discs or erasable storage devices.

[0019] Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0021] Figure 1 shows a diagram of an electronic circuit for controlling gain according to various embodiments;

[0022] Figure 2 A diagram showing a configuration of a gain control circuit according to various embodiments;

[0023] Figure 3A A diagram showing a configuration of a path unit of a gain control circuit according to various embodiments;

[0024] Figure 3B A diagram showing an example of an implementation of a path unit of a gain control circuit according to various embodiments;

[0025] Figure 4A A diagram showing an example of an implementation of a through path of a gain control circuit according to various embodiments; Figure 4B A diagram showing an implementation of a through path of a gain control circuit according to various embodiments; Figure 4CA diagram showing an example of an implementation of a through path of a gain control circuit according to various embodiments;

[0026] Figure 5A shows a graph comparing the performance of examples of implementations of a through path of a gain control circuit according to various embodiments; Figure 5B shows a graph comparing the performance of examples of implementations of a through path of a gain control circuit according to various embodiments;

[0027] Fig. 6A A diagram showing an example of implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments; Figure 6B A diagram showing an example of implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments; and Figure 6C A diagram showing an example of implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments;

[0028] Fig. 7A A diagram showing characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments; Figure 7B A diagram showing characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments; Figure 7C A diagram showing characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments;

[0029] Figure 8 A diagram showing an example of an implementation of an attenuation enabling unit of a gain control circuit according to various embodiments;

[0030] Fig. 9A A diagram showing a configuration of a shunt unit of a gain control circuit according to various embodiments;

[0031] Fig. 9B A diagram showing an example of an implementation of a shunt unit of a gain control circuit according to various embodiments;

[0032] Fig. 10A A diagram showing a reverse bias state of a transistor caused by a bias providing unit in a gain control circuit according to various embodiments; Fig. 10B A diagram showing a reverse bias state of a transistor caused by a bias providing unit in a gain control circuit according to various embodiments;

[0033] Fig.11 A diagram showing an example of an implementation of a gain control circuit according to various embodiments; and

[0034] Fig. 12A a graph illustrating performance of a gain control circuit according to various embodiments; and Fig. 12B is a graph of performance of a gain control circuit according to various embodiments. DETAILED DESCRIPTION

[0035] Discussed below Figures 1 to 12B The various embodiments used to describe the principles of the present disclosure in this patent document are exemplary only and should not be interpreted in any way to limit the scope of the present disclosure. Those skilled in the art will understand that the principles of the present disclosure can be implemented in any appropriately arranged system or device.

[0036] The terms used in the present disclosure are only used to describe specific embodiments, and are not intended to limit the present disclosure. Unless defined differently in context, singular expressions may include plural expressions. Unless otherwise defined, all terms used herein (including technical terms and scientific terms) have the same meaning as the meanings commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in common dictionaries may be interpreted as having the same meaning as the contextual meanings in the relevant technical field, and should not be interpreted as having ideal or overly formal meanings, unless clearly defined in the present disclosure. In some cases, even the terms defined in the present disclosure should not be interpreted as excluding embodiments of the present disclosure.

[0037] Hereinafter, various embodiments of the present disclosure will be described based on a hardware method. However, various embodiments of the present disclosure include techniques using both hardware and software, and thus various embodiments of the present disclosure may not exclude the viewpoint of software.

[0038] In the following, the present disclosure relates to an apparatus comprising an electronic circuit for controlling the gain of a signal. In particular, the present disclosure relates to the implementation of an attenuator and describes the structure of a circuit of an attenuator implemented using the on-resistance of a transistor.

[0039] Hereinafter, for the convenience of description, terms for indicating signals, terms for materials, terms for structures, terms for shapes, etc. are used. Therefore, the present disclosure is not limited to the terms used in the specification, and other terms having the same technical meaning may be used.

[0040] Figure 1 Schematic diagram of an electronic circuit for controlling gain according to various embodiments is shown. Figure 1 , the electronic circuit includes a gain control circuit 110 and a controller 120 .

[0041] The gain control circuit 110 may include an input terminal (IN) and an output terminal (OUT), and may control (e.g., increase, decrease, or maintain) the gain of a signal input via the input terminal (IN) and output a signal whose gain is controlled via the output terminal (OUT). The signal may include a radio frequency (RF) signal.

[0042] The controller 120 may control the operation of the gain control circuit 110. The controller 120 may determine the change in gain to be controlled by the gain control circuit 110 according to the amplitude of the desired output signal, and may generate and output a signal for controlling the operation of the gain control circuit 110. According to an embodiment, the controller 120 may convert the desired gain change value into a control signal for directly controlling an element in the gain control circuit 110. To this end, the controller 120 may include at least one of the following: a processor, a microprocessor, a microcontroller, a memory, and a control signal generating circuit.

[0043] Figure 2 FIG. 1 is a diagram showing a configuration of a gain control circuit according to various embodiments. Figure 2 The gain control circuit 110 may include a path unit 210 , an input matching unit 220 a , an output matching unit 220 b , an attenuation enabling unit 230 , a shunt unit 240 , and a bias providing unit 250 .

[0044] The path unit 210 may form an impedance for controlling the gain of a signal. According to various embodiments, the path unit 210 may include at least one element that forms a resistance and at least one element that performs a switch. For example, the path unit 210 may include at least one transistor, and may perform a switch by controlling a voltage applied to a gate terminal of the transistor, and may form a resistance using an on-resistance of the transistor. Here, the on-resistance represents the resistance of the transistor itself determined by the length and width of the transistor. As the attenuation amount of the signal gain increases, the path unit 210 may form a greater impedance.

[0045] The input matching unit 220a may form the input impedance of the gain control circuit 110, and the output matching unit 220b may form the output impedance of the gain control circuit 110. The input matching unit 220a and the output matching unit 220b may form an input / output impedance of a predetermined size (e.g., 50Ω). The input matching unit 220a and the output matching unit 220b may include at least one element (e.g., an inductor or a capacitor) selected based on the characteristics of another element (e.g., the path unit 210, etc.). According to an embodiment, the input matching unit 220a and the output matching unit 220b may be excluded.

[0046] The attenuation enabling unit 230 may selectively connect the path unit 210 and the shunt unit 240. If the gain control circuit 110 performs attenuation, the attenuation enabling unit 230 may connect the path unit 210 and the shunt unit 240. On the contrary, if the gain control circuit 110 passes the signal without performing attenuation, the attenuation enabling unit 230 may open the path between the path unit 210 and the shunt unit 240. To this end, the attenuation enabling unit 230 may include at least one switch.

[0047] When the gain control circuit 110 performs attenuation, the shunt unit 240 can form the required impedance and additional path. According to various embodiments, the shunt unit 240 may include at least one element that forms a resistance and at least one element that performs a switch. For example, the path unit 210 may include at least one transistor, and the switch may be performed by controlling the voltage applied to the gate terminal of the transistor, and the resistance may be formed using the on-resistance of the transistor. As the attenuation amount of the signal gain increases, the shunt unit 240 may form a larger impedance.

[0048] The bias providing unit 250 may provide a bias voltage to enable a transistor included in at least one of the path unit 210, the attenuation enabling unit 230, and the shunt unit 240 to operate in a reverse bias state. The bias providing unit 250 may provide a voltage of a predetermined magnitude to a source terminal and a drain terminal to increase the linearity of the transistor in a cut-off state. To this end, the bias providing unit 250 may include at least one voltage source.

[0049] Figure 3A FIG. 1 is a diagram showing a configuration of a path unit of a gain control circuit according to various embodiments. Figure 3A , the path unit 210 may include a through path 310 and a plurality of attenuation paths 320 - 1 to 320 -N.

[0050] The through path 310 is a path through which a signal flows when the change in gain is minimal. The through path 310 may form an impedance value smaller than the impedance value of each of the plurality of attenuation paths 320-1 to 320-N. The plurality of attenuation paths 320-1 to 320-N are paths for providing different gain changes and may form different impedance values.

[0051] The on-resistance of the transistors may be used to form the impedance value in each of the through path 310 and the plurality of attenuation paths 320-1 to 320-N. Therefore, the through path 310 and each of the plurality of attenuation paths 320-1 to 320-N may include a set of transistors, the number and size of which are different from each other. The through path 310 and the plurality of attenuation paths 320-1 to 320-N may be as follows: Figure 3B Implementation shown.

[0052] Figure 3B FIG. 2 is a diagram showing an example of an implementation of a path unit of a gain control circuit according to various embodiments. The path unit 210 may be as follows: Figure 3B In this case, Figure 3B The implementation examples do not limit the present disclosure, and the path unit 210 may be variously implemented. Figure 3B The case where one straight-through path and four attenuation paths are implemented is shown.

[0053] Reference Figure 3B , the through path 310 may include a transistor 311 and an inductor 312. The transistor 311 may be used as a switch, and the on-resistance of the transistor 311 and the inductance of the inductor 312 may form the impedance of the through path 310. One end of the inductor 312 is connected to the drain terminal of the transistor 311, and the other end of the inductor 312 is connected to the source terminal of the transistor 311. As a switch, the on / off of the transistor 311 may be controlled according to a control signal provided to a gate terminal.

[0054] The first attenuation path 320-1 may form an impedance value greater than the impedance value of the through path 310 and smaller than the impedance values ​​of the second attenuation path 320-2, the third attenuation path 320-3, and the fourth attenuation path 320-4. The first attenuation path 320-1 may include a transistor 321. The on-resistance value of the transistor 321 may be greater than the on-resistance of the transistor 311. To this end, the width or length of the transistor 321 may be smaller than the width or length of the transistor 311.

[0055] The second attenuation path 320-2 may form an impedance value greater than the impedance values ​​of the through path 310 and the first attenuation path 320-1, and less than the impedance values ​​of the third attenuation path 320-3 and the fourth attenuation path 320-4. The second attenuation path 320-2 may include a transistor 322 and a transistor 323 connected (stacked) in a stack structure. The sum of the on-resistance values ​​of the transistor 322 and the transistor 323 may be greater than the on-resistance value of the transistor 321.

[0056] The third attenuation path 320-3 may form an impedance value greater than the impedance values ​​of the through path 310, the first attenuation path 320-1, and the second attenuation path 320-2, and less than the impedance value of the fourth attenuation path 320-4. The third attenuation path 320-3 may include a transistor 324, a transistor 325, and a transistor 326 connected in a stack structure. The sum of the on-resistance values ​​of the transistor 324, the transistor 325, and the transistor 326 may be greater than the sum of the on-resistance values ​​of the transistor 322 and the transistor 323.

[0057] The fourth attenuation path 320-4 may form an impedance value greater than the impedance values ​​of the through path 310, the first attenuation path 320-1, the second attenuation path 320-2, and the third attenuation path 320-3. The fourth attenuation path 320-4 may include a transistor 327, a transistor 328, and a transistor 329. The sum of the on-resistance values ​​of the transistor 327, the transistor 328, and the transistor 329 may be greater than the sum of the on-resistance values ​​of the transistor 324, the transistor 325, and the transistor 326.

[0058] In such Figure 3B In the structure shown, the transistors included in the same path can be controlled to be turned on / off equivalently. If one of the multiple paths 310, 320-1, 320-2, 320-3 and 320-4 is turned on and the remaining paths are turned off, the signal flows in a single path in the on state, and the gain of the signal can be attenuated according to the impedance value formed in the corresponding path. The state in which the through path 310 is turned on is called "through mode", and the state in which one of the attenuation paths 320-1, 320-2, 320-3 and 320-4 is turned on is "attenuation mode". For example, in order to apply the minimum gain change, that is, in the case of the through mode, the transistor 311 in the through path 310 is turned on and the attenuation paths 320-1 to 320-4 are disconnected. In order to disconnect the attenuation paths 320-1 to 320-4, the transistor 321 in the first attenuation path 320-1 can be turned off, at least one or all of the transistors 322 and 323 in the second attenuation path 320-2 can be turned off, at least one or all of the transistors 324 and 326 in the third attenuation path 320-3 can be turned off, and at least one or all of the transistors 327 and 329 in the fourth attenuation path 320-4 can be turned off.

[0059] According to an embodiment, the path unit 210 may be as follows Figure 3B is implemented as shown. Figure 3B In the example of FIG. 3 , the through path 310 may include a single transistor and a single inductor. According to another embodiment, the through path 310 may be as follows: Figure 4A , Figure 4B or Figure 4C Implemented as shown.

[0060] Figure 4A A diagram showing an example of an implementation of a through path of a gain control circuit according to various embodiments; Figure 4B A diagram showing an example of an implementation of a through path of a gain control circuit according to various embodiments; and Figure 4C 1 is a diagram showing an example of an implementation of a through path of a gain control circuit according to various embodiments. The through path 310 may be as follows: Figure 4A , Figure 4B or Figure 4C In this case, Figure 4A , Figure 4B or Figure 4C The examples of implementations may not limit the present disclosure, and the through path 310 may be implemented differently.

[0061] According to the embodiment, Figure 4A As shown, the through path 310 may be configured with a transistor 411 .

[0062] According to another embodiment, Figure 4B As shown, the through path 310 may be configured with two transistors 421 and 422 connected in a stack structure, and a transistor 423 connected to a node for connecting the two transistors 421 and 422 through a drain terminal.

[0063] According to yet another embodiment, Figure 4C As shown, the through path 310 may be configured with a transistor 431 and an inductor 432 connected in parallel. Here, the inductor 432 may be used to eliminate the parasitic capacitance caused by the transistor 431.

[0064] According to Figure 4A , Figure 4B or Figure 4C According to the structure of the through path 310 implemented as shown, the minimum attenuation and the maximum attenuation of the gain control circuit 110 can be different. For example, as the width of the transistor included in the through path 310 becomes wider, the minimum attenuation becomes lower. As the width of the transistor becomes narrower, Figure 4A and Figure 4B The maximum attenuation of the two implementation examples shown in becomes higher. As the width of the transistor becomes narrower, Figure 4C The maximum attenuation of the implementation example shown in FIG. Figure 4A , Figure 4B or Figure 4C The minimum attenuation of the three examples of implementation shown is as follows Figure 5A As shown, and its maximum attenuation is Figure 5B shown.

[0065] Figure 5A shows a graph comparing the performance of examples of implementations of a through path of a gain control circuit according to various embodiments; and Figure 5B A graph is shown comparing the performance of examples of implementations of a through path of a gain control circuit according to various embodiments. Figure 5A and Figure 5B Three examples of implementation are involved, Figure 5A shows the minimum attenuation according to the width of the transistor, Figure 5B The maximum attenuation according to the width of the transistor is shown. Figure 5A , Figure 4CThe implementation of can provide the lowest minimum attenuation. In addition, refer to Figure 5B , Figure 4C The implementation of can provide the highest maximum attenuation within a predetermined width (e.g., 192 μm). Therefore, it can be understood that Figure 4C However, depending on the purpose of the implementation, the through path 310 can be as follows Figure 4A , Figure 4B or Figure 4C It may be implemented as shown, or may be implemented in another structure.

[0066] Fig. 6A A diagram showing an example of implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments; Figure 6B A diagram showing an example of implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments; and Figure 6C 220a and the output matching unit 220b may be implemented as follows: Fig. 6A , Figure 6B or Figure 6C In this case, Fig. 6A , Figure 6B or Figure 6C The implementation examples may not limit the present disclosure, and the input matching unit 220a and the output matching unit 220b may be implemented differently.

[0067] According to an embodiment, the input matching unit 220a and the output matching unit 220b may be omitted. Fig. 6A shown.

[0068] According to another embodiment, Figure 6B As shown, the input matching unit 220a and the output matching unit 220b may be configured with an inductor 621a or an inductor 621b connected in parallel. Figure 6B , one end of the input matching unit 220a is connected to the input end of the path unit 210, and the other end includes a grounding inductor 621a. One end of the output matching unit 220b is connected to the input end of the path unit 210, and the other end includes a grounding inductor 621b. Inductors 621a and 621b can be used to perform compensation associated with parasitic capacitance caused by transistors included in the path unit 210.

[0069] According to yet another embodiment, Figure 6CAs shown, the input matching unit 220a and the output matching unit 220b can be configured with an inductor 631a or 631b connected in parallel, a capacitor 632a or 632b connected in parallel, and a switch 633a or 633b connected to the capacitor 632a or 632b. The inductors 631a and 631b can be used to perform compensation associated with parasitic capacitance caused by the transistor included in the path unit 210. The capacitors 632a and 632b can be used to compensate for the difference in parasitic capacitance between the on state and the off state of the through path 310. Therefore, the switches 633a and 633b can be controlled according to the on / off state of the through path 310. For example, when the through path 310 is turned on, the switch can be closed, and when the through path 310 is disconnected, the switch can be disconnected.

[0070] According to Fig. 6A , Figure 6B or Figure 6C The input impedance and output impedance of the input matching unit 220a and the output matching unit 220b can be different. Fig. 6A , Figure 6B or Figure 6C The input / output impedance values ​​of the implementation can be as 7A to 7C The shown are plotted on a Smith chart.

[0071] Fig. 7A A diagram showing characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments; Figure 7B A diagram showing characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments; and Figure 7C is a diagram showing characteristics of an example of implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments. 7A to 7C represents an input / output impedance value when one of the five paths of the path unit 210 is used. Fig. 7A Yes Fig. 6A An example of an input matching unit 220a and an output matching unit 220b is shown implemented. Figure 7B Yes Figure 6B An example of an input matching unit 220a and an output matching unit 220b is shown implemented. Figure 7C Yes Figure 6C An example of an input matching unit 220a and an output matching unit 220b is shown. 7A to 7C , when Fig. 6A When compared with the implementation of Figure 6B or Figure 6C The implementation can provide an impedance value closer to 50Ω.

[0072] Figure 8 2 is a diagram showing an example of an implementation of an attenuation enabling unit of a gain control circuit according to various embodiments. The attenuation enabling unit 230 may be as follows: Figure 8 In this case, Figure 8 The implementation examples do not limit the present disclosure, and the decay enabling unit 230 may be variously implemented.

[0073] Reference Figure 8 , the attenuation enabling unit 230 may have a structure in which a first portion 230a and a second portion 230b are connected in parallel. The first portion 230a includes transistors 801a, 802a, and 803a connected in a stacked structure, and the second portion 230b includes transistors 801b, 802b, and 803b connected in a stacked structure. If the gain control circuit 110 does not perform attenuation, that is, if the through path 310 is turned on, at least one or all of the transistors 801a, 802a, and 803a included in the first portion 230a are turned off, and at least one or all of the transistors 801b, 802b, and 803b included in the second portion 230b are turned off. In contrast, if the gain control circuit 110 performs attenuation, that is, if one of the attenuation paths 320-1 to 320-N is turned on, the transistors 801a, 802a, and 803a included in the first portion 230a are turned on, and the transistors 801b, 802b, and 803b included in the second portion 230b are turned on.

[0074] Fig. 9A is a diagram showing a configuration of a shunt unit of a gain control circuit according to various embodiments. Fig. 9A , the diversion unit 240 includes a plurality of diversion paths 910 - 1 to 910 -N.

[0075] One end of the plurality of shunt paths 910-1 to 910-N is grounded via capacitor 920. The plurality of shunt paths 910-1 to 910-N may form different impedance values. In each of the plurality of shunt paths 910-1 to 910-N, the impedance value may be formed using the on-resistance of the transistor. An example of implementation of the plurality of shunt paths 910-1 to 910-N may be as follows: Fig. 9B shown.

[0076] Fig. 9B 1 is a diagram showing an example of an implementation of a shunt unit of a gain control circuit according to various embodiments. The shunt unit 240 may be as follows Fig. 9B In this case, Fig. 9B The implementation examples do not limit the present disclosure, and the diversion unit 240 may be variously implemented. Fig. 9B The case where four split flow paths are implemented is shown.

[0077] Reference Fig. 9B , the first shunt path 910-1 forms an impedance value greater than the impedance values ​​of the second shunt path 910-2, the third shunt path 910-3, and the fourth shunt path 910-4. The first shunt path 910-1 may include a transistor 911 and a transistor 912 connected in a stack structure. The sum of the on-resistance values ​​of the transistor 911 and the transistor 912 may be greater than the on-resistance values ​​of the other paths 910-2, 910-3, and 910-4.

[0078] The second shunt path 910-2 may form an impedance value smaller than the impedance value of the first shunt path 910-1 and greater than the impedance values ​​of the third shunt path 910-3 and the fourth shunt path 910-4. The second shunt path 910-2 may include a transistor 913 and a transistor 914 connected in a stack structure. The sum of the on-resistance values ​​of the transistor 913 and the transistor 914 may be less than the on-resistance value of the transistor 911 and the transistor 912.

[0079] The third shunt path 910-3 may form an impedance value smaller than the impedance values ​​of the first shunt path 910-1 and the second shunt path 910-2 and larger than the impedance value of the fourth shunt path 910-4. The third shunt path 910-3 may include a transistor 915. The on-resistance value of the transistor 915 is smaller than the sum of the on-resistance values ​​of the transistors 913 and 914.

[0080] The fourth shunt path 910-4 may form an impedance value smaller than the impedance values ​​of the first shunt path 910-1, the second shunt path 910-2, and the third shunt path 910-3. The fourth shunt path 910-4 may include a transistor 916. The on-resistance value of the transistor 916 may be smaller than the on-resistance value of the transistor 915.

[0081] In such Fig. 9B In the structure shown, the transistors included in the same path can be controlled to be turned on / off equivalently. For example, in order to apply the minimum gain change, that is, in the case of the through mode, at least one or all of the transistors 911 and 912 in the first shunt path 910-1 are turned off, at least one or all of the transistors 913 and 914 in the second shunt path 910-2 are turned off, the transistor 915 in the third shunt path 910-3 is turned off, and the transistor 916 in the fourth shunt path 910-4 is turned off. As another example, in the case of the attenuation mode, at least one of the first shunt path 910-1, the second shunt path 910-2, the third shunt path 910-3 and the fourth shunt path 910-4 is controlled to be in the on state.

[0082] As described in various embodiments, the on-resistance of the transistor can be used to form an impedance for attenuating the signal gain. In this case, a plurality of transistors connected in a stack structure can be used. If a plurality of transistors are connected in a stack structure, an impedance corresponding to the sum of the on-resistances of the plurality of transistors can be formed. If a single transistor with a constant on-resistance is used, a voltage difference may be generated between the source terminal and the drain terminal due to the reduction in gain. Therefore, the corresponding transistor may work abnormally, and the linearity may deteriorate. Therefore, as described in the embodiment, if a plurality of transistors are connected in a stack structure, and the transistor is turned on, the voltage difference between the source terminal and the drain terminal of each transistor is relatively low, so the linearity may be improved.

[0083] Similarly, if the transistor is turned off, a reverse bias is applied by the bias providing unit 250, and the linearity when the transistor is turned off can be improved. An example of applying a reverse bias can be as follows: Fig. 10A and Fig. 10B shown.

[0084] Fig. 10A A diagram showing a reverse bias state of a transistor caused by a bias providing unit in a gain control circuit according to various embodiments; and Fig. 10B A diagram showing a reverse bias state of a transistor caused by a bias providing unit in a gain control circuit according to various embodiments. Fig. 10A shows the transistor in the off state, while Fig. 10B The transistor is shown in the on state.

[0085] Reference Fig. 10A If V off (eg, 0 V) ​​is applied to the gate terminal of transistor 1001, transistor 1001 is turned off. Fig. 10B If V on (e.g., 1.8V) is applied to the gate terminal of transistor 1001, and transistor 1001 is turned on. In this case, V bias (e.g., 0.9V) is applied to the source and drain terminals. Since V bias , V of transistor 1001 GS -V bias , and transistor 1001 operates in a reverse biased state. Therefore, when with V bias Compared with the case of 0, V on Need to be increased V bias For example, if the gate voltage required to turn on transistor 1001 (not reverse biased) is 0.9V, then the gate voltage required to turn on transistor 1001 (reverse biased) is 0.9V. bias )The required gate voltage increases to 0.9+V bias .

[0086] Fig.11 Diagram showing an example of an implementation of a gain control circuit according to various embodiments. Fig.11 is an example of an implementation of the gain control circuit 110, and shows how Figure 3B , Figure 8 and Fig. 9B The example of the circuit in which the path unit 210, the attenuation enabling unit 230 and the shunt unit 240 are combined is shown. Fig.11 , providing multiple control signals C 0 To C 9 Each of the attenuation values ​​controls the switching operation of at least one transistor. The control signal C of the gain mode defined by the attenuation value 0 To C 9 The setting values ​​are shown in Table 1 below.

[0087] [Table 1]

[0088] Gain Mode Code <![CDATA[C 0 ]]> <![CDATA[C 1 ]]> <![CDATA[C 2 ]]> <![CDATA[C 3 ]]> <![CDATA[C 4 ]]> <![CDATA[C 5 ]]> <![CDATA[C 6 ]]> <![CDATA[C 7 ]]> <![CDATA[C 8 ]]> <![CDATA[C 9 ]]> -2 000 1 0 0 0 0 0 0 0 0 0 -5 001 0 1 0 0 0 1 1 0 0 0 -8 010 0 0 1 0 0 1 0 1 0 0 -11 011 0 0 0 1 0 1 0 0 1 0 -14 100 0 0 0 0 1 1 0 0 0 1

[0089] According to Table 1, in the mode corresponding to code 100, C 6 , C 7 and C 8 is set to 0. According to another embodiment, in the mode corresponding to code 100, C 6 , C 7 and C 8 At least one of can be set to 1.

[0090] Fig. 12A a graph illustrating performance of a gain control circuit according to various embodiments; and Fig. 12B is a graph of performance of a gain control circuit according to various embodiments. Fig. 12A and Fig. 12B An input third-order intercept point (IIP3) according to a change in the electric power of a signal input to the gain control circuit 110 is shown.

[0091] Fig. 12A A case where at least one of the path unit 210, the attenuation enabling unit 230, and the shunt unit 240 is configured with transistors connected in a stack structure is compared with a case where at least one of the path unit 210, the attenuation enabling unit 230, and the shunt unit 240 is configured with a single transistor without using a stack structure. Fig. 12A , when the stack structure is used, it is recognized that the IIP3 is relatively high. For example, if the electric power of the input signal is -30dBm, the IIP3 can be improved by about 4dB.

[0092] Fig. 12BThe case where reverse bias is used is compared to the case where reverse bias is not used. Fig. 12B , when using reverse bias, it is recognized that IIP3 is relatively high. For example, if the electric power of the input signal is -40dBm, IIP3 can be improved by about 11dB.

[0093] The methods according to the embodiments described in the claims and / or the specification of the present disclosure may be implemented in hardware, software, or a combination of hardware and software.

[0094] When the method is implemented by software, a computer-readable storage medium for storing one or more programs (software modules) may be provided. One or more programs stored in the computer-readable storage medium may be configured to be executed by one or more processors in an electronic device. At least one program may include instructions for causing an electronic device to perform the method according to the various embodiments of the present disclosure as defined by the accompanying claims and / or disclosed herein.

[0095] The program (software module or software) can be stored in a non-volatile memory, which includes random access memory and flash memory, read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic disk storage device, compact disk-ROM (CD-ROM), digital versatile disk (DVD) or other types of optical storage devices or tapes. Alternatively, any combination of some or all of them can form a memory in which the program is stored. In addition, multiple such memories can be included in the electronic device.

[0096] In addition, the program can be stored in an attachable storage device that can be accessed through a communication network, such as the Internet, an intranet, a local area network (LAN), a wide area network (WAN), and a storage area network (SAN), or a combination thereof. Such a storage device can access the electronic device via an external port. In addition, a separate storage device on a communication network can access a portable electronic device.

[0097] In the above detailed embodiments of the present disclosure, the components included in the present disclosure are expressed in the singular or plural, depending on the detailed embodiments presented. However, for ease of description, the singular form or plural form is selected to be suitable for the presented situation, and the various embodiments of the present disclosure are not limited to its single element or multiple elements. In addition, multiple elements expressed in the description can be configured as a single element, or a single element in the description can be configured as multiple elements.

[0098] Although the present disclosure has been shown and described with reference to certain embodiments of the present disclosure, it will be appreciated by those skilled in the art that various changes may be made in form and detail without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be defined as being limited to the embodiments, but should be defined by the appended claims and their equivalents.

[0099] Although the present disclosure has been described with various embodiments, various changes and modifications may be suggested to one skilled in the art. The present disclosure is intended to encompass such changes and modifications as fall within the scope of the appended claims.

Claims

1. A device comprising an electronic circuit, the device comprising: a path unit configured to form a first impedance for controlling a gain of an input signal; as well as a shunt unit configured to form a second impedance to attenuate between the path unit and the ground; and an attenuation enabling unit, the attenuation enabling unit selectively connecting the path unit and the shunt unit, and configured as follows: When the electronic circuit performs attenuation, the path unit and the shunt unit are connected, and When the electronic circuit passes the input signal without performing attenuation, disconnecting the path between the path unit and the shunt unit, The path unit uses the on-resistance of at least one transistor to form the first impedance. The attenuation enabling unit includes a structure in which a first group of transistors and a second group of transistors are connected in parallel with each other, and The first group of transistors are connected in a stack structure, and the second group of transistors are connected in a stack structure.

2. The device according to claim 1, wherein: The path unit includes a plurality of paths forming different impedance values, and Each of the plurality of paths includes at least one transistor that functions as a switch.

3. The device according to claim 2, wherein: At least one transistor included in a first path among the plurality of paths corresponding to a gain change of the input signal is turned on, and At least one transistor included in at least one path remaining after excluding the first path from the plurality of paths is turned off.

4. The device according to claim 2, wherein: The plurality of paths include a through path that provides minimal gain variation, and The through path includes a transistor and an inductor connected in parallel.

5. The device according to claim 1, further comprising: an input matching unit, the input matching unit being connected to an input end of the input signal, Therein, the input matching unit comprises at least one inductor for performing compensation associated with a parasitic capacitance of the at least one transistor.

6. The device according to claim 1, wherein: The at least one transistor is controlled to be in a reverse biased state.

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