Thin Film Transistor - Liquid Crystal Display Panel and Its Manufacturing Method

Abstract

The present disclosure provides a thin film transistor liquid crystal display panel and a method for manufacturing the same. The display panel has an array substrate, a counter substrate, and sealant, and includes a substrate layer, a first passivation protection layer, an organic film layer, and a second passivation protection layer. The second passivation protection layer extends to an external region outside the sealant in the orthographic projection on the substrate, and the display panel further includes a water isolation layer covering a part of the orthographic projection of the second passivation protection layer on the substrate layer in the external region, so that the second passivation protection layer does not contact the external environment of the display panel. The thin film transistor liquid crystal display panel provided by the present disclosure can prevent the organic film from exhausting gas and affecting the performance of the TFT, while ensuring the waterproof property of the display panel under harsh conditions.

Description

Technical Field

[0001] The present disclosure relates to the field of thin film transistor liquid crystal displays, and particularly to a thin film transistor liquid crystal display panel and a method for manufacturing the same. Background Art

[0002] Oxide thin film transistors are gradually being used in thin film transistor (TFT) liquid crystal display panels. Oxide thin film transistors use oxide semiconductors as the active layer material to replace the commonly used α-Si semiconductors in thin film transistors, and have advantages such as high mobility, good large-area uniformity, and low preparation process temperature, and may be used in the next generation of flat panel displays.

[0003] However, the α-Si thin film transistors in the display panels in the related art cannot be simply replaced with oxide thin film transistors. In a display panel based on thin film transistors, there are generally many film layers, some of which are organic films. The organic films will have a problem of outgassing during use, that is, sublimated gases are released to their surroundings. Such gases have little effect on the α-Si semiconductor active layer in the α-Si thin film transistors, but in a display panel based on oxide thin film transistors, outgassing may interact with the oxide semiconductor active layer, thus seriously adversely affecting the performance of the oxide thin film transistors.

[0004] Furthermore, for thin film transistors in a display panel that include components vulnerable to outgassing of organic films, there is a need to reduce or prevent the influence of outgassing.

[0005] In addition, the requirements for a thin film transistor liquid crystal display panel to maintain its performance under harsh conditions are getting higher and higher. The current thin film transistor liquid crystal display panels need to have better performance in a Pressure Cooker Test (PCT).

[0006] There is a need for improvement in thin film transistor liquid crystal display panels. Summary of the Invention

[0007] In one aspect, the present disclosure provides a thin film transistor liquid crystal display panel, the display panel having an effective display area and a border area, and including:

[0008] An array substrate, a counter substrate opposite to the array substrate, the array substrate including a substrate layer and thin film transistors on a side of the substrate layer close to the counter substrate;

[0009] A liquid crystal layer and spacers between the array substrate and the counter substrate; and

[0010] The sealant that bonds the array substrate and the counter substrate in the border area, and the positive projection of the sealant on the substrate layer divides the border area into an inner area surrounded by the positive projection of the sealant, a sealant area where the positive projection of the sealant is located, and an outer area outside the positive projection of the sealant.

[0011] Wherein, the display panel further includes a first passivation protection layer on the side of the thin film transistor close to the counter substrate, an organic film layer on the side of the first passivation protection layer close to the counter substrate, and a second passivation protection layer on the side of the organic film layer close to the counter substrate, wherein the permeability of the exhaust gas of the organic film layer to the second passivation protection layer is higher than that to the first passivation protection layer.

[0012] Wherein, the positive projection of the second passivation protection layer on the substrate layer extends to the outer area.

[0013] Wherein, the display panel further includes a water isolation layer that covers the part of the positive projection of the second passivation protection layer on the substrate layer in the outer area, so that the second passivation protection layer does not contact the external environment of the display panel.

[0014] Optionally, the thin film transistor is an oxide thin film transistor.

[0015] Optionally, the display panel further includes a pixel electrode layer on the side of the second passivation protection layer close to the counter substrate in the effective display area, and

[0016] The water isolation layer is arranged on the same layer as the pixel electrode layer.

[0017] Optionally, the material of the water isolation layer includes indium tin oxide.

[0018] Optionally, the water isolation layer extends into the interior of the display panel through the second passivation protection layer and the sealant, so that the positive projection of the water isolation layer on the substrate layer extends to the inner area.

[0019] Optionally, the water isolation layer covers the part of the positive projection of all layers of the array substrate except the substrate layer on the substrate layer in the outer area, so that all layers of the array substrate except the substrate layer do not contact the external environment of the display panel.

[0020] Optionally, the outer edge of the positive projection of the water isolation layer on the substrate layer is located in the outer area and has a certain distance from the edge of the display panel, and the distance is not zero.

[0021] Optionally, the positive projection of the water isolation layer on the substrate layer covers the entire outer area.

[0022] Optionally, the display panel further includes a pixel electrode layer in the effective display area on a side of the second passivation protection layer close to the counter substrate, and the water isolation layer is disposed on the same layer as the pixel electrode layer, and

[0023] the display panel further includes a via conduction medium layer disposed on the same layer as the pixel electrode layer and the water isolation layer, and

[0024] the water isolation layer is disconnected from the via conduction medium layer.

[0025] In one aspect, the present disclosure provides a method for manufacturing the above display panel, and the method includes the following steps:

[0026] After forming the second passivation protection layer, the pixel electrode layer and the water isolation layer are simultaneously formed by a mask deposition method, and

[0027] after forming the water isolation layer, the array substrate and the counter substrate are bonded with a sealing glue.

[0028] Optionally, before forming the water isolation layer formed by the mask deposition method, a predetermined sealing glue area is set;

[0029] The inner edge of the orthographic projection of the water isolation layer formed by the mask deposition method on the substrate layer is within the inner edge of the orthographic projection of the predetermined sealing glue area on the substrate layer, and the distance from the inner edge of the orthographic projection of the predetermined sealing glue area on the substrate layer is 1.8 μm or more,

[0030] Sealing glue is coated in the predetermined sealing glue area to bond the array substrate and the counter substrate with the sealing glue. Description of the Drawings

[0031] Figure 1 Schematically shows a solution to the exhaust problem.

[0032] Figure 2 Schematically shows the partitioning of the border area.

[0033] Figure 3 Schematically shows an embodiment of the present disclosure.

[0034] Figure 4 Schematically shows another embodiment of the present disclosure.

[0035] Figure 5 Schematically shows another embodiment of the present disclosure.

[0036] Figure 6 Schematically shows another embodiment of the present disclosure.

[0037] Figure 7 Another embodiment of the present disclosure is schematically illustrated.

[0038] Figure 8 Another embodiment of the present disclosure is schematically illustrated.

[0039] Figure 9 Another embodiment of the present disclosure is schematically illustrated.

[0040] Figure 10 Another embodiment of the present disclosure is schematically illustrated.

[0041] Figure 11 Another embodiment of the present disclosure is schematically illustrated.

[0042] Figure 12 The via holes in an embodiment of the present disclosure are schematically illustrated. Specific embodiments

[0043] For thin film transistors in a display panel that include components vulnerable to the outgassing of the organic film, there is a need to reduce or prevent the impact of outgassing. Components vulnerable to the outgassing of the organic film can be any component of the thin film transistor, such as the active layer. For example, in a display panel of an array substrate based on oxide thin film transistors, the outgassing generated by the organic film layer on the side close to the opposite substrate may penetrate into the oxide semiconductor active layer and interact with it, which will have a serious adverse impact on the performance of the oxide thin film transistor. To this end, different environments can be set on both sides of the organic film layer that generates outgassing to induce the outgassing away from the oxide semiconductor active layer of the oxide thin film transistor.

[0044] Figure 1 A solution to the outgassing problem is schematically illustrated. Figure 1 Shown is a schematic cross-sectional view of a liquid crystal display panel. In the figure, 1 represents the array substrate, 2 represents the opposite substrate, 3 represents the sealant for bonding the array substrate and the opposite substrate, 4 represents the liquid crystal layer, which is sealed by the array substrate 1, the opposite substrate 2, and the sealant 3. The liquid crystal display panel further includes spacers 5. The sealant is bonded around the entire periphery of the display panel in the border area and serves to prevent moisture in the external environment from intruding.

[0045] Figure 1Schematically shows a cross-section of the display panel border area and the active display area (AA), where the left part schematically shows a TFT in the AA and the layered structure near the corresponding pixel, which is in the AA, and the right part schematically shows the layered structure at the display panel border area. The part between the left and right parts is omitted. In the figure, the same legend represents the film layers formed in the same layer in the AA area and the border area. In the omitted part, these film layers can be continuous or discontinuous.

[0046] The projection of the sealant on the array substrate can divide the border area into an inner area (I), a sealant area (A), and an outer area (O).

[0047] The array substrate 1 includes a substrate layer 101. In the AA, an oxide thin film transistor is exemplarily shown. The structure of the oxide thin film transistor can include source and drain electrodes, a gate electrode, a gate insulating layer, an active layer, an interlayer dielectric layer, etc. In the oxide thin film transistor shown in the figure, a gate electrode 102, source / drain electrodes 103 / 104, an active layer 105, a gate insulating layer 106, and a first passivation protection layer 107 are provided on the side of the substrate layer 101 close to the counter substrate 2. The active layer 105 is an oxide semiconductor active layer. In Figure 1 , there may be a gate electrode 102 and a gate insulating layer 106 between the active layer 105 and the substrate layer 101. There is a first passivation protection layer 107 on the side of the active layer 105 close to the counter substrate 2. There is an organic film layer 108 on the side of the first passivation protection layer 107 close to the counter substrate 2. The function of the organic film layer 108 in the oxide thin film transistor liquid crystal display panel is to reduce the data line-common electrode capacitance, improve the aperture ratio of the array substrate, and reduce power consumption. The organic film layer can be, for example, an acrylic epoxy resin layer. There is a common electrode 109 on the side of the organic film layer 108 close to the counter substrate 2. The organic film layer 108 has a problem of gas exhaust, and may penetrate through the first passivation protection layer 107 and affect the active layer 105. For this reason, a second passivation protection layer 110 is provided on the other side of the organic film layer 108, and the permeability of the gas exhaust of the organic film layer 108 to the second passivation protection layer 110 is higher than the permeability to the first passivation protection layer 107. For this reason, a material with a less dense texture compared to the material of the first passivation protection layer 107 can be selected. At this time, the gas exhaust released from the organic film layer 108 will penetrate into the second passivation protection layer 110 and not penetrate into the first passivation protection layer 107, so as to protect the oxide active layer 105 from the damage of the gas exhaust. Figure 1 Although only one oxide TFT is shown in, it can be understood that both the first passivation protection layer 107 and the second passivation protection layer 110 can extend throughout the display panel, so as to also protect other parts not shown in the AA Figure 1The oxide thin-film transistor shown in []. Moreover, as described below, the first passivation protection layer 107 and the second passivation protection layer 110 also extend to the border of the display panel until the ends are exposed to the environment. There may also be other film layers, and the present disclosure does not limit this. A pixel electrode 111 is also provided on the array substrate for emitting light from the liquid crystal layer. An alignment layer 112 for aligning the liquid crystal may also be provided on the array substrate. The alignment layer may be made of, for example, polyimide.

[0048] Figure 1 The counter substrate 2 in [ ] is a color filter substrate, where 201 represents a glass substrate, 202 represents a color filter layer, 203 represents an optically transparent layer, and 204 represents a black matrix. The color filter layer 202 may be provided only at the pixels in the AA region for emitting light, and the black matrix 204 may be provided either at the boundary of the color filter layer or in the border region. The black matrix in the border region and the AA region may be provided on the same layer. An alignment layer 205 for aligning the liquid crystal may also be provided on the counter substrate 2. The alignment layer 205 may be prepared using the same material as the alignment layer 112, but different materials may also be used. In Figure 1 the exemplary solution of [ ], the alignment layer 205 is prepared using the same material as the alignment layer 112 and is represented by the same legend.

[0049] Between the array substrate 1 and the counter substrate 2 is a liquid crystal layer 4, and spacers 5 are also provided therebetween.

[0050] In Figure 1 the border region shown in the right part, the sealant 3 bonds and seals the array substrate 1 and the counter substrate 2, and seals the liquid crystal layer 4 within the display panel. According to the orthographic projection of the sealant 3 on the array substrate 1, the border region can be divided into a sealant region A where the orthographic projection of the sealant is located, an outer region O on the side of the sealant region A close to the external environment, and an inner region I on the side of the sealant region A close to the AA region. The ends of the gate insulating layer 106, the first passivation protection layer 107, and the second passivation protection layer 110 all extend to the outer region O and are in contact with the external environment, that is, they can be in contact with environmental moisture. There are also components formed on the same layer as the gate and source / drain electrodes in the border region, such as metal wires 102′, 103′, which may be dummy electrodes or data lines, etc. It should be noted that the positions of these components are only schematic.

[0051] Figure 1The described solution has a drawback. Since the second passivation protection layer 110 extends across the entire array substrate until beyond the region sealed by the sealant 3, it is in direct contact with the external environment of the display panel. Due to the relatively less dense texture of the second passivation protection layer 110, it is insufficient to resist the penetration of environmental moisture in a high-humidity environment, and thus forms a moisture transmission path for environmental moisture to enter the inside of the sealant sealed area, resulting in deterioration of the display panel performance.

[0052] The present disclosure proposes a thin-film transistor liquid crystal display panel, the display panel having an active display area and a border area, and comprising:

[0053] an array substrate and a counter substrate opposite to the array substrate, the array substrate including a substrate layer and thin-film transistors on a side of the substrate layer close to the counter substrate; and

[0054] a sealant that bonds the array substrate and the counter substrate in the border area, a positive projection of the sealant on the substrate layer divides the border area into an inner area surrounded by the positive projection of the sealant, a sealant area where the positive projection of the sealant is located, and an outer area outside the positive projection of the sealant,

[0055] wherein, the display panel further includes a first passivation protection layer on a side of the thin-film transistor close to the counter substrate, an organic film layer on a side of the first passivation protection layer close to the counter substrate, and a second passivation protection layer on a side of the organic film layer close to the counter substrate, wherein the permeability of the exhaust gas of the organic film layer to the second passivation protection layer is higher than that to the first passivation protection layer,

[0056] wherein, a positive projection of the second passivation protection layer on the substrate layer extends to the outer area,

[0057] wherein, the display panel further includes a water isolation layer, the water isolation layer covers a part of the positive projection of the second passivation protection layer on the substrate layer in the outer area, so that the second passivation protection layer is not in contact with the external environment of the display panel.

[0058] A water isolation layer is added in the display panel of the present disclosure to solve the problem that the second passivation protection layer is exposed to environmental moisture.

[0059] The thin-film transistor liquid crystal display panel of the present disclosure has an active display area and a border area. The active area and the border area are well-known concepts in the art. The display panel of the present disclosure includes an array substrate and a counter substrate opposite to the array substrate, and the two are bonded by a sealant.

[0060] The array substrate includes a substrate layer and various film layers and components disposed on the substrate layer. In a display panel, the thin-film transistors of the array substrate are disposed on the side of the substrate layer close to the counter substrate, or between the substrate layer and the counter substrate. The counter substrate can be, for example, a color filter substrate.

[0061] The scheme of bonding the array substrate and the counter substrate with a sealing glue is well-known in the art. The sealing glue is located in the border area around the display panel, so as not to affect the display. While bonding and fixing the two substrates, the sealing glue also seals the space between the array substrate and the counter substrate to accommodate liquid crystal, and at the same time prevents water and oxygen in the environment from entering. Between the counter substrate and the array substrate, there may also be required film layers or components. For example, when the display panel is a liquid crystal display panel and the counter substrate is a color filter substrate, there may also be a liquid crystal layer between the array substrate and the counter substrate.

[0062] Viewed from the orthographic projection on the substrate layer, the sealing glue divides the border area into three regions: an inner region surrounded by the orthographic projection of the sealing glue, a sealing glue region where the orthographic projection of the sealing glue is located, and an outer region outside the orthographic projection of the sealing glue. Figure 2 Schematically shows the partitioning of the border area according to the orthographic projection of the sealing glue on the substrate layer. In a rectangular display panel, the central gray part is the projection area of the effective display area AA, and the periphery is the projection area of the border area. When the sealing glue 3 is formed as an annular band with a certain width, its projection is the sealing glue region A. The inside thereof is the inner region I, and the outside thereof is the outer region O. For clarity, Figure 2 the dimensions in are not drawn according to the actual scale.

[0063] The thin-film transistors of the present disclosure include source and drain electrodes, a gate electrode, a gate insulating layer, and an active layer as basic components of the transistor. On the side of the thin-film transistor close to the counter substrate, there is a first passivation protection layer, an organic film layer, and a second passivation protection layer. The organic film layer of the thin-film transistors of the present disclosure is basically sandwiched between the first passivation protection layer and the second passivation protection layer. The permeability of the exhaust gas of the organic film layer to the second passivation protection layer is higher than that to the first passivation protection layer. Therefore, the exhaust gas will not penetrate in the direction of the thin-film transistor, but will penetrate into the second passivation protection layer.

[0064] The second passivation protection layer spreads basically within the entire range of the display panel and extends to the outside of the sealing glue. Therefore, its orthographic projection extends into the outer region.

[0065] The display panel of the present disclosure includes a water isolation layer that covers the part of the orthographic projection of the second passivation protection layer in the outer region on the substrate layer, so that the second passivation protection layer does not contact the external environment of the display panel.

[0066] The present disclosure solves the problem of a moisture transmission path connected to the environment due to the presence of the second passivation protection layer that prevents exhaust from damaging the thin film transistor by providing a water-isolating layer.

[0067] Figure 3 One embodiment of the present disclosure is schematically shown.

[0068] exist Figure 3 In the figure, 1 represents the array substrate, 2 represents the counter substrate, 3 represents the sealant that bonds the array substrate and the counter substrate together, and 4 represents the liquid crystal layer, which is sealed by the array substrate 1, the counter substrate 2, and the sealant 3. The liquid crystal display panel also includes spacers 5. The sealant surrounds the entire perimeter of the display panel, bonding it in the border area and preventing moisture from entering the external environment.

[0069] Figure 3 The cross-section of the display panel border area and the active display area (AA) is schematically shown, wherein the left portion schematically shows a TFT in AA and the layered structure near the corresponding pixel, which is in AA, and the right portion schematically shows the layered structure in the display panel border area. The portion between the left and right portions is omitted. In the figure, the same legend indicates the film layers formed in the same layer in the AA area and the border area. In the omitted portion, these film layers can be continuous or discontinuous.

[0070] The projection of the frame sealant on the array substrate can divide the frame area into an inner area (I), a frame sealant area (A) and an outer area (O).

[0071] The array substrate 1 includes a substrate layer 101. In AA, an oxide thin film transistor is exemplarily shown. In the exemplary embodiments of the present disclosure, oxide thin film transistors are used as examples for description, and the second passivation protection layer is used to protect the oxide active layer from being affected by the exhaust of the organic film layer. However, it can be understood that the structure of the present disclosure can also be used for other types of thin film transistor liquid crystal display panels to prevent exhaust from affecting the performance of the thin film transistor, and at the same time to prevent moisture from entering the interior of the display panel under harsh conditions. The structure of the oxide thin film transistor may include a source and drain electrode, a gate electrode, a gate insulating layer, an oxide semiconductor active layer, and an appropriate interlayer dielectric layer. In the oxide thin film transistor shown in the figure, a gate electrode 102, a source / drain electrode 103 / 104, an active layer 105, a gate insulating layer 106, and a first passivation protection layer 107 are provided on the side of the substrate layer 101 close to the opposing substrate 2. The active layer 105 is an oxide semiconductor active layer. In Figure 3In this case, a gate 102 and a gate insulating layer 106 may be present between the active layer 105 and the substrate layer 101. A first passivation protection layer 107 is provided on the side of the active layer 105 close to the counter substrate 2. An organic film layer 108 is provided on the side of the first passivation protection layer 107 close to the counter substrate 2. The function of the organic film layer 108 in the oxide thin-film transistor liquid crystal display panel is to reduce the data line-common electrode capacitance, improve the aperture ratio of the array substrate, and reduce power consumption. The organic film layer may be, for example, an acrylic epoxy resin layer. A common electrode 109 is provided on the side of the organic film layer 108 close to the object substrate 2. The organic film layer 108 has a problem of exhausting gas, and may penetrate through the first passivation protection layer 107 and affect the active layer 105. Therefore, a second passivation protection layer 110 is provided on the other side of the organic film layer 108, and the permeability of the exhaust gas of the organic film layer 108 to the second passivation protection layer 110 is higher than that to the first passivation protection layer 107. For this purpose, a material with a less dense texture compared to the material of the first passivation protection layer 107 can be selected. In addition to using a material with a less dense texture, other suitable means can also be used to provide a second passivation protection layer with higher gas permeability. For example, a material having a micro gas permeation path or a component for accelerating gas diffusion can be used to form the second passivation protection layer. At this time, the exhaust gas released from the organic film layer 108 will penetrate into the second passivation protection layer 110 instead of the first passivation protection layer 107, so that the oxide active layer 105 can be protected from the damage of the exhaust gas. Figure 3 Although only one TFT is shown in this case, it can be understood that both the first passivation protection layer 107 and the second passivation protection layer 110 can extend throughout the display panel, so as to also protect other thin-film transistors located in the AA area that are not shown in Figure 3 this case. Moreover, as described below, the first passivation protection layer 107 and the second passivation protection layer 110 also extend to the border of the display panel until the ends are exposed to the environment. There may also be other film layers, which are not limited in this disclosure. A pixel electrode 111 is further provided on the array substrate for emitting light from the liquid crystal layer. An alignment layer 112 for aligning the liquid crystal may also be provided on the array substrate. The alignment layer may be made of, for example, polyimide.

[0072] Figure 3 The counter substrate 2 in this case is a color filter substrate, where 201 represents a glass substrate, 202 represents a color filter layer, 203 represents an optically transparent layer, and 204 represents a black matrix. The color filter layer 202 may be provided only at the pixels in the AA area for emitting light, and the black matrix 204 may be provided either at the boundary of the color filter layer or in the border area. The black matrix in the border area and the AA area may be provided on the same layer. An alignment layer 205 for aligning the liquid crystal may also be provided on the counter substrate 2. The alignment layer 205 may be prepared using the same material as the alignment layer 112, but different materials may also be used. InFigure 3 In an exemplary embodiment, the alignment layer 205 is made of the same material as the alignment layer 112 and is represented by the same legend.

[0073] There is a liquid crystal layer 4 between the array substrate 1 and the counter substrate 2, and spacers 5 are also provided therebetween.

[0074] In Figure 3 In the border area shown in the right part, the sealant 3 bonds and seals the array substrate 1 and the counter substrate 2, and seals the liquid crystal layer 4 within the display panel. According to the orthographic projection of the sealant 3 on the array substrate 1, the border area can be divided into a sealant area A where the orthographic projection of the sealant is located, an outer area O on the side of the sealant area A close to the external environment, and an inner area I on the side of the sealant area A close to the AA side. The ends of the gate insulating layer 106, the first passivation protection layer 107, and the second passivation protection layer 110 all extend to the outer area O and are in contact with the external environment, that is, they can be in contact with environmental moisture. The organic film layer 108 does not extend to the outer area and terminates before reaching the sealant area. At the termination of the organic film layer 108, the first passivation protection layer 107 and the second passivation protection layer 110 merge and contact each other. There are also components formed in the same layer as the gate and source / drain electrodes in the border area, such as metal lines 102', 103', which can be dummy electrodes or data lines, etc. It should be noted that the positions of these components are only schematic.

[0075] Specifically, in the AA region of the display panel, one side of the substrate layer 101 of the array substrate has a gate layer 102, the side of the gate layer 102 away from the substrate layer 101 has a gate insulating layer 106, and the side of the gate insulating layer 106 away from the substrate layer 101 has an oxide semiconductor active layer 105, whose orthographic projection on the substrate layer 101 overlaps with the orthographic projection of the gate layer 102. In the present disclosure, the overlap may include partial overlap. Source / drain electrodes 103 / 104 electrically connected to the oxide semiconductor active layer 105 are provided. The first passivation protection layer 107 covers the active layer 105 and the source / drain electrodes 103 / 104 on the side away from the substrate layer 101. An organic film layer 108 is provided on the side of the first passivation protection layer 107 away from the substrate layer 101. A common electrode 109 is provided on the side of a part of the organic film layer 108 away from the substrate layer 101, and a second passivation protection layer 110 is provided on the side of the common electrode 109 and the organic film layer 108 away from the substrate layer 101. The organic film layer 108 is in contact with both the second passivation protection layer 110 and the first passivation protection layer 107. A pixel electrode layer 111 is provided on the side of the second passivation protection layer 108 away from the substrate layer 101, whose orthographic projection on the substrate layer 101 overlaps with the orthographic projection of the common electrode 110 on the substrate layer 101. A first alignment layer 112 is provided in the region outside the pixel electrode layer 111. On the side of the pixel electrode layer 111 away from the substrate layer 101, a liquid crystal layer 4 is provided, and a second alignment layer 205, an optically transparent layer 203, a color filter layer 202, a black matrix 204, a glass substrate 201, etc. are further provided. Spacers 5 are provided in the liquid crystal layer 4.

[0076] Specifically, in the border region, a sealant 3 is provided, which bonds the array substrate 1 and the counter substrate 2 and seals the liquid crystal layer 4 within the display panel. The orthographic projection of the sealant 3 on the substrate layer divides the border region into a sealant region A, an inner region I, and an outer region O.

[0077] The array substrate 1 includes a substrate layer 101. A gate insulating layer 106 is provided on the side of the substrate layer close to the counter substrate 2, which is provided on the same layer as the gate insulating layer 106 in the AA region. A first passivation protection layer 107 is provided on the side of the gate insulating layer 106 close to the counter substrate 2, which is provided on the same layer as the first passivation protection layer 107 in the AA region. A second passivation protection layer 110 is provided on the side of the first passivation protection layer 107 close to the counter substrate 2, which is provided on the same layer as the second passivation protection layer 110 in the AA region. In the inner region I of the border region, an organic film layer 108 may further be provided between the first passivation protection layer 107 and the second passivation protection layer 110, which is provided on the same layer as the organic film layer 108 in the AA region. The material layers provided on the same layer as the gate insulating layer 106, the first passivation protection layer 107, and the second passivation protection layer 110 in the AA region all extend beyond the sealing range of the sealant 3, that is, their orthographic projections on the substrate layer 101 extend into the outer region O.

[0078] In the inner region I, on the side of the second passivation protection layer 110 close to the counter substrate 2, there is also a first alignment layer 112, which can be a polyimide layer.

[0079] A liquid crystal layer 4 is provided between the array substrate 1 and the counter substrate 2, and it is defined in the display panel by the sealant 3.

[0080] The counter substrate includes a substrate 201, a black matrix 204 on the side of the substrate 201 close to the array substrate 1, and an optically transparent layer 203 on the side of the black matrix close to the array substrate 1. Their orthographic projections on the substrate layer 101 extend to the outer region O. In the inner region I, on the side of the optically transparent layer 203 close to the array substrate 1, there is also a second alignment layer 205, which can be a polyimide layer. The liquid crystals in the liquid crystal layer 3 can be aligned by the first alignment layer 112 and / or the second alignment layer 205. In addition, spacers 5 are attached on the side of the counter substrate 2 close to the array substrate 1. It can be understood that the spacers can also be provided on the side of the array substrate 1 close to the counter substrate.

[0081] In the array substrate in the border region, there may also be components 102' and 103' formed in the same layer as the gate and the source-drain electrodes respectively. Their positions are schematic and can be used to form data lines, dummy electrodes, etc.

[0082] Figure 3 A water isolation layer 120 is provided, which covers the part of the orthographic projection of the second passivation protection layer 110 on the substrate layer 101 in the outer region O. That is, it completely covers the part of the second passivation protection layer 110 outside the sealant, thereby preventing the second passivation protection layer 110 from contacting environmental moisture, preventing the formation of a transmission path for the second passivation protection layer 110 with loose texture to enter the panel interior, and also preventing water vapor from entering under high temperature, high pressure and high humidity conditions. In Figure 3 In it, the water isolation layer 120 extends from the outside of the sealant to the edge of the display panel and also extends in the direction of the substrate layer 101, completely covering the lateral end face of the second passivation protection layer 110. In the present disclosure, the lateral direction refers to the direction parallel to the substrate layer.

[0083] By providing the water isolation layer 120, Figure 3 The embodiment of the present disclosure shown completely isolates the second passivation protection layer 110 outside the sealant from environmental moisture, thereby avoiding the deterioration of the display panel caused by the entry of water under high pressure, high temperature and high humidity conditions.

[0084] It should be understood that the various film layers of the display device in the effective display area on the left side of the figure in the present disclosure may also adopt other arrangements, as long as there are organic film layers that meet the requirements of the present disclosure and the first passivation protection layer and the second passivation protection layer in contact therewith. For example, the common electrode may also be located on the side of the counter substrate facing the array substrate. This also applies to the embodiments shown in other figures.

[0085] In one embodiment, the thin film transistor is an oxide thin film transistor. The oxide thin film transistor includes an oxide semiconductor active layer. The structure of the present disclosure is particularly suitable for an oxide thin film transistor liquid crystal display panel, and can fully protect the oxide semiconductor active layer therein from the influence of the exhaust gas of the organic film layer.

[0086] In one embodiment, the outer edge of the orthographic projection of the water barrier layer on the substrate layer is located in the outer area, and there is a certain distance from the edge of the display panel, and the distance is not zero. It can also be said that the outer edge of the orthographic projection of the water barrier layer on the substrate layer is inside the edge of the substrate layer.

[0087] Figure 4 Another embodiment of the present disclosure is schematically shown. In the figure, the same reference numerals represent the same structures. Figure 3 compared with Figure 3 In Figure 4 , the second passivation protection layer 110 does not extend to the edge of the display panel. In other words, the orthographic projection of the second passivation protection layer 110 on the substrate layer 101 does not extend to the edge of the substrate layer. Therefore, the outer edge of the orthographic projection of the water barrier layer 120 on the substrate layer 101 can be inside the edge of the substrate layer 101. This structure is easier to form than the Figure 3 scheme, and the structure is stable, because Figure 3 the water barrier layer 120 covering the lateral end of the second passivation protection layer 110 is not easily formed by the deposition method and the end face close to the substrate layer 101 is a free end, and the stability is slightly poor.

[0088] In one embodiment, the orthographic projection of the water barrier layer on the substrate layer covers the entire outer area.

[0089] Figure 5 Another embodiment of the present disclosure is schematically shown. In the figure, the same reference numerals represent the same structures. Figure 4 In Figure 5 , the second passivation protection layer 110 also does not extend to the edge of the display panel. Compared with Figure 4 In Figure 5 , the outer edge of the orthographic projection of the water barrier layer 120 on the substrate layer 101 can reach the edge of the substrate layer 101, that is, cover the entire outer area O. This structure is more Figure 4The solution is easier to form because there is no need to specifically control the distance between the edge of the water barrier layer and the edge of the display panel, thus simplifying the mask and deposition processes.

[0090] In one embodiment, the water barrier layer covers the part of the positive projection of all layers of the array substrate except the substrate layer in the external region on the substrate layer, such that all layers of the array substrate except the substrate layer do not contact the external environment of the display panel.

[0091] Figure 6 Another embodiment of the present disclosure is schematically shown. In the figure, the same reference numerals as Figure 3 represent the same structures. Compared with Figure 3 , the water barrier layer 120 not only covers the second passivation protection layer 110, but also completely covers all the film layers of the array substrate except the substrate layer 101, such as the first passivation protection layer 107 and the gate insulating layer 106. This structure can further enclose other film layers of the array substrate, thereby further enhancing the waterproof property of the display panel under harsh conditions. Moreover, this solution does not require precise definition of the lower boundary of the water barrier layer at the lateral end face of the array substrate, simplifying the manufacturing process. The substrate layer 101 is waterproof, such as a glass substrate, so its lateral end face does not need to be covered by the water barrier layer 120. However, as Figure 6 shows, the lateral end face of the substrate layer can also be partially covered by the water barrier layer 120. Moreover, the lateral end face of the substrate layer can also be completely covered by the water barrier layer 120.

[0092] Figure 7 Another embodiment of the present disclosure is schematically shown. In the figure, the same reference numerals as Figure 6 represent the same structures. Compared with Figure 6 , Figure 7 the second passivation protection layer 110, the first passivation protection layer 107, and the gate insulating layer 106 of Figure 6 do not extend to the edge of the display panel. In other words, the positive projections of the second passivation protection layer 110, the first passivation protection layer 107, and the gate insulating layer 106 on the substrate layer 101 do not extend to the edge of the substrate layer. Therefore, the positive projection of the outer edge of the water barrier layer 120 on the substrate layer 101 can be inside the edge of the substrate layer 101. This structure is easier to form than the solution of Figure 6 , and the structure is stable because Figure 6 the water barrier layer 120 covering the lateral end of the second passivation protection layer 110 in Figure 6 is not easy to form by the deposition method and its end face close to the substrate layer 101 is a free end, with slightly poor stability.

[0093] Figure 8 Another embodiment of the present disclosure is schematically shown. In the figure, the same reference numerals as Figure 7 represent the same structures. Figure 8The second passivation protection layer 110, the first passivation protection layer 107, and the gate insulating layer 106 therein also do not extend to the edge of the display panel. Compared with Figure 7 that, Figure 8 the orthographic projection of the edge of the water isolation layer 120 on the substrate layer 101 can reach the edge of the substrate layer 101, that is, cover the entire outer region O. This structure is easier to form than Figure 7 the solution of, because there is no need to specifically control the distance between the edge of the water isolation layer and the edge of the display panel, thereby simplifying the mask and deposition processes.

[0094] It should be understood that in the display panel of the present disclosure, similar to Figures 6 - 8 the embodiment shown, the morphology of the outer edge of the water isolation layer 120 can be appropriately adjusted to cooperate with the specific second passivation protection layer 110, the first passivation protection layer 107, the gate insulating layer 106, and any other film layers on the substrate layer 101 and extending outside the sealant 3. The water isolation layer 120 can also only cover a part of the above film layers, for example, only cover the second passivation protection layer 110 and the first passivation protection layer 103, but not cover the gate insulating layer 106.

[0095] In Figures 2 - 8 the solution shown, a potential problem is that usually after the water isolation layer 120 is formed, the array substrate and the counter substrate are bonded. Therefore, if the water isolation layer is only designed to extend to the outer surface of the sealant, there may be a gap between the water isolation layer and the sealant due to the coating accuracy error, and it is difficult to ensure the sealing between the sealant 3 and the water isolation layer 120. And even if the sealant part is accurately formed at the inner edge of the water isolation layer 120 or slightly covers the inner edge of the water isolation layer, there may still be a potential moisture intrusion path at the shorter interface between the two.

[0096] In one embodiment, the water isolation layer extends into the display panel through between the second passivation protection layer and the sealant, such that the orthographic projection of the water isolation layer on the substrate layer extends to the inner region.

[0097] Figure 9 Another embodiment of the present disclosure is schematically shown. In the figure, the same reference numerals represent the same structures as Figure 8 that. Different from Figure 8 the water isolation layer 120 of, Figure 9 the water isolation layer 120 of extends into the display panel through between the second passivation protection layer 110 and the sealant 3, and the orthographic projection of the water isolation layer 120 on the substrate layer 101 extends to the inner region I. In this way, the interface length between the water isolation layer 120 and the sealant 3 is greatly increased, and the excessive accuracy requirement for coating is also avoided.

[0098] It should be understood that Figure 9 the structural morphology of the middle water barrier layer 120 in the outer region O can also be appropriately selected. For example, it is the same as any one of the embodiments such as Figures 3 - 7 in the embodiments

[0099] In one embodiment, the display panel further includes a pixel electrode layer on the side of the second passivation protection layer close to the counter substrate in the effective display area, and the water barrier layer is arranged on the same layer as the pixel electrode layer.

[0100] Figure 10 Another embodiment of the present disclosure is schematically shown. In the figure, the same reference numerals represent the same structures as Figure 9 the same. The difference from Figure 9 is that in Figure 10 the water barrier layer 120 is arranged on the same layer as the pixel electrode layer 111 and is represented by the same color.

[0101] In the present disclosure, being arranged on the same layer means that the water barrier layer 120 and the pixel electrode layer 111 are prepared simultaneously in the same manufacturing step, rather than meaning that the two are at the same relative height with respect to the substrate layer. Arranging the water barrier layer 120 and the pixel electrode layer 111 on the same layer can, without adding new manufacturing steps, use existing equipment and materials in related technologies and realize the preparation of the water barrier layer 120 only by replacing the mask.

[0102] Preferably, the materials of the water barrier layer 120 and the pixel electrode layer 111 are indium tin oxide (ITO). ITO has excellent water barrier properties, good deposition film-forming performance, and can also be well adhered to the sealant, and is suitable as the water barrier layer material.

[0103] Figure 11 Another embodiment of the present disclosure is schematically shown. In the figure, the same reference numerals represent the same structures as Figure 10 the same. The difference from Figure 10 is that Figure 11 in the counter substrate, the black matrix 204 is indented inward by a certain distance compared with the substrate 201, is not exposed to the environment, and is sealed by an optically transparent layer. Since the black matrix material has poor water tightness Figure 11 the embodiment of the present disclosure is beneficial to protecting the inside of the display panel from moisture intrusion.

[0104] In one embodiment, the display panel further includes a pixel electrode layer on the side of the second passivation protection layer close to the counter substrate in the effective display area, and the water barrier layer is arranged on the same layer as the pixel electrode layer, and

[0105] the display panel further includes a via conduction medium layer arranged on the same layer as the pixel electrode layer and the water barrier layer, and

[0106] The water isolation layer is disconnected from the via hole conduction medium layer.

[0107] It should be noted that, in order to reduce the number of masks in the manufacturing process, some via holes (also known as vias) are usually designed in the border area of the display substrate by using the pixel electrode layer material (such as connecting Com ITO and the gate / source-drain metal lines), and the pixel electrode layer material acts as a conduction medium. Therefore, when using the pixel electrode layer material to form the water isolation layer of the present disclosure in the same layer, it is necessary to disconnect around the above-mentioned via holes (the specific disconnection pattern can be circular, square, etc., without limitation) to avoid short circuits between each line.

[0108] For example, when the via hole is located in the internal area, one embodiment can be as Figure 12 shown. Figure 12 In, the following figure is a cross-sectional view, and the above figure is a top view. The via hole penetrates through the gate insulating layer 106 and the conduction medium is used to conduct the electrical components 102' and 103', and the via hole conduction medium b is formed in the same layer as the water isolation layer a (i.e., 120). From the top view, around the via hole, the water isolation layer a is disconnected from the conduction medium b in the via hole through the annular disconnection area c. The annular disconnection area can be realized by using a patterned mask during the formation process.

[0109] The above has exemplarily illustrated some embodiments of the structure of the display panel of the present disclosure through the drawings. It should be understood that the display panel may have other components that are not exemplarily shown in the drawings as long as they do not violate the spirit of the present application.

[0110] The materials and dimensional characteristics of the structure of the present disclosure can be appropriately selected. In particular, the organic film layer can be an acrylic epoxy resin layer. It can be formed by coating a coating composition containing acrylic epoxy resin, photosensitizer and solvent. The material of the first passivation protection layer can be SiNx, SiNO or a mixed layer of the two. The material of the second passivation protection layer can be SiNx, SiNO or a mixed layer of the two. In addition to using ITO, the material of the water isolation layer can also be metal Al, Cu or other oxide layers that are easy to form a film and suitable for the TFT substrate. The thickness range of the water isolation layer can be

[0111] The water isolation layer provided by the present disclosure can prevent the components in the TFT display panel (such as the oxide active layer) from deteriorating due to outgassing, and at the same time can resist moisture intrusion in a high-pressure, high-temperature and high-humidity environment.

[0112] The present disclosure also provides a method for manufacturing the above-mentioned display panel, and the method includes the following steps:

[0113] After forming the second passivation protection layer, the pixel electrode layer and the water isolation layer are simultaneously formed by the mask deposition method, and

[0114] After forming the water-blocking layer, bond the array substrate and the counter substrate with sealing glue.

[0115] The other components of the display panel can be formed in any suitable manner in the related art, and the present disclosure does not limit this.

[0116] The method of the present disclosure further includes the conventional steps of forming other layers of the array substrate and providing a counter substrate, liquid crystal, and cell alignment. The method of the present disclosure is characterized in that after forming the second passivation protection layer, the pixel electrode layer and the water-blocking layer are formed by a mask deposition method. This can obtain the water-blocking layer by only changing the mask without adding a dedicated water-blocking layer preparation process.

[0117] In the method of the present disclosure, the sealing glue bonding is performed after obtaining the water-blocking layer. If the sealing glue bonding is performed first, it will be difficult to form the water-blocking layer at the edge of the display panel.

[0118] As long as the above steps of the method of the present disclosure satisfy the required sequence, and other appropriate actions can be performed between the actions. For example, after forming the water-blocking layer and before bonding, a pixel preparation step can also be included.

[0119] Preferably, a predetermined sealing glue area is set before forming the water-blocking layer formed by the mask deposition method;

[0120] The inner edge of the orthographic projection of the water-blocking layer formed by the mask deposition method on the substrate layer is within the inner edge of the orthographic projection of the predetermined sealing glue area on the substrate layer, and the distance from the inner edge of the orthographic projection of the predetermined sealing glue area on the substrate layer is 1.8 μm or more.

[0121] Apply the sealing glue in the predetermined sealing glue area to bond the array substrate and the counter substrate.

[0122] The predetermined sealing glue area is the area where the sealing glue is expected to be applied. Considering that there is at least a 0.8 μm coating error for the sealing glue and at least a 1 μm edge error for the deposition of the water-blocking layer, in order to ensure the formation of the water-blocking layer in the embodiment shown, for example Figure 10 The inner edge of the orthographic projection of the water-blocking layer on the substrate layer is within the inner edge of the orthographic projection of the predetermined sealing glue area on the substrate layer, and the distance from the inner edge of the orthographic projection of the predetermined sealing glue area on the substrate layer should be 1.8 μm or more.

[0123] The method of the present disclosure can conveniently form the required water-blocking layer.

[0124] Examples

[0125] Comparative Example 1-1

[0126] Prepare multiple batches in a conventional mannerFigure 1 The 15.6-inch full high definition (FHD) oxide thin film transistor liquid crystal display panel shown, wherein the organic film layer 104 is an acrylic epoxy resin layer, which is formed by coating a coating composition containing acrylic epoxy resin, photosensitizer and solvent. The material of the oxide semiconductor active layer 102 is IGZO (indium gallium zinc oxide), the first passivation protection layer 103 is a silicon nitride layer with a refractive index of 1.90, and the second passivation protection layer is a silicon nitride layer with a refractive index of 1.87. The magnitude of the refractive index reflects the compactness of the film layer. The larger the refractive index, the higher the compactness. The display panel does not include the water isolation film proposed in the present disclosure. The TFT performance of the prepared display panel is measured and PCT test is carried out. Among them, the conditions of the PCT test are temperature 121 °C, humidity 100%, and pressure 2 atmospheres. The result is that the display panel has qualified TFT performance, but fails after 6 hours under the PCT test, and the failure rate fluctuates among batches.

[0127] Comparative Examples 1-2

[0128] A display panel prepared in the same manner as Comparative Example 1-1, the only difference being that the second passivation protection layer is changed to a silicon nitride layer with a refractive index of 1.89. The TFT performance of the prepared display panel is measured and PCT test is carried out. The result is that the display panel can withstand the 24-hour PCT test, and the failure rate is stable among batches; however, the TFT performance is unqualified. The result compared with that of Comparative Example 1 shows that if the compactness of the second passivation protection layer is improved, the display panel can withstand the PCT test, but it will have an adverse effect on its TFT performance. Without relying on any theory, the unqualified TFT performance is caused by the outgassing of the organic film therein.

[0129] Example 1

[0130] A display panel prepared in the same manner as Comparative Example 1-1, the difference being that a water isolation layer 120 as shown is provided. Figure 10 The TFT performance of the prepared display panel is measured and PCT test is carried out. The result is that the display panel can withstand the 24-hour PCT test, and the failure rate is stable among batches, and the TFT performance is also completely qualified. The result compared with that of Comparative Examples 1-1 and 1-2 shows that setting the water isolation layer of the present disclosure can maintain the qualified TFT performance while ensuring that the display panel withstands the PCT test.

[0131] Comparative Example 2-1

[0132] Prepare multiple batches in a conventional manner Figure 1The 15.6-inch ultra-high definition (UHD) oxide thin film transistor liquid crystal display panel shown, in which the organic film layer 104 is an acrylic epoxy resin layer, which is formed by coating a coating composition containing acrylic epoxy resin, photosensitizer and solvent. The material of the oxide semiconductor active layer 102 is IGZO (indium gallium zinc oxide), the first passivation protection layer 103 is a silicon nitride layer with a refractive index of 1.90, and the second passivation protection layer is a silicon nitride layer with a refractive index of 1.87. The magnitude of the refractive index reflects the compactness of the film layer. The larger the refractive index, the higher the compactness. The display panel does not include the water isolation film proposed in the present disclosure. The TFT performance of the prepared display panel was measured and PCT tests were carried out. Among them, the conditions of the PCT test were a temperature of 121 °C, a humidity of 100%, and a pressure of 2 atmospheres. The results were that the display panel had qualified TFT performance, but failed after 6 hours under the PCT test, and the failure rate fluctuated among batches.

[0133] Comparative Example 2-2

[0134] A display panel prepared in the same manner as Comparative Example 2-1, the only difference being that the second passivation protection layer was changed to a silicon nitride layer with a refractive index of 1.89. The TFT performance of the prepared display panel was measured and PCT tests were carried out. The results were that the display panel could withstand the 24-hour PCT test, and the failure rate was stable among batches; however, the TFT performance was unqualified. Comparing the results with those of Comparative Example 1 shows that if the compactness of the second passivation protection layer is increased, the display panel can withstand the PCT test, but it will have an adverse effect on its TFT performance. Without relying on any theory, the unqualified TFT performance is due to the outgassing of the organic film therein.

[0135] Example 2

[0136] A display panel prepared in the same manner as Comparative Example 2-1, the difference being that a water isolation layer 120 as Figure 10 shown was provided. The TFT performance of the prepared display panel was measured and PCT tests were carried out. The results were that the display panel could withstand the 24-hour PCT test, and the failure rate was stable among batches, and the TFT performance was also completely qualified. Comparing the results with those of Comparative Examples 2-1 and 2-2 shows that providing the water isolation layer of the present disclosure can maintain the qualified TFT performance while ensuring that the display panel can withstand the PCT test.

[0137] Comparative Example 3-1

[0138] Prepare multiple batches in a conventional manner Figure 1The 14-inch full high definition (FHD) oxide thin film transistor liquid crystal display panel shown in the figure, where the organic film layer 104 is an acrylic epoxy resin layer, which is formed by coating a coating composition containing acrylic epoxy resin, photosensitizer and solvent. The material of the oxide semiconductor active layer 102 is IGZO (indium gallium zinc oxide), the first passivation protection layer 103 is a silicon nitride layer with a refractive index of 1.90, and the second passivation protection layer is a silicon nitride layer with a refractive index of 1.80. The magnitude of the refractive index reflects the density of the film layer. The larger the refractive index, the higher the density. The display panel does not include the water isolation film proposed in the present disclosure. The TFT performance of the manufactured display panel is measured and PCT test is carried out. Among them, the conditions of the PCT test are temperature 121 °C, humidity 100%, and pressure 2 atmospheres. The result is that the display panel has qualified TFT performance, but fails after 12 hours under the PCT test, and the failure rate of each batch fluctuates, ranging from 40% to 100%.

[0139] Example 3

[0140] A display panel prepared in the same manner as Comparative Example 3-1, except that a water isolation layer 120 as shown in the figure is provided. The TFT performance of the manufactured display panel is measured and PCT test is carried out. The result is that the display panel can withstand the 24-hour PCT test, and the failure rate of each batch is stable, and the TFT performance is also completely qualified. The comparison result with the result of Comparative Example 3-1 shows that setting the water isolation layer of the present disclosure can maintain the qualified TFT performance while ensuring that the display panel withstands the PCT test. Figure 10 The thin film transistor liquid crystal display panel provided by the present disclosure can prevent the exhaust of the organic film from affecting the TFT performance while ensuring the waterproofness of the display panel under harsh conditions.

[0141] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

[0142] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. A thin film transistor liquid crystal display panel, the display panel having an active display area and a border area, and comprising: An array substrate, a counter substrate opposite to the array substrate, the array substrate including a substrate layer and thin film transistors on a side of the substrate layer close to the counter substrate; A liquid crystal layer and spacers between the array substrate and the counter substrate; And A sealant in the border area for bonding the array substrate and the counter substrate, a positive projection of the sealant on the substrate layer divides the border area into an inner area surrounded by the positive projection of the sealant, a sealant area where the positive projection of the sealant is located, and an outer area outside the positive projection of the sealant, Wherein, the display panel further includes a first passivation protection layer on a side of the thin film transistor close to the counter substrate, an organic film layer on a side of the first passivation protection layer close to the counter substrate, and a second passivation protection layer on a side of the organic film layer close to the counter substrate, wherein the permeability of the exhaust gas of the organic film layer to the second passivation protection layer is higher than that to the first passivation protection layer in the active display area and the border area, and wherein the material of the second passivation protection layer is a material with relatively less dense texture compared with the material of the first passivation protection layer, Wherein, a positive projection of the second passivation protection layer on the substrate layer extends to the outer area, Wherein, the display panel further includes a water isolation layer, the water isolation layer covers a part of the positive projection of the second passivation protection layer on the substrate layer in the outer area, so that the second passivation protection layer does not contact the external environment of the display panel.

2. The display panel according to claim 1, wherein, The thin film transistor is an oxide thin film transistor.

3. The display panel according to claim 1, wherein, The display panel further includes a pixel electrode layer on a side of the second passivation protection layer close to the counter substrate in the active display area, and The water isolation layer is arranged on the same layer as the pixel electrode layer.

4. The display panel according to any one of claims 1-3, wherein, The material of the water isolation layer includes indium tin oxide.

5. The display panel according to claim 1, wherein, The water isolation layer extends into the interior of the display panel through between the second passivation protection layer and the sealant, so that a positive projection of the water isolation layer on the substrate layer extends to the inner area.

6. The display panel according to claim 1, wherein, The water isolation layer covers a part of the positive projection of all layers of the array substrate except the substrate layer on the substrate layer in the outer area, so that all layers of the array substrate except the substrate layer do not contact the external environment of the display panel.

7. The display panel according to claim 1, wherein, An outer edge of a positive projection of the water isolation layer on the substrate layer is located in the outer area and has a certain distance from the edge of the display panel, and the distance is not zero.

8. The display panel according to claim 1, wherein, A positive projection of the water isolation layer on the substrate layer covers the entire outer area.

9. The display panel according to claim 1, wherein, the display panel further includes a pixel electrode layer on one side of the second passivation protection layer close to the counter substrate in the effective display area, and the water isolation layer is arranged on the same layer as the pixel electrode layer, and the display panel further includes a via conduction medium layer arranged on the same layer as the pixel electrode layer and the water isolation layer, and the water isolation layer is disconnected from the via conduction medium layer.

10. A method for manufacturing the display panel according to any one of claims 1-9, the method comprising the following steps: after forming the second passivation protection layer, simultaneously forming the pixel electrode layer and the water isolation layer by a mask deposition method, and after forming the water isolation layer, bonding the array substrate and the counter substrate with a sealing glue.

11. The method according to claim 10, wherein, before the water isolation layer formed by the mask deposition method, a predetermined sealing glue area is set; the inner edge of the orthographic projection of the water isolation layer formed by the mask deposition method on the substrate layer is within the inner edge of the orthographic projection of the predetermined sealing glue area on the substrate layer, and the distance from the inner edge of the orthographic projection of the predetermined sealing glue area on the substrate layer is 1.8 μm or more, applying the sealing glue in the predetermined sealing glue area to bond the array substrate and the counter substrate with the sealing glue.

Images