Multi-chip package

Abstract

A multi-chip package is provided. The multi-chip package includes: a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control the driving strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to: receive first test data and second test data from the first output driver and the second output driver whose driving strengths are set by the strength control module, respectively, and output detection data for detecting whether the first bonding wire and the second bonding wire are short-circuited based on the first test data and the second test data.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0003644, filed with the Korean Intellectual Property Office on January 11, 2019, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a multi - chip package. Background art

[0004] A plurality of semiconductor chips are mounted inside a multi - chip package. The plurality of semiconductor chips mounted inside the multi - chip package are electrically connected to each other via bonding wires inside the multi - chip package. Here, when the multi - chip package corresponds to a memory system such as an embedded multimedia card (eMMC) system and a universal flash storage (UFS) system, the plurality of semiconductor chips may include a plurality of (non - volatile) memory chips for storing data, and a memory controller for controlling and accessing the plurality of memory chips.

[0005] The bonding wires between the memory controller and the plurality of memory chips are not directly connected to the external terminals of the multi - chip package. Therefore, in the case of a defect such as a short - circuit of two bonding wires or a defect of forming an open - circuit path between the memory controller and the memory chip, it is difficult to detect the defect only by using the signal applied to the external terminals. Summary of the invention

[0006] Aspects of the present disclosure provide for accurately detecting defects such as short - circuits and open - circuit paths that may occur inside a multi - chip package.

[0007] However, aspects of the present disclosure are not limited to the content set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the following detailed description of the present disclosure.

[0008] According to an aspect of the present disclosure, there is provided a multi - chip package including: a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and an intensity control module configured to control the driving intensity of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to: receive first test data and second test data from the first output driver and the second output driver whose driving intensities are set by the intensity control module, respectively, and output detection data for detecting whether the first bonding wire and the second bonding wire are short - circuited based on the first test data and the second test data.

[0009] According to another aspect of the present disclosure, a multi-chip package is provided, including: a memory chip on a printed circuit board; a memory controller electrically connected to the memory chip through bonding wires and including an interface circuit for driving the memory chip; and a strength control module configured to control the driving strengths of an output driver of the memory chip and the interface circuit respectively, wherein the interface circuit is configured to: use the output driver of the memory chip and the interface circuit to output detection data for detecting whether there is an open channel between the memory chip and the interface circuit.

[0010] According to still another aspect of the present disclosure, a multi-chip package is provided, including: a memory chip on a printed circuit board; and a memory controller electrically connected to the memory chip through bonding wires and including an interface circuit configured to drive the memory chip, wherein the interface circuit includes: a first driving transistor configured to provide a power supply voltage to the memory chip, and a second driving transistor configured to provide a ground voltage to the memory chip, and the interface circuit is configured to: use the first driving transistor and the second driving transistor to detect whether the channel between the memory chip and the memory controller is open. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] By describing the exemplary embodiments of the present disclosure in detail with reference to the accompanying drawings, the above and other aspects and features of the present disclosure will become clearer. In the drawings:

[0012] Figure 1 is a cross-sectional view showing a multi-chip package according to an exemplary embodiment of the present disclosure;

[0013] Figure 2 is a block diagram showing the operation in the normal mode of the multi-chip package of Figure 1 ;

[0014] Figure 3 is a diagram showing an exemplary embodiment of an interface circuit 135 of the multi-chip package of Figure 2 ;

[0015] Figure 4 is a diagram showing an example of the operation in the test mode of the multi-chip package of Figure 1 ;

[0016] Figure 5 is a diagram showing an example of the operation of the interface circuit 135 of the multi-chip package of Figure 4 ;

[0017] Figure 6 is a diagram showing an example of the operation in the test mode of the multi-chip package of Figure 1 ;

[0018] Figure 7 is a diagram showing an operation example of an interface circuit 135 of a multi-chip package; Figure 6 of;

[0019] Figure 8 is a diagram showing Figure 1 the operation of a multi-chip package of;

[0020] Figure 9 is a cross-sectional view of a multi-chip package according to an example embodiment of the present disclosure;

[0021] Figure 10 is a diagram showing Figure 9 a multi-chip package of;

[0022] Figure 11 is a diagram showing the operation in Figure 9 a test mode of a multi-chip package of;

[0023] Figure 12 is a diagram showing a multi-chip package according to an example embodiment of the present disclosure;

[0024] Figure 13 is a diagram showing the operation in Figure 12 a test mode of a multi-chip package of;

[0025] Figure 14 is a diagram showing a multi-chip package according to an example embodiment of the present disclosure; and

[0026] Figure 15 is a diagram showing the operation in Figure 14 a test mode of a multi-chip package of. Detailed Description of the Embodiment

[0027] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings. However, those of ordinary skill in the art to which the present disclosure pertains will understand that the present disclosure can be implemented in other specific forms without changing the technical idea or basic features of the present disclosure. Therefore, it should be understood that the following example embodiments are illustrative and not restrictive in all respects.

[0028] Figure 1 is a cross-sectional view of a multi-chip package according to an example embodiment of the present disclosure.

[0029] Referring to Figure 1 , the multi-chip package 1 includes a package 100 and external terminals 110. In addition, the package 100 includes semiconductor chips 130 and multiple semiconductor chips 141 to 148 mounted on a printed circuit board 120.

[0030] It will be understood that, as described herein, an element "on" another element can be "above" or "below" that other element. Additionally, it will be understood that, as described herein, an element "on" another element can be directly on that other element, such that the elements are in direct contact with each other, or can be indirectly on the other element, such that the elements are isolated from direct contact with each other by one or more intermediate structures and / or spaces.

[0031] Here, the multi-chip package 1 can be a memory system that provides a large-capacity and high-speed memory device. For example, the multi-chip package 1 can be an embedded multimedia card (eMMC system) or a universal flash storage (UFS) system, which includes non-volatile memory devices (i.e., a plurality of semiconductor chips 141 to 148) based on NAND-type flash memory, and includes a memory controller (i.e., semiconductor chip 130) for controlling the non-volatile memory devices.

[0032] In this specification, for ease of explanation, assuming that the multi-chip package 1 is implemented as such a memory system, the semiconductor chip 130 will be described as the memory controller 130, and the plurality of semiconductor chips 141 to 148 will be described as the plurality of memory chips 141 to 148. However, the scope of the present disclosure is not limited thereto, and the semiconductor chip 130 and the plurality of semiconductor chips 141 to 148 can be implemented as chips including any semiconductor circuit.

[0033] On the other hand, in some exemplary embodiments of the present disclosure, the multi-chip package 1 can be implemented as a package such as a package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip-on-board (COB), ceramic dual in-line package (CERDIP), metal quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level manufacturing package (WFP), and wafer-level process stack package (WSP), but the scope of the present disclosure is not limited thereto.

[0034] As described above, the package 100 may include a memory controller 130 and a plurality of memory chips 141 to 148. In some example embodiments, the memory controller 130 may include hardware such as logic circuits; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processor may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0035] In the present example embodiment, the external terminals 110 may be implemented as a plurality of package balls, but the scope of the present disclosure is not limited thereto.

[0036] In the present example embodiment, the printed circuit board 120 may include a plurality of conductive layers separated by insulating layers therein and through electrodes (through-silicon vias TSVs). The conductive layers and through electrodes of the printed circuit board 120 may be electrically connected to the external terminals 110 of the multi-chip package 1.

[0037] The memory controller 130 may be electrically connected to the external terminals 110 of the multi-chip package 1 via bonding wires A1. The bonding wires A1 may be connected between the pads of the through electrodes of the printed circuit board 120 connected to the external terminals 110 and the pads of the memory controller 130. In some example embodiments of the present disclosure, the bonding wires A1 may be connected between the pads connected to the conductive layers of the printed circuit board 120 connected to the external terminals 110 and the pads of the memory controller 130.

[0038] Each of the plurality of memory chips 141 to 148 may include a non-volatile memory device. The non-volatile memory device may include non-volatile memory elements such as NAND type flash memories, NOR type flash memories, phase change memories (PRAMs), resistive memories (ReRAMs), and magnetoresistive memories (MRAMs). For ease of explanation, in this specification, the non-volatile memory device is described based on a NAND type flash memory.

[0039] The non-volatile memory device includes a memory cell array, which includes a plurality of memory cells formed by a plurality of rows corresponding to word lines and a plurality of columns corresponding to bit lines. Each memory cell may store 1 bit of data or M bits of data (where M is an integer of 2 or greater). Each memory cell may be implemented as a memory cell having a charge storage layer such as a floating gate or a charge trap layer, or a memory cell having a variable resistance element or the like.

[0040] The memory cell array can be implemented in a single-layer array structure or a two-dimensional array structure, or can be implemented in a multi-layer array structure or a three-dimensional array structure. In some exemplary embodiments of the present disclosure, the three-dimensional array structure may include vertically arranged NAND strings such that at least one memory cell is located above another memory cell.

[0041] Non-volatile memory devices of multiple memory chips 141 to 148 may constitute a single channel controlled by the memory controller 130. In some example embodiments of the present disclosure, non-volatile memory devices operating independently of each other may constitute a single channel. For example, multiple memory chips 141 to 144 may constitute a first channel, and multiple memory chips 145 to 148 may constitute a second channel.

[0042] Multiple memory chips 141 to 144 may be electrically connected to the memory controller 130 via bonding wires B1 to B4. The bonding wires B1 to B4 may send commands, addresses, and data provided from the memory controller 130 to multiple memory chips 141 to 144. The bonding wires B1 to B4 may constitute signal lines of the channel.

[0043] For example, the bonding wire B1 may be connected between the memory controller 130 and the memory chip 141, the bonding wire B2 may be connected between the memory chip 141 and the memory chip 142, the bonding wire B3 may be connected between the memory chip 142 and the memory chip 143, and the bonding wire B4 may be connected between the memory chip 143 and the memory chip 144.

[0044] Multiple memory chips 145 to 148 may be electrically connected to the memory controller 130 via bonding wires C1 to C4. The bonding wires C1 to C4 may send commands, addresses, and data provided from the memory controller 130 to multiple memory chips 145 to 148. The bonding wires C1 to C4 may constitute signal lines of the channel.

[0045] For example, the bonding wire C1 may be connected between the memory controller 130 and the memory chip 145, the bonding wire C2 may be connected between the memory chip 145 and the memory chip 146, the bonding wire C3 may be connected between the memory chip 146 and the memory chip 147, and the bonding wire C4 may be connected between the memory chip 147 and the memory chip 148.

[0046] The bonding wires (B1 to B4 and C1 to C4) between the memory controller 130 and multiple memory chips 141 to 148 are not directly connected to the external terminals 110 of the multi-chip package 1. However, defects may occur during the manufacturing process of the multi-chip package 1.

[0047] As an example of a defect, two or more bonding wires B4 and C1 may be short-circuited. The bonding wires for the multi-chip package 1 have a thin thickness and are made of a metal such as gold, but are not individually provided with an insulating coating. Thus, after the printed circuit board 120, the memory controller 130, the plurality of memory chips 141 to 148, etc. are all mounted on the multi-chip package 1 and the bonding wires (B1 to B4 and C1 to C4) are connected, a short circuit may occur between the bonding wires (B1 to B4 and C1 to C4) during the process of filling the material for filling the package 100A.

[0048] As another example of a defect, when some of the bonding wires (B1 to B4 and C1 to C4) connected to the memory controller 130 or the plurality of memory chips 141 to 148 are separated from the memory controller 130 or the plurality of memory chips 141 to 148 during the manufacturing process, an open channel may occur between the memory controller 130 and the memory chips 141 to 148.

[0049] However, since the bonding wires (B1 to B4 and C1 to C4) are not directly connected to the external terminals 110 of the multi-chip package 1, it is difficult to detect the defects occurring in the multi-chip package 1 only by the signals applied to the external terminals 110. Hereinafter, various exemplary embodiments of the present disclosure for accurately detecting defects such as short circuits and open channels that may occur inside the multi-chip package 1 will be described.

[0050] Figure 2 is a block diagram showing the operation of the multi-chip package in the Figure 1 normal mode. In addition, Figure 3 is a diagram showing an exemplary embodiment of the interface circuit 135 of the Figure 2 multi-chip package.

[0051] First, referring to Figure 2 and Figure 1 , the multi-chip package 1 can operate in the normal mode. The normal mode is an operation mode of the multi-chip package 1 distinguished from the test mode described later, and the memory controller 130 of the multi-chip package 1 of the present disclosure can read the data stored in the memory chips 144 and 145 in the normal mode or can record data in the memory chips 144 and 145 in the normal mode.

[0052] First, the memory chip 145 includes an output driver that outputs data to the bonding pad 1452. The output driver of the memory chip 145 may include driving transistors TR1 and TR2 that are connected in series with each other and gated by a signal S1. Here, the driving transistor TR1 may supply the power supply voltage VDD to the bonding pad 1452, and the driving transistor TR2 may supply the ground voltage to the bonding pad 1452.

[0053] The bonding pad 1452 is electrically connected to the bonding pad 133 of the memory controller 130 via a bonding wire C1. As a result, the memory controller 130 can receive the data D1 read from the memory chip 145 through the bonding pad 133.

[0054] On the other hand, the memory chip 144 includes an output driver that outputs data to the bonding pad 1442. The output driver of the memory chip 144 may include driving transistors TR3 and TR4 that are connected in series with each other and gated by a signal S2. Here, the driving transistor TR3 may supply the power supply voltage VDD to the bonding pad 1442, and the driving transistor TR4 may supply the ground voltage to the bonding pad 1442.

[0055] The bonding pad 1442 is electrically connected to the bonding pad 132 of the memory controller 130 via bonding wires B4 to B1. As a result, the memory controller 130 can receive the data D2 read from the memory chip 144 through the bonding pad 132.

[0056] In this exemplary embodiment, the memory controller 130 includes the above-mentioned bonding pads 132 and 133, and a bonding pad 139 that is electrically connected to an external terminal 110 via a bonding wire A1 Figure 1 In addition, the memory controller 130 includes an interface circuit 135 disposed between the bonding pads 132 and 133 and the bonding pad 139.

[0057] The interface circuit 135 can receive the input of the data D1 read from the memory chip 145 through the bonding pad 133, and can receive the input of the data D2 read from the memory chip 144 through the bonding pad D2. In addition, the interface circuit 135 can output one of the data D1 and D2 to the external terminal 110 via the bonding pad 139 in the normal mode.

[0058] Specifically, in this exemplary embodiment, the interface circuit 135 includes a path selection logic device 137 and a test logic device 138.

[0059] The path selection logic device 137 can operate in the normal mode or the test mode. For example, a setting value for setting the operation mode can be provided to the path selection logic device 137 from the outside, such as Figure 2"Mode = normal" in and Figure 4 as shown by "Mode = test" in. In the normal mode, the path selection logic device 137 can control the test logic device 138 to output only one output of the output drivers of the memory chip 145 and the output driver of the memory chip 144.

[0060] That is, the path selection logic device 137 can control the test logic device 138 to output only the data D1 provided by the output driver of the memory chip 145 as the data D3 among the data D1 provided by the output driver of the memory chip 145 and the data D2 provided by the output driver of the memory chip 144, where the data D1 has a first logic value H and the data D2 has a second logic value L. For this purpose, the path selection logic device 137 can provide a selection signal SEL to the test logic device 138.

[0061] Next, referring to Figure 3 , the path selection logic device 137 provides a first selection signal SEL1 and a second selection signal SEL2 for controlling the test logic device 138 to the test logic device 138.

[0062] In the normal mode, the test logic device 138 bypasses the data selected by the path selection logic device 137. However, the test logic device 138 can be implemented to include multiple logic gates G1, G2, and G3, which play their roles in the test mode described later.

[0063] Specifically, the test logic device 138 can include: a first logic gate G1 that receives the data D1 and the first selection signal SEL1 and performs a first logical operation to output intermediate data D4; a second logic gate G2 that receives the data D2 and the second selection signal SEL2 and performs a second logical operation to output intermediate data D5; and a third logic gate G3 that receives the intermediate data D4 and the intermediate data D5 and performs a third logical operation to output the data D3.

[0064] When the logic value of the first selection signal SEL1 is the first logic value H and the logic value of the second selection signal SEL2 is the second logic value L, the test logic device 138 operates in the normal mode and outputs the data D1 as the data D3. Figure 3 This situation is shown.

[0065] Alternatively, when the logic value of the first selection signal SEL1 is the second logic value L and the logic value of the second selection signal SEL2 is the first logic value H, the test logic device 138 operates in the normal mode and outputs the data D2 as the data D3.

[0066] Alternatively, when the logical values of both the first selection signal SEL1 and the second selection signal SEL2 are the second logical value L, the test logic device 138 operates in the test mode.

[0067] Specifically, when the test logic device 138 operates in the test mode, the data D1 and the data D2 are test data and the data D3 is the detected data, which will be described below with reference to Figure 8 this.

[0068] In addition, in the present exemplary embodiment, the first logical operation and the second logical operation may include a NOR logical operation, and the third logical operation may include a NAND logical operation. However, the specific implementation of the test logic device 138 is not limited to this exemplary embodiment and can be modified as much as needed.

[0069] In the present exemplary embodiment, since the path selection logic device 137 operates in the normal mode, the test logic device 138 bypasses the data selected by the path selection logic device 137, and the final memory controller 130 can output the value read from the memory chip 144 or the memory chip 145 to the external terminal 110.

[0070] Figure 4 is a block diagram showing an operation example in the test mode of a Figure 1 multi-chip package. In addition, Figure 5 is a diagram showing an operation example of the interface circuit 135 of a Figure 4 multi-chip package.

[0071] First, referring to Figure 4 this example, a short circuit occurs between the bonding wire C1 and the bonding wires B4 to B1. As a result, a circuit path is formed between the bonding pad 1452 and the bonding pad 1442.

[0072] The multi-chip package 1 can operate in a test mode for detecting defects to detect such defects. For this purpose, the multi-chip package 1 may further include an intensity control module 150. The intensity control module 150 may be implemented inside the memory controller 130 or may be implemented at any position outside the memory controller 130. In addition, the intensity control module 150 may be mounted on at least one of the plurality of memory chips 141 to 148.

[0073] The intensity control module 150 controls the driving intensities of the output drivers of the memory chip 145 and the output driver of the memory chip 144, respectively. Here, the driving intensity is related to the amount of load that can be driven by the driving transistor, and there is the following relationship: when the driving intensity is high, the amount of load that can be driven is large, and when the driving intensity is low, the amount of load that can be driven is small.

[0074] That is, the strength control module 150 sets the driving strengths of the output drivers of the memory chip 144 and the memory chip 145 to be different from each other, such that the driving strength of the output driver of the memory chip 145 does not match the driving strength of the output driver of the memory chip 144.

[0075] For example, the strength control module 150 can set the driving strength of the driving transistor TR1 of the output driver of the memory chip 145 to 1, and can set the driving strength of the driving transistor TR4 of the output driver of the memory chip 144 to 10. In addition, the multi-chip package 1 appropriately sets the signals S1 and S2, and turns on the driving transistor TR1 of the memory chip 145 and the driving transistor TR4 of the memory chip 144.

[0076] When there is no short circuit between the bonding wire C1 and the bonding wires B4 to B1, when the driving transistor TR1 of the memory chip 145 and the driving transistor TR4 of the memory chip 144 are turned on, the bonding pad 1452 and the bonding pad 133 have the first logic value H, and the bonding pad 1442 and the bonding pad 132L have the second logic value L.

[0077] When a short circuit occurs between the bonding wire C1 and the bonding wires B4 to B1, and according to the voltage division performed by setting the driving strength of the driving transistor TR4 to be greater than the driving strength of the driving transistor TR1, the bonding pads 1452, 1442, 133, and 132 all have the second logic value L.

[0078] That is, in the case of the first test data D1 provided to the memory controller 130 via the bonding pad 1452 and the bonding pad 133, a data flip occurs in which the value changes from the first logic value H to the second logic value L by the strength control module 150. As a result, the value of the data output via the bonding pad 139 also changes from the first logic value H to the second logic value L.

[0079] The strength control module 150 sets the driving strengths of the output drivers of the memory chip 144 and the memory chip 145 to be different from each other, such that the data flip of the first test data D1 or the second test data D2 occurs in this way.

[0080] Then, the interface circuit 135 receives the first test data D1 and the second test data D2 from the output drivers of the memory chip 144 and the memory chip 145 whose driving strengths are set by the strength control module 150 respectively, and outputs detection data D3 for detecting whether the bonding wire C1 and the bonding wires B4 to B1 are short-circuited according to the first test data D1 and the second test data D2.

[0081] Next, referring to Figure 5 , the path selection logic device 137 can provide a first selection signal SEL1 and a second selection signal SEL2 to the test logic device 138 for controlling the test logic device 138 to generate the detection data D3 according to the first test data D1 and the second test data D2. Here, the first selection signal SEL1 and the second selection signal SEL2 can have a second logic value L.

[0082] The first logic gate G1 of the test logic device 138 receives the first test data D1 and the first selection signal SEL1, and performs a first logic operation to generate intermediate data D4, and the second logic gate G2 receives the second test data D2 and the second selection signal SEL2, and performs a second logic operation to output intermediate data D5. In addition, the third logic gate G3 receives the intermediate data D4 and the intermediate data D5, and performs a third logic operation to output the detection data D3.

[0083] Here, when there is no short circuit between the first bonding wire C1 and the bonding wires B4 to B1, the detection data D3 includes a first logic value H, and when there is a short circuit between the bonding wire C1 and the bonding wires B4 to B1, the detection data D3 includes a second logic value L different from the first logic value H.

[0084] That is, in the present exemplary embodiment, the first test data D1 flips from the first logic value H to the second logic value L, and the value of the intermediate data D4 flips from the second logic value L to the first logic value H again, so the detection data D3 flips from the first logic value H to the second logic value L again.

[0085] That is, the intensity control module 150 sets the driving intensity of the driving transistor TR4 of the output driver of the memory chip 144 to be greater than the driving intensity of the driving transistor TR1 of the output driver of the memory chip 145, thereby causing data flipping.

[0086] Since the detection data D3 determined in this way is output via the external terminal 110, it is possible to accurately detect defects such as short circuits that may occur in the multi-chip package 1 by analyzing the detection data D3.

[0087] Figure 6 is a block diagram showing an operation example in the test mode of the multi-chip package in Figure 1 . Figure 7 is a diagram showing an operation example of the interface circuit 135 of the multi-chip package in Figure 6 .

[0088] First, referring to Figure 6, in the same manner as in the previous example, a short circuit occurs between bonding wire C1 and bonding wires B4 to B1. As a result, a circuit path is formed between bonding pad 1452 and bonding pad 1442.

[0089] In the present exemplary embodiment, the strength control module 150 may set the driving strength of the driving transistor TR3 of the output driver of the memory chip 144 to 1, and may set the driving strength of the driving transistor TR2 of the output driver of the memory chip 145 to 10. In addition, the multi-chip package 1 appropriately sets signals S1 and S2 to turn on the driving transistor TR2 of the memory chip 145 and the driving transistor TR3 of the memory chip 144.

[0090] In the case where no short circuit occurs between bonding wire C1 and bonding wires B4 to B1, when the driving transistor TR2 of the memory chip 145 and the driving transistor TR3 of the memory chip 144 are turned on, bonding pad 1452 and bonding pad 133 have the second logic value L, and bonding pad 1442 and bonding pad 132 have the first logic value H.

[0091] When a short circuit occurs between bonding wire C1 and bonding wires B4 to B1, and according to the voltage division by setting the driving strength of the driving transistor TR2 to be greater than the driving strength of the driving transistor TR3, bonding pads 1452, 1442, 133, and 132 all have the second logic value L.

[0092] That is, in the case where the second test data D2 is provided to the memory controller 130 via bonding pad 1442 and bonding pad 132, a data flip occurs in which the value changes from the first logic value H to the second logic value L by the strength control module 150. As a result, the value of the data output through bonding pad 139 also changes from the first logic value H to the second logic value L.

[0093] Next, referring to Figure 7 , here, when no short circuit occurs between the first bonding wire C1 and bonding wires B4 to B1, the detection data D3 includes the first logic value H, and when a short circuit occurs between the first bonding wire C1 and bonding wires B4 to B1, the detection data D3 includes the second logic value L different from the first logic value H.

[0094] That is, in the present exemplary embodiment, the second test data D2 flips from the first logic value H to the second logic value L, the value of the intermediate data D5 flips from the second logic value L to the first logic value H again, and thus the detection data D3 flips from the first logic value H to the second logic value L again.

[0095] That is, the intensity control module 150 sets the driving intensity of the driving transistor TR3 of the output driver of the memory chip 144 to be less than the driving intensity of the driving transistor TR2 of the output driver of the memory chip 145, thereby causing data inversion.

[0096] Since the detection data D3 determined in this way is output through the external terminal 110, defects such as short circuits that may occur inside the multi-chip package 1 can be accurately detected by analyzing the detection data D3.

[0097] Figure 8 is a table showing Figure 1 the operation of the multi-chip package.

[0098] Reference Figure 8 , case "1" corresponds to the example embodiment described in reference Figure 4 and Figure 5 , and case "2" corresponds to the example embodiment described in reference Figure 6 and Figure 7 .

[0099] In the case of "1", when the driving intensity of the driving transistor TR1 of the memory chip 145 is set to be weak in channel #0 between the memory chip 145 and the memory controller 130, and the driving intensity of the driving transistor TR4 of the memory chip 144 is set to be strong in channel #1 between the memory chip 144 and the memory controller 130, if there is a short circuit defect, since the test data D1 is inverted from the first logic value H, the detection data D3 has the second logic value L.

[0100] In the case of "2", when the driving intensity of the driving transistor TR2 of the memory chip 145 is set to be strong in channel #0 between the memory chip 145 and the memory controller 130, and the driving intensity of the driving transistor TR3 of the memory chip 144 is set to be weak in channel #1 between the memory chip 144 and the memory controller 130, if there is a short circuit defect, since the test data D2 is inverted from the first logic value H, the detection data D3 has the second logic value L.

[0101] Since the detection data D3 determined in this way is output through the external terminal 110, defects such as short circuits that may occur in the multi-chip package 1 can be accurately detected by analyzing the detection data D3.

[0102] Figure 9 is a cross-sectional view showing a semiconductor package according to an example embodiment of the present disclosure.

[0103] Reference Figure 9, the multi-chip package 1 includes a package 100 and external terminals 110. In addition, the package 100 includes a memory controller 130 and a plurality of memory chips 141 to 148 mounted on a printed circuit board 120.

[0104] The non-volatile memory devices of the plurality of memory chips 141 to 148 may constitute a single channel controlled by the memory controller 130. In some example embodiments of the present disclosure, non-volatile memory devices operating independently of each other may constitute a single channel. For example, the plurality of memory chips 141 to 144 constitute a first channel, and the plurality of memory chips 145 to 148 may constitute a second channel.

[0105] The plurality of memory chips 141 to 144 may be electrically connected to the memory controller 130 through bonding wires B1 to B4. The bonding wires B1 to B4 may send commands, addresses, and data provided from the memory controller 130 to the plurality of memory chips 141 to 144. The bonding wires B1 to B4 may constitute signal lines of the channel.

[0106] For example, the bonding wire B1 may be connected between the memory controller 130 and the memory chip 141, the bonding wire B2 may be connected between the memory chip 141 and the memory chip 142, the bonding wire B3 may be connected between the memory chip 142 and the memory chip 143, and the bonding wire B4 may be connected between the memory chip 143 and the memory chip 144.

[0107] The plurality of memory chips 145 to 148 may be electrically connected to the memory controller 130 via bonding wires C1 to C4. The bonding wires C1 to C4 may send commands, addresses, and data provided from the memory controller 130 to the plurality of memory chips 145 to 148. The bonding wires C1 to C4 may constitute signal lines of the channel.

[0108] For example, the bonding wire C1 may be connected between the memory controller 130 and the memory chip 145, the bonding wire C2 may be connected between the memory chip 145 and the memory chip 146, the bonding wire C3 may be connected between the memory chip 146 and the memory chip 147, and the bonding wire C4 may be connected between the memory chip 147 and the memory chip 148.

[0109] In this example embodiment, the memory chip 146 of the multi-chip package 1 is not connected to the bonding wire. In other words, this forms an open circuit in the channel between the memory controller 130 and the memory chip 146.

[0110] Figure 10 shows Figure 9 block diagram of the multi-chip package. In addition, Figure 11 shows inFigure 9 Block diagram of an operation example in a test mode of a multi-chip package.

[0111] Refer together Figure 10 and Figure 11 In the present exemplary embodiment, the interface circuit 135 supports on-die termination (ODT). ODT is a technique for placing a termination resistor for impedance matching of a transmission line inside a semiconductor chip. Since this technique is a well-known technique, a detailed description thereof will not be provided in this specification.

[0112] In the present exemplary embodiment, the multi-chip package 1 may further include a strength control module 150. The strength control module 150 may be implemented inside the memory controller 130, or may be implemented at any position outside the memory controller 130. Additionally, the strength control module 150 may be mounted on at least one of the plurality of memory chips 141 to 148.

[0113] The strength control module 150 controls the driving strength of the output driver of the memory chip 146 and the driving strength of the interface circuit 135, respectively. Here, the driving strength is related to the amount of load that can be driven by a driving transistor, and there is the following relationship: when the driving strength is high, the amount of load that can be driven is large, and when the driving strength is low, the amount of load that can be driven is small.

[0114] Specifically, the strength control module 150 sets the driving strength of the output driver of the memory chip 146 and the driving strength of the interface circuit 135 such that data inversion of the data output from the output driver of the memory chip 146 occurs.

[0115] For example, the output driver of the memory chip 146 includes a driving transistor TR5 that provides a power supply voltage VDD and a driving transistor TR6 that provides a ground voltage. In addition, the interface circuit 135 includes a driving transistor TR7 that provides a power supply voltage VDD and a driving transistor TR8 that provides a ground voltage.

[0116] In this case, the strength control module 150 sets the driving strength of the driving transistor TR8 to be less than the driving strength of the driving transistor TR7. In addition, the driving strength of the driving transistor TR6 is set to be greater than the driving strength of the driving transistor TR7.

[0117] In the present exemplary embodiment, since the strength control module 150 sets the driving strength of the driving transistor TR7 to 3 and sets the driving strength of the driving transistor TR8 to 1, the driving strength of the driving transistor TR8 is less than the driving strength of the driving transistor TR7.

[0118] In addition, in the present exemplary embodiment, since the strength control module 150 sets the driving strength of the driving transistor TR6 to 10, the driving strength of the driving transistor TR6 is greater than that of the driving transistor TR7.

[0119] In addition, the strength control module 150 sets the driving strength of the driving transistor TR5 to 5.

[0120] When there is no open channel between the memory chip 146 and the interface circuit 135, the value output from the memory chip 146 is sent to the bonding pad 134 and output through the bonding pad 139. In this case, since the driving strength of the driving transistor TR5 is 5 and the driving strength of the driving transistor TR6 is 10, according to the voltage division, the bonding pad 134 needs to have the second logic value L.

[0121] However, as Figure 11 shown, when an open channel occurs between the memory chip 146 and the interface circuit 135, since the driving strength of the driving transistor TR7 is 3 and the driving strength of the driving transistor TR8 is 1, according to the voltage division, the bonding pad 134 flips from the second logic value L to the first logic value H.

[0122] That is, the interface circuit 135 can use the output driver of the memory chip 146 and the interface circuit 135 whose driving strength is set by the strength control module 150 to output the detection data D6 for detecting whether an open channel occurs between the memory chip 146 and the interface circuit 135.

[0123] Here, when there is no open channel between the memory chip 146 and the interface circuit 135, the detection data D6 includes the second logic value L, and when an open channel occurs between the memory chip 146 and the interface circuit 135, the detection data D6 can include the first logic value H different from the second logic value L.

[0124] By analyzing the thus determined detection data D6, defects such as open circuits that may occur inside the multi-chip package 1 can be accurately detected.

[0125] Figure 12 is a block diagram showing a multi-chip package according to an exemplary embodiment of the present disclosure. Figure 13 is shown in Figure 12 the block diagram of an operation example in the test mode of the multi-chip package.

[0126] Refer to Figure 12, the interface circuit 135 includes a driving transistor TR9 that supplies the power supply voltage VDD to the memory chip 146, and a driving transistor TR10 that supplies the ground voltage to the memory chip 146. In the present exemplary embodiment, the driving transistor TR9 and the driving transistor TR10 can be used to detect whether the channel between the memory chip 146 and the memory controller 130 is open.

[0127] In the present exemplary embodiment, the memory chip 146 further includes: bonding pads 1462 electrically connected to bonding wires C1 to C2; and a pull-up circuit 1464 electrically connected to the bonding pads 1462 to pull up the bonding pads 1462. Here, the configuration of the pull-up circuit 1464 is not limited to a specific circuit, and can be implemented as any circuit that pulls up the voltage level of the bonding pads 1462. In addition, the pull-up circuit 1464 can be implemented inside the memory chip 146 or can be implemented outside the memory chip 146.

[0128] In the test mode, the pull-up circuit 1464 of the memory chip 146 and the driving transistor TR10 of the interface circuit can be turned on.

[0129] As Figure 12 shown, when there is no open channel between the memory chip 146 and the memory controller 130, the amount of current flowing through the driving transistor TR10 increases. As Figure 13 shown, when there is an open channel between the memory chip 146 and the memory controller 130, the amount of current flowing through the driving transistor TR10 does not increase.

[0130] Therefore, in the present exemplary embodiment, it is possible to detect whether the channel between the memory chip 146 and the memory controller 130 is open by monitoring the change in the amount of current flowing through the driving transistor TR10.

[0131] Figure 14 is a block diagram showing a multi-chip package according to an exemplary embodiment of the present disclosure. Figure 15 is shown in Figure 14 the operation example in the test mode of the multi-chip package.

[0132] Refer to Figure 14 , the interface circuit 135 includes a driving transistor TR9 that supplies the power supply voltage VDD to the memory chip 146, and a driving transistor TR10 that supplies the ground voltage to the memory chip 146. In addition, in the present exemplary embodiment, the driving transistor TR9 and the driving transistor TR10 can be used to detect whether the channel between the memory chip 146 and the memory controller 130 is open.

[0133] In this exemplary embodiment, the memory chip 146 further includes: bonding pads 1462 electrically connected to bonding wires C1 to C2; and a pull-down circuit 1466 electrically connected to the bonding pads 1462 to pull down the bonding pads 1462. Here, the configuration of the pull-down circuit 1466 is not limited to a specific circuit and can be implemented as any circuit that pulls down the voltage level of the bonding pads 1462. In addition, the pull-down circuit 1466 can be implemented inside the memory chip 146 or can be implemented outside the memory chip 146.

[0134] In the test mode, the pull-down circuit 1466 of the memory chip 146 and the driving transistor TR9 of the interface circuit can be turned on.

[0135] As Figure 14 shown, when there is no open channel between the memory chip 146 and the memory controller 130, the amount of current flowing through the driving transistor TR9 increases. As Figure 15 shown, when there is an open channel between the memory chip 146 and the memory controller 130, the amount of current flowing through the driving transistor TR9 does not increase.

[0136] Therefore, in this exemplary embodiment, it is possible to detect whether the channel between the memory chip 146 and the memory controller 130 is open by monitoring the change in the amount of current flowing through the driving transistor TR9.

[0137] According to the various exemplary embodiments of the present disclosure described so far, defects such as short circuits and open circuits that may occur inside the multi-chip package can be accurately detected.

[0138] At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the exemplary embodiments without substantially departing from the principles of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are disclosed only for general and descriptive purposes and not for the purpose of limitation.

Claims

1. A multi-chip package, comprising: a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; as well as a strength control module configured to control the driving strength of each of the first output driver of the first memory chip and the second output driver of the second memory chip, The memory controller includes an interface circuit, and the interface circuit is configured to: receiving first test data and second test data from the first output driver and the second output driver, respectively, whose drive strengths are set by the strength control module; and outputting detection data for detecting whether the first bonding wire and the second bonding wire are short-circuited based on the first test data and the second test data, Wherein, the interface circuit includes a path selection logic device and a test logic device, The path selection logic device is configured to provide the test logic device with a first selection signal and a second selection signal for controlling the test logic device, and The test logic device comprises: a first logic gate configured to receive the first test data and the first selection signal and perform a first logic operation to output first intermediate data, a second logic gate configured to receive the second test data and the second selection signal and perform a second logic operation to output second intermediate data, and a third logic gate configured to receive the first intermediate data and the second intermediate data and perform a third logic operation to output the detection data, The strength control module is configured to set the driving strength of the first output driver and the driving strength of the second output driver to be different from each other.

2. The multi-chip package according to claim 1, wherein: The strength control module is configured to set the driving strength of the first output driver and the driving strength of the second output driver to be different from each other, so that data inversion of the first test data or the second test data occurs.

3. The multi-chip package according to claim 2, wherein: The strength control module is configured to set the driving strength of the driving transistor of the second output driver to be greater than the driving strength of the driving transistor of the first output driver.

4. The multi-chip package according to claim 2, wherein: The strength control module is configured to set the driving strength of the driving transistor of the second output driver to be smaller than the driving strength of the driving transistor of the first output driver.

5. The multi-chip package according to claim 1, wherein Based on operating in a test mode, the path selection logic device is configured to control the test logic device to generate the detection data according to the first test data and the second test data. The multi-chip package according to claim 5 , wherein: Based on operation in a normal mode, the path selection logic device is configured to control the test logic device to select only one output of the first output driver and the second output driver.

7. The multi-chip package according to claim 1, wherein: The test logic device outputs the detection data to an external terminal through a bonding pad.

8. The multi-chip package according to claim 1, wherein Based on the fact that no short circuit occurs between the first bonding wire and the second bonding wire, the detection data includes a first logic value, and Based on the occurrence of a short circuit between the first bonding wire and the second bonding wire, the detection data includes a second logic value, the second logic value being different from the first logic value.

9. A multi-chip package, comprising: memory chips on printed circuit boards; a memory controller electrically connected to the memory chip through bonding wires and comprising an interface circuit for driving the memory chip; as well as a strength control module configured to control the drive strength of the output driver of the memory chip and the drive strength of the interface circuit respectively; wherein the interface circuit is configured to: use the output driver of the memory chip and the interface circuit to output detection data for detecting whether an open channel exists between the memory chip and the interface circuit; The strength control module is configured to respectively set the driving strength of the output driver of the memory chip and the driving strength of the interface circuit, so that data flipping of data output from the interface circuit occurs.

10. The multi-chip package according to claim 9, wherein The interface circuit includes a first driving transistor configured to provide a power supply voltage, and a second driving transistor configured to provide a ground voltage, and The intensity control module is configured to set the driving intensity of the second driving transistor to be smaller than the driving intensity of the first driving transistor. The multi-chip package according to claim 10 , wherein: The strength control module is configured to set the driving strength of the third driving transistor of the memory chip to be greater than the driving strength of the first driving transistor.

12. The multi-chip package according to claim 9, wherein Based on the absence of an open channel between the memory chip and the interface circuit, the detection data includes a first logic value, and based on the presence of an open channel between the memory chip and the interface circuit, the detection data includes a second logic value, the second logic value being different from the first logic value.

13. A multi-chip package, comprising: memory chips on printed circuit boards; as well as a memory controller electrically connected to the memory chip through bonding wires and including an interface circuit configured to drive the memory chip, Wherein, the interface circuit includes: a first driving transistor configured to provide a power supply voltage to the memory chip, and a second driving transistor configured to provide a ground voltage to the memory chip; and The interface circuit is configured to detect whether a channel between the memory chip and the memory controller is open using a change in an amount of current flowing through the first drive transistor or the second drive transistor.

14. The multi-chip package according to claim 13, wherein: The memory chip comprises: a bonding pad electrically connected to the bonding wire, and The pull-up circuit is electrically connected to the bonding pad to pull up the voltage level of the bonding pad.

15. The multi-chip package according to claim 14, wherein Based on the absence of an open channel between the memory chip and the memory controller, the amount of current flowing through the second driving transistor increases, and based on the presence of an open channel between the memory chip and the memory controller, the amount of current flowing through the second driving transistor does not increase.

16. The multi-chip package according to claim 13, wherein: The memory chip comprises: a bonding pad electrically connected to the bonding wire, and The pull-down circuit is electrically connected to the bonding pad to pull down the bonding pad.

17. The multi-chip package according to claim 16, wherein: Based on the absence of an open channel between the memory chip and the memory controller, the amount of current flowing through the first driving transistor increases, and based on the presence of an open channel between the memory chip and the memory controller, the amount of current flowing through the first driving transistor does not increase.

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