Organic light emitting diode display device and manufacturing method thereof

Abstract

An organic light-emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes: a substrate including a display area and a pad area; a first thin-film transistor disposed on the display area; an organic light-emitting diode (OLED) connected to the first thin-film transistor; a pad electrode disposed on the pad area; and a pad contact electrode disposed on an upper portion of the pad electrode and electrically connected to the pad electrode. The OLED includes an anode, an organic emission layer, and a cathode. The anode includes a lower layer, an intermediate layer, and an upper layer. The pad contact electrode is formed from the material of the anode's lower layer.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0005325 filed on January 15, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to an organic light emitting diode display and a manufacturing method thereof, and more particularly, to an organic light emitting diode display including a three-layer structure and a manufacturing method thereof. Background Art

[0003] As a display device for displaying images, an organic light emitting diode (OLED) display has received a lot of attention.

[0004] Unlike liquid crystal display (LCD) devices, OLED displays have the characteristic of eliminating the self-emission of light sources, so they can be made thinner and lighter. In addition, OLED displays have high-quality characteristics such as low power consumption, high brightness, and high response speed.

[0005] However, compared to liquid crystal displays, OLED displays have a complex pixel structure, use more masks, and require long processing time.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the Invention

[0007] The present invention has been made in an effort to provide an organic light emitting diode display that can be manufactured by using fewer masks and a method of manufacturing the same.

[0008] According to an exemplary embodiment, an organic light-emitting diode display includes: a substrate including a display area and a pad area; a first thin-film transistor disposed on the display area; an organic light-emitting diode connected to the first thin-film transistor; a pad electrode disposed on the pad area; and a pad contact electrode disposed on an upper portion of the pad electrode and electrically connected to the pad electrode. The organic light-emitting diode includes an anode, an organic emission layer, and a cathode. The anode includes a lower layer, an intermediate layer, and an upper layer. The pad contact electrode is formed from the material of the lower layer of the anode.

[0009] The pad electrode may extend from a signal line connected to the first thin film transistor.

[0010] The lower layer may include titanium (Ti).

[0011] The middle layer may contain silver (Ag), and the upper layer may contain indium tin oxide (ITO) or a transparent conductive material other than indium tin oxide.

[0012] The organic light emitting diode display may further include an upper insulating layer disposed below the lower layer. The upper insulating layer may include an organic material.

[0013] The lower layer can contact the upper insulating layer to increase adhesion to the upper insulating layer and prevent silver (Ag) of the intermediate layer from diffusing downward toward the first thin film transistor. The intermediate layer can reflect light emitted from the organic emission layer upward, and the upper layer can inject holes into the organic emission layer.

[0014] The first thin film transistor disposed on the display area may be a driving transistor.

[0015] The organic light emitting diode display may further include: a second thin film transistor disposed on the display area to transmit the data voltage to the gate electrode of the driving transistor; and a third thin film transistor disposed on the display area to initialize the voltage of the output side electrode of the driving transistor.

[0016] The organic light emitting diode display may further include a data line to which a data voltage is transmitted. The pad electrode may be an extension of the data line into the pad region.

[0017] The organic light emitting diode display may further include a driving voltage line configured to transmit a driving voltage to the driving transistor, a driving low voltage line configured to transmit a driving low voltage to the cathode, and an initialization voltage line connected to the third thin film transistor.

[0018] The organic light emitting diode display may further include a metal layer disposed between the first semiconductor layer of the driving transistor and the substrate.

[0019] The organic light emitting diode display may further include a cover layer covering the organic light emitting diode to prevent moisture or air from penetrating into the organic light emitting diode. The cover layer may include a first inorganic layer, an organic layer, and a second inorganic layer stacked on each other.

[0020] The organic light-emitting diode display may further include: an upper substrate facing the substrate; a light-blocking layer disposed on the upper substrate and having an opening; and a color conversion layer disposed in the opening of the light-blocking layer. The color conversion layer may convert light emitted from the organic emission layer into one of three primary colors.

[0021] According to an exemplary embodiment of the present inventive concept, a method for manufacturing an organic light-emitting diode display may be provided as follows: A substrate including a display region and a pad region is prepared; an upper insulating layer is formed on the substrate; a preheat treatment is performed on the upper insulating layer; and multiple layers including a lower layer are formed on the upper insulating layer. The multiple layers form an anode and a pad contact electrode of the organic light-emitting diode in the display region and the pad region, respectively.

[0022] The preheating treatment may be performed at a temperature of 120° C. for 1 to 3 minutes.

[0023] The lower layer may include titanium (Ti).

[0024] The plurality of layers may further include an intermediate layer including silver (Ag) and an upper layer including indium tin oxide (ITO) or a transparent conductive material other than ITO.

[0025] The step of forming an anode and a pad contact electrode of an organic light emitting diode may include the following steps: patterning the multiple layers to form multiple first patterned layers serving as anodes of the organic light emitting diode and multiple second patterned layers serving as preliminary pad contact electrodes in the display area and the pad area, respectively; and removing the multiple second patterned layers except the patterned lower layer serving as the pad contact electrode in the pad area.

[0026] The plurality of layers further include an intermediate layer and an upper layer. Patterning the plurality of layers may include sequentially stacking a lower layer, an intermediate layer, an upper layer, and a photoresist and exposing the photoresist to light to form a photoresist pattern; wet-etching the intermediate layer and the upper layer using the photoresist pattern as a mask; and dry-etching the lower layer. Removing the plurality of second patterned layers may include removing the photoresist pattern on the pad region; and wet-etching the upper layer and the intermediate layer on the pad region.

[0027] The photoresist pattern may be formed by using a half-tone mask so that a thickness of the photoresist pattern on the pad area may be smaller than a thickness of the photoresist pattern on the display area.

[0028] The manufacturing method may further include, between the step of preparing the substrate and the step of forming the upper insulating layer: forming a buffer layer on the substrate; forming a semiconductor layer on the buffer layer; forming a gate insulating layer on the semiconductor layer; forming a gate conductive layer on the gate insulating layer; forming an interlayer insulating layer on the gate conductive layer; forming a data conductive layer on the interlayer insulating layer; and forming a passivation layer on the data conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A cross-sectional view of an organic light emitting diode display according to an exemplary embodiment is shown.

[0030] Figure 2 A manufacturing sequence of an organic light emitting diode display according to an exemplary embodiment is shown.

[0031] Figure 3 is a detailed view illustrating an anode manufacturing process in a manufacturing process of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0032] Figures 4 to 13 It is shown according to each manufacturing step Figure 1 A cross-sectional view of an organic light emitting diode display.

[0033] Figure 14 An equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment is shown.

[0034] Figure 15 A timing diagram illustrating signals applied to one pixel of an organic light emitting diode display according to an exemplary embodiment is shown.

[0035] Figure 16 A layout diagram of pixels of an organic light emitting diode display according to an exemplary embodiment is shown.

[0036] Figure 17 Shown along Figure 16 A sectional view taken along line XVII-XVII.

[0037] Figure 18 A layout diagram of a pad area according to an exemplary embodiment is shown.

[0038] Figure 19 Shown along Figure 18 A sectional view taken along line XIX-XIX.

[0039] Figure 20 A cross-sectional view of an organic light emitting diode display according to an exemplary embodiment is shown.

[0040] Figures 21 to 23 Graphs showing etching effects depending on the preheat treatment process. DETAILED DESCRIPTION

[0041] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art will realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.

[0042] In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals designate the same or similar constituent elements throughout the specification.

[0043] In addition, since the sizes and thicknesses of the components shown in the drawings are arbitrarily given for better understanding and ease of description, the present invention is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0044] It will be understood that when an element, such as a layer, film, region, or substrate, is referred to as being "on" another element, the element can be directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, the terms "above" or "on" mean being above or below a target portion, and do not necessarily mean being on the upper side of a target portion based on the direction of gravity.

[0045] In addition, unless explicitly described to the contrary, the word “comprise” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0046] Furthermore, in the specification, the phrase "in a plan view" means when the target portion is viewed from above, and the phrase "in a cross-sectional view" means when a cross section taken by vertically cutting the target portion is viewed from the side.

[0047] In the following, reference will be made to Figure 1 An organic light emitting diode display according to an exemplary embodiment is described.

[0048] Figure 1 A cross-sectional view of an organic light emitting diode display according to an exemplary embodiment is shown.

[0049] According to the present exemplary embodiment, the organic light emitting diode display includes a substrate 10, a metal layer 115, a buffer layer 11, a first semiconductor layer 121, a gate insulating layer 12, gate conductive layers 154 and 154-1, an interlayer insulating layer 13, data conductive layers 161, 161-1, 175, and 171-1, a passivation layer 14, an upper insulating layer 15, an anode 191, an organic emission layer 35, a cathode 196, a spacer 30, and a pad (or "pad") contact electrode 197. Here, the anode 191, the organic emission layer 35, and the cathode 196 together constitute an organic light emitting diode (OLED).

[0050] The organic light emitting diode and the thin film transistor connected thereto are formed on a substrate 10. The substrate 10 may be formed as a rigid substrate such as glass. However, the present invention is not limited thereto. According to another exemplary embodiment, the substrate 10 may be formed of a flexible film such as plastic or polyimide (PI).

[0051] The metal layer 115 is formed on the substrate 10. The metal layer 115 can be formed of a conductive metal material. The metal material used for the metal layer 115 can include titanium (Ti), molybdenum (Mo), copper (Cu), etc., and can be formed into a single-layer structure using only a single metal material or a double-layer structure using two metal materials. For example, a double-layer structure can be obtained by forming titanium (Ti) as a lower layer and copper (Cu) as an upper layer. In order to improve the performance of the thin film transistor, the metal layer 115 is formed at the position of the first semiconductor layer 121 in which the thin film transistor is to be formed, thereby constantly maintaining the voltage characteristics of the first semiconductor layer 121.

[0052] The substrate 10 and the metal layer 115 are covered with a buffer layer 11. The buffer layer 11 may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed as an inorganic insulating layer.

[0053] A first semiconductor layer 121 is formed on the buffer layer 11. The first semiconductor layer 121 may be formed of an oxide semiconductor. For ease of description, in this exemplary embodiment, it is assumed that the first semiconductor layer 121 is formed of indium gallium zinc oxide (IGZO). The first semiconductor layer 121 is formed at a location where a thin film transistor is to be formed and includes a channel region, a source region, and a drain region.

[0054] The first semiconductor layer 121 and the buffer layer 11 are covered by a gate insulating layer 12. The gate insulating layer 12 may be formed to include, for example, silicon oxide (SiO x ) inorganic insulating layer. According to another exemplary embodiment, the gate insulating layer 12 may include silicon nitride (SiN x ). The gate insulating layer 12 of this exemplary embodiment is formed only in the region where the gate conductive layers 154 and 154 - 1 to be described later are provided. However, the present invention is not limited thereto. For example, the gate insulating layer 12 may be formed on the entire region of the substrate 10.

[0055] Gate conductive layers 154 and 154-1 are formed on the gate insulating layer 12. The gate conductive layers 154 and 154-1 include a gate electrode 154 and a first electrode 154-1 for a storage capacitor, respectively. The gate electrode 154 is formed at a position overlapping the channel region of the first semiconductor layer 121. The gate insulating layer 12 having the same shape as the gate electrode 154 is disposed between the gate electrode 154 and the first semiconductor layer 121. The gate insulating layer 12 having the same shape as the first electrode 154-1 for the storage capacitor is also formed below the first electrode 154-1. According to another exemplary embodiment, the gate electrode 154 and the first electrode 154-1 for the storage capacitor may be electrically connected to each other. The gate conductive layers 154 and 154-1 may be formed of a metal material. In this embodiment, the gate conductive layers 154 and 154-1 are formed to have a double-layer structure including a lower layer containing titanium (Ti) and an upper layer containing copper (Cu). However, the present invention is not limited to this. According to another exemplary embodiment, the gate conductive layers 154 and 154 - 1 may be formed of a single layer or may be formed of various metal materials.

[0056] The exposed buffer layer 11, the gate conductive layers 154 and 154-1 having exposed side surfaces, and the gate insulating layer 12 having exposed side surfaces are covered with an interlayer insulating layer 13. The interlayer insulating layer 13 may be made of a material such as silicon oxide (SiO x ), silicon nitride (SiN x ) or an inorganic insulating layer of silicon oxynitride (SiON). The interlayer insulating layer 13 may be formed of an inorganic insulating layer, and it may be thickly formed to have a specific thickness or greater. In the case of an inorganic insulating layer, a step provided at the lower portion of the layer is also provided at the upper portion thereof, but when the inorganic insulating layer is thickly formed, the step at the lower portion may be provided less at the upper portion, thereby reducing the step. In an exemplary embodiment, the interlayer insulating layer 13 may provide a flattened surface for subsequent processes thereof.

[0057] Openings 50 and 51 for exposing the source and drain regions of the first semiconductor layer 121 are respectively formed in the interlayer insulating layer 13. In addition, an opening 71 exposing the metal layer 115 is formed in the interlayer insulating layer 13 and the buffer layer 11.

[0058] The data conductive layers 161, 161-1, 175, and 171-1 are formed on the interlayer insulating layer 13. The data conductive layers 161, 161-1, 175, and 171-1 include an output side electrode 161, an input side electrode 175 (hereinafter also referred to as a driving voltage line), a second electrode 161-1 for a storage capacitor, and a pad electrode 171-1.

[0059] The output-side electrode 161 is electrically connected to the drain region of the first semiconductor layer 121 of the thin film transistor through the opening 50, and is electrically connected to the metal layer 115 through another opening 71. That is, as an electrode for transmitting the output of the thin film transistor to another element, the drain electrode (i.e., the output-side electrode 161) can transmit the output of the thin film transistor to the metal layer 115. In addition, the drain electrode can transmit the output current of the thin film transistor to the anode 191 to be described later. The input-side electrode 175 is electrically connected to the source region of the first semiconductor layer 121 of the thin film transistor through the opening 51.

[0060] Although not shown, the input side electrode 175 may be electrically connected to a driving voltage line to which the driving voltage ELVDD is applied. As a result, the thin film transistor may transmit an output current to the output side electrode 161 by utilizing a voltage difference between the input side electrode 175 and the gate electrode 154 .

[0061] The second electrode 161-1 for the storage capacitor is formed on the first electrode 154-1 for the storage capacitor and constitutes a storage capacitor together with the first electrode 154-1 for the storage capacitor and the interlayer insulating layer 13 provided therebetween. The second electrode 161-1 for the storage capacitor can be connected to a specific terminal and, in this exemplary embodiment, can be electrically connected to the output-side electrode 161. According to another exemplary embodiment, the second electrode 161-1 for the storage capacitor can be electrically connected to a driving voltage line to which the driving voltage ELVDD is applied.

[0062] The pad electrode 171-1 is provided on the data line 171 (see Figure 14 ) and is disposed in a pad region located around a display region, rather than in a display region for displaying an image. The data voltage transmitted to the pad electrode 171-1 may be transmitted to each pixel PX through a data line 171 (see FIG. Figure 14 ).

[0063] The data conductive layers 161, 161-1, 175, and 171-1 may be formed of a metal material. In this exemplary embodiment, they are formed into a double-layer structure including a lower layer containing titanium (Ti) and an upper layer containing copper (Cu). However, the present invention is not limited thereto. In an exemplary embodiment, the data conductive layers 161, 161-1, 175, and 171-1 may be formed of a single layer or may be formed of various metal materials.

[0064] The passivation layer 14 is formed on the data conductive layers 161, 161-1, 175, and 171-1 and the exposed interlayer insulating layer 13. The passivation layer 14 may be formed of an inorganic insulating layer such as silicon oxynitride (SiON). The present invention is not limited thereto. In an exemplary embodiment, the passivation layer 14 may be formed of silicon oxide (SiOx ) or silicon nitride (SiN x )form.

[0065] The upper insulating layer 15 is formed on the passivation layer 14. In the present exemplary embodiment, the upper insulating layer 15 may be formed of an organic insulator such as polyimide (PI). The present invention is not limited thereto. According to another exemplary embodiment, the upper insulating layer 15 may be formed of various organic insulating materials.

[0066] The passivation layer 14 and the upper insulating layer 15 include an opening 81 exposing the output-side electrode 161 and an opening 84 exposing the pad electrode 171 - 1 located in the pad region.

[0067] An anode 191 having a three-layer structure and a pad contact electrode 197 having a single-layer structure are formed on the upper insulating layer 15. The anode 191 and the pad contact electrode 197 can be formed using the same process, and the pad contact electrode 197 can be formed by removing at least one layer of the anode 191 having multiple layers. For example, the anode 191 has a three-layer structure, and the pad contact electrode 197 has a single-layer structure formed by removing two layers of the three-layer structure. For example, the anode 191 may include a lower layer 191a containing titanium (Ti), an intermediate layer 191b containing silver (Ag), and an upper layer 191c containing indium tin oxide (ITO), and the pad contact electrode 197 may be formed of the same layer as the lower layer 191a of the anode 191. In an exemplary embodiment, the pad contact electrode 197 and the lower layer 191a of the anode 191 may be layers containing titanium (Ti). However, the present invention is not limited thereto. In exemplary embodiments, the lower layer 191 a of the anode 191 may be formed of various conductive materials including a transparent conductive material such as ITO or indium zinc oxide (IZO), in addition to a metal material.

[0068] The anode 191 is electrically connected to the output side electrode 161 through the opening 81 formed in the passivation layer 14 and the upper insulating layer 15. As a result, the output current of the output side electrode 161 is transmitted to the anode 191 which is one electrode of the organic light emitting diode (OLED).

[0069] The pad contact electrode 197 is electrically connected to the pad electrode 171-1 through the opening 84 formed in the passivation layer 14 and the upper insulating layer 15. That is, the data voltage supplied from the outside (data driver) is transmitted to the pad contact electrode 197 and transmitted to the data line 171 through the pad electrode 171-1. The pad contact electrode 197 can be formed to be wider than the pad electrode 171-1 to easily receive the voltage from the outside. In addition, the pad contact electrode 197 is exposed to be connected to a connector (not shown) and will be covered by the connector when the connector is connected to it.

[0070] In the present exemplary embodiment, because the upper layers of the multiple layers of the data conductive layers 161, 161-1, 175, and 171-1 may contain copper (Cu), their contact characteristics may be poor when electrically connected to the pad contact electrode 197 and the anode 191 through the openings 81 and 84. In the exemplary embodiment, the contact characteristics of the upper layers of each of the data conductive layers 161, 161-1, 175, and 171-1 may include their adhesion to each of the pad contact electrode 197 and the anode 191. To overcome this poor contact characteristic, a layer for improving the contact characteristic may be additionally formed. However, according to the exemplary embodiment of the present invention, without an additional process, the contact characteristics with copper (Cu) are improved by making the lower layer 191a of the anode 191 and the pad contact electrode 197 contain titanium (Ti), without forming an additional layer (e.g., an ITO layer).

[0071] The organic emission layer 35 and the partition wall 30 are formed on the anode 191. In this exemplary embodiment, the partition wall 30 may be formed of an organic material such as polyimide (PI). The partition wall 30 may define the position where the organic emission layer 35 will be formed and may be formed along the outer periphery of the anode 191.

[0072] The organic emission layer 35 is formed in the opening 30-1 defined by the partition wall 30. Figure 1 , but auxiliary layers such as an electron injection layer, an electron transport layer, a hole transport layer, or a hole injection layer are also included above and / or below the organic emission layer 35. The organic emission layer 35 may be formed to emit red, green, or blue light depending on its type. However, in Figure 20 In an exemplary embodiment, a layer for displaying a single color may be further included, and the emission layer may be configured to display one color. In other words, all light emitted through the organic emission layer 35 may display the same color, but the color conversion layer 230, which will be described later, provided in each pixel PX may display three primary colors of light such as red, green, and blue.

[0073] Cathode 196 is formed as a transparent conductive layer on partition wall 30 and organic emission layer 35. That is, light emitted from organic emission layer 35 is transmitted to the outside through cathode 196, making the light visible to the user's eyes. This structure is called a front emission structure.

[0074] The anode 191, the organic emission layer 35, the partition wall 30, and the cathode 196 are not formed in the pad region but are formed in the display region.

[0075] Although not shown, Figure 20 A capping layer 240 is formed on the cathode electrode 196 to block air or moisture from penetrating into the organic emission layer 35 .

[0076] The thin film transistor described above may be a driving transistor that generates an output current to control the emission level of an organic light emitting diode (OLED).

[0077] The organic light-emitting diode display is divided into a display area and a pad area. The pad area refers to the peripheral area where the pad electrode 171-1 is provided, and the display area refers to the area other than the pad area. According to another exemplary embodiment, the pad area may be included in the peripheral area, and the peripheral area is the area surrounding the display area. The display area is the area in which pixels PX including organic light-emitting diodes (OLEDs) are formed to display images.

[0078] In the following, reference will be made to Figures 2 to 15 Description based on Figure 1 An exemplary embodiment of a method for manufacturing an organic light emitting diode display.

[0079] Figure 2 shows a manufacturing sequence of an organic light emitting diode display according to an exemplary embodiment, Figure 3 is a detailed diagram illustrating an anode manufacturing process in a manufacturing process of an organic light emitting diode display according to an exemplary embodiment of the present invention, Figures 4 to 13 It is shown according to each manufacturing step Figure 1 A cross-sectional view of an organic light emitting diode display.

[0080] first, Figure 2 The manufacturing process from the substrate 10 to the partition wall 30 is shown, and Figures 4 to 13 against Figure 2 Each step is shown in Figure 1 The process completed in the exemplary embodiment of FIG. Figure 3 Shown in more detail Figure 2 The fourteenth step (Pad Anode) is divided into several steps.

[0081] In the following, reference will be made to Figure 2 The steps corresponding to Figures 4 to 13 To describe Figure 2 The various steps of the present invention will be described when describing the fourteenth step (Pad Anode). Figure 3 Detailed steps.

[0082] First, in Figure 2 In order to easily distinguish each step, the steps are classified by sequentially numbering the steps in a box, and the reference numerals located outside the box are represented by the reference numerals of the layers or components related to the steps to identify the layers or components formed. Figure 2 In FIG. 1 , a process using a mask is represented by M, and the number before M represents the number of the mask.

[0083] Figure 2 The first step (Glass substrate) represents a step of preparing the substrate 10. In the present exemplary embodiment, a glass substrate is used as the substrate 10.

[0084] The second step (BML) represents a step of forming a metal layer 115 on the substrate 10. Figure 2 , the "1M" in the second step means that the metal layer 115 is formed by using a first mask 1M. That is, after the material for forming the metal layer 115 is stacked, the metal layer 115 is patterned using the first mask 1M. In this case, a photoresist is stacked on the material for forming the metal layer 115, and a photoresist pattern is first formed by exposing the photoresist using the first mask 1M, and then the material for forming the metal layer 115 is patterned according to the photoresist pattern to form the metal layer 115. Unless otherwise described, each layer can be formed in the same manner as described above. The metal material for the metal layer 115 can be titanium (Ti), molybdenum (Mo), copper (Cu), etc., and can be formed to have a single-layer structure using only a single metal material or a double-layer structure using two metal materials. For example, a double-layer structure can be obtained by forming a lower layer with titanium (Ti) and an upper layer with copper (Cu).

[0085] Figure 4 , a cross-sectional view is shown after the first step (Glass substrate) and the second step (BML) are completed.

[0086] The third step (Buffer) represents a step of stacking a buffer layer 11 on the substrate 10 and the metal layer 115. In the third step (Buffer), no separate mask is used to form a pattern. The buffer layer 11 can be made of a material such as silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed as an inorganic insulating layer.

[0087] The fourth step (Active) represents a step of forming the first semiconductor layer 121 in a specific pattern on the buffer layer 11 by using the second mask 2M. The first semiconductor layer 121 may be formed of an oxide semiconductor, for example, indium gallium zinc oxide (IGZO).

[0088] Figure 5 , a cross-sectional view is shown after the third step (Buffer) and the fourth step (Active) are completed.

[0089] The fifth step (GI) represents a step of stacking the gate insulating layer 12 on the buffer layer 11 and the first semiconductor layer 121, and does not form a pattern by using a separate mask. In this case, Figure 1 Different from the above, the gate insulating layer 12 is completely stacked on the buffer layer 11 and the first semiconductor layer 121. The gate insulating layer 12 can be made of silicon oxide (SiO x ) is formed of an inorganic insulating layer. According to another exemplary embodiment, the gate insulating layer 12 may include silicon nitride (SiN x ).

[0090] The sixth step (Gate) represents a step of stacking materials for gate conductive layers 154 and 154-1 on the gate insulating layer 12 and forming the gate conductive layers 154 and 154-1 by using the third mask 3M. In this case, the gate insulating layer 12 provided below the gate conductive layers 154 and 154-1 is also etched together, thereby Figure 1 The gate insulating layer 12 is provided only below the gate conductive layers 154 and 154-1 as shown in FIG. The material for forming the gate conductive layers 154 and 154-1 is formed to have a double-layer structure including a lower layer including titanium (Ti) and an upper layer including copper (Cu).

[0091] Figure 6 and Figure 7 , cross-sectional views for the fifth step (GI) and the sixth step (Gate) are shown. Figure 6 FIG. 1 shows a preliminary gate conductive layer 154' in the sixth step (Gate). Figure 7 Patterns of the gate conductive layers 154 and 154 - 1 and the gate insulating layer 12 formed by etching the gate insulating layer 12 and the preliminary gate conductive layer 154 ′ using the third mask 3M are shown.

[0092] The seventh step (ILD) represents a step of stacking an interlayer insulating layer 13 on the gate conductive layers 154 and 154-1 and the buffer layer 11 without using a separate mask. The interlayer insulating layer 13 may be thicker than other inorganic insulating layers. The interlayer insulating layer 13 may also be made of a material such as silicon oxide (SiO x ), silicon nitride (SiN x ) or an inorganic insulating layer of silicon oxynitride (SiON).

[0093] The eighth step (ANL) represents a step of annealing the interlayer insulating layer 13 .

[0094] The ninth step (CNT1+CNT2+Dry Etch) represents a step of forming openings 50, 51, and 71 in the interlayer insulating layer 13 and the buffer layer 11. Specifically, the openings 50 and 51 are formed in the interlayer insulating layer 13 using the fourth mask 4M and the opening 71 is formed in the buffer layer 11 using the fifth mask 5M. In this case, the interlayer insulating layer 13 can be dry-etched using the fourth mask 4M to form the openings 50 and 51 that respectively expose the drain region and the source region of the first semiconductor layer 121. At the same time, the opening 71 that exposes the metal layer 115 can be formed by etching the interlayer insulating layer 13 through the fourth mask 4M and further by etching the buffer layer 11 through the fifth mask 5M to expose the metal layer 115. However, depending on the mask, only the interlayer insulating layer 13 can be removed by forming the openings 50 and 51 using the fourth mask 4M, and the interlayer insulating layer 13 and the buffer layer 11 can be sequentially removed by forming only the opening 71 using the fifth mask 5M.

[0095] Figure 8 , a cross-sectional view after completing the seventh step (ILD), the eighth step (ANL), and the ninth step (CNT1+CNT2+DryEtch) is shown.

[0096] The tenth step (S / D) is a step of forming data conductive layers 161, 161-1, 175, and 171-1 using a sixth mask 6M. Specifically, materials for the data conductive layers 161, 161-1, 175, and 171-1 are stacked and then patterned using the sixth mask 6M to form the data conductive layers 161, 161-1, 175, and 171-1. In this case, the output-side electrode 161 and the input-side electrode 175 in the data conductive layers 161, 161-1, 175, and 171-1 are electrically connected to the source region and the drain region of the first semiconductor layer 121 through the openings 50 and 51, respectively, and the output-side electrode 161 in the data conductive layers 161, 161-1, 175, and 171-1 is electrically connected to the metal layer 115 through the opening 71. The material for the data conductive layers 161, 161-1, 175, and 171-1 is formed to have a double-layered structure including a lower layer including titanium (Ti) and an upper layer including copper (Cu), such as the material for the gate conductive layers 154 and 154-1.

[0097] Figure 9 , a cross-sectional view after completion of the tenth step (S / D) is shown.

[0098] The eleventh step (PVX) represents a step of stacking a passivation layer 14 on the data conductive layers 161, 161-1, 175, and 171-1 and the interlayer insulating layer 13 without using a mask. In the present exemplary embodiment, the passivation layer 14 may be formed of an inorganic insulating layer such as silicon oxynitride (SiON).

[0099] The twelfth step (VIA) represents a step of stacking the upper insulating layer 15 on the passivation layer 14. In the present exemplary embodiment, the upper insulating layer 15 may be formed of an organic insulator such as polyimide (PI).

[0100] In the thirteenth step ( CNT3 ), openings 81 and 84 are formed by etching the upper insulating layer 15 and the passivation layer 14 using the seventh mask 7M, thereby exposing the output-side electrode 161 and the pad electrode 171 - 1 .

[0101] Figure 10 , a cross-sectional view after completing the eleventh step (PVX), the twelfth step (VIA), and the thirteenth step (CNT3) is shown.

[0102] The fourteenth step (Pad Anode) represents a step of sequentially stacking three layers (hereinafter also referred to as anode materials) and then etching the three layers using an eighth mask 8M to form an anode 191 having the three layers as is and a pad contact electrode 197 having a single layer. A half-tone mask can be used as the eighth mask 8M. In this exemplary embodiment, the three layers are formed to include a lower layer 191a containing titanium (Ti), an intermediate layer 191b containing silver (Ag), and an upper layer 191c containing indium tin oxide (ITO). Figure 11 and Figure 12 The fourteenth step (PadAnode) is shown in FIG. Figure 3 The fourteenth step (Pad Anode) is described separately in detail.

[0103] The fifteenth step (HPDL) represents a step of forming the partition wall 30 by using the ninth mask 9M. In the present exemplary embodiment, the partition wall 30 may be formed of an organic material such as polyimide (PI). Figure 13 , a cross-sectional view after completion of the fifteenth step (HPDL) is shown.

[0104] The process may further include forming an organic emission layer 35 on the anode 191 exposed by the partition wall 30 and forming a cathode 196 covering the partition wall 30 and the organic emission layer 35 .

[0105] In the following, reference will be made to Figure 3 Describe the fourteenth step (Pad Anode) in detail and Figure 11 and Figure 12 Describe them sequentially Figure 3 Sub-steps of the fourteenth step shown in .

[0106] like Figure 3As shown in , the fourteenth step (PadAnode) includes the fourteenth-1 step (Anode Photo / Anode1stWet Etch), the fourteenth-2 step (TiDry Etch), the fourteenth-3 step (PR Ashing) and the fourteenth-4 step (Anode 2ndWet Etch / PR strip). In addition, Figure 3 The display area PXL and the pad area PAD are separately shown.

[0107] Step 14-1 (Anode Photo / Anode 1st Wet Etch) represents the following steps: a photoresist pattern is formed by sequentially stacking an anode material layer 191' and a photoresist PR and exposing the photoresist PR, and then etching it by a first wet etching process. Here, the anode material layer 191' includes a plurality of layers including a lower layer material 191a' for forming a lower layer 191a, an intermediate layer material 191b' for forming an intermediate layer 191b, and an upper layer material 191c' for forming an upper layer 191c. That is, titanium (Ti) is formed on the entire upper insulating layer 15, and then silver (Ag) is completely formed on the titanium (Ti). Thereafter, indium tin oxide (ITO) is completely formed on the silver (Ag). The titanium (Ti) is formed to have or greater thickness. Figure 3 , the lower layer material 191a' containing titanium (Ti) is stacked to have to The intermediate layer material 191b' containing silver (Ag) is stacked to have a thickness of and the upper layer material 191c' containing indium tin oxide (ITO) is stacked to have a thickness of Here, the lower layer material 191a' containing titanium (Ti) can improve the contact characteristics with the upper insulating layer 15 and can prevent the silver (Ag) of the intermediate layer 191b from diffusing downward to, for example, a transistor. The intermediate layer material 191b' containing silver (Ag) can be used to reflect light emitted from the organic emission layer 35 upward. The upper layer material 191c' containing indium tin oxide (ITO) can also be used as a hole injection layer for the organic emission layer 35. The upper layer material 191c' may contain a transparent conductive material other than ITO.

[0108] exist Figure 3In an exemplary embodiment, the lower layer material 191a' may include titanium (Ti), the intermediate layer material 191b' may include silver (Ag), and the upper layer material 191c' may include indium tin oxide (ITO), but the lower layer material 191a', the intermediate layer material 191b' or the upper layer material 191c' may be expanded and applied to materials including titanium (Ti), silver (Ag) or indium tin oxide (ITO).

[0109] Openings 81 and 84 for exposing the output side electrode 161 and the pad electrode 171 - 1 are formed in the upper insulating layer 15 and the passivation layer 14 , respectively, so that the anode material layer 191 ′ is also formed in the openings 81 and 84 and connected to the output side electrode 161 and the pad electrode 171 - 1 . Figure 11 A cross-sectional view of this state is shown in FIG.

[0110] The anode material layer 191' is stacked, and then a photoresist PR is stacked thereon. Then, the photoresist PR is exposed and developed using an eighth mask 8M to form a pattern of the photoresist PR. Here, the eighth mask 8M is a half-tone mask having a transmissive region, a light-blocking region, and a transflective region, and the transflective region is used to form a pattern of the photoresist PR provided in the pad region PAD. In other words, the photoresist PR exposed through the transflective region of the eighth mask 8M is formed to an intermediate thickness without completely removing the photoresist PR or having a maximum thickness.

[0111] Next, the pattern of the photoresist PR is used as a mask to perform a first wet etch (1st Wet Etch). The etchant used in the first wet etch (1st Wet Etch) (i.e., an anode etchant) is an etchant that can etch the intermediate layer material 191b' containing silver (Ag) and the upper layer material 191c' containing indium tin oxide (ITO) without etching the lower layer material 191a' containing titanium (Ti). As a result, when the first wet etch (1st Wet Etch) is performed, the intermediate layer material 191b' containing silver (Ag) and the upper layer material 191c' containing indium tin oxide (ITO) are etched, while the lower layer material 191a' containing titanium (Ti) is completely connected without being etched. The anode etchant may include phosphoric acid, nitric acid, or acetic acid.

[0112] In the fourteenth-2 step (TiDry Etch), dry etching is performed by using the pattern of the photoresist PR as a mask to etch the lower layer material 191a' containing titanium (Ti). In this case, the pattern of the photoresist PR is also etched to have a reduced thickness. At the same time, because the upper insulating layer 15 is provided below the lower layer material 191a' containing titanium (Ti), the upper insulating layer 15 is also partially etched. The upper insulating layer 15 may be an organic layer such as polyimide (PI), and titanium (Ti) may be included in the lower layer 191a to be dry-etched, so the titanium (Ti) in contact with the organic layer of the upper insulating layer 15 may be oxidized to produce titanium oxide (TiO x When titanium oxide (TiO x ) when titanium oxide (TiO x ) will interfere with dry etching. However, in this exemplary embodiment, in order to prevent the generation of titanium oxide (TiO x ), a pre-heat treatment (Pre-heat) is performed before stacking a lower layer material 191a' containing titanium (Ti) on the upper insulating layer 15 by sputtering. Here, the pre-heat treatment means that the upper insulating layer 15 is heat-treated before depositing the lower layer material 191a' containing titanium (Ti). The pre-heat treatment is to heat-treat the upper insulating layer 15 at a temperature of 80°C or higher for 1 minute or more. In an exemplary embodiment, the pre-heat treatment may be performed at a temperature of approximately 120°C for approximately 1 minute to 3 minutes. In an exemplary embodiment, a plurality of layers (i.e., the anode material layer 191') may be patterned to form a plurality of first patterned layers as the anode 191 of the organic light emitting diode and a plurality of second patterned layers as the preliminary pad contact electrode 197' in the display area PXL and the pad area PAD, respectively.

[0113] Will refer to Figure 21 Describe in detail the reduction of titanium oxide (TiO x )'s production and preheating treatment conditions.

[0114] The fourteenth-3 step (PR Ashing) is a process of removing the pattern of the photoresist PR remaining in the pad area PAD after the fourteenth-2 step (TiDry Etch) In this case, the pattern of the photoresist PR provided in the display area PXL remains without being removed.

[0115] Thereafter, in step 14-4 (Anode 2nd Wet Etch / PR strip), a second wet etch (2nd Wet Etch) is performed using the pattern of the photoresist PR remaining in the display region PXL as a mask, and then a stripping process is performed to remove the pattern of the photoresist PR provided in the display region PXL. In an exemplary embodiment, the plurality of second patterned layers excluding the patterned lower layer serving as the pad contact electrode 197 may be removed in the pad region PAD.

[0116] First, the anodic etchant used in the first wet etching (1st Wet Etch) is also used in the second wet etching (2nd Wet Etch). The anodic etchant may include phosphoric acid, nitric acid, or acetic acid. The middle layer material 191b' containing silver (Ag) and the upper layer material 191c' containing indium tin oxide (ITO) formed in the pad area PAD are etched by the second wet etching, and the lower layer material 191a' containing titanium (Ti) is retained without being etched, so that the pad contact electrode 197 has a single-layer structure formed only by the lower layer 191a containing titanium (Ti).

[0117] Thereafter, a process of removing the photoresist PR (stripping process) is performed using a liquid for removing the photoresist PR (PR stripper).

[0118] The anode 191 has a three-layer structure through this process, and two layers of the three-layer structure are removed to form the pad contact electrode 197 having a single-layer structure.

[0119] In the foregoing, we have focused on Figure 1 The cross-sectional structure of the organic light emitting diode display and the manufacturing method thereof are described. Figures 14 to 19 The circuit diagram, waveform diagram, layout diagram, etc. of one pixel PX are described in detail.

[0120] With Figure 1 The organic light emitting diode display having a cross-sectional structure shown in FIG. Figure 14 The pixel circuit diagram shown in FIG, and having Figure 15 A waveform signal can be applied to Figure 14 pixel circuit.

[0121] Figure 14 shows an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment, Figure 15 A timing diagram illustrating signals applied to one pixel of an organic light emitting diode display according to an exemplary embodiment is shown.

[0122] Reference Figure 14, a pixel PX of the organic light emitting diode display includes a plurality of transistors T1 , T2 , and T3 connected to various signal lines 151 , 152 , 171 , and 173 , a storage capacitor Cst, an additional capacitor Ca, and an organic light emitting diode OLED.

[0123] As a basis Figure 14 An organic light emitting diode display according to an exemplary embodiment of the present invention illustrates an organic light emitting diode display used with high resolution, and the structure of one pixel PX will be described as follows.

[0124] The transistors T1, T2, and T3 included in one pixel PX include a driving transistor T1 for transmitting an output current to the organic light emitting diode OLED, a second transistor T2 (also referred to as a switching transistor) connected to the scan line 151, and a third transistor T3 (also referred to as an initialization transistor or a sensing transistor) connected to the previous stage scan line 152. According to another exemplary embodiment, a signal line for applying a gate-on voltage having a timing different from that of the previous stage scan line 152 may be connected to the third transistor T3.

[0125] The scan line 151 is connected to a gate driver (not shown) to transmit a scan signal Sn to the gate electrode of the second transistor T2 .

[0126] The previous stage scan line 152 is connected to the gate driver and transmits the previous stage scan signal S(n-1) applied to the pixel PX disposed at the previous stage to the gate electrode of the third transistor T3.

[0127] The data line 171 is a wiring for transmitting a data voltage Dm generated by a data driver (not shown), and one data line 171 may be formed for each pixel column. One data line 171 and one scan line 151 are used to select a pixel PX and input the data voltage Dm to the corresponding pixel PX. The organic light emitting diode OLED (also known as an organic light emitting element) changes its emission brightness according to the data voltage Dm supplied to the pixel PX.

[0128] The driving voltage ELVDD is applied to one electrode of the driving transistor T1 , and the driving low voltage ELVSS is applied to one electrode of the organic light emitting diode OLED.

[0129] Hereinafter, the transistor will be described.

[0130] First, the driving transistor T1 is used to adjust the magnitude of the current output according to the data voltage Dm applied to its gate electrode, and the driving current Id output from the driving transistor T1 is applied to the organic light emitting diode OLED to adjust the brightness of the organic light emitting diode OLED according to the data voltage Dm. For this purpose, the first electrode (input side electrode) of the driving transistor T1 is configured to receive the driving voltage ELVDD, and the second electrode (output side electrode) of the driving transistor T1 is connected to the first electrode (hereinafter referred to as the anode or pixel electrode) of the organic light emitting diode OLED. In addition, the gate electrode of the driving transistor T1 can be connected to the second electrode (output side electrode) of the second transistor T2 to receive the data voltage Dm.

[0131] The gate electrode of the driving transistor T1 is connected to the first electrode of the storage capacitor Cst. The storage capacitor Cst is used to ensure that the data voltage Dm transmitted to the gate electrode of the driving transistor T1 is maintained for one frame. Therefore, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and the driving current Id output by the driving transistor T1 changes to be output constantly for one frame.

[0132] According to an exemplary embodiment, the driving transistor T1 further includes a metal layer 115 located below the semiconductor layer having its channel. The metal layer 115 is stacked with the channel and gate electrode of the driving transistor T1 to improve the performance of the driving transistor T1 and maintain the voltage of the gate electrode. Since the metal layer 115 is stacked with the gate electrode, the voltage of the gate electrode is maintained to compensate for the effect of the storage capacitor Cst. Hereinafter, the capacitor added by the stacking between the metal layer 115 and the gate electrode of the driving transistor T1 is referred to as a stacking capacitor (not shown). The metal layer 115 is electrically connected to the second electrode (output side electrode) of the driving transistor T1 and is therefore also connected to the anode of the organic light emitting diode OLED.

[0133] The second transistor T2 is used to receive the data voltage Dm into the pixel PX. The gate electrode of the second transistor T2 is connected to the scan line 151, the first electrode of the second transistor T2 is connected to the data line 171, and the second electrode (output-side electrode) of the second transistor T2 is connected to the gate electrode of the driving transistor T1. When the second transistor T2 is turned on by the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the gate electrode of the driving transistor T1 to be stored in the storage capacitor Cst.

[0134] The third transistor T3 is used to initialize the second electrode (output-side electrode) of the driving transistor T1, the second electrode of the storage capacitor Cst, and the anode of the organic light-emitting diode OLED. The gate electrode of the third transistor T3 is connected to the previous-stage scan line 152, and the first electrode of the third transistor T3 is connected to the initialization voltage line 173. The second electrode (output-side electrode) of the third transistor T3 is electrically connected to the second electrode (output-side electrode) of the driving transistor T1, and is therefore also connected to the anode of the organic light-emitting diode OLED and the metal layer 115.

[0135] The initialization voltage line 173 not only supplies the initialization voltage Vint but also serves as a wiring for sensing the voltage of the anode connected to the second electrode of the third transistor T3 according to a period. In this case, the initialization voltage line 173 can be referred to as a sensing line. As a result, the third transistor T3 can also be referred to as a sensing transistor.

[0136] The operation of the third transistor T3 will now be described. When the organic light emitting diode OLED emits light, the voltage of the anode is stored in the second electrode of the storage capacitor Cst. In this case, the data voltage Dm is stored in the first electrode of the storage capacitor Cst. In this case, when the gate-on voltage is applied to the gate electrode of the third transistor T3, the initialization voltage line 173 operates as a sensing line, and the voltage of the anode is transmitted to the sensor (not shown) through the sensing line. Hereinafter, this is also referred to as the sensing (SS) period. Then, the initialization voltage line 173 applies the initialization voltage Vint to initialize the voltage of the anode during the remaining period in the period in which the gate-on voltage is applied to the gate electrode of the third transistor T3. Hereinafter, this is referred to as the initialization period.

[0137] When the voltage sensed during the sensing (SS) period differs from the anode voltage expected in the determination based on the applied data voltage Dm, the data voltage Dm may be corrected and supplied to the pixel PX. For example, the characteristics of the driving transistor T1 may be changed. In this case, the data voltage Dm may be appropriately adjusted according to the changed characteristics by sensing the change in the characteristics, so that the organic light emitting diode OLED emits light normally.

[0138] The two electrodes of the storage capacitor Cst are used to maintain the data voltage Dm and the anode voltage of the organic light emitting diode OLED (the voltage of the output-side electrode of the driving transistor T1 ) for one frame.

[0139] However, in recent years, as high-resolution organic light-emitting diode displays are manufactured, the area occupied by the pixel PX has been reduced. Consequently, the area for forming the storage capacitor Cst is reduced, and it may be impossible to ensure that the storage capacitance can be maintained for one frame. Therefore, an additional capacitor may be further included.

[0140] exist Figure 14 In the exemplary embodiment, an additional capacitor Ca is further included to ensure sufficient storage capacitance to maintain the anode voltage of the organic light emitting diode OLED for one frame.

[0141] The additional capacitor Ca has a first electrode connected to the anode electrode of the organic light emitting diode OLED and a second electrode to which the driving voltage ELVDD is applied to maintain the anode voltage of the organic light emitting diode OLED.

[0142] According to another exemplary embodiment, a stack capacitor is formed by the stacking between the metal layer 115 and the gate electrode of the driving transistor T1 .

[0143] Will pass Figure 15 The waveform diagram is applied to Figure 14 The operation of one pixel PX of the organic light emitting diode display according to an exemplary embodiment will be described with reference to a structure of the pixel PX.

[0144] exist Figure 15 In the example, a signal represented by SCAN is applied to the scan line 151, and a signal represented by SENSING is applied to the previous-stage scan line 152.

[0145] During the sensing / initialization period, a high-level previous scan signal S(n-1) is supplied to the pixel PX through the previous scan line 152. Then, the third transistor T3, which receives the previous scan signal S(n-1), is turned on. In this case, the voltage stored in the anode of the organic light emitting diode OLED is checked through the initialization voltage line 173 (sensing (SS) period), and then the anode voltage of the organic light emitting diode OLED is changed to the initialization voltage Vint to initialize the anode of the organic light emitting diode OLED (initialization period).

[0146] When the driving transistor T1 provided in each pixel PX has different threshold voltages (Vth) due to process variations or changes in characteristics of the driving transistor T1 over a long period of time, these are sensed during the sensing time, thereby causing the organic light emitting diode OLED to emit light normally.

[0147] Then, during a data writing period, a high-level scan signal Sn is applied to the pixel PX through the scan line 151. The second transistor T2 is turned on by the high-level scan signal Sn. When the second transistor T2 is turned on, the data voltage Dm is input to the gate electrode of the driving transistor T1 through the second transistor T2 to be stored in the first electrode of the storage capacitor Cst.

[0148] The degree of conduction of the driving transistor T1 is determined by the data voltage Dm applied to its gate electrode, and the output of the driving transistor T1 is determined by the degree of conduction thereof, and the output of the driving transistor T1 is transmitted to the anode of the organic light emitting diode OLED. In this case, the anode voltage of the organic light emitting diode OLED is stored in the stack capacitor or the additional capacitor Ca and the storage capacitor Cst and maintained for one frame.

[0149] In the above, based on Figure 14 The circuit diagram describes the pixel structure.

[0150] In the following, reference will be made to Figures 16 to 19 It is described how the pixel PX is implemented according to an exemplary embodiment.

[0151] Figure 16 and Figure 17 A layout diagram and a cross-sectional view showing one pixel of a display area are shown. Figure 18 and Figure 19 Layout and cross-sectional views of the pad area are shown.

[0152] First, refer to Figure 16 and Figure 17 The structure of one pixel PX in the display area is described.

[0153] Figure 16 shows a layout diagram of pixels of an organic light emitting diode display according to an exemplary embodiment, Figure 17 Shown along Figure 16 A sectional view taken along line XVII-XVII.

[0154] Reference Figure 16 and Figure 17 In the organic light emitting diode display according to an exemplary embodiment of the present invention, a metal layer 115, semiconductor layers 121, 122 and 123, gate conductive layers 151, 152, 153, 154, 154-1, 154-2, 157, 158 and 159, data conductive layers 171, 173, 175, 176, 161, 161-1, 162, 166 and 167, an anode 191, an organic emission layer 35 and a cathode 196 are formed on a substrate 10, and unless the layers are connected through an opening, the layers are insulated from each other with an insulating layer located therebetween.

[0155] The substrate 10 may be formed of a glass substrate or a flexible substrate such as plastic or polyimide (PI). In the case of a flexible substrate, unlike a glass substrate, an additional inorganic insulating layer may be formed.

[0156] A metal layer 115 is formed on the substrate 10. The metal layer 115 includes a connector and a channel-overlapping portion that overlaps the channel of the driving transistor T1. The connector of the metal layer 115 is connected to the output-side electrode 161 of the driving transistor T1, which will be described later. Because the output-side electrode 161 of the driving transistor T1 receives the voltage of the anode 191, the metal layer 115 also receives the voltage of the anode 191. The metal layer 115 and the gate electrode 154 of the driving transistor T1 can form a stacked capacitor.

[0157] The buffer layer 11 is disposed on the substrate 10 and the metal layer 115 to cover the substrate 10 and the metal layer 115. The buffer layer 11 may be formed of a conductive metal material.

[0158] Semiconductor layers 121, 122, and 123 are formed on the buffer layer 11. The semiconductor layers 121, 122, and 123 include a channel of the driving transistor T1, a channel of the second transistor T2, and a channel of the third transistor T3, respectively. According to this exemplary embodiment, the semiconductor layers 121, 122, and 123 may be formed of an oxide semiconductor. The first semiconductor layer 121, which serves as the semiconductor layer of the driving transistor T1, includes a channel region and source and drain regions disposed on opposite sides of the channel region. The second semiconductor layer 122, which serves as the semiconductor layer of the second transistor T2, includes a channel region and source and drain regions disposed on opposite sides of the channel region. The third semiconductor layer 123, which serves as the semiconductor layer of the third transistor T3, includes a channel region and source and drain regions disposed on opposite sides of the channel region.

[0159] The channel region of each of the semiconductor layers 121 , 122 , and 123 may be formed as two lines including an opening at the center of a quadrangle, or may be formed as only one line connecting a source region and a drain region.

[0160] The source and drain regions of each semiconductor layer 121, 122, and 123 are electrically connected to the first electrode (input side electrode) and the second electrode (output side electrode) of the corresponding transistor, respectively. In addition, the source and drain regions extend to be electrically connected to other layers through the opening.

[0161] exist Figure 16 In the exemplary embodiment of the present invention, the first semiconductor layer 121 and the third semiconductor layer 123 are connected to each other.

[0162] The gate insulating layer 12 is disposed on the semiconductor layers 121, 122, and 123 and the buffer layer 11 to cover the semiconductor layers 121, 122, and 123 and the buffer layer 11. The gate insulating layer 12 may be formed of an inorganic insulating material.

[0163] The gate conductive layers 151, 152, 153, 154, 154-1, 154-2, 157, 158, and 159 are provided on the gate insulating layer 12. The gate conductive layers 151, 152, 153, 154, 154-1, 154-2, 157, 158, and 159 include a scan line 151, a previous stage scan line 152, an initialization voltage transmission unit 153, a gate electrode 154 of the driving transistor T1, a first electrode 154-1 of the storage capacitor Cst, an output side electrode 154-2 of the second transistor T2, a gate electrode 157 of the second transistor T2, a gate electrode 158 of the third transistor T3, and a horizontal driving voltage line 159. The gate electrode 154 of the driving transistor T1 is connected to the first electrode 154-1 of the storage capacitor Cst and the output side electrode 154-2 of the second transistor T2.

[0164] The scan line 151 extends in a first direction (horizontal direction), and the previous-stage scan line 152 also extends in the first direction (horizontal direction).

[0165] The initialization voltage transmission unit 153 has an island shape extending in the first direction. The initialization voltage transmission unit 153 is a structure formed for each predetermined number of pixel columns to connect a plurality of pixels PX to the initialization voltage line 173. For example, the initialization voltage transmission unit 153 extends through adjacent pixels PX in the first direction to a position where the initialization voltage line 173 is to be formed. In this exemplary embodiment, one initialization voltage line 173 is formed for each pixel PX including three sub-pixels PX1, PX2, and PX3.

[0166] The horizontal driving voltage line 159 extends in a first direction (horizontal direction) and intersects with the driving voltage line 175 extending in a second direction (vertical direction). The horizontal driving voltage line 159 is provided between pixels PX adjacent in the row direction and is electrically connected to the driving voltage line 175 through the opening 57 for each of the sub-pixels PX1, PX2, and PX3 adjacent in the column direction.

[0167] The gate electrode 154 of the driving transistor T1 overlaps the first semiconductor layer 121 in which the channel of the driving transistor T1 is provided, is connected to the first electrode 154-1 of the storage capacitor Cst, and is also connected to the output-side electrode 154-2 of the second transistor T2 through the first electrode 154-1 of the storage capacitor Cst. As a result, the data voltage Dm transmitted to the pixel PX through the second transistor T2 is also transmitted to the first electrode 154-1 of the storage capacitor Cst and the gate electrode 154 of the driving transistor T1 through the opening 43.

[0168] In addition, the first electrode 154 - 1 of the storage capacitor Cst and the extension portion of the metal layer 115 overlap each other to constitute a stacked capacitor.

[0169] Figure 16 Three sub-pixels PX1 , PX2 , and PX3 constituting one pixel PX are shown, and extensions of the gate electrodes 154 of the driving transistors T1 of the sub-pixels PX1 , PX2 , and PX3 are shown to have various sizes.

[0170] The gate electrode 157 of the second transistor T2 has an island structure and overlaps the second semiconductor layer 122 of the second transistor T2. The channel of the second transistor T2 is formed at a position where the second semiconductor layer 122 of the second transistor T2 and the gate electrode 157 overlap each other. The gate electrode 157 of the second transistor T2 is electrically connected to the current-stage scan line (also simply referred to as the scan line) 151 through the second gate electrode connector 162. The current-stage scan line 151 is connected to the second gate electrode connector 162 through the opening 72, and the second gate electrode connector 162 is connected to the gate electrode 157 of the second transistor T2 through the opening 46.

[0171] The gate electrode 158 of the third transistor T3 has an island structure and overlaps the third semiconductor layer 123 of the third transistor T3. The channel of the third transistor T3 is formed at a position where the third semiconductor layer 123 and the gate electrode 158 overlap each other. The gate electrode 158 is electrically connected to the previous-stage scan line 152 via a third gate electrode connector 167. The previous-stage scan line 152 is electrically connected to the third gate electrode connector 167 through the opening 77, and the third gate electrode connector 167 is electrically connected to the gate electrode 158 of the third transistor T3 through the opening 54.

[0172] Interlayer insulating layer 13 is provided on gate conductive layers 151, 152, 153, 154, 154-1, 154-2, 157, 158, and 159 and gate insulating layer 12 to cover them. Interlayer insulating layer 13 may be formed thickly of an inorganic insulating material.

[0173] The data conductive layers 171, 173, 175, 176, 161, 161-1, 162, 166, and 167 are provided on the interlayer insulating layer 13. The data conductive layers 171, 173, 175, 176, 161, 161-1, 162, 166, and 167 include a data line 171, an initialization voltage line 173, a driving voltage line 175, a driving low voltage line 176, an output side electrode 161 of a driving transistor T1, a second electrode 161-1 of a storage capacitor Cst, a second gate electrode connector 162, a first electrode (input side electrode) 166 of a third transistor T3, and a third gate electrode connector 167.

[0174] The data line 171 is formed for each pixel column and extends in a second direction (vertical direction) perpendicular to the first direction. The data line 171 is connected to the second semiconductor layer 122 of the second transistor T2 via the opening 41 to apply the data voltage Dm to the second transistor T2. The data line 171 extends to the pad region, and a pad electrode 171-1 having an extended width is provided in the pad region. The pad electrode 171-1 and the data line 171 may be formed integrally, and the reference Figure 18 and Figure 19 The pad electrode 171 - 1 is described.

[0175] Initialization voltage line 173 extends in the second direction to apply initialization voltage Vint. In this exemplary embodiment, initialization voltage line 173 is not formed for each pixel column, but rather one initialization voltage line 173 is formed for each pixel PX, which includes three sub-pixels PX1, PX2, and PX3. Initialization voltage line 173 is connected to initialization voltage transmission unit 153 through opening 63, and initialization voltage transmission unit 153 is connected to first electrode 166 of third transistor T3 through opening 79. First electrode 166 of third transistor T3 is connected to third semiconductor layer 123 of third transistor T3 through opening 48. As a result, initialization voltage Vint is applied to first electrode (input-side electrode) 166 of third transistor T3 of each pixel PX.

[0176] The driving voltage line 175 and the driving low voltage line 176 also extend in the second direction (vertical direction). The driving voltage line 175 is provided in each of the three sub-pixels PX1, PX2 and PX3, but the driving low voltage line 176 is provided in one pixel PX including the three sub-pixels PX1, PX2 and PX3. The driving voltage line 175 transmits the driving voltage ELVDD and is connected to the first semiconductor layer 121 of the driving transistor T1 through the two openings 51 to transmit the driving voltage ELVDD to the first electrode of the driving transistor T1. Compared with the driving low voltage line 176, the driving voltage line 175 may have a narrow width. The driving low voltage line 176 may have a narrow width in an area overlapping with a wiring provided in another layer, Figure 16 , the driving low voltage line 176 has a narrow width at a portion overlapping the scan line 151. The driving low voltage line 176 having a wide width forms an electrical connection structure to transmit the driving low voltage ELVSS to the cathode 196 provided at its upper portion. For example, in order to form a contact using a laser or the like and electrically connect the contact, a certain horizontal width is required.

[0177] The output side electrode 161 of the driving transistor T1 is electrically connected to the first semiconductor layer 121 of the driving transistor T1 through the opening 50 and extends to the second electrode 161-1 of the storage capacitor Cst. Thereafter, the output side electrode 161 is extended again to be electrically connected to the anode 191 described later through the opening 81.

[0178] The second gate electrode link 162 electrically connects the current stage scan line 151 to the gate electrode 157 of the second transistor T2 via the two openings 46 and 72 .

[0179] The first electrode 166 of the third transistor T3 is connected to the third semiconductor layer 123 through the opening 48 to serve as an input side electrode, and extends to be electrically connected to the initialization voltage transmission unit 153 through the opening 79. As a result, the initialization voltage Vint is directly transmitted to the first electrode 166 of the third transistor T3.

[0180] The third gate electrode connection member 167 electrically connects the previous stage scan line 152 to the gate electrode 158 of the third transistor T3 via the two openings 54 and 77 .

[0181] The passivation layer 14 is disposed on the data conductive layers 171, 173, 175, 176, 161, 161-1, 162, 166, and 167 and the interlayer insulating layer 13. The passivation layer 14 may be formed of an inorganic insulating layer.

[0182] The upper insulating layer 15 is provided on the passivation layer 14. The upper insulating layer 15 may be formed of an organic layer. The anode 191 and the pad contact electrode 197 are formed on the upper insulating layer 15. The pad contact electrode 197 is shown separately. Figure 18 and Figure 19 and will refer to Figure 18 and Figure 19 The pad contact electrode 197 is described in detail.

[0183] The anode 191 transmits the current output from the driving transistor T1 to the first electrode of the organic light emitting diode OLED to the organic emission layer 35. The anode 191 is electrically connected to the second electrode 161-1 for the storage capacitor Cst through the opening 81. The second electrode 161-1 for the storage capacitor Cst is connected to the output side electrode 161 of the driving transistor T1 to transmit the output of the driving transistor T1 to the anode 191. Figure 17 , the anode 191 has a three-layer structure including a lower layer 191a, an intermediate layer 191b, and an upper layer 191c. In contrast, the pad contact electrode 197 is formed as a single layer formed of the same material as that of the lower layer 191a (see FIG. Figure 19 ).

[0184] Reference Figure 16The anode 191 is disposed over the entire surface of the pixel PX to overlap the driving transistor T1, the second transistor T2, and the third transistor T3, and a side of the driving voltage line 175 and a side of the anode 191 overlap each other side by side.

[0185] Here, the additional capacitor Ca is formed at a region where the anode electrode 191 and the driving voltage line 175 overlap each other.

[0186] The anode 191 overlaps the driving voltage line 175 but does not overlap the driving low voltage line 176. However, according to another exemplary embodiment, the anode 191 may overlap the driving low voltage line 176 to constitute an additional capacitor.

[0187] A partition wall 30 having an opening 30-1 is disposed on the anode 191, an organic emission layer 35 is disposed in the opening 30-1 of the partition wall 30, and a cathode 196 is formed to cover the partition wall 30 and the organic emission layer 35. Although not shown, the cathode 196 is electrically connected to the driving low voltage line 176 to receive the driving low voltage ELVSS.

[0188] In the following, reference will be made to Figure 18 and Figure 19 The structure of the pad area is described in detail.

[0189] Figure 18 shows a layout diagram of a pad area according to an exemplary embodiment, Figure 19 Shown along Figure 18 A sectional view taken along line XIX-XIX.

[0190] Reference Figure 18 , a pad electrode 171 - 1 and a pad contact electrode 197 electrically connected to the pad electrode 171 - 1 through the opening 84 are formed in the pad region.

[0191] The pad electrode 171 - 1 represents an extended end portion of the data line 171 extending through the display area to the pad area. The pad electrode 171 - 1 is included in the data conductive layer in the same manner as the data line 171 .

[0192] Reference Figure 19 The pad electrode 171 - 1 is covered with the passivation layer 14 and the upper insulating layer 15 , and an opening 84 exposing a portion of the pad electrode 171 - 1 is formed in the passivation layer 14 and the upper insulating layer 15 .

[0193] The pad contact electrode 197 is formed on the upper insulating layer 15 and is electrically connected to the pad electrode 171-1 through the opening 84. The pad contact electrode 197 may have a width wider than that of the pad electrode 171-1.

[0194] In addition, if Figure 19As shown in FIG, the pad contact electrode 197 has a single-layer structure different from the three-layer structure of the anode 191 formed by the same process. The pad contact electrode 197 may be formed of the same material as the lower layer 191a of the three-layer structure of the anode 191.

[0195] Already referenced Figure 18 and Figure 19 The pad electrode 171 - 1 provided at one end portion of the data line 171 is described.

[0196] Reference Figure 1 Since the gate conductive layers 154 and 154-1 and the data conductive layers 161, 161-1, 175, and 171-1 have the same double-layer structure, the pad electrode disposed at the end of the scan line 151 may have the same double-layer structure as that of the gate conductive layers 154 and 154-1. Figure 18 and Figure 19 However, since the pad electrode provided at the end of the scan line 151 is provided in the gate conductive layer rather than the data conductive layer, the difference is that the pad electrode is provided below the interlayer insulating layer 13. The pad contact electrode electrically connected to the pad electrode provided at the end of the scan line 151 has a structure similar to that of FIG. Figure 18 and Figure 19 and may be formed of the same material as that of the lower layer 191a of the anode 191. According to another exemplary embodiment, an additional connector may be formed in the data conductive layer to facilitate connection between the gate conductive layer and the pad contact electrode.

[0197] In the following, reference will be made to Figure 20 A cross-sectional structure of an organic light emitting diode display including a color conversion layer is described.

[0198] Figure 20 A cross-sectional view of an organic light emitting diode display according to an exemplary embodiment is shown.

[0199] like Figure 20 As shown in the cross-sectional view, except Figure 1 In addition to the constituent elements of OLED, the organic light emitting diode display further includes an upper substrate 10 - 1 , an adhesive layer 250 , a light blocking layer 220 , a color conversion layer 230 , and a cover layer 240 configured to cover the organic light emitting diode OLED.

[0200] The following will be based on Figure 1 The different exemplary embodiments are described Figure 20 An exemplary embodiment of .

[0201] The partition wall 30 and the cathode 196 are covered with a capping layer 240. The capping layer 240 may include three layers of inorganic layer / organic layer / inorganic layer and serves to prevent water or air from penetrating from the outside into the organic emission layer 35. The pad region where the pad contact electrode 197 is provided may not be covered by the capping layer 240.

[0202] Meanwhile, a light blocking layer 220 and a color conversion layer 230 are provided on the upper substrate 10-1. The upper substrate 10-1 may be formed of the same glass as the glass of the substrate 10 provided at its lower portion. However, according to another exemplary embodiment, both the substrate 10 and the upper substrate 10-1 may be formed of a flexible material.

[0203] The color conversion layer 230 is provided in a region through which light emitted from the organic emission layer 35 is transmitted to the lower surface of the upper substrate 10-1, and the light blocking layer 220 is provided between the color conversion layers 230. For example, an opening is formed in the light blocking layer 220, and the color conversion layer 230 is provided in the opening of the light blocking layer 220. The light blocking layer 220 may extend to the pad region as well as the display region.

[0204] The color conversion layer 230 is used to convert the light of a specific color (e.g., blue light) emitted from the organic emission layer 35 into light having one of the primary colors, such as red and green, by adjusting the wavelength of the light. Typically, the color conversion layer 230 may include a quantum dot (QD) material. In an exemplary embodiment, all light emitted by the organic emission layer 35 displays the same color, but the three primary colors of light, such as red, green, and blue, may be displayed by the color conversion layer 230 provided in each pixel PX.

[0205] Meanwhile, in addition to the color conversion layer 230, a color filter layer (not shown) may be included to improve color purity. When the color purity is improved as described above, each primary color is displayed more clearly. However, if sufficient color purity is ensured by the color conversion layer 230 alone, the additional color filter layer may not be included.

[0206] According to another exemplary embodiment, the organic emission layer 35 may emit one of red, green, and blue light (three primary color lights) for each pixel PX, and the color conversion layer 230 or the color filter layer may not be included.

[0207] Reference Figure 20 , the cover layer 240, the color conversion layer 230 and the light blocking layer 220 are attached by the adhesive layer 250. Figure 20 An adhesive layer 250 is shown disposed on the pad area and the pad contact electrode 197, but the pad contact electrode 197 needs to receive a signal from a driving chip or a printed circuit board (PCB) and therefore may be connected to a separate signal line, while the adhesive layer 250 may be disposed thereon to cover the signal line.

[0208] In the following, reference will be made to Figures 21 to 23 Describes a method for removing the titanium oxide (TiO) by preheating x ) process conditions that cause dry etching problems.

[0209] Figures 21 to 23 Graphs showing etching effects depending on the preheat treatment process.

[0210] In the case when titanium (Ti) is dry-etched, the organic layer provided under the titanium is also dry-etched, and titanium oxide (TiO x ), thereby forming titanium oxide (TiO x ) to stop the dry etching so that some areas will not be etched.

[0211] Compared with the case where only titanium (Ti) is present, when titanium oxide (TiO x ) is formed, the sheet resistance (Rs [unit: Ω / square]) increases. Therefore, refer to Figures 21 to 23 , the sheet resistance Rs was used to estimate the titanium oxide (TiO x ) thickness.

[0212] first, Figure 21 The sheet resistance Rs is compared in the case where the curing process is performed twice, no treatment is performed (N / A), and pre-heating treatment (Pre-heat) is performed multiple times. Here, the curing process refers to a process of heat treatment at a high temperature of 230°C for one hour. The pre-heating treatment (Pre-heat) refers to a process of heat-treating the upper insulating layer 15, which is an organic layer provided under the titanium (Ti), at a relatively low temperature before stacking the titanium (Ti). Figure 21 In the case of , pre-heating was performed at 120°C.

[0213] like Figure 21 As shown, it is observed that the sheet resistance Rs is reduced more in the case where the curing process is performed twice than in the case where no treatment is performed (N / A), but the difference is not significant.

[0214] However, it was observed that even if the preheating treatment (Pre-heat) was performed for a short time of less than 1 minute, the sheet resistance Rs was significantly reduced, and when it exceeded 1 minute, the sheet resistance Rs was further reduced to have a value within a certain range. The value of the sheet resistance Rs was about 76Ω / square to 77Ω / square, where titanium oxide (TiO x ) is expected to have a thickness of

[0215] Reference Figure 21It was observed that the best effect on the sheet resistance Rs was obtained in a pre-heating treatment (Pre-heat) of about 1 minute to about 3 minutes.

[0216] exist Figure 21 In this embodiment, the influence of the preheating treatment (Pre-heat) on the sheet resistance Rs was measured by fixing the temperature for the preheating treatment (Pre-heat) to 120° C. and varying the time of the preheating treatment (Pre-heat).

[0217] In the following, reference will be made to Figure 22 The sheet resistance Rs compared by changing the temperature for the preheating process (Pre-heat) is described. In this case, the time for the preheating process (Pre-heat) is 1 minute.

[0218] exist Figure 22 In the figure, the bar graph shows the value of the sheet resistance Rs, and the numerical value shown in the circle represents the value of titanium oxide (TiO x ) thickness.

[0219] It was observed that regardless of the pre-heating temperature, the titanium oxide (TiO x ) thickness is greatly reduced, and less titanium oxide (TiO x ).

[0220] based on Figure 21 and Figure 22 According to the test results, the temperature for the preheating treatment (Pre-heat) may be around 120° C., and the time for the preheating treatment (Pre-heat) may be 1 minute to 3 minutes.

[0221] Reference Figure 23 , the difference between the sheet resistance Rs when there is no preheating treatment (Pre-heat) and when the preheating treatment (Pre-heat) is appropriately performed is compared, and the difference between the sheet resistance Rs when there is no preheating treatment (Pre-heat) and when the preheating treatment (Pre-heat) is appropriately performed is compared. x ) The difference between the thickness of Figure 23 In the process, a pre-heating treatment (Pre-heat) was performed at 120° C. for 3 minutes.

[0222] Without pre-heat treatment, titanium oxide (TiO x ) has a thickness of The sheet resistance Rs is 78.7Ω / square. However, when the preheating process (Pre-heat) is performed, the titanium oxide (TiO x ) has a thickness of The sheet resistance Rs is 74.5Ω / square. x ) may be a thickness of titanium oxide (TiO x ) is nearly twice the thickness of the titanium layer. In other words, if the pre-heat treatment (Pre-heat) is not performed, etching will not be performed in at least a portion of the titanium layer during dry etching. However, when the pre-heat treatment (Pre-heat) is appropriately performed, the titanium oxide (TiO x ) is reduced to about half, so that the problem does not occur even if the titanium layer is dry-etched.

[0223] While the invention has been described in connection with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An organic light emitting diode display, comprising: a substrate including a display area and a pad area; A first thin film transistor is provided on the display area; an organic light emitting diode connected to the first thin film transistor; a pad electrode, disposed on the pad area; an upper insulating layer covering the pad electrode and including a through hole exposing the pad electrode; and a pad contact electrode disposed on an upper portion of the pad electrode and contacting and electrically connected to the pad electrode through the through hole penetrating the upper insulating layer, The organic light emitting diode comprises an anode, an organic emission layer and a cathode. The anode comprises a lower layer, an intermediate layer and an upper layer, the pad contact electrode includes only one layer formed of the same material as that of the lower layer of the anode, The lower layer and the pad contact electrode are directly disposed on the upper insulating layer, The upper insulating layer includes an organic material, The lower layer and the pad contact electrode each contain titanium and titanium oxide generated by contact with the upper insulating layer, and Before forming the lower layer and the pad contact electrode on the upper insulating layer, the upper insulating layer undergoes a preheating process to reduce an amount of titanium oxide in the lower layer and the pad contact electrode generated by contact with the upper insulating layer.

2. The organic light emitting diode display according to claim 1, in, The intermediate layer comprises silver, and The upper layer includes indium tin oxide or a transparent conductive material other than indium tin oxide.

3. The organic light emitting diode display according to claim 2, wherein: The upper insulating layer is disposed below the lower layer, The lower layer contacts the upper insulating layer to increase adhesion to the upper insulating layer and prevent the silver of the intermediate layer from diffusing downward toward the first thin film transistor. The intermediate layer reflects light emitted from the organic emission layer upward, and The upper layer injects holes into the organic emission layer.

4. The organic light emitting diode display according to claim 1, in, The first thin film transistor provided on the display area is a driving transistor, and The organic light emitting diode display further comprises: a second thin film transistor, disposed on the display area to transmit a data voltage to the gate electrode of the driving transistor; a third thin film transistor, disposed on the display area to initialize the voltage of the output-side electrode of the driving transistor; a data line to which the data voltage is transmitted, wherein the pad electrode is an extension of the data line into the pad area; a driving voltage line configured to transmit a driving voltage to the driving transistor; a driving low voltage line configured to transmit a driving low voltage to the cathode; and An initialization voltage line is connected to the third thin film transistor.

5. The organic light emitting diode display according to claim 4, further comprising: a metal layer, disposed between the first semiconductor layer of the driving transistor and the substrate; as well as a cover layer covering the organic light emitting diode to prevent moisture or air from penetrating into the organic light emitting diode, The capping layer includes a first inorganic layer, an organic layer, and a second inorganic layer stacked on each other.

6. The organic light emitting diode display according to claim 4, further comprising: an upper substrate facing the substrate; a light-blocking layer, disposed on the upper substrate and having an opening; as well as A color conversion layer is provided in the opening of the light-blocking layer. The color conversion layer converts light emitted from the organic emission layer into one of three primary colors.

7. A method for manufacturing an organic light emitting diode display, the method comprising the following steps: preparing a substrate including a display area and a pad area; forming a pad electrode in the pad region; forming an upper insulating layer covering the pad electrode on the substrate; forming a through hole in the upper insulating layer to expose the pad electrode; performing a preheating treatment on the upper insulating layer; forming a plurality of layers including a lower layer on the upper insulating layer; and forming an anode and a pad contact electrode of an organic light emitting diode from the plurality of layers in the display region and the pad region, respectively, Wherein, the anode comprises the lower layer, the middle layer and the upper layer, The pad contact electrode includes only one layer formed of the same material as that of the lower layer of the anode, and The pad contact electrode contacts and is electrically connected to the pad electrode through the through hole penetrating the upper insulating layer.

8. The manufacturing method according to claim 7, in, The preheating treatment is performed at a temperature of 120° C. for 1 to 3 minutes.

9. The manufacturing method according to claim 7, in, The lower layer includes titanium, the middle layer includes silver, and the upper layer includes indium tin oxide or a transparent conductive material other than indium tin oxide.

10. The manufacturing method according to claim 7, in, The step of forming the anode and the pad contact electrode of the organic light emitting diode comprises the following steps: patterning the plurality of layers to form a plurality of first patterned layers serving as the anodes of the organic light emitting diodes and a plurality of second patterned layers serving as preliminary pad contact electrodes in the display region and the pad region, respectively; and removing the plurality of second patterned layers except for the lower layer patterned as the pad contact electrode in the pad region, wherein the plurality of layers further comprises the middle layer and the upper layer, The step of patterning the multiple layers includes: forming a photoresist pattern by sequentially stacking the lower layer, the middle layer, the upper layer, and a photoresist and exposing the photoresist to light; wet-etching the middle layer and the upper layer by using the photoresist pattern as a mask; and dry-etching the lower layer. The step of removing the plurality of second patterned layers comprises: removing the photoresist pattern on the pad area; and wet etching the upper layer and the middle layer on the pad area. The photoresist pattern is formed by using a half-tone mask so that a thickness of the photoresist pattern on the pad area is smaller than a thickness of the photoresist pattern on the display area.

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