Method for manufacturing an integrated component with improved space occupancy and integrated component

Abstract

Embodiments of the present disclosure relate to methods for manufacturing integrated components with improved space efficiency and the integrated components. A first wafer of semiconductor material has a surface. A second wafer of semiconductor material includes a substrate and a structural layer on the substrate. The structural layer integrates a detector device for monitoring electromagnetic radiation. The structural layer of the second wafer is coupled to the surface of the first wafer. The substrate of the second wafer is shaped to form a stator, a rotor, and a moving mass of a micromirror. The stator and rotor form an assembly for capacitively driving the moving mass.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Italian Patent Application No. 102019000000917, filed on January 22, 2019, the entire contents of which are incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present invention relates to a method for manufacturing an integrated component and an integrated component. In particular, the present invention relates to a method for manufacturing a component comprising a micromirror and a thermal MOS (TMOS) transistor, which is particularly suitable for use in a system for 3D reconstruction of a human body illuminated by near-infrared (NIR) radiation. Background Art

[0004] A known type of medical examination envisages the generation of a 3D image, obtained starting from a human body irradiated with NIR radiation, which allows the reconstruction of the body's own thermal spectrum and, therefore, the identification of underlying diseases or conditions (such as rheumatoid arthritis, Raynaud's syndrome, knee osteoarthritis, etc.). Various systems are known in the art for performing such medical examinations, which require both a light source in the NIR spectrum for irradiating the part of the patient's body under examination with incident radiation and a detector suitable for measuring the radiation generated by the irradiated part of the body. Consequently, a broad and poorly positioned beam of incident radiation is generated, which reduces the precision and accuracy of the signal emitted by the body under examination and acquired by the detector.

[0005] A known type of detector envisions the use of a thermal MOS (TMOS) transistor. A TMOS transistor is a field-effect transistor device that is typically used in sensor applications for determining the amount of radiation emitted by an object or person under examination. The emitted radiation received by the TMOS transistor results in the generation of charge carriers in the conductive channel of the TMOS transistor and, therefore, in a change in the output current; the output current can be set in relation to the amount of radiation emitted by the object under examination.

[0006] It is also known in the art to use micrometer-sized mirrors (i.e., micromirrors of the microelectromechanical systems (MEMS) type) in order to deflect radiation impinging on a body under examination and direct it towards specific areas of the body. Typically, micromirrors are obtained by depositing a metal (such as gold or aluminum) on a mobile mass of a bare die to create a reflective surface (e.g., so as to achieve a reflectivity greater than 98%). The actuation of the mobile mass of the micromirror is typically of the piezoelectric, capacitive, or magnetic type.

[0007] In particular, capacitive actuation is enabled by currents supplied to the stator and rotor of the micromirror. Such currents generate a capacitance difference across the micromirror's moving mass, allowing the mass, which is subject to torque, to be controlled. The micromirror is typically driven at the resonant frequency of the moving mass.

[0008] Known systems present various disadvantages. In particular, they consist of a large number of components that are physically separate from one another. This leads to an increase in the overall system size and difficulties in achieving coordinated operation of the system components (for example, difficulties in effectively directing radiation to a specific point on the human body to be analyzed and detecting the radiation emitted by the human body with a high degree of accuracy).

[0009] There is a need in the art to provide a method of manufacturing an integrated component and a corresponding integrated component that overcomes the limitations of the prior art. Summary of the Invention

[0010] According to the present invention, a method of manufacturing an integrated component, and an integrated component are provided.

[0011] In an embodiment, a method for manufacturing an integrated component includes: providing a first wafer of semiconductor material, the first wafer having a surface; providing a second wafer of semiconductor material, the second wafer including a substrate and a structural layer on the substrate, the structural layer integrating a detector device for detecting electromagnetic radiation; coupling the structural layer of the second wafer to the surface of the first wafer; and processing the substrate of the second wafer to form a stator, a rotor and a moving mass block of a micromirror, the stator and the rotor forming a capacitive drive component for capacitively driving the moving mass block.

[0012] In an embodiment, the integrated component comprises: a first wafer of semiconductor material having a surface; and a second wafer of semiconductor material comprising a substrate and a structural layer on the substrate, the structural layer integrating a detector device for detecting electromagnetic radiation, wherein the structural layer of the second wafer is coupled to the surface of the first wafer, and wherein a stator, a rotor and a moving mass block of the micromirror are integrated in the substrate of the second wafer, the stator and the rotor forming a capacitive drive component for capacitively driving the moving mass block. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Preferred embodiments of the present invention will now be described, by way of non-limiting examples only, for a better understanding of the invention, with reference to the accompanying drawings, in which:

[0014] Figures 1 to 11 Steps for fabricating an integrated component according to an embodiment are shown in side cross-sectional view;

[0015] Figure 12 It includes Figures 1 to 11a schematic illustration of a system of integrated components manufactured in the steps of

[0016] Figure 13 An integrated component according to another embodiment is shown. DETAILED DESCRIPTION

[0017] Figures 1 to 11 The steps of manufacturing the integrated component 1 are illustrated in a side cross-sectional view with a three-axis Cartesian coordinate system having an X axis, a Y axis and a Z axis. Figure 11 As illustrated more fully below, the integrated component 1 comprises a detector device, in particular a thermal MOS (TMOS) transistor, and a micromirror, in particular a micromirror obtained via MEMS technology.

[0018] refer to Figure 1 A first wafer 100 is arranged, comprising a substrate 2 made of a semiconductor material such as silicon, comprising a top surface 2a opposite a bottom surface 2b along the Z axis. The thickness of substrate 2, measured along the Z axis, between top surface 2a and bottom surface 2b, is, for example, between 300 μm and 600 μm. Here, an insulating layer 9 made of silicon oxide (thermal oxide) surrounds substrate 2 and (as an example) has a thickness of approximately 1 μm.

[0019] Reference again Figure 1 , the insulating layer 9 is formed by photolithography and etching steps known in the art in order to remove selective portions thereof at the top surface 2a. More particularly, the insulating layer 9 is removed from the region of the top surface 2a where at least two bonding rings are to be formed, a first bonding ring being identified by reference numeral 4 (with segments 4a and 4b) and a second bonding ring being identified by reference numeral 5 (with segments 5a and 5b). In addition, the insulating layer 9 is likewise removed from the region of the top surface 2a where at least one bonding pad 3 and at least one metal contact 8 are to be formed. As will be explained more fully below, the insulating layer 9 is likewise removed from the region of the top surface 2a where trenches for the operation of the TMOS transistor and the micromirror are to be formed (in particular, in the portion of the top surface 2a bounded internally by the bonding rings 4 and 5).

[0020] Then, a masked implantation step is performed in a manner known per se in the art to form an implanted doped region 10 (particularly of N type) in a position corresponding to top surface 2 a. Implanted doped region 10 extends in the portion of top surface 2 a between bonding rings 4 and 5 .

[0021] In one embodiment, the formation of the bonding rings 4 and 5, the bonding pad 3, and the metal contact 8 is achieved simultaneously and includes: a step of depositing a metal layer (in particular, depositing germanium, for example, by sputtering) on ​​the top surface 2a of the substrate 2; and subsequent steps of photolithographic and etching definition of the deposited metal layer. The photolithographic step and the subsequent etching step are performed using a suitable mask configured to define (according to design specifications) the desired shape and extension of the bonding rings 4 and 5, the bonding pad 3, and the metal contact 8.

[0022] Bonding rings 4, 5 and bond pad 3 are formed to be in electrical contact with substrate 2. Metal contact 8 is formed at and in electrical contact with doped region 10. Doped region 10 provides electrical contact between metal contact 8 and substrate 2; metal contact 8 functions as a ground reference terminal in use.

[0023] refer to Figure 2 , an etching step of the first wafer 100 is performed to form a first groove 16 (for the operation of the micromirror). For this purpose, a first mask 15 is used, which has a first opening 15a; the first mask 15 is such that when it is used it covers the top surface 2a of the substrate 2 except for the surface area of ​​the substrate 2 designed to accommodate the first groove 16 (i.e. at the first opening 15a). In particular, the first groove 16 is formed on the inner side of the second bonding ring 5 between the segment 5a and the segment 5b of the second bonding ring 5 (i.e. in the cross-sectional view). The dry etching step indicated by the arrow 17 enables the portion of the substrate 2 not protected by the first mask 15 to be removed. The dry etching is carried out to a depth Z1 measured from the top surface 2a in the direction of the Z axis, which depth Z1 is several tens of micrometers (e.g. 60 μm). According to one embodiment, the first trench 16 is provided by means of deep reactive ion etching (DRIE).

[0024] Then( Figure 3 ), a second trench 21 (for the operation of the TMOS transistor) is formed, and the formation of the first trench 16 is similarly completed using a second etching mask 20. In particular, the second mask 20 has a first opening similar to the first opening 15a already present in the first mask 15 (and is therefore identified by the same reference numerals) and a second opening 20a at the surface area where the second trench 21 is to be formed. In particular, the second trench 21 is formed on the inner side of the first bonding ring 4 (i.e., between the segments 4a and 4b of the first bonding ring 4 in a cross-sectional view).

[0025] By implementing especially Figure 2The substrate 2 is selectively removed to form the second trench by a dry etch (identified by arrow 22) of the same type as that shown in FIG, and the etching of the first trench 16 is continued. Figure 3 The etching represented in is carried out until the first trench 16 reaches a depth along the Z axis equal to approximately 160 μm and the second trench 21 reaches a depth Z2 equal to approximately 100 μm (measured along the Z axis starting from the top surface 2 a ).

[0026] The first trench 16 and the second trench 21 are disposed to be spaced apart from each other by a distance X1 along the X-axis direction in a cross-sectional view, the distance X1 being equal to several hundred micrometers (eg, 100-200 μm).

[0027] use Figure 2 An additional etching step (e.g., via RIE) of the first mask 15 (or a similar mask having openings 15 a at the trenches 16) is performed in a manner known in the art to produce a blackening of the first trenches 16, thereby obtaining black silicon. Black silicon has a high radiation absorption coefficient (typically greater than 95%, in particular equal to or higher than 99%) and is used, in use, to reduce the reflection of undesired light radiation from the first trenches 16 toward the micromirrors.

[0028] In a manner known per se to a person skilled in the art, other methods for reducing the reflectivity of the first trenches 16 may be implemented, for example via deposition of a non-reflective material (eg carbon black, or other organic materials suitable for this purpose).

[0029] Alternatively, the blackening step of the first trench can be performed using Figure 3 In this case, in addition to the blackening of the first trench 16, the blackening process of silicon also leads to the blackening of the second trench 21. In this embodiment, because the blackening process of silicon is used in the embodiment of FIG. Figure 3 The second mask 20 already being present after the etching step has the advantage of speeding up the manufacturing steps.

[0030] refer to Figure 4 , a second pre-processed wafer 200 is now shown. The wafer 200 is Figure 1 The same three-axis coordinate system, having an X-axis, a Y-axis, and a Z-axis, is shown in a side cross-sectional view.

[0031] The second wafer 200 is manufactured using CMOS technology via processes and techniques known per se in the art (which do not form part of the present invention).

[0032] The second wafer 200 includes a substrate 28 of a semiconductor material such as silicon (having a thickness ranging from 500 μm to 900 μm, preferably 750 μm), and a structure portion 32 extends on the substrate 28. The structure portion 32 has a first surface 32 a and a second surface 32 b, and extending between the first surface 32 a and the second surface 32 b is a region 29 (e.g., including one or more layers of epitaxial silicon, a dielectric layer, and a metal layer) and an insulating layer 33 interposed between the region 29 and the substrate 28. The insulating layer 33 functions as an electrical insulator toward the substrate 28.

[0033] The second wafer 200 includes a third bonding ring 40 (at Figure 4 Segments 40a and 40b are shown in FIG. 4 and 4 and fourth bonding ring 42 is shown in FIG. Figure 4 (Segments 42a and 42b are shown in FIG. ). Third bond ring 40 and fourth bond ring 42 are both made of a metal material selected so as to form a eutectic alloy with the metal material used to form first bond ring 4 and second bond ring 5 of wafer 100. In one embodiment, the metal material of first bond ring 4 and second bond ring 5 is germanium, and the metal material of third bond ring 40 and fourth bond ring 42 is aluminum. Formation of the eutectic alloy includes a bonding step within a temperature range of between 200°C and 400°C, thereby creating a metal alloy that provides a permanent bond between the aluminum and germanium.

[0034] In particular, when the fourth bonding ring 42 and the first bonding ring 4 are coupled together, a bond is formed that ensures a hermetic seal; that is, the bond prevents gas molecules (such as air) from passing through it. The same applies to the coupling between the third bonding ring 40 and the second bonding ring 5.

[0035] According to one aspect of the present invention, region 29 accommodates a TMOS transistor 26, which is integrated in region 29 and disposed facing first surface 32 a of structural body 32. TMOS transistor 26 extends inside fourth bonding ring 42. TMOS transistor 26 is electrically coupled to a conductive pad 38 (e.g., made of germanium) on the outside of fourth bonding ring 42, which extends on first surface 32 a of structural body 32.

[0036] One or more conductive vias 35 electrically contacting conductive pads 38 extend completely through region 29 and insulating layer 33 until the one or more conductive vias 35 reach and contact substrate 28. The one or more conductive vias 35 are electrically insulated from region 29. Conductive pads 38 are also electrically connected to TMOS transistor 26 and have the function of receiving the output signal of TMOS transistor 26. For this purpose, substrate 28 is a doped type substrate (e.g., an N-type doped type substrate), or has a doped region (e.g., an N-type doped region), or has a conductive path (e.g., a metal path) for transmitting the signal of the TMOS transistor to the conductive pad, where the signal is obtained.

[0037] Conductive pad 38 is electrically insulated from region 29 by bottom dielectric layer 34, which extends between conductive pad 38 and region 29 except for the portion where conductive via 35 is present, and is insulated at the sides by side dielectric layer 36. As described more fully below, dielectric layer 36 exposes a top portion of conductive pad 38 to enable top electrical contact of conductive pad 38.

[0038] A metal contact 44 having the function of a ground reference contact extends on the first surface 32 a of the structural body 32 between the third bonding ring 40 and the fourth bonding ring 42 .

[0039] Conductive vias 46 extend through regions 29 at metal contacts 44 , electrically connecting metal contacts 44 to substrate 28 .

[0040] refer to Figure 5 The first surface 32 a of the structure portion 32 is covered by a passivation material layer 50 , such as silicon nitride (Si 3 N 4 ), which has a thickness of, for example, between 1 and 3 μm.

[0041] Passivation layer 50 is shaped by means of a photolithography or etching step using a third mask 52 and selectively etching passivation layer 50. In particular, third mask 52 covers and protects from etching portions of passivation layer 50 that extend in regions corresponding to TMOS transistor 26, third bonding ring 40, fourth bonding ring 42, metal contact 44, conductive pad 38, and dielectric layer 36 that laterally insulates conductive pad 38.

[0042] Then( Figure 6), a second etch, such as dry etching or DRIE, is performed to remove selective portions of structure portion 32 in areas corresponding to exposed areas (i.e., areas no longer covered by passivation layer 50). In this step, passivation layer 50 serves as an etching mask to protect the surface areas of wafer 200 covered by passivation layer 50. The removal of the selective portions of structure portion 32 continues until substrate 28 is reached.

[0043] Next, the passivation layer 50 is completely removed from the wafer 200. Figure 5 During the etching step 51 the portions covered by the third mask 52 are exposed.

[0044] Reference again Figure 6 , third bonding ring 40 defines a first ring region 60 at the top, which is formed by a portion of structural body 32 that was not previously removed and extends below third bonding ring 40. Fourth bonding ring 42 defines a second ring region 62 at the top, which is formed by a corresponding portion of structural body 32 that was not previously removed and extends below fourth bonding ring 42. Region 64 completely accommodates TMOS transistor 26, while region 66 completely accommodates conductive via 35 and conductive pad 38, and region 66 is covered on the surface by dielectric layer 36. In addition, region 68 is formed, which is defined at the top by metal contact 44 and accommodates conductive via 46.

[0045] refer to Figure 7 , according to a method known in the art as "flip chip", Figure 6 The wafer 200 is flipped 180° and is arranged with Figure 3 contact with the wafer 100.

[0046] In particular, the method is performed to provide the following electrical contacts: bond pad 3 in electrical contact with conductive pad 38 ; metal contact 44 in electrical contact with metal contact 8 ; first bond ring 4 in electrical contact with fourth bond ring 42 ; and second bond ring 5 in electrical contact with third bond ring 40 .

[0047] A stack 250 is thus obtained, formed by arranging the wafer 200 on top of the wafer 100 along the Z axis.

[0048] The electrical contacts thus formed are then heated, for example by means of a step of heating the stack 250 to a temperature ranging between 200° C. and 400° C., in order to produce a eutectic alloy between the metal of the elements 3 , 4 , 8 , 5 and the metal of the respective elements 38 , 42 , 44 , 40 .

[0049] The contact between the first bonding ring 4 and the fourth bonding ring 42 defines a first cavity 70 adapted to accommodate the TMOS transistor 26 , which thus faces the second trench 21 .

[0050] The contact between the second bonding ring 5 and the third bonding ring 40 defines a second cavity 72 suitable for accommodating the micromirror so that the micromirror will face the first trench 16 .

[0051] Substrate 28 has a first surface 80a and a second surface 80b opposite to each other along the Z axis. Second surface 80b of substrate 28 (belonging to wafer 200) faces first surface 2a of substrate 2 (belonging to wafer 100). In contrast, first surface 80a of substrate 28 is exposed to the external environment.

[0052] First surface 80a of substrate 28 is subsequently ground, wherein the thickness of substrate 28 is reduced along the Z-axis direction if necessary until a final thickness of several tens of micrometers is reached, and for example, a final thickness of approximately 65 μm is reached.

[0053] Then, metal contacts 74-77 are formed on first surface 80a of substrate 28 using deposition, photolithography, and etching techniques known in the art. For example, metal contacts 74-77 are made of aluminum, titanium, gold, or a titanium-gold alloy. In particular, metal contact 74 is formed to be vertically aligned (i.e., along the Z axis) with conductive pad 38, metal contact 75 is vertically aligned with metal contact 44, metal contact 76 (according to a non-limiting embodiment) is vertically aligned with segment 40a of third bond ring 40, and metal contact 77 (according to a non-limiting embodiment) is vertically aligned with segment 40b of third bond ring 40. More generally, and without implying any limitation of the present invention, metal contacts 76 and 77 are vertically aligned with respective portions of bond ring 5 and bond ring 40.

[0054] Metal contacts 74 and 75 are electrically coupled to conductive vias 35 and 46, respectively, by means of conductive paths and / or vias 71a, 71b inside substrate 28 and previously obtained for that purpose; whereas metal contacts 76, 77 are electrically coupled to substrate 28 (or to conductive regions of substrate 28).

[0055] In this manner, metal contact 74 forms a pad for supplying the current signal from TMOS transistor 26 .

[0056] Through hole 35 connects TMOS transistor to metal contact 74, and passes through in the dielectric layer interior of the stacked body formed so far.In this case, the contact 38 that is usually used for wire bonding to read output signal is used as extra bonding layer.Assuming that TMOS transistor 26 is overturned due to the flip chip operation described previously, through hole 35 carries signal to metal contact 74 by silicon, so that the signal of TMOS transistor 26 supplied at metal contact 74 place can be read for example via wire bonding.Metal contact 75 is suitable for being used as the ground contact of micromirror.As described more fully hereinafter, metal contact 76 and metal contact 77 supply drive current to the rotor and stator of micromirror.

[0057] In particular, refer to Figure 8 , additional photolithography and etching steps (not shown in detail) are performed to shape substrate 28 at surface 80a.

[0058] In particular, substrate 28 is etched to form a plurality of functional regions.

[0059] A first region 90 of substrate 28 is bounded on top by metal contact 74, and a second region 91 is bounded on top by metal contact 75. First region 90 and second region 91 have the function of defining points of electrical contact for taking the output signal of TMOS transistor 26 and providing a ground reference signal, respectively.

[0060] A third region 92 of substrate 28 houses TMOS transistor 26 .

[0061] A fourth region 93 of substrate 28 forms part of a micromirror, in particular forming a mobile mass carrying a reflective element, which is suspended above cavity 72 and first groove 16 by means of a torsion spring of a type known per se in the art.

[0062] A fifth region 94 of substrate 28 carries metal contacts 76 on top and forms the micromirror's rotor. A sixth region 95 of substrate 28 carries metal contacts 77 on top and forms the micromirror's stator. Both fifth region 94 (rotor) and sixth region 95 (stator) are capacitively coupled to fourth region 93 (moving mass) in a manner known per se in the art, and thus, when fifth region 94 and sixth region 95 are appropriately biased, generate oscillations of the micromirror's moving mass. In use, the micromirror's stator and rotor are biased via respective metal contacts 76 and 77.

[0063] Furthermore, seventh region 96 extends so as to vertically correspond to segment 42b of fourth key ring 42. Eighth region 97 and ninth region 98 extend laterally beside first region 90.

[0064] It may be noted that the aforementioned regions 90 - 97 are electrically insulated from each other.

[0065] refer to Figure 9 The third wafer 300 (eg, having a thickness ranging between 300 μm and 700 μm, preferably 400 μm) is coupled to the stack 250 , in particular on the second wafer 200 .

[0066] In particular, two or more coupling (or bonding) elements 101a, 101b are arranged to mechanically couple the third wafer 300 to the second wafer 200. In particular, the coupling elements 101a, 101b are arranged outside the metal contacts 74 and 77, respectively. For example, the coupling element 101a is coupled to the eighth region 97, whereas the coupling element 101b is coupled to the sixth region 95.

[0067] The coupling elements 101a, 101b have a shape, extension and thickness making it possible to structurally support the third wafer 300 and avoid contact between the third wafer 300 and the second wafer 200 (except, of course, at the coupling point between the two wafers 200, 300).

[0068] The coupling elements 101 a , 101 b may be formed via sputtering a metal alloy including aluminum and copper, and the coupling elements 101 a , 101 b may be fixed to the wafers 300 and 200 via low-temperature temporary bonding.

[0069] The third wafer 300 functions as a mask to protect and process the stack 250, and can be made of a semiconductor material such as silicon. Wafer 300 undergoes photolithography and etching steps to form openings 310 at the moving masses 93 of the micromirror. Openings 310 can be formed before or after the coupling step between wafer 300 and stack 250, depending on the appropriate form apparent to those skilled in the art.

[0070] For example, the deposition step of the reflective material of the metal material (in Figure 9 The step represented by the arrow 105 in FIG1 is performed, for example, via a sputtering technique. The metal deposition step 105 enables the metal layer 103 to be created on the areas not covered by the third wafer 300, i.e. the metal layer 103 can be created on the fourth area 93 (the moving mass of the micromirror). The metal layer 103 can be made of a highly reflective metal (e.g. with a reflection coefficient higher than 95% - typically with a reflection coefficient between 95% and 98%) such as aluminum, gold or AlCu. Thus, the micromirror (on Figure 9 The manufacture of (indicated by reference numeral 104 in the figure).

[0071] Once deposition is complete, the third wafer 300 and the coupling elements 101a, 101b are removed.

[0072] Next comes the step of producing a protective cover for the stack 250 thus obtained.

[0073] Next reference Figures 10A to 11 An embodiment of a protective cover will be described.

[0074] refer to Figure 10A , the fourth wafer 400 is processed to create a protective cover. In particular, the fourth wafer 400 includes a substrate 111 of a semiconductor material, such as silicon, having a first surface 111a and a second surface 111b. The thickness of the substrate 111 between the first surface 111a and the second surface 111b (i.e., along the Z axis) is in the range of approximately 300 μm to 800 μm (e.g., 400 μm). The substrate 111 can be a pre-processed type substrate and can include, for example, one or more epitaxial layers.

[0075] In a machining step, the fourth wafer 400 is subjected to photolithography and etching steps to remove selective portions of the substrate 111 so as to form recesses 111a' at the first surface 111a. The recesses 111a' are formed in regions of the wafer 400 that are to be fabricated in subsequent manufacturing steps ( Figure 11 ) will be oriented to face the stack 250, in particular, the TMOS transistor 26.

[0076] The recess 111a' has a depth of, for example, about 5 μm along the Z axis from the first surface 111a, and a width of, for example, about 50 μm along the X axis. In a top view in a plane XY defined by the X axis and the Y axis, the recess has a quadrilateral shape (for example, a square), or a circular or substantially polygonal shape. The recess 111a' is configured to accommodate a gas-absorbing material, known in the art as a "getter," which is formed in the Figure 10A Indicated by reference numeral 110 .

[0077] Getter 110 is usually made of a material deposited in the form of a layer, and getter 110 has the function of absorbing specific gas molecules. The material used as the getter layer is known in the art and includes, for example, a metal such as aluminum (Al), barium (Ba), zirconium (Zr), titanium (Ti), vanadium (V), iron (Fe), or a mixture or alloy thereof, such as zirconium aluminum, zirconium vanadium iron, zirconium nickel, zirconium cobalt (particularly Zr / Co / O alloy). The getter material can be deposited in the recess 111a' by means of a stripping process. In this case, during the deposition step of the getter material, the same photoresist as that used for photolithographically defining the recess 111a' is also maintained on the wafer 400. Subsequent stripping steps make it possible to remove the photoresist from the wafer 400 in a self-aligned manner, and only the getter material is retained in the inner side of the recess 111a'.

[0078] Furthermore, a plurality of coupling regions are formed, in particular glass frit regions 112-114 are formed, the cross-sectional views of which (112a, 112b; 113a, 113b; 114a, 114b) are shown in FIG. Figure 10A Each coupling region has a thickness along the Z axis of, for example, approximately 5 μm, and a width in a cross-sectional view along the X axis equal to, for example, approximately 10 μm.

[0079] In a top view in plane XY, coupling region 112 is a ring enclosing coupling regions 113, 114 and the interior of getter 110. In various embodiments, coupling region 112 is not a ring but is instead formed by a plurality of regions physically separated from one another.

[0080] In the top view in plane XY, the coupling region 113 is a ring having a diameter greater than the distance along the X axis between the stator and the rotor of the micromirror 104, so that when the wafer 400 is coupled to the stack 250 ( Figure 11 ), the coupling region 113 extends outside the stator region and the rotor region (or in a position corresponding thereto), thereby completely surrounding the micromirror 104.

[0081] Obviously, the coupling region 113 may not be annular and may instead be formed by a plurality of regions that are physically separated from each other and thus only partially surround the micromirror 104. In fact, the micromirror 104 does not need to be located in a closed or airtight chamber.

[0082] In a top view in plane XY, the coupling region 114 is a ring that encloses the getter 110. As described more fully below, when the wafer 400 is coupled to the stack 250 ( FIG. 11 ), the coupling region 114 forms a hermetic coupling, thereby isolating the internal environment, including the getter, from the external environment. To this end, the coupling region 114 completely surrounds the getter 110 and can in any case have a shape other than a circle (e.g., an elliptical or polygonal shape).

[0083] Then, Figure 10A The structure is subjected to Figure 10B ) a photolithography and etching process (eg, an RIE or DRIE process) for removing selective portions of the fourth wafer 400 throughout its thickness.

[0084] Specifically, the fourth wafer 400 is etched to remove the top portion of the wafer 400 that is not protected by the coupling regions 112-114. Furthermore, the inner surface of the wafer 400 defined by the coupling region 114 (where the getter 110 is present) is not etched. Consequently, a plurality of structural support regions 120-123 and a cover region 124 are formed.

[0085] A first through-opening 131 extending in a position corresponding to the rotor contact 76 is between the structural support region 122 and the cover region 124 and is shaped to form a passage for providing electrical contact (e.g., via wire bonding) with the rotor contact 76. A second through-opening 133 extending in a position corresponding to the stator contact 77 is between the structural support region 120 and the structural support region 121 and is shaped to form a passage for providing electrical contact (e.g., via wire bonding) with the stator contact 77. A third through-opening 134 extending in a position corresponding to the micromirror 104 is between the structural support region 121 and the structural support region 122 and is shaped to form an optical passage for radiation incident on and exiting the reflective layer 103 of the micromirror 104. A fourth through-opening 135 extending in a position corresponding to the metal contact 74 is between the structural support region 123 and the cover region 124 and is shaped so as to form a via for providing electrical contact with the metal contact 74 (eg, by means of wire bonding).

[0086] As reference Figure 11 As shown in the figure, Figure 10B The structure is set up with Figure 9 The stack 250 is contacted (using a flip chip method).

[0087] In particular, the outer coupling region 112 is arranged to contact the eighth region 97 and the sixth region 95 of the second wafer 200 ; the coupling region 114 is arranged to contact the ninth region 98 and the seventh region 96 ; and the coupling region 113 is arranged to contact the fifth region 94 and the sixth region 95 .

[0088] In more detail, coupling region 112 extends outside of metal contacts 74 and 77, which are accessible from the outside via a previously made hole through wafer 400. In a top view in plane XY, coupling region 114 completely surrounds TMOS transistor 26 to form a gas-tight chamber 140 that is isolated from the ambient fluid outside of said chamber 140. Coupling region 113 (as previously described, at least partially) surrounds the moving mass of micromirror 104, thereby exposing the reflective layer of micromirror 104 and making it accessible from the outside for the light beam to be incident thereon. Furthermore, metal contacts 76 and 75 are accessible via a previously made hole through wafer 400.

[0089] After coupling between wafer 400 and stack 250 , the resulting structure (stack 450 ) is heated to a high temperature (eg, 350-450° C.) to melt the glass frit of coupling regions 112 - 114 and achieve permanent bonding of wafer 400 to wafer 200 .

[0090] The getter 110 is then activated to generate a pressure P1 inside the chamber 140 containing the TMOS transistor, which is lower than the pressure P2 outside the chamber 140. For example, the pressure P1 is in the range of 10 -2 to 10 -3 Between millibars (mbar).

[0091] The micromirror (and in particular the mass) is capacitively actuated by appropriately biasing (in a manner known per se in the art and not constituting the subject of the present invention) the rotor (i.e., the fifth region 94 enables biasing via the metal contact 76) and the stator (enabling biasing via the metal contact 77). Said biasing results in an imbalance of the mobile mass, which is driven into oscillation, in particular at its resonant frequency.

[0092] Combined with reference Figure 11 and 12 During use, the micromirror 104 receives optical radiation R1 on the reflective layer through the corresponding opening in the wafer 400 and directs the reflected optical radiation R2 toward a point in space or a human body 150 (eg, an area of ​​a patient's body).

[0093] The incidence of the optical radiation R2 on the human body 150 leads to an increase in the temperature of the human body 150 , and thus radiation R3 is emitted by the human body 150 , the intensity of which depends on the temperature of the human body 150 itself.

[0094] Because TMOS transistor 26 is sensitive to electromagnetic radiation R3 emitted by human body 150, the temperature increase of human body 150 is detected by TMOS transistor 26 and converted into a current signal at the output of TMOS transistor 26. The vacuum present in chamber 140 containing TMOS transistor 26 thermally decouples chamber 140 from the external environment, and this vacuum can improve the accuracy of the measurement.

[0095] Since the temperature measurement is independent of the direction of incidence of the electromagnetic radiation on the TMOS transistor 26 , no measurement problems arise even if electromagnetic radiation R3 emitted by a heated human body 150 impinges on the back of the TMOS transistor 26 .

[0096] Additionally, it is known in the art that a warm human body emits electromagnetic radiation in the infrared, and this electromagnetic radiation is largely not absorbed and blocked by a layer of semiconductor material having a thickness of several hundred micrometers, such as region 124 of wafer 400 covering chamber 140. Therefore, covering region 124 does not prevent the electromagnetic radiation from reaching the TMOS transistor so that the electromagnetic radiation can be detected.

[0097] Alternatively, the area above the micromirror 104 is not covered by a layer of material such as to block optical radiation incident on the reflective layer.

[0098] The electrical signal generated at the output of the TMOS transistor 26 is acquired via the metal contact 74 for subsequent processing.

[0099] Figure 13 Another embodiment of a protective cover is shown.

[0100] In this case, the cover is not obtained via processing of a wafer 400 of semiconductor material, but rather a wafer 500 of a material transparent to the optical radiation that, in use, impinges on the reflective layer of the micromirrors 104 is used (for example glass).

[0101] With the same Figure 10A and Figure 10B, wafer 500 is processed by techniques known per se to form footprints 124′ for TMOS transistor 26, which footprints 124′ are similar to footprints 124 described above and have a similar function. However, in this case, through-openings are formed through wafer 500 only at the areas aligned along the Z axis with metal contacts 74, 75, 76, and 77 (when wafer 500 and stack 250 are coupled together).

[0102] The coupling between the wafer 500 and the stack 250 is obtained by a flip chip process, Figure 13 of stack 550.

[0103] exist Figure 13 In the embodiment, there is no getter.

[0104] Instead, a cover area 125 (for example made of glass, as already described) is present, which extends over the reflective layer of the micromirror 104 .

[0105] With the help of reference Figures 10A to 11 The coupling regions depicted are similar and are therefore denoted by the same reference numerals as coupling regions 112 - 114 , with wafer 500 coupled to wafer 200 .

[0106] In order to obtain a pressure P1 (which is lower than P2 ) inside the chamber 140 accommodating the TMOS transistor 26 , coupling between the wafer 500 and the stack 250 is performed in an environment of the pressure P1 .

[0107] The micromirror cover area 125 enables protection of the micromirror 104 and at the same time allows the penetration of optical radiation coming from the outside and impinging on the reflective layer of the mobile mass during use.

[0108] In this embodiment, both the chamber 141 of the micromirror and the chamber 140 of the TMOS transistor are in a low voltage condition ( P1 ).

[0109] The advantages provided by the present invention are apparent upon examination of the features of the present invention provided in light of this disclosure.

[0110] In particular, integrating the micromirror and the TMOS transistor in one and the same wafer enables the area necessary to manufacture a system comprising the TMOS transistor and the micromirror to be reduced, and thus makes it possible to obtain a small and easy-to-handle device.

[0111] Due to the possibility of controlling the radiation incident on the body to be heated via the micromirrors in an efficient and accurate manner, the measurements using TMOS transistors are more accurate than those currently available in the prior art.

[0112] The use of a compact and integrated system enables the time required to obtain measurement results to be reduced and also enables the system to be used at room temperature.

[0113] The use of TMOS transistors integrated with micromirrors facilitates the identification of known diseases and conditions, thus having a positive impact on preventive medicine.

[0114] Furthermore, the integrated component described above can be easily generalized to meet a variety of needs, rather than being used only in the diagnostic field. These variants can be obtained by adjusting the parameters of the TMOS transistor according to the frequency of the infrared radiation to be measured and depending on the application itself.

[0115] Finally, it is clear that modifications and variations may be made to the invention described and illustrated herein without departing from the scope of the invention as defined in the appended claims.

[0116] In particular, an alternative embodiment includes an integrated component 1 in which the cover region 124 is absent. Consequently, the TMOS transistor 26 is not fluidically and thermally isolated from the external environment. Noise in the electromagnetic radiation R3 measured by the TMOS transistor 26 (e.g., due to thermal fluctuations of the external environment) can be eliminated by performing the measurement in a differential mode with the assistance of, for example, a temperature sensor integrated into the component 1, coupled to the component 1, or arranged in the vicinity of the component 1. The temperature sensor is adapted to record the temperature of the external environment and to provide an electrical signal at its output that is proportional to the temperature of the external environment; thus, the effects of thermal fluctuations of the external environment can be subtracted from the electrical signal from the TMOS transistor 26, thereby enabling highly accurate measurements to be achieved even without the cover region 124 and the airtight chamber 140.

Claims

1. A method for manufacturing an integrated component, comprising: providing a first wafer of semiconductor material, the first wafer having a surface; providing a second wafer of semiconductor material, the second wafer comprising a substrate and a structural layer on the substrate, the structural layer integrating a detector device configured to detect electromagnetic radiation; coupling the structural layer of the second wafer to the surface of the first wafer; as well as The substrate of the second wafer is processed to form a stator, a rotor, and a moving mass of a micromirror, the stator and the rotor forming a capacitive drive assembly for capacitively driving the moving mass.

2. The method according to claim 1, further comprising: coupling a first cover to the substrate of the second wafer corresponding to the detector device, and Wherein coupling the structural layers and coupling the first cover are performed so as to form a first airtight chamber accommodating the detector device.

3. The method according to claim 2, further comprising: coupling a second cover to the substrate of the second wafer at the micromirror, and Wherein coupling the structural layer and coupling the second cover are performed to form a second airtight chamber accommodating the micromirror.

4. The method according to claim 2, further comprising: forming a stator contact electrically coupled to the stator of the micromirror; as well as forming a rotor contact electrically coupled to the rotor of the micromirror, Wherein coupling the first cover includes coupling a third wafer to the substrate of the second wafer and shaping the third wafer to form the first cover, a first through-opening at the rotor contact, and a second through-opening at the stator contact.

5. The method according to claim 4, further comprising: coupling a second cover to the substrate of the second wafer at the micromirror, and Wherein coupling the structural layer and coupling the second cover are performed to form a second airtight chamber accommodating the micromirror.

6. The method of claim 5, wherein coupling the second cover comprises: The third wafer is shaped to form the first cover, the second cover, the first through-opening, and the second through-opening.

7. The method of claim 5, wherein the first cover and the second cover are jointly formed by processing a same glass wafer.

8. The method of claim 1 , wherein the step of coupling the structural layer of the second wafer to the surface of the first wafer comprises: forming a first coupling ring on the structural layer to surround the detector device, the first coupling ring being made of a first material; forming a second coupling ring on the surface of the first wafer, wherein the second coupling ring is made of a second material; placing the first coupling ring and the second coupling ring in contact with each other; and A heat treatment is performed to form a eutectic bond between the first material and the second material.

9. The method according to claim 1, further comprising: coupling a first cover to the substrate of the second wafer corresponding to the detector device; wherein coupling the structural layers and coupling the first cover are performed so as to form a first airtight chamber housing the detector device; forming a recess in the first cover, the recess extending onto the airtight chamber; and A getter material is mounted in the recess.

10. The method according to claim 1, further comprising: forming a first trench and a second trench in the first wafer starting from the surface; as well as processing at least the first groove to reduce reflectivity of the first groove, wherein coupling the structured layer of the second wafer to the surface of the first wafer comprises: arranging the second trench to face the detector device; and Wherein processing the substrate of the second wafer includes forming the stator, the rotor, and the moving mass so that the stator, the rotor, and the moving mass face the first groove.

11. An integrated component comprising: a first wafer of semiconductor material, the first wafer having a surface; as well as a second wafer of semiconductor material, said second wafer comprising a substrate and a structural layer on said substrate, said structural layer integrating a detector device for detecting electromagnetic radiation; wherein the structural layer of the second wafer is coupled to the surface of the first wafer; as well as A stator, a rotor and a moving mass of a micromirror are integrated in the substrate of the second wafer, the stator and the rotor forming a capacitive drive assembly for capacitively driving the moving mass.

12. The integrated component according to claim 11, further comprising: a first cover coupled to the substrate at the detector device, and Wherein the structural layer and the first cover are coupled to the surface and the substrate, respectively, so as to define a first airtight chamber housing the detector device.

13. The integrated component according to claim 12, further comprising: a second cover coupled to the substrate at the micromirror, and The structural layer and the second cover are coupled to the surface and the substrate, respectively, so as to define a second airtight chamber accommodating the micromirror.

14. The integrated component according to claim 12, further comprising: a stator contact electrically coupled to the stator of the micromirror; a rotor contact electrically coupled to the rotor of the micromirror; as well as A third wafer is coupled to the substrate and is shaped to form the first cover, a first through-opening at the rotor contact, and a second through-opening at the stator contact.

15. The integrated component according to claim 14, further comprising: a second cover coupled to the substrate at the micromirror, and The structural layer and the second cover are coupled to the surface and the substrate, respectively, so as to define a second airtight chamber accommodating the micromirror. 16 . The integrated component according to claim 15 , wherein the third wafer is shaped so as to form the first cover, the second cover, the first through-opening, and the second through-opening.

17. The integrated component according to claim 15, wherein the first cover and the second cover are made of glass.

18. The integrated component according to claim 11, further comprising: a first coupling ring extending over the structural layer and surrounding the detector device, the first coupling ring being made of a first material; as well as a second coupling ring extending on the surface of the first wafer, the second coupling ring being made of a second material; The first coupling ring and the second coupling ring are in contact with each other, and the first material and the second material form a eutectic bond.

19. The integrated component according to claim 11, further comprising: a first cover coupled to the substrate at the detector device; wherein the structural layer and the first cover are coupled to the surface and the substrate, respectively, so as to define a first airtight chamber housing the detector device; a recess in the cover, the recess being within the airtight chamber; as well as A getter layer is provided in the recess.

20. The integrated component according to claim 11, further comprising: a first trench extending in the first wafer from the surface, the first trench facing the stator, the rotor, and the moving mass, wherein the first trench has reduced reflectivity; as well as A second trench extends in the first wafer starting from the surface, the second trench facing the detector device.

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