Variable resistance memory device

Abstract

A variable resistance memory device includes memory cell stacks arranged in a first direction, the memory cell stacks including a first memory cell stack and a second memory cell stack. Each of the memory cell stacks includes a plurality of word lines and a memory cell connected to each of the plurality of word lines, each of the plurality of word lines extending in a second direction crossing the first direction and arranged in a third direction crossing the first and second directions. Each of the memory cells includes a switching element and a variable resistance element. Each of the plurality of word lines of the first memory cell stack has a first thickness in the first direction, the first thickness being smaller than a second thickness of each of the plurality of word lines of the second memory cell stack in the first direction.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0008898, filed on January 23, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to variable resistance memory devices. Background Technology

[0004] Semiconductor devices can be classified as either memory devices or logic devices. Memory devices store logical data. Generally, semiconductor memory devices can be categorized into volatile memory devices and non-volatile memory devices. Volatile memory devices may lose their stored data when their power is interrupted. For example, volatile memory devices can include dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. Conversely, non-volatile memory devices retain their stored data even when their power is interrupted. For example, non-volatile memory devices can include programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory devices. Summary of the Invention

[0005] Some exemplary embodiments of the present invention can provide variable resistance memory devices capable of improving electrical characteristics.

[0006] According to some exemplary embodiments of the present invention, a variable resistor memory device may include a stack of memory cells arranged along a first direction, the stack including a first memory cell stack and a second memory cell stack, and each of the memory cell stacks includes multiple word lines and memory cells connected to the multiple word lines. Each of the multiple word lines extends along a second direction intersecting the first direction and is arranged along a third direction intersecting the first and second directions. The memory cell includes a switching element and a variable resistor element. Each of the multiple word lines of the first memory cell stack may have a first thickness in the first direction, the first thickness being less than a second thickness of each of the multiple word lines of the second memory cell stack in the second direction.

[0007] According to some exemplary embodiments of the present invention, a variable resistance memory device may include a stack of memory cells on a substrate, wherein the stack of memory cells includes: a word line having a thickness in a first direction, extending along a second direction and arranged upward along a third direction intersecting the second direction; a bit line extending along the third direction and arranged along the second direction; and memory cells disposed at the intersection of the word line and the bit line, wherein each of the memory cells includes a switching element and a variable resistance element. The thickness of the word line in the first direction of at least one of the memory cell stacks may differ from the thickness of the word lines in the first direction of other memory cell stacks.

[0008] According to some exemplary embodiments of the present invention, a variable resistance memory device may include a substrate and a stacked structure arranged along a first direction on the top surface of the substrate, wherein each of the stacked structures includes word lines, bit lines, and memory cells, wherein the word lines extend along a second direction parallel to the top surface of the substrate and are arranged along a third direction perpendicular to the top surface of the substrate, the word lines including first sub-word lines and second sub-word lines spaced apart from the first sub-word lines in the first direction, the first direction intersecting the second and third directions, bit lines may be located between the first and second sub-word lines and may be arranged along the second direction, and memory cells are located at the intersections of the first sub-word lines and bit lines and at the intersections of the second word lines and bit lines, wherein each of the memory cells includes a switching element and a variable resistance element. The thickness of the word line in at least one of the stacked structures in the first direction may differ from the thickness of the word lines in the first direction of other stacked structures. Attached Figure Description

[0009] The inventive concept will become more apparent from the accompanying drawings and detailed description.

[0010] Figure 1 This is a block diagram illustrating some example embodiments of a variable resistance memory device according to the present invention.

[0011] Figure 2 This is a plan view illustrating some example embodiments of a variable resistance memory device according to the present invention.

[0012] Figure 3 It is along Figure 2 Cross-sectional views taken from lines I-I' and II-II'.

[0013] Figure 4 It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' are shown to illustrate a variable resistance memory device according to some exemplary embodiments of the concept of the present invention.

[0014] Figure 5 and Figure 6 It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' are shown to illustrate a variable resistance memory device according to some exemplary embodiments of the concept of the present invention.

[0015] Figures 7 to 10 It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' illustrate a method for manufacturing a variable resistance memory device according to some exemplary embodiments of the invention.

[0016] Figure 11 and Figure 12 It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' are shown to illustrate a variable resistance memory device according to some exemplary embodiments of the concept of the present invention.

[0017] Figure 13 and Figure 14 yes Figure 11 A magnified view of region 'Q'.

[0018] Figure 15 This is a perspective view schematically illustrating some example embodiments of a variable resistance memory device according to the present invention.

[0019] Figures 16A to 16D This is a perspective view illustrating a unit memory cell of a variable resistance memory device according to some exemplary embodiments of the present invention.

[0020] Figure 17 This is a plan view illustrating some example embodiments of a variable resistance memory device according to the present invention.

[0021] Figure 18 It is along Figure 17 A cross-sectional view taken from line I-I'.

[0022] Figure 19 It is along Figure 17 The cross-sectional view taken from line II-II'.

[0023] Figure 20 It is shown Figure 17 A plan view showing the arrangement of word lines, bit lines, and memory cells.

[0024] Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A This is a plan view illustrating a method for manufacturing a variable resistance memory device according to some exemplary embodiments of the present invention.

[0025] Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 25B They are along Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A A cross-sectional view taken from line I-I'.

[0026] Figure 21C , Figure 22C , Figure 23C , Figure 24C and Figure 25C They are along Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A The cross-sectional view taken from line II-II'.

[0027] Figure 26 This is a plan view illustrating some example embodiments of a variable resistance memory device according to the present invention. Detailed Implementation

[0028] Figure 1 This is a block diagram illustrating some exemplary embodiments of a variable resistance memory device according to a concept conceived in this invention. The variable resistance memory device 20 may include a memory cell array 21, a row decoder 22, a write driver 26, a sense amplifier 23, and a column decoder 25.

[0029] The memory cell array 21 may include memory cells connected to word lines WL and bit lines BL. In some example embodiments, the memory cells in each row may be connected to one word line in the word lines WL. The memory cells in each column may be connected to one bit line in the bit lines BL. The memory cell array 21 may correspond to at least one memory cell stack in the memory cell stack described later. The memory cell array 21 may include variable resistance memory cells, such as phase-change memory cells.

[0030] The row decoder 22 can be connected to the memory cell array 21 via the sense amplifier 23 and word lines WL. The row decoder 22 can receive a row address signal RA. The row decoder 22 can select a word line in the word lines WL in response to the row address signal RA. The row decoder 22 can apply a selection voltage or selection current to the selected word line, and can apply a non-selection voltage or non-selection current to the unselected word line.

[0031] The sense amplifier 23 can read voltage or current to read data from a selected memory cell. In some example embodiments, the sense amplifier 23 can perform a read operation on the selected memory cell to determine or check the range of resistance values ​​of the selected memory cell, thereby reading data.

[0032] The write driver 26 can be connected to the memory cell array 21 via bit line BL. The write driver 26 can apply voltage or current to the bit line BL to write data to selected memory cells. In some example embodiments, the write driver 26 can perform a set operation or a reset operation on the selected memory cell to change the resistance value of the selected memory cell, thereby writing or erasing data.

[0033] Column decoder 25 can receive column address signal CA. Column decoder 25 can select at least one bit line in bit line BL in response to column address signal CA. To achieve this, column decoder 25 can select and control some write drivers 26.

[0034] Figure 2 This is a plan view illustrating some example embodiments of a variable resistance memory device according to the present invention. Figure 3 It is along Figure 2 Cross-sectional views taken from lines I-I' and II-II'.

[0035] Reference Figure 2 and Figure 3 The memory cell stack MCA can be disposed on the substrate 100. In some example embodiments, the memory cell stack MCA may include a first memory cell stack MCA1 and a second memory cell stack MCA2, which are arranged or stacked in a first direction D1 perpendicular to the top surface of the substrate 100. For ease of explanation, two memory cell stack MCAs are used as an example for illustration. However, in some example embodiments, three or more memory cell stack MCAs may be disposed on the substrate 100.

[0036] Each of the memory cell stack MCAs may include a word line CL1 disposed on the substrate 100 and a bit line CL2 disposed on the word line CL1. In some example embodiments, the first memory cell stack MCA1 may include a first word line CL1_1, a first bit line CL2_1, and a memory cell MC between the first word line CL1_1 and the first bit line CL2_1. See reference Figure 1 As described, word line CL1 can be an interconnect connected to row decoder 22. In some example embodiments, word line CL1 can be connected to row decoder 22 via readout amplifier 23. Bit line CL2 can be an interconnect connected to column decoder 25. In some example embodiments, bit line CL2 can be connected to column decoder 25 via write driver 26.

[0037] The first memory cell stack MCA1 will be described in more detail below. Each first word line CL1_1 may extend in a second direction D2 intersecting the first direction D1, and may be arranged in a third direction D3 intersecting the first direction D1 and the second direction D2. The second direction D2 and the third direction D3 may be directions parallel to the top surface of the substrate 100. Each first bit line CL2_1 may extend in the third direction D3, and may be arranged in the second direction D2.

[0038] The first word line CL1_1 and the first bit line CL2_1 may comprise conductive materials such as copper or aluminum. The first word line CL1_1 and the first bit line CL2_1 may also comprise conductive metal nitrides such as TiN or WN.

[0039] Memory cells MC can be disposed at the intersection of the first word line CL1_1 and the first bit line CL2_1, respectively. Each memory cell MC may include a variable resistor element CR and a switching element SW. Each memory cell MC may also include an intermediate electrode ME between the variable resistor element CR and the switching element SW. The variable resistor element CR may be disposed between the switching element SW and the substrate 100. Alternatively, the switching element SW may be disposed between the variable resistor element CR and the substrate 100. In the following description, for the purpose of simplicity, an exemplary embodiment in which the variable resistor element CR is disposed between the first word line CL1_1 and the switching element SW will be described. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0040] The first word line CL1_1 can be disposed in the lower interlayer insulating layer 107. The variable resistor element CR can be disposed in the recessed region RS formed in the first to third interlayer insulating layers 111, 113, and 115 on the first word line CL1_1. In some example embodiments, the first to third interlayer insulating layers 111, 113, and 115 may comprise silicon nitride or silicon oxynitride. When viewed in a plan view, the recessed region RS can be disposed at the intersection of the first word line CL1_1 and the first first word line CL2_1, and thus can be arranged in two dimensions. Alternatively, the variable resistor element CR can have a line shape extending in a second direction D2 or a third direction D3.

[0041] The variable resistance element CR can be formed from at least one of materials having the property of storing logical data. When the variable resistance memory device according to some exemplary embodiments of the present invention is a phase change memory device, the variable resistance element CR can include a material whose phase can be reversibly changed between a crystalline phase and an amorphous phase depending on temperature. In some exemplary embodiments, the phase transition temperature between the crystalline phase and the amorphous phase of the variable resistance element CR can be in the range of about 250 degrees Celsius to about 350 degrees Celsius. The variable resistance element CR can be formed from a compound including at least one of Te and Se (i.e., chalcogenide elements) and at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C. In some exemplary embodiments, the variable resistance element CR can include at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe. In some example embodiments, the variable resistance element CR may have a superlattice structure in which layers including Ge and layers not including Ge are repeatedly and alternately stacked. In some example embodiments, the variable resistance element CR may have a structure in which GeTe layers and SbTe layers are repeatedly and alternately stacked.

[0042] Heater electrodes HE can be disposed between the first word line CL1_1 and the variable resistor element CR. Each heater electrode HE can connect a pair of variable resistor elements CR adjacent to each other in the second direction D2 to the first word line CL1_1. In some example embodiments, each of the heater electrodes HE may include a horizontal portion connected to the first word line CL1_1 and a pair of vertical portions extending from the two ends of the horizontal portion to the pair of variable resistor elements CR, respectively. Alternatively, when viewed in a plan view, the heater electrodes HE can be disposed at the intersection of the first word line CL1_1 and the first first word line CL2_1, and thus can be arranged in two dimensions.

[0043] The heater electrode HE can heat the variable resistance element CR to change the phase of the variable resistance element CR. The heater electrode HE can be formed of a material with a resistivity greater than that of the first word line CL1_1. In some exemplary embodiments, the heater electrode HE may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, and TiO.

[0044] Spacer pattern 127 may be disposed between each of the heater electrodes HE and the second interlayer insulating layer 113. Spacer pattern 127 may extend along both the horizontal and vertical portions of the heater electrodes HE. In some example embodiments, spacer pattern 127 may comprise silicon oxide and / or silicon oxynitride.

[0045] The lower portion of the recessed region RS can be occupied by a variable resistor element CR, and the upper portion of the recessed region RS can be occupied by an intermediate electrode ME. The intermediate electrode ME can electrically connect the variable resistor element CR to the switching element SW, and can prevent the variable resistor element CR from directly contacting the switching element SW. In some example embodiments, the intermediate electrode ME may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN. The top surfaces of the first to third interlayer insulating layers 111, 113, and 115 may be substantially coplanar with the top surface of the intermediate electrode ME. Alternatively, the intermediate electrode ME may be disposed on the first to third interlayer insulating layers 111, 113, and 115.

[0046] Each of the switching elements SW may include a bidirectional threshold switch (OTS) element with bidirectional characteristics. In some example embodiments, each of the switching elements SW may include an element based on a threshold switching phenomenon having a nonlinear IV curve (e.g., an S-shaped IV curve). The switching element SW may have a phase transition temperature between a crystalline and amorphous phase that is higher than that between a crystalline and amorphous phase of the variable resistive element CR. In some example embodiments, the phase transition temperature of the switching element SW may be in the range of approximately 350 degrees Celsius to approximately 450 degrees Celsius. Therefore, when operating the variable resistive memory device according to an example embodiment of the present invention, the phase of the variable resistive element CR may reversibly change between a crystalline and amorphous phase by means of an operating voltage (e.g., a programming voltage), but even when an operating voltage is applied to the switching element SW, the switching element SW remains in a substantially amorphous state without a phase transition. In this specification, the term "substantially amorphous state" may include an amorphous state and may also include a case where grain boundaries or crystalline portions are locally present in a portion of the assembly.

[0047] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes a tolerance of ±10% around said value. When a range is specified, the range includes all values ​​therebetween in increments such as 0.1%.

[0048] The switching element SW can be formed from a compound comprising at least one of Te and Se (e.g., chalcogenide elements) and at least one of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. In addition to the compound, the switching element SW may also include a thermally stabilizing element. The thermally stabilizing element may include at least one of C, N, and O.

[0049] The bottom carbon electrode pattern 142 may be disposed between the switching element SW and the intermediate electrode ME. In some example embodiments, the bottom carbon electrode pattern 142 may include a conductive material containing carbon.

[0050] The top electrode TE can be disposed between the switching element SW and the first line CL2_1. The top electrodes TE can be disposed separately on the switching element SW and can be separated from each other. In other words, the top electrodes TE can be arranged in a two-dimensional arrangement along rows and columns. Alternatively, each of the top electrodes TE can be collectively connected to the switching element SW arranged along the third direction D3.

[0051] The first line CL2_1 may be disposed on the top electrode TE. The first lines CL2_1 may be spaced apart from each other by a second insulating layer 117 in the second direction D2. In some example embodiments, the second insulating layer 117 may comprise silicon oxide or silicon oxynitride. The second insulating layer 117 may comprise a plurality of insulating patterns separated from each other by the first lines CL2_1. A first insulating layer 161 may be disposed to fill the space between the switching elements SW. In some example embodiments, the first insulating layer 161 may comprise silicon oxide or silicon oxynitride.

[0052] The top electrode TE may include a first carbon electrode pattern 152, a metal pattern 154, and a second carbon electrode pattern 156 stacked sequentially. The first carbon electrode pattern 152 and the second carbon electrode pattern 156 may include a carbon-containing conductive material. The metal pattern 154 may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN. In some example embodiments, the first carbon electrode pattern 152 may be thicker than the second carbon electrode pattern 156. Alternatively, at least one of the first carbon electrode pattern 152, the metal pattern 154, and the second carbon electrode pattern 156 may be omitted in the top electrode TE.

[0053] A sidewall insulating layer 146 may be disposed between the first insulating layer 161 and the switching element SW. The sidewall insulating layer 146 may extend below the bottom surface of the first insulating layer 161. In some example embodiments, the sidewall insulating layer 146 may extend between the first insulating layer 161 and the first to third interlayer insulating layers 111, 113, and 115. The sidewall insulating layer 146 may extend onto the sidewall of the top electrode TE. In some example embodiments, the uppermost surface of the sidewall insulating layer 146 may be substantially coplanar with the top surface of the top electrode TE. The sidewall insulating layer 146 may not include oxygen. The sidewall insulating layer 146 may include a material with a dielectric constant greater than that of the first insulating layer 161. In some example embodiments, the sidewall insulating layer 146 may include a silicon nitride layer.

[0054] The second memory cell stack MCA2 may be spaced apart from the first memory cell stack MCA1, wherein a third insulating layer 109 is inserted between the second memory cell stack MCA2 and the first memory cell stack MCA1. In some example embodiments, the third insulating layer 109 may include a silicon oxide layer. The second memory cell stack MCA2 may have substantially the same structure as the first memory cell stack MCA1. In some example embodiments, the second memory cell stack MCA2 may include a second word line CL1_2, a second bit line CL2_2, and memory cells MC between the second word line CL1_2 and the second bit line CL2_2. The second word line CL1_2 may be disposed in the lower interlayer insulating layer 108. The memory cells MC may be disposed in the first to third interlayer insulating layers 112, 114, and 116 and the first insulating layer 162. The second bit line CL2_2 may be disposed in the second insulating layer 118.

[0055] The thickness of the word line of at least one memory cell stack MCA in the memory cell stack MCA in the first direction D1 may differ from the thickness of the word lines of the other memory cell stack MCAs in the memory cell stack MCA. In some example embodiments, the second thickness t2 of the second word line CL1_2 of the second memory cell stack MCA2 in the first direction D1 may be greater than the first thickness t1 of the first word line CL1_1 of the first memory cell stack MCA1 in the first direction D1. In some example embodiments, the second thickness t2 may be in the range of approximately 1.3 times to approximately 3 times the first thickness t1.

[0056] The thickness of the first bit line CL2_1 can be substantially equal to the thickness of the second bit line CL2_2. In some example embodiments, the thickness of the first bit line CL2_1 and the thickness of the second bit line CL2_2 can be substantially equal to the first thickness t1 of the first word line CL1_1.

[0057] Figure 4It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' illustrate a variable resistive memory device according to some exemplary embodiments of the invention. In this exemplary embodiment, the second thickness t2 of the second word line CL1_2 of the second memory cell stack MCA2 in the first direction D1 may be less than the first thickness t1 of the first word line CL1_1 of the first memory cell stack MCA1 in the first direction D1. In some exemplary embodiments, the first thickness t1 may be in the range of approximately 1.3 times to approximately 3 times the second thickness t2.

[0058] The thickness of word line CL1 is proportional to the capacitance between word lines CL1 of the corresponding memory cell stack MCA. When a variable-resistance memory device according to some embodiments is operated, a snap-back phenomenon may occur. Under certain conditions, the snap-back phenomenon produces a sudden negative resistance. The variable-resistance memory device of the present invention can remain in the off state at voltages below a critical voltage and can snap back to the on state in response to voltages above the critical voltage. A variable-resistance memory device in the on state can use the characteristic of maintaining the voltage, for example, at a holding voltage level, to allow current to flow rapidly. Therefore, a specific voltage can be reduced rapidly.

[0059] This ripple effect can cause overcurrent to flow through the variable resistor CR, resulting in read interference. In other words, when reading from the variable resistor CR which is in a set state, an overcurrent can momentarily flow through the variable resistor CR, triggering a reset write operation. This ripple effect can be affected by the capacitance between the word lines CL1 of the corresponding memory cell stack MCA. In other words, a large capacitance between the word lines CL1 can mitigate the ripple effect, while a small capacitance can amplify it.

[0060] According to some exemplary embodiments of the present invention, ripple effects can be controlled by adjusting the thickness of the word lines in the memory cell stack. In other words, ripple effects can be mitigated by increasing the word line thickness, or enhanced by decreasing the word line thickness. Therefore, the electrical characteristics of the variable resistance memory device can be improved.

[0061] Figure 5 and Figure 6 It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' illustrate a variable resistive memory device according to some exemplary embodiments of the invention. In the following, for ease of explanation, descriptions of the same components as those in the exemplary embodiments described above will be omitted or briefly mentioned.

[0062] Reference Figure 5The variable resistance memory device according to this example embodiment may include a first memory cell stack MCA1 to a fourth memory cell stack MCA4 sequentially stacked on a substrate 100. The first memory cell stacks MCA1 to the fourth memory cell stacks MCA4 may be spaced apart from each other, wherein a third insulating layer 194 is inserted between the first memory cell stacks MCA1 to the fourth memory cell stacks MCA4. Each of the first memory cell stacks MCA1 to the fourth memory cell stacks MCA4 may include an insulating layer 191, an insulating layer 192, and an insulating layer 193.

[0063] Figure 5 The diagram shows a stack of four memory cells. However, the exemplary embodiments of the present invention are not limited thereto. In some exemplary embodiments, five or more memory cell stacks may be provided. The first memory cell stack MCA1 to the fourth memory cell stack MCA4 may each include a first word line CL1_1 to a fourth word line CL1_4 and a first bit line CL2_1 to a fourth bit line CL2_4.

[0064] The second thickness t2 of the second word line CL1_2 can be greater than the first thickness t1 of the word lines of the other memory cell stacks MCA1, MCA3, and MCA4. The second thickness t2 can be greater than the average thickness of the other word lines. The thicknesses of the first bit line CL2_1 to the fourth bit line CL2_4 can be equal to each other. The thicknesses of the first bit line CL2_1 to the fourth bit line CL2_4 can be substantially equal to the first thickness t1. In some example embodiments, two or more memory cell stacks with word lines having a second thickness t2 can be configured, and / or two or more memory cell stacks with word lines having a first thickness t1 can be configured.

[0065] Reference Figure 6 The second thickness t2 of the second word line CL1_2 can be greater than the first thickness t1 of the word lines of the other memory cell stacks MCA1 and MCA3. The third thickness t3 of the fourth word line CL1_4 can be less than the first thickness t1. The second thickness t2 of the second word line CL1_2 can be greater than the average thickness of the other word lines, and the third thickness t3 of the fourth word line CL1_4 can be less than the average thickness of the other word lines. In some example embodiments, multiple memory cell stacks with word lines having a second thickness t2 can be configured, and / or multiple memory cell stacks with word lines having a third thickness t3 can be configured.

[0066] Figures 7 to 10 It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' illustrate a method for manufacturing a variable resistance memory device according to some exemplary embodiments of the invention.

[0067] Reference Figure 2 and Figure 7 A first word line CL1_1 can be formed on the substrate 100. The first word line CL1_1 can be disposed in the lower interlayer insulating layer 107. A first interlayer insulating layer 111 can be formed on the first word line CL1_1, and then trenches TC can be formed in the first interlayer insulating layer 111. The formation of the trenches TC may include anisotropic etching. Each of the trenches TC may intersect the first word line CL1_1. In some example embodiments, the first interlayer insulating layer 111 may be formed of silicon nitride or silicon oxynitride.

[0068] An electrode layer 121 and a spacer layer 126 may be sequentially formed on a first interlayer insulating layer 111 having a trench TC. The electrode layer 121 and spacer layer 126 may be formed conformally along the shape or contour of the trench TC. In some example embodiments, the electrode layer 121 may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, and TiO. In some example embodiments, the spacer layer 126 may include at least one of silicon oxide and silicon oxynitride. A second interlayer insulating layer 113 filling the trench TC may be formed on the spacer layer 126. In some example embodiments, the second interlayer insulating layer 113 may be formed of the same material as the first interlayer insulating layer 111.

[0069] Reference Figure 2 and Figure 8 A planarization process can be performed until the first interlayer insulating layer 111 is exposed. Thereafter, the second interlayer insulating layer 113, the spacer layer 126, and the electrode layer 121 can be etched to form the opening region OP. As a result, the heater electrode HE can be formed from the electrode layer 121, and the spacer pattern 127 can be formed from the spacer layer 126. Subsequently, a third interlayer insulating layer 115 can be formed to fill the opening region OP. In some example embodiments, the third interlayer insulating layer 115 can be formed from the same material as the first interlayer insulating layer 111.

[0070] A recessed region RS can be formed to expose the heater electrode HE. Forming the recessed region RS may include etching the upper portion of the spacer pattern 127 and etching the upper portion of the heater electrode HE. Subsequently, an isotropic wet etching process can be performed to expand the empty space formed by etching the upper portion of the heater electrode HE and the upper portion of the spacer pattern 127. In some example embodiments, an etchant comprising phosphoric acid may be used to perform the isotropic wet etching process.

[0071] Reference Figure 2 and Figure 9In each of the recessed regions RS, a variable resistance element CR and an intermediate electrode ME can be sequentially formed. In some example embodiments, a variable resistance layer can be formed to fill the recessed region RS, and then the top of the variable resistance layer can be etched to form the variable resistance element CR. The variable resistance layer can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0072] An intermediate electrode ME can be formed in the upper part of the recessed region RS. In some example embodiments, an electrode layer can be formed on the resulting structure having a variable resistive element CR, and then the electrode layer can be planarized to form the intermediate electrode ME. Alternatively, the process of forming the intermediate electrode ME can be omitted. In some example embodiments, the intermediate electrode ME may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0073] A bottom carbon electrode layer 141, a switching layer 143, and top electrode layers 151, 153, and 155 can be sequentially formed on the resulting structure having an intermediate electrode ME. A mask layer 157 can be formed on the top electrode layers 151, 153, and 155. The top electrode layers 151, 153, and 155 may include a first carbon electrode layer 151, a metal layer 153, and a second carbon electrode layer 155. The first carbon electrode layer 151 and the second carbon electrode layer 155 can be formed from a conductive material including carbon. The metal layer 153 can be formed from at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN. In some example embodiments, the switch layer 143 may be formed of a compound comprising at least one of Te and Se (i.e., chalcogenide elements) and at least one of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. In addition to compounds, the switch layer 143 may also include thermally stabilizing elements.

[0074] Reference Figure 2 and Figure 10A mask pattern can be formed from mask layer 157, and then the mask pattern can be used as an etching mask to sequentially etch the top electrode layers 151, 153, and 155, the switching layer 143, and the bottom carbon electrode layer 141. As a result, an upper structure can be formed, each of which includes a bottom carbon electrode pattern 142, a switching element SW, and a top electrode TE. The top electrode TE may include a first carbon electrode pattern 152, a metal pattern 154, and a second carbon electrode pattern 156. The upper structures may be spaced apart from each other in the third direction D3 and the second direction D2, and may be arranged in two dimensions.

[0075] The sidewall insulating layer 146 may be formed to cover the upper structure. In some example embodiments, the sidewall insulating layer 146 may be formed by a CVD process. The sidewall insulating layer 146 may be formed from an oxygen-free material. In some example embodiments, the sidewall insulating layer 146 may include a silicon nitride layer.

[0076] Refer again Figure 2 and Figure 3 A first insulating layer 161 can be formed between the upper structures. Afterward, a planarization process can be performed. During the planarization process, the mask pattern can be removed. Additionally, a portion of the second carbon electrode pattern 156 and a portion of the sidewall insulating layer 146 can also be removed. As a result, after the planarization process, the thickness of the second carbon electrode pattern 156 can be less than the thickness of the first carbon electrode pattern 152.

[0077] A first line CL2_1 can be formed on the top electrode TE. The formation of the first line CL2_1 may include forming a conductive layer on the top electrode TE and patterning that conductive layer. Subsequently, a second insulating layer 117 may be formed to fill the space between the first lines CL2_1. In some example embodiments, each of the first insulating layer 161 and the second insulating layer 117 may include a silicon oxide layer and / or a silicon oxynitride layer.

[0078] The formation of the first memory cell stack MCA1 can be completed through the above process. Subsequently, a third insulating layer 109 can be formed on the first memory cell stack MCA1. Then, by repeating the reference... Figures 7 to 10 and Figure 3 The aforementioned process forms a second memory cell stack MCA2.

[0079] Figure 11 and Figure 12 It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' are shown to illustrate a variable resistance memory device according to some exemplary embodiments of the concept of the present invention. Figure 13 and Figure 14 yes Figure 11 A magnified view of region 'Q'.

[0080] Reference Figure 2 and Figure 11 A variable resistance memory device according to this example embodiment may include a first memory cell stack MCA1 to a fifth memory cell stack MCA5 sequentially stacked on a substrate 100. Adjacent memory cell stacks may share bit lines. In some example embodiments, a second memory cell stack MCA2 and a third memory cell stack MCA3 may share a second bit line CL2_2, and a fourth memory cell stack MCA4 and a fifth memory cell stack MCA5 may share a third bit line CL2_3. The second thickness t2 of the third word line CL1_3 may be greater than the first thickness t1 of the word lines of the other memory cell stacks.

[0081] Reference Figure 12 The second thickness t2 of the third word line CL1_3 can be greater than the first thickness t1 of the word lines of the other memory cell stacks MCA1 and MCA5. The third thickness t3 of the second word line CL1_2 can be less than the first thickness t1.

[0082] Figure 11 and Figure 12 Each of the memory cells can have Figure 13 or Figure 14 The structure. For example... Figure 13 As shown, in some exemplary embodiments, the bottom electrode BE, the switching element SW, the intermediate electrode ME, and the variable resistor element CR can be stacked sequentially. Alternatively, as... Figure 14 As shown, the variable resistor element CR, heater electrode HE, intermediate electrode ME, switching element SW, and upper electrode TE can be stacked sequentially.

[0083] Figure 15 This is a perspective view schematically illustrating some example embodiments of a variable resistance memory device according to the present invention.

[0084] Reference Figure 15 A word line CL1 and a bit line CL2 intersecting the word line CL1 can be configured. The word line CL1 can extend in a second direction D2. The word line CL1 can include a first sub-word line CL1a disposed on one side of the bit line CL2 and a second sub-word line CL1b disposed on the other side of the bit line CL2. The second sub-word line CL1b can be spaced apart from the first sub-word line CL1a in a first direction D1 that intersects the second direction D2. The first sub-word lines CL1a can be spaced apart from each other in a third direction D3 perpendicular to the first direction D1 and the second direction D2, and the second sub-word lines CL1b can also be spaced apart from each other in the third direction D3. The bit line CL2 can extend in the third direction D3 and can be spaced apart from each other in the second direction D2.

[0085] Memory cells MC can be located at the intersections of word line CL1 and bit line CL2. Memory cells MC can include a first memory cell MC1 located at the intersection of the first sub-word line CL1a and bit line CL2, and a second memory cell MC2 located at the intersection of the second sub-word line CL1b and bit line CL2. The first memory cells MC1 can be spaced apart from each other on the third direction D3. The second memory cells MC2 can be spaced apart from each other on the third direction D3.

[0086] Each of the memory cells MC may include a variable resistive element CR and a switching element SW. Each of the memory cells MC may also include an electrode E1 disposed between the variable resistive element CR and the switching element SW. (See below for details.) Figures 16A to 16D Describe electrode E1 in detail.

[0087] The first width t1 of the first sub-word line CL1a in the first direction D1 can be greater than the second width t2 of the second sub-word line CL1b in the first direction D1. The width of the bit line CL2 in the first direction D1 can be substantially equal to the second width t2. However, exemplary embodiments of the present invention are not limited thereto. The widths of the sub-word lines CL1a and CL1b are not limited to those described above, and refer to... Figures 2 to 14 The features of the described example embodiments can be applied to sub-word lines CL1a and CL1b.

[0088] Each of the first memory cell MC1 and each of the second memory cell MC2 may be symmetrical with respect to a corresponding bit line in bit line CL2. In some example embodiments, the variable resistor element CR of each of the first memory cell MC1 and the variable resistor element CR of each of the second memory cell MC2 may be connected together to the corresponding bit line CL2, and the switching element SW of each of the first memory cell MC1 and the switching element SW of each of the second memory cell MC2 may be connected to a corresponding first sub-word line in the first sub-word line CL1a and a corresponding second sub-word line in the second sub-word line CL1b, respectively.

[0089] Figures 16A to 16D This is a perspective view illustrating a unit memory cell of a variable resistive memory device according to some exemplary embodiments of the concept of the present invention. (Refer to...) Figures 16A to 16D The memory cell MC can be positioned between word lines CL1 and bit lines CL2 that intersect each other. In some example embodiments, such as Figure 16A As shown, the memory cell MC may further include a first electrode E1 disposed between the variable resistive element CR and the switching element SW. In some example embodiments, such as Figure 16BAs shown, the memory cell MC may further include a first electrode E1 disposed between the variable resistor element CR and the switching element SW, and a second electrode E2 disposed between the variable resistor element CR and the bit line CL2. In some example embodiments, such as Figure 16C As shown, the memory cell MC may further include a first electrode E1 disposed between a variable resistor element CR and a switching element SW, and a third electrode E3 disposed between the switching element SW and a word line CL1. The third electrode E3 may be spaced apart from the first electrode E1, wherein the switching element SW is inserted between the third electrode E3 and the first electrode E1. In some example embodiments, such as... Figure 16D As shown, the memory cell MC may further include a first electrode E1 disposed between a variable resistor element CR and a switching element SW, a second electrode E2 disposed between the variable resistor element CR and a bit line CL2, and a third electrode E3 disposed between the switching element SW and a word line CL1.

[0090] Figure 17 This is a plan view illustrating some example embodiments of a variable resistance memory device according to the present invention. Figure 18 It is along Figure 17 A cross-sectional view taken from line I-I'. Figure 19 It is along Figure 17 The cross-sectional view taken from line II-II'. Figure 20 It is shown Figure 17 A plan view showing the arrangement of word lines, bit lines, and memory cells. Figures 17 to 20 Show Figure 15 Detailed exemplary embodiments are provided, and for the purposes of ease and convenience of explanation, references to [specific examples] will be omitted or briefly mentioned. Figure 15 The same features and / or components are described in the exemplary embodiments.

[0091] Reference Figures 17 to 20 The stacked structure SS can be disposed on the substrate 100. The stacked structure SS may include a first memory cell stack MCA1 and a second memory cell stack MCA2. Multiple stacked structures SS can be disposed, and the multiple stacked structures SS can be separated from each other in the first direction D1, wherein an isolation insulating pattern 130 is inserted between the multiple stacked structures SS.

[0092] The stacked structure SS may extend in a second direction D2 parallel to the top surface 100u of the substrate 100. An insulating pattern 130 may cover each of the two sidewalls SS_S of the stacked structure SS. In some example embodiments, the insulating pattern 130 may include oxides, nitrides, and / or oxynitrides.

[0093] The stacked structure SS may include insulating layers 110 and word lines CL1 alternately stacked on a third direction D3 perpendicular to the top surface 100u of the substrate 100. A pair of word lines CL1 may be arranged on each of the insulating layers 110. On each insulating layer 110, the pair of word lines CL1 may be spaced apart from each other in the first direction D1. The word lines CL1 may include a first sub-word line CL1a and a second sub-word line CL1b. The pair of word lines CL1 may include one first sub-word line from the first sub-word line CL1a and one second sub-word line from the second sub-word line CL1b.

[0094] The stacked structure SS may include a bit line CL2 disposed between a first sub-word line CL1a and a second sub-word line CL1b. The bit line CL2 may extend in a third direction D3 and may be spaced apart from each other in a second direction D2. The word line CL1 and the bit line CL2 may include metals (e.g., copper, tungsten, or aluminum) and / or metal nitrides (e.g., tantalum nitride, titanium nitride, or tungsten nitride). In some example embodiments, the insulating layer 110 may include silicon nitride.

[0095] The stacked structure SS may further include a filler insulating pattern 120 disposed between the first sub-word line CL1a and the second sub-word line CL1b. The filler insulating pattern 120 may extend in a third direction D3 and may be spaced apart from each other in a second direction D2. The bit line CL2 and the filler insulating pattern 120 may be disposed alternately along the second direction D2. In some example embodiments, the filler insulating pattern 120 may include oxides, nitrides, and / or oxynitrides.

[0096] The stacked structure SS may include memory cells MC (e.g., a first memory cell MC1 and a second memory cell MC2) respectively disposed at the intersection of word line CL1 and bit line CL2. Each of the memory cells MC may include a variable resistor element CR, a switching element SW, and a first electrode E1 disposed between the variable resistor element CR and the switching element SW. In some example embodiments, the switching element SW may be a diode. In this case, the switching element SW may include a first junction pattern 175a and a second junction pattern 175b having different conductivity types from each other. The first junction pattern 175a may have a first conductivity type, and the second junction pattern 175b may have a second conductivity type different from the first conductivity type. In some example embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type. Alternatively, the first conductivity type may be N-type, and the second conductivity type may be P-type. The second junction pattern 175b may include a dopant of the second conductivity type. The first junction pattern 175a may include a dopant of the first conductivity type and a dopant of the second conductivity type. Here, in the first junction pattern 175a, the concentration of the dopant of the first conductivity type may be greater than the concentration of the dopant of the second conductivity type. In some example embodiments, the switching element SW can be a silicon diode or an oxide diode with rectification characteristics. In other words, the switching element SW can be a silicon diode of P-type silicon or N-type silicon, or it can be a P-type NiO diode. x and N-type TiO x Oxide diodes, or P-type CuO diodes x and N-type TiO x The oxide diode. In some example embodiments, the switching element SW may include a bidirectional threshold switch (OTS) element with bidirectional characteristics.

[0097] The first sub-word line CL1a, the first memory cell MC1, and the bit line CL2 can form a first memory cell stack MCA1, and the second sub-word line CL1b, the second memory cell MC2, and the bit line CL2 can form a second memory cell stack MCA2. In other words, as... Figure 11 and Figure 12 In an exemplary embodiment, the first memory cell stack MCA1 and the second memory cell stack MCA2 may share a bit line CL2. The first width t1 of the first sub-word line CL1a in the first direction D1 may be greater than the second width t2 of the second sub-word line CL1b in the first direction D1.

[0098] Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A This is a plan view illustrating a method for manufacturing a variable resistance memory device according to some exemplary embodiments of the present invention. Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 25B They are along Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A A cross-sectional view taken from line I-I'. Figure 21C , Figure 22C , Figure 23C , Figure 24C and Figure 25C They are along Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A The cross-sectional view taken from line II-II'.

[0099] Reference Figures 21A to 21C A thin-layer structure TS can be formed on substrate 100. The thin-layer structure TS may include an insulating layer 110 and a sacrificial layer 175 stacked on the top surface 100u of substrate 100. The insulating layer 110 and the sacrificial layer 175 may be stacked alternately and repeatedly on a third-direction D3. The sacrificial layer 175 may include silicon doped with a dopant of a second conductivity type or a metal oxide doped with a dopant of a second conductivity type. The insulating layer 110 may include a material with etch selectivity relative to the sacrificial layer 175. In some example embodiments, the insulating layer 110 may include silicon nitride.

[0100] A fill insulating pattern 120 may be formed in a thin-layer structure TS. The fill insulating pattern 120 may penetrate the thin-layer structure TS and may contact the top surface 100u of the substrate 100. In some example embodiments, the formation of the fill insulating pattern 120 may include forming a via 120H penetrating the thin-layer structure TS, forming a fill insulating layer on the thin-layer structure TS to fill the via 120H, and planarizing the fill insulating layer.

[0101] Reference Figures 22A to 22CA trench 130T can be formed to penetrate the thin-layer structure TS. The trench 130T can extend along a second direction D2. The sidewalls of the sacrificial layer 175 exposed by each of the trenches 130T can be recessed to form a first recessed region R1 between the insulating layers 110. The first recessed region R1 can include a first region RL and a second region RR spaced apart from the first region RL in the first direction D1, wherein a filling insulating pattern 120 is inserted between the first region RL and the second region RR. The depth t5 of the first region RL in the first direction D1 can be greater than the depth t6 of the second region RR in the direction opposite to the first direction D1. The difference between depths t5 and t6 can be achieved or formed by various methods. In some example embodiments, the formation of the first region RL and the second region RR can be performed by using different etching processes with different mask patterns. In some example embodiments, the mask pattern can expose the trench 130T on one side of the filling insulating pattern 120 and can cover the trench 130T on the other side of the filling insulating pattern 120. The processing time and / or etching amount of different etching processes can be adjusted to produce a difference between depths t5 and t6.

[0102] In some example embodiments, the formation of the first recessed region R1 may include etching the sacrificial layer 175 by performing an etching process that has etch selectivity relative to the insulating layer 110, the filling insulating pattern 120, and the substrate 100. The first recessed region R1 may extend laterally from each of the trenches 130T. The first recessed regions R1 may extend in a second direction D2 and may be spaced apart from each other in a third direction D3.

[0103] Reference Figures 23A to 23C The portion of the sacrificial layer 175 exposed by the first recessed region R1 may be doped with a dopant of a first conductivity type. Therefore, a first junction pattern 175a may be formed on one side of each of the sacrificial layers 175. The dopant of the first conductivity type may be different from a dopant of a second conductivity type. The sacrificial layer 175 may include a dopant of the second conductivity type, and the first junction pattern 175a may be formed by doping a portion of each of the sacrificial layers 175 with a dopant of the first conductivity type. Therefore, the first junction pattern 175a may include a dopant of the first conductivity type and a dopant of the second conductivity type. In the first junction pattern 175a, the concentration of the dopant of the first conductivity type may be greater than the concentration of the dopant of the second conductivity type.

[0104] After forming the first junction pattern 175a, word lines CL1 can be formed in the first recessed regions R1. In some example embodiments, the formation of word lines CL1 may include: forming at least a portion of each of the trenches 130T and the first recessed region R1 on the thin-layer structure TS, and removing the first conductive layer disposed outside the first recessed region R1. The first conductive layer may include a metal (e.g., copper, tungsten, or aluminum) and / or a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride). Afterwards, insulating patterns 130 may be formed in the trenches 130T.

[0105] Reference Figures 24A to 24C Vertical vias 140H can be formed to penetrate the thin-layer structure TS. The vertical vias 140H can be spaced apart from each other along a second direction D2 between the insulating patterns 130. Each of the vertical vias 140H can expose the sidewalls of the insulating layer 110 and the sacrificial layer 175, and can also expose the top surface 100u of the substrate 100. The sidewalls of the sacrificial layer 175 exposed by each of the vertical vias 140H can be recessed to form a second recessed region R2 between the insulating layers 110. In some example embodiments, the formation of the second recessed region R2 may include etching the sacrificial layer 175 by performing an etching process that has etch selectivity relative to the insulating layer 110, the filling insulating pattern 120, and the substrate 100.

[0106] A first electrode E1 may be formed on one side of each exposed sacrificial layer 175 in the second recessed region R2. In some example embodiments, forming the first electrode E1 may include: forming a metal layer covering the sidewalls of each exposed sacrificial layer 175 in the second recessed region R2, performing a heat treatment process to react the sidewalls of the sacrificial layer 175 with the metal layer, and removing the remaining portion of the metal layer that does not react with the sidewalls of the sacrificial layer 175. In this case, the first electrode E1 may include a metal silicide. The remaining portion of the sacrificial layer 175 that does not react with the metal layer may be defined as a second junction pattern 175b. The second junction pattern 175b may include a dopant of a second conductivity type. The first junction pattern 175a and the second junction pattern 175b may constitute a switching element SW. The first junction pattern 175a and the second junction pattern 175b may have a first conductivity type and a second conductivity type, respectively.

[0107] Reference Figures 25A to 25CA variable resistor element CR can be formed in each of the second recessed regions R2. The formation of the variable resistor element CR may include: forming a variable resistor material layer that fills at least a portion of the second recessed region R2 and the vertical hole 140H, and removing the variable resistor material layer from the vertical hole 140H. Therefore, the variable resistor element CR can be locally formed in each of the second recessed regions R2. The switching element SW, the first electrode E1, and the variable resistor element CR can constitute a memory cell MC. In an exemplary embodiment of the present invention, the switching element SW and the variable resistor element CR can be horizontally arranged on the top surface 100u of the substrate 100. In this case, photolithography for forming the switching element SW and the variable resistor element CR is not required, and the difficulty of etching for forming the switching element SW and the variable resistor element CR can be reduced. In other words, a memory cell MC including the switching element SW and the variable resistor element CR can be easily formed.

[0108] Bit lines CL2 can be formed in the vertical vias 140H. Forming the bit lines CL2 may include: forming a second conductive layer on the thin-film structure TS that fills the vertical vias 140H, and planarizing the second conductive layer until the top surface of the thin-film structure TS is exposed. The second conductive layer may include a metal and / or a metal nitride.

[0109] Figure 26 This is a plan view illustrating some example embodiments of a variable resistance memory device according to the present invention. Figure 26 Example embodiments may be similar to Figures 17 to 20 Example embodiments, and will be omitted below. Figures 17 to 20 The same features and / or components are described in the example embodiments.

[0110] Reference Figure 26Stacked structures SS2, SS1, and SS3 can be arranged along a first direction D1. The first stacked structure SS1 can be arranged between the second stacked structure SS2 and the third stacked structure SS3, and the first to third stacked structures SS1, SS2, and SS3 can be spaced apart from each other, wherein an insulating pattern 130 is inserted between the first to third stacked structures SS1, SS2, and SS3. The first stacked structure SS1 may include a first memory cell stack MCA1 and a second memory cell stack MCA2; the second stacked structure SS2 may include a third memory cell stack MCA3 and a fourth memory cell stack MCA4; and the third stacked structure SS3 may include a fifth memory cell stack MCA5 and a sixth memory cell stack MCA6. The first stack structure SS1 may include a first word line CL1_1, which is arranged to have a first bit line CL2_1 inserted between them; the second stack structure SS2 may include a second word line CL1_2, which is arranged to have a second bit line CL2_2 inserted between them; and the third stack structure SS3 may include a third word line CL1_3, which is arranged to have a third bit line CL2_3 inserted between them.

[0111] In this example embodiment, the thickness of the sub-word lines included in each of the stacked structures SS1 to SS3 in the first direction D1 may be equal to each other. In some example embodiments, the first sub-word line CL1a and the second sub-word line CL1b of the first stacked structure SS1 may have a first thickness t1 that is equal to each other in the first direction D1. The thickness of the word line of at least one of the stacked structures SS1, SS2, and SS3 in the first direction D1 may be different from the thickness of the word lines of the other stacked structures in the first direction D1. In some example embodiments, the first width t1 of the first word line CL1_1 of the first stacked structure SS1 may be greater than the second width t2 of the second word line CL1_2 of the second stacked structure SS2. The thickness of the third word line CL1_3 of the third stacked structure SS3 in the first direction D1 may be equal to or less than the second width t2.

[0112] In a variable-resistance memory device according to an exemplary embodiment of the present invention, ripple effects can be controlled by adjusting the thickness of the word lines in the memory cell stack. In other words, ripple effects can be mitigated by increasing the word line thickness, or enhanced by decreasing the word line thickness. Therefore, the electrical characteristics of the variable-resistance memory device can be improved.

[0113] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above exemplary embodiments are not restrictive but illustrative. Accordingly, the scope of the inventive concept is determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be limited or constrained by the foregoing description.

Claims

1. A variable resistance memory device, comprising: a substrate; and stacked structures on a top surface of the substrate, arranged along a first direction, wherein each of the stacked structures includes: word lines extending along a second direction parallel to the top surface of the substrate and arranged along a third direction perpendicular to the top surface of the substrate, the word lines including a first sub-word line and a second sub-word line spaced apart from the first sub-word line in the first direction, the first direction intersecting the second direction and the third direction, bit lines between the first sub-word line and the second sub-word line and arranged along the second direction, and memory cells at intersections of the first sub-word line and the bit lines and intersections of the second sub-word line and the bit lines, wherein each of the memory cells includes a switching element and a variable resistance element, wherein the stacked structures include a first stacked structure including the first sub-word line and the second sub-word line and a second stacked structure including a third sub-word line and a fourth sub-word line, wherein a width of at least one of the first to fourth sub-word lines in the first direction is different from a width of the other sub-word lines in the first direction.

2. The variable resistance memory device of claim 1, wherein, a first width of the first sub-word line in the first direction is greater than a second width of the second sub-word line in the first direction.

3. The variable resistance memory device of claim 1, wherein, the second sub-word line is connected to the bit line through a second memory cell, wherein the first sub-word line is connected to the bit line through a first memory cell, wherein the first memory cell includes a first switching element and a first variable resistance element between the first switching element and the bit line, and wherein the second memory cell includes a second switching element and a second variable resistance element between the second switching element and the bit line.

4. The variable resistance memory device of claim 1, wherein, a first width of the first sub-word line in the first direction is greater than a third width of the third sub-word line in the first direction.

5. The variable resistance memory device of claim 4, wherein, the first width is equal to a second width of the second sub-word line in the first direction, and wherein the third width is equal to a fourth width of the fourth sub-word line in the first direction.

6. The variable resistance memory device of claim 1, wherein, a width of the first sub-word line in the first direction is greater than a width of the bit line in the first direction.

7. A variable resistance memory device, comprising: a memory cell stack arranged along a first direction, the memory cell stack including a first memory cell stack and a second memory cell stack, and each of the memory cell stacks including: a plurality of word lines, each of the plurality of word lines extending along a second direction intersecting the first direction and arranged along a third direction intersecting the first direction and the second direction, and a memory cell connected to each of the plurality of word lines, each of the memory cells including a switching element and a variable resistance element, Each of the plurality of word lines of the first memory cell stack has a first thickness in the first direction, the first thickness being smaller than a second thickness of each of the plurality of word lines of the second memory cell stack in the first direction.

8. The variable resistance memory device of claim 7, wherein, Each of the memory cell stacks further includes a plurality of bit lines, each of the plurality of bit lines extending along the third direction and arranged along the second direction, and The memory cells are disposed at intersections of the plurality of word lines and the plurality of bit lines.

9. The variable resistance memory device of claim 7, wherein, Each of the memory cell stacks further includes a plurality of bit lines, each of the plurality of bit lines extending along the third direction and arranged along the second direction, and The plurality of bit lines and the plurality of word lines alternate in the first direction.

10. The variable resistance memory device of claim 7, wherein, Each of the memory cell stacks further includes a plurality of bit lines, each of the plurality of bit lines extending along the third direction and arranged along the second direction, and Each of the plurality of bit lines in each of the memory cell stacks has a thickness in the first direction that is substantially equal to each other.

11. The variable resistance memory device of claim 10, wherein, The second thickness is greater than a thickness of each of the plurality of bit lines in the first direction.

12. The variable resistance memory device of claim 7, wherein, The memory cell stacks include a third memory cell stack, and A third thickness of the plurality of word lines of the third memory cell stack in the first direction is smaller than the first thickness.

13. The variable resistance memory device of claim 7, wherein, The memory cell stacks include a plurality of memory cell stacks having the second thickness.

14. The variable resistance memory device of claim 7, further comprising: a substrate having a top surface perpendicular to the first direction, wherein the memory cell stacks are sequentially stacked on the substrate in the first direction, and wherein the second direction is parallel to the top surface of the substrate.

15. The variable resistance memory device of claim 14, wherein, The switching element includes a material having a phase transition temperature higher than a phase transition temperature of the variable resistance element.

16. The variable resistance memory device of claim 7, further comprising: a substrate having a top surface perpendicular to the third direction, wherein the first direction is parallel to the top surface of the substrate.

17. The variable resistance memory device of claim 16, further comprising: a plurality of bit lines extending along the third direction and arranged along the second direction, wherein the plurality of word lines of the second memory cell stack are connected to the bit lines through second memory cells, and wherein the plurality of word lines of the first memory cell stack are connected to the bit lines through first memory cells.

18. The variable resistance memory device of claim 17, wherein, The first memory cell includes a first switching element and a first variable resistance element between the first switching element and the bit line, and wherein the second memory cell includes a second switching element and a second variable resistance element between the second switching element and the bit line.

19. A variable resistance memory device, comprising: memory cell stacks on a substrate, wherein each of the memory cell stacks includes: a first memory cell stack and a second memory cell stack, and wherein the first memory cell stack includes a first switching element and a first variable resistance element between the first switching element and a bit line, and wherein the second memory cell stack includes a second switching element and a second variable resistance element between the second switching element and the bit line. word lines having a thickness in a first direction and extending along a second direction and arranged along a third direction intersecting the second direction, bit lines extending along the third direction and arranged along the second direction, memory cells provided at intersections of the word lines and the bit lines, wherein each of the memory cells includes a switching element and a variable resistance element, wherein a thickness of the word lines of at least one of the memory cell stacks in the first direction is different from thicknesses of the word lines of the other memory cell stacks in the first direction.

20. The variable resistance memory device of claim 19, wherein, The variable resistance memory device includes first word lines and second word lines, wherein the first word lines include a plurality of the word lines arranged along the third direction, and the second word lines include a plurality of the word lines arranged along the third direction, wherein the first word lines are spaced apart from the second word lines in the first direction.

21. The variable resistance memory device of claim 20, wherein, A first thickness of each of the first word lines in the first direction is smaller than a second thickness of each of the second word lines in the first direction.

22. The variable resistance memory device of claim 20, wherein, The variable resistance memory device includes third word lines including a plurality of the word lines arranged along the third direction and extending along the second direction, and wherein a third thickness of each of the third word lines in the first direction is smaller than the first thickness of each of the first word lines in the first direction.

23. The variable resistance memory device of claim 20, wherein, The first word lines and the second word lines are connected to the bit lines through the memory cells.

24. The variable resistance memory device of claim 19, wherein, The thickness of the word lines of the at least one of the memory cell stacks in the first direction is greater than an average of the thicknesses of the word lines of the other memory cell stacks in the first direction.

25. The variable resistance memory device of claim 20, wherein, A top surface of the substrate is perpendicular to the third direction, and wherein the first direction is parallel to the top surface of the substrate.

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