An LED chip and a manufacturing method thereof

Abstract

Disclosed are an LED chip and a manufacturing method thereof. The LED chip comprises a substrate, a first LED structure and a second LED structure, and the first LED structure and the second LED structure share the substrate. The LED chip of the present application comprises the first LED structure and the second LED structure, and the first LED structure and the second LED structure share the substrate. The first epitaxial layer of the first LED structure and the second epitaxial layer of the second LED structure can be controlled to emit light respectively or simultaneously, thereby improving the light emitting brightness and uniformity of the LED chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to an LED chip and a manufacturing method thereof. BACKGROUND

[0002] Since commercialization in the early 1990s, LED has been widely used in indoor and outdoor display screens, projection display lighting sources, backlights, landscape lighting, advertising, traffic indication and other fields after development for more than twenty years, and is known as the most competitive new generation of solid light source in the twenty-first century. However, for LED, to replace traditional light sources and enter the high-end lighting field, the improvement of light emission brightness and light emission uniformity is crucial.

[0003] The existing LED chip forming step includes: growing a light emitting epitaxial layer on a substrate, making positive and negative electrodes on the light emitting epitaxial layer, and emitting photons after the positive and negative electrodes are electrified. The LED chip with a single light emitting epitaxial layer usually realizes full 360° light emission as a single light emitting source, and the light emission brightness is relatively low. In addition, the existing LED chip has five light emitting surfaces, and the fixing support of the LED chip limits the light emitting surface of the LED chip in the use process, resulting in that the light emission brightness of the LED chip is higher in the vertical direction, and the light emission brightness is weaker in the horizontal direction of the side wall, the light emission is not uniform, and the LED chip is not suitable for the backlight field which requires light emission brightness in the horizontal direction. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide an LED chip and a manufacturing method thereof, the LED chip comprising a first LED structure and a second LED structure, the first LED structure and the second LED structure sharing a substrate, and a first epitaxial layer of the first LED structure and a second epitaxial layer of the second LED structure being capable of being controlled to emit light respectively or simultaneously, thereby improving the light emission brightness and light emission uniformity of the LED chip and expanding the application range of the LED chip.

[0005] According to a first aspect of the present application, an LED chip is provided, comprising:

[0006] a substrate;

[0007] a first LED structure and a second LED structure, the first LED structure and the second LED structure sharing the substrate.

[0008] Further, the first LED structure comprises:

[0009] a first epitaxial layer located on a first surface of the substrate, the first epitaxial layer comprising a first semiconductor layer, a first light emitting layer and a second semiconductor layer arranged in sequence from bottom to top;

[0010] A first PN step is located in the first epitaxial layer, a first upper step surface of the first PN step is the second semiconductor layer, a first lower step surface is the first semiconductor layer, and a first PN step side surface is formed between the first upper step surface and the first lower step surface;

[0011] A first current spreading layer is located on the second semiconductor layer and covers part of the second semiconductor layer;

[0012] A first electrode is located on the first semiconductor layer and is electrically connected to the first semiconductor layer;

[0013] A second electrode is located on the first current spreading layer and is electrically connected to the second semiconductor layer through the first current spreading layer, and the first electrode and the second electrode are isolated from each other;

[0014] The second LED structure comprises:

[0015] A second epitaxial layer is located on the second surface of the substrate, and the second epitaxial layer comprises a third semiconductor layer, a second light-emitting layer, and a fourth semiconductor layer arranged in sequence from top to bottom;

[0016] A second PN step is located in the second epitaxial layer, a second upper step surface of the second PN step is the third semiconductor layer, a second lower step surface is the fourth semiconductor layer, and a second PN step side surface is formed between the second upper step surface and the second lower step surface;

[0017] A second current spreading layer is located below the fourth semiconductor layer and covers part of the fourth semiconductor layer;

[0018] A third electrode is located below the third semiconductor layer and is electrically connected to the third semiconductor layer;

[0019] A fourth electrode is located below the second current spreading layer and is electrically connected to the fourth semiconductor layer through the second current spreading layer, and the third electrode and the fourth electrode are isolated from each other.

[0020] Further, the first current spreading layer has a first opening, part of the second semiconductor layer is exposed through the first opening, and the second electrode is electrically connected to the second semiconductor layer through the first opening;

[0021] The second current spreading layer has a second opening, part of the fourth semiconductor layer is exposed through the second opening, and the fourth electrode is electrically connected to the fourth semiconductor layer through the second opening.

[0022] Further, the first electrode and the third electrode are isolated from each other, and the second electrode and the fourth electrode are isolated from each other.

[0023] Further, the first electrode is electrically connected with the third electrode, and the second electrode is electrically connected with the fourth electrode.

[0024] Further, the first LED structure further comprises:

[0025] A first passivation layer is located on the first electrode and the second electrode, covering the exposed first current spreading layer, the first semiconductor layer, the second semiconductor layer, and the first PN step side surface, the first passivation layer comprising a third opening and a fourth opening, the first electrode being exposed through the third opening, and the second electrode being exposed through the fourth opening;

[0026] The second LED structure further comprises:

[0027] A second passivation layer is located under the third electrode and the fourth electrode, covering the exposed second current spreading layer, the third semiconductor layer, the fourth semiconductor layer, and the second PN step side surface, the second passivation layer comprising a fifth opening and a sixth opening, the third electrode being exposed through the fifth opening, and the fourth electrode being exposed through the sixth opening.

[0028] Further, the first LED structure and the second LED structure further comprise:

[0029] A first via is located at a first lower step surface of the first PN step and a second upper step surface of the second PN step, penetrating the first semiconductor layer, the substrate, and the third semiconductor layer;

[0030] A second via is located in the first opening and the second opening, penetrating the first semiconductor layer, the first light emitting layer, the second semiconductor layer, the first current spreading layer, the substrate, the third semiconductor layer, the second light emitting layer, the fourth semiconductor layer, and the second current spreading layer.

[0031] Further, the first LED structure further comprises:

[0032] A first passivation layer is located on the first current spreading layer, covering part of the first current spreading layer, the exposed second semiconductor layer, part of the first semiconductor layer, the first PN step side surface, part of the inner wall of the first via, and part of the inner wall of the second via, the first passivation layer comprising a seventh opening, an eighth opening, a ninth opening, and a tenth opening, the first semiconductor layer being exposed through the seventh opening and the eighth opening, and the first current spreading layer being exposed through the ninth opening and the tenth opening;

[0033] The second LED structure further comprises:

[0034] A second passivation layer is located under the second current spreading layer, covering part of the second current spreading layer, the exposed fourth semiconductor layer, part of the third semiconductor layer, the second PN step side surface, part of the inner wall of the first via hole and the second via hole, the second passivation layer comprises an eleventh opening, a twelfth opening, a thirteenth opening and a fourteenth opening, the third semiconductor layer is exposed through the eleventh opening and the twelfth opening, and the second current spreading layer is exposed through the thirteenth opening and the fourteenth opening.

[0035] The first passivation layer and the second passivation layer jointly cover the entire inner wall of the first via hole and the second via hole.

[0036] Further, the first electrode is located on the first passivation layer, covering the exposed first semiconductor layer and the first passivation layer of the inner wall of the first via hole, and the first electrode is electrically connected with the first semiconductor layer through the seventh opening and the eighth opening.

[0037] The second electrode is located on the first passivation layer, covering the exposed first current spreading layer and the first passivation layer of the inner wall of the second via hole, and the second electrode is electrically connected with the first current spreading layer through the ninth opening and the tenth opening.

[0038] The third electrode is located under the second passivation layer, covering the exposed third semiconductor layer and the second passivation layer of the inner wall of the first via hole, and the third electrode is electrically connected with the third semiconductor layer through the eleventh opening and the twelfth opening.

[0039] The fourth electrode is located under the second passivation layer, covering the exposed second current spreading layer and the second passivation layer of the inner wall of the second via hole, and the fourth electrode is electrically connected with the second current spreading layer through the thirteenth opening and the fourteenth opening.

[0040] The first electrode and the third electrode jointly cover the first passivation layer and the second passivation layer of the inner wall of the first via hole, and the second electrode and the fourth electrode jointly cover the first passivation layer and the second passivation layer of the inner wall of the second via hole.

[0041] Further, the first semiconductor layer is an N-type semiconductor layer, the first light-emitting layer is configured as a quantum well layer, and the second semiconductor layer is a P-type semiconductor layer.

[0042] The third semiconductor layer is an N-type semiconductor layer, the second light-emitting layer is a quantum well layer, and the fourth semiconductor layer is a P-type semiconductor layer.

[0043] Further, the substrate includes a patterned substrate and a non-patterned substrate.

[0044] Further, the substrate includes a first substrate layer, a punched area, and a second substrate layer, the punched area is located between the first substrate layer and the second substrate layer, and the punched area includes a third via hole.

[0045] According to a second aspect of the present application, a method for manufacturing an LED chip is provided, comprising:

[0046] manufacturing a first LED structure on a first surface of a substrate;

[0047] manufacturing a second LED structure on a second surface of the substrate, the first LED structure and the second LED structure sharing the substrate.

[0048] Further, the first LED structure includes a first epitaxial layer, and the second LED structure includes a second epitaxial layer, the first epitaxial layer and the second epitaxial layer are simultaneously manufactured, the first epitaxial layer includes a first semiconductor layer, a first light-emitting layer, and a second semiconductor layer arranged in sequence from bottom to top, and the second epitaxial layer includes a third semiconductor layer, a second light-emitting layer, and a fourth semiconductor layer arranged in sequence from top to bottom.

[0049] Further, the manufacturing of the first LED structure on the first surface of the substrate includes:

[0050] forming a first current spreading layer on the second semiconductor layer, the first current spreading layer having a first opening, and the first opening exposing part of the second semiconductor layer;

[0051] forming a first PN step in the first epitaxial layer, a first upper step surface of the first PN step being the second semiconductor layer, a first lower step surface being the first semiconductor layer, and a first PN step side surface being formed between the first upper step surface and the first lower step surface.

[0052] Further, the manufacturing of the first LED structure on the first surface of the substrate further includes:

[0053] forming a first electrode on the first semiconductor layer and a second electrode on the first current spreading layer;

[0054] forming a first passivation layer on the first electrode and the second electrode, the first passivation layer covering the exposed first current spreading layer, the first semiconductor layer, the second semiconductor layer, and the first PN step side surface, the first passivation layer including a third opening and a fourth opening, the first electrode being exposed through the third opening, and the second electrode being exposed through the fourth opening.

[0055] Further, after the first LED structure is manufactured on the first surface of the substrate, the second LED structure is manufactured on the second surface of the substrate, and the second LED structure comprises:

[0056] A second current spreading layer is formed under the fourth semiconductor layer, the second current spreading layer has a second opening, and the second opening exposes part of the fourth semiconductor layer;

[0057] A second PN step is formed in the second epitaxial layer, a second upper step surface of the second PN step is the third semiconductor layer, a second lower step surface of the second PN step is the fourth semiconductor layer, and a second PN step side surface is formed between the second upper step surface and the second lower step surface.

[0058] Further, after the first LED structure is manufactured on the first surface of the substrate, the second LED structure is manufactured on the second surface of the substrate, and the second LED structure comprises:

[0059] A third electrode is formed under the third semiconductor layer, and a fourth electrode is formed under the second current spreading layer;

[0060] A second passivation layer is formed under the third electrode and the fourth electrode, the second passivation layer covers the exposed second current spreading layer, the third semiconductor layer, the fourth semiconductor layer, and the second PN step side surface, the second passivation layer comprises a fifth opening and a sixth opening, the third electrode is exposed through the fifth opening, and the fourth electrode is exposed through the sixth opening.

[0061] Further, the first LED structure manufactured on the first surface of the substrate further comprises:

[0062] A first via hole is formed on the first lower step surface of the first PN step, and the first via hole penetrates through the first semiconductor layer, the substrate, the third semiconductor, the second light emitting layer, and the fourth semiconductor layer;

[0063] A second via hole is formed in the first opening, and the second via hole penetrates through the first semiconductor layer, the first light emitting layer, the second semiconductor layer, the first current spreading layer, the substrate, the third semiconductor layer, the second light emitting layer, and the fourth semiconductor layer.

[0064] Further, the first LED structure manufactured on the first surface of the substrate further comprises:

[0065] forming a first passivation layer on the first current spreading layer, the first passivation layer covering part of the first current spreading layer, the exposed second semiconductor layer, part of the first semiconductor layer, the first PN step side surface, part of the inner wall of the first via hole and the second via hole, the first passivation layer comprising a seventh opening, an eighth opening, a ninth opening and a tenth opening, the first semiconductor layer being exposed through the seventh opening and the eighth opening, the first current spreading layer being exposed through the ninth opening and the tenth opening.

[0066] Further, the manufacturing the first LED structure on the first surface of the substrate further comprises:

[0067] forming a first electrode and a second electrode on the first passivation layer, the first electrode covering the exposed first semiconductor layer and the first passivation layer of the inner wall of the first via hole, the first electrode being electrically connected with the first semiconductor layer through the seventh opening and the eighth opening, the second electrode covering the exposed first current spreading layer and the first passivation layer of the inner wall of the second via hole, the second electrode being electrically connected with the first current spreading layer through the ninth opening and the tenth opening.

[0068] Further, after the manufacturing the first LED structure on the first surface of the substrate, the manufacturing the second LED structure on the second surface of the substrate further comprises:

[0069] forming a second passivation layer under the second current spreading layer, the second passivation layer covering part of the second current spreading layer, the exposed fourth semiconductor layer, part of the third semiconductor layer, the second PN step side surface, part of the inner wall of the first via hole and the second via hole, the second passivation layer comprising an eleventh opening, a twelfth opening, a thirteenth opening and a fourteenth opening, the third semiconductor layer being exposed through the eleventh opening and the twelfth opening, the second current spreading layer being exposed through the thirteenth opening and the fourteenth opening,

[0070] the first passivation layer and the second passivation layer jointly cover the entire inner wall of the first via hole and the second via hole.

[0071] Further, after the manufacturing the first LED structure on the first surface of the substrate, the manufacturing the second LED structure on the second surface of the substrate further comprises:

[0072] A third electrode and a fourth electrode are formed under the second passivation layer. The third electrode covers the exposed third semiconductor layer and the second passivation layer on the inner wall of the first via. The third electrode is electrically connected to the third semiconductor layer through the eleventh and twelfth openings. The fourth electrode covers the exposed second current spreading layer and the second passivation layer on the inner wall of the second via. The fourth electrode is electrically connected to the second current spreading layer through the thirteenth and fourteenth openings.

[0073] The first electrode and the third electrode together cover the first passivation layer and the second passivation layer on the inner wall of the first via, and the second electrode and the fourth electrode together cover the first passivation layer and the second passivation layer on the inner wall of the second via.

[0074] Furthermore, prior to fabricating the second LED structure on the second surface of the substrate, the manufacturing method further includes...

[0075] A bonding protective layer is formed above the first LED structure;

[0076] After fabricating the second LED structure on the second surface of the substrate, the manufacturing method further includes:

[0077] Remove the bonding protective layer above the first LED structure.

[0078] Further, the substrate includes: a first substrate layer, a perforated area, and a second substrate layer, wherein the perforated area is located between the first substrate layer and the second substrate layer.

[0079] The manufacturing method further includes, before fabricating the first LED structure on the first surface of the substrate or after fabricating the second LED structure on the second surface of the substrate:

[0080] A third through hole is formed in the punching area.

[0081] According to a third aspect of the present invention, a lamp is provided, comprising: an LED chip as described above.

[0082] The first embodiment of this invention provides an LED chip and a method for manufacturing an LED chip. The LED chip includes a first LED structure and a second LED structure, which share a common substrate. The first epitaxial layer of the first LED structure and the second epitaxial layer of the second LED structure can be controlled to emit light separately or simultaneously. Simultaneous emission of the first and second LED structures increases the emission angle of the LED chip and improves its brightness. The LED chip has six emitting surfaces, achieving uniform emission across the entire circumference in both the vertical and horizontal directions, thus improving the uniformity of light emission. The emitting surfaces can be applied laterally to address and improve issues such as excessive frontal emission, noticeable bright spots, and uneven surface emission in display / backlight applications. Attached Figure Description

[0083] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0084] Figure 1 A cross-sectional schematic diagram of an LED chip according to a first embodiment of the present invention is shown;

[0085] Figures 2 to 10 Cross-sectional views of different stages of the LED chip manufacturing method according to the first embodiment of the present invention are shown;

[0086] Figure 11 A cross-sectional schematic diagram of an LED chip provided according to a second embodiment of the present invention is shown;

[0087] Figures 12 to 21 Cross-sectional views of different stages of the LED chip manufacturing method according to the second embodiment of the present invention are shown. Detailed Implementation

[0088] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0089] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0090] Figure 1 A cross-sectional schematic diagram of an LED chip according to a first embodiment of the present invention is shown. Figure 1 As shown, the LED chip 100 includes:

[0091] Substrate 101; First LED structure 100a and second LED structure 100b, both sharing a substrate 101. First LED structure 100a includes: a first epitaxial layer located on a first surface of substrate 101; the first epitaxial layer includes a first semiconductor layer 102, a first light-emitting layer 103, and a second semiconductor layer 104, sequentially disposed from bottom to top; the first semiconductor layer 102 is located above substrate 101 and is an N-type semiconductor layer. The first light-emitting layer 103 is located above the first semiconductor layer 102 and is constructed as a quantum well layer. The second semiconductor layer 104 is located above the first light-emitting layer 103 and is a P-type semiconductor layer. A first PN step is located in the first epitaxial layer. The first upper step surface of the first PN step is the second semiconductor layer 104, and the first lower step surface is the first semiconductor layer 102. The first upper step surface and the first lower step surface are connected to form the side surface 109a of the first PN step. A first current spreading layer 108 is located on the second semiconductor layer 104 and covers a portion of the second semiconductor layer 104. The first current spreading layer 108 has a first opening 116, which exposes a portion of the second semiconductor layer 104. A first electrode 110a is located on the first semiconductor layer 102 and is electrically connected to the first semiconductor layer 102. The second electrode 110b is isolated from the first electrode 110a and is located on the first current spreading layer 108. It is electrically connected to the second semiconductor layer 104 through the first opening 116. The first passivation layer 111 is located on the first electrode 110a and the second electrode 110b, covering the exposed first current spreading layer 108, the first semiconductor layer 102, the second semiconductor layer 104, and the first PN step side 109a. The first passivation layer 111 includes a third opening 117 and a fourth opening 118. The first electrode 110a is exposed through the third opening 117, and the second electrode 110b is exposed through the fourth opening 118.

[0092] The second LED structure 100b includes: a second epitaxial layer located on the second surface of a substrate 101; the second epitaxial layer includes a third semiconductor layer 105, a second light-emitting layer 106, and a fourth semiconductor layer 107 disposed sequentially from top to bottom; the third semiconductor layer 105 is located below the substrate 101 and is an N-type semiconductor layer; the second light-emitting layer 106 is located below the third semiconductor layer 105 and is a quantum well layer; and the fourth semiconductor layer 107 is located below the second light-emitting layer 106 and is a P-type semiconductor layer. A second PN step is located in the second epitaxial layer. The second upper step surface of the second PN step is the third semiconductor layer 105, and the second lower step surface is the fourth semiconductor layer 107. The connection between the second upper step surface and the second lower step surface forms the side surface 109b of the second PN step. A second current spreading layer 113 is located below the fourth semiconductor layer 107, covering a portion of the fourth semiconductor layer 107. The second current spreading layer 113 has a second opening (opposite to the first opening 116), exposing a portion of the fourth semiconductor layer 107. The materials of the first current spreading layer 108 and the second current spreading layer 113 are, for example, ITO. The first current spreading layer 108 and the second current spreading layer 113 promote current spreading, improving the current spreading effect of the LED chip. The third electrode 114a is located below the third semiconductor layer 105 and is electrically connected to the third semiconductor layer 105. The fourth electrode 114b is isolated from the third electrode 114a, located below the second current spreading layer 113, and is electrically connected to the fourth semiconductor layer 107 through the second opening. The first electrode 110a is isolated from the third electrode 114a, and the second electrode 110b is isolated from the fourth electrode 114b. The second passivation layer 115 is located below the third electrode 114a and the fourth electrode 114b, covering the exposed second current spreading layer 113, the third semiconductor layer 105, the fourth semiconductor layer 107, and the second PN step sidewall 109b. The second passivation layer 115 includes a fifth opening (opposite to the third opening 117) and a sixth opening (opposite to the fourth opening 118), exposing the third electrode 114a through the fifth opening and the fourth electrode 114b through the sixth opening.

[0093] The substrate 101 can be a patterned substrate or a non-patterned substrate. The material of the substrate 101 can be sapphire, Si (silicon), SiC (silicon carbide), GaN (gallium nitride), ZnO (zinc oxide), etc. The substrate 101 includes: a first substrate layer 101a, a perforated region 101b, and a second substrate layer 101c. The perforated region 101b is an intermediate layer of the substrate 101, located between the first substrate layer 101a and the second substrate layer 101c. The perforated region 101b includes one or more third vias, the axis of which is parallel to the first and second surfaces of the substrate 101. If the substrate 101 is relatively thick, LED chips 100 can be connected in series through one or more third vias in the perforated region 101b, facilitating the fabrication of LED omnidirectional light-emitting flexible or rigid filaments, bulbs, lamps, etc. The connecting material can be a metal or other highly thermally conductive material to improve the heat dissipation of the LED chips. It is easy to understand that whether the substrate 101 is provided with a punched area 101b depends on the needs of the actual engineering application. In some embodiments, the substrate 101 may not be provided with a punched area 101b.

[0094] Figures 2 to 10 Cross-sectional views of different stages of the LED chip manufacturing method according to the first embodiment of the present invention are shown. (Reference) Figures 2-10 The method for manufacturing the LED chip includes the following steps.

[0095] like Figure 2 and Figure 3 As shown, a first epitaxial layer is formed on the first surface of the substrate 101, and a second epitaxial layer is formed on the second surface of the substrate 101. The first epitaxial layer includes a first semiconductor layer 102, a first light-emitting layer 103 and a second semiconductor layer 104 arranged sequentially from bottom to top. The second epitaxial layer includes a third semiconductor layer 105, a second light-emitting layer 106 and a fourth semiconductor layer 107 arranged sequentially from top to bottom.

[0096] The substrate 101 can be a patterned substrate or a non-patterned substrate. When the substrate 101 is a patterned substrate (PSS), a photoresist pattern is etched on the first and second surfaces of the substrate 101 using a photolithography process. Then, the substrate 101 is etched using an etching technique to form patterned grooves on the surface of the substrate 101 to improve light extraction efficiency.

[0097] Specifically, a transparent material is grown on the first surface of substrate 101 as a patterning substrate, and a layer of photoresist is uniformly coated on the first surface of substrate 101. A corresponding photomask is then placed on the first surface of substrate 101, and the photoresist is exposed using ultraviolet light. A developing solution is applied to the first surface of substrate 101 to remove the photoresist from the corresponding pattern on the photomask. The patterned area on the first surface of substrate 101 is developed using a plasma scanner to remove residual photoresist. A layer of backing adhesive is coated on the second surface of substrate 101, and then the transparent material is etched using a corresponding etching solution. The photoresist on the first surface of substrate 101 is removed using a photoresist remover. Substrate 101 is then immersed in the corresponding etching solution to etch the first surface of substrate 101. After the patterning of the first surface of substrate 101 is completed, the backing adhesive on the second surface of substrate 101 is removed.

[0098] A transparent material is grown on the second surface of substrate 101 as a patterning substrate, and a layer of photoresist is uniformly coated on the second surface of substrate 101. A corresponding photomask is then placed on the second surface of substrate 101, and the photoresist is exposed using ultraviolet light. A developer is applied to the second surface of substrate 101 to remove the photoresist corresponding to the pattern on the photomask. The patterned area on the second surface of substrate 101 is developed using a plasma scanner to remove residual photoresist. A layer of backing adhesive is coated on the first surface of substrate 101, and then the transparent material is etched using a corresponding etching solution. The photoresist on the second surface of substrate 101 is removed using a photoresist remover. Substrate 101 is then immersed in the corresponding etching solution to etch the second surface of substrate 101. After the patterning of the second surface of substrate 101 is complete, the backing adhesive on the first surface of substrate 101 is removed.

[0099] It should be noted that one or more third vias can be etched in the drilling region 101b of the substrate 101 using etching, laser, or other techniques before the first epitaxial layer and the second epitaxial layer are grown on the first and second surfaces of the substrate 101, respectively. Alternatively, they can be etched according to... Figures 2 to 10 The LED chip manufacturing method of the first embodiment of the present invention shown is as follows: after the LED chip is fabricated, the drilling area 101b of the substrate 101 is etched by etching, laser or other techniques to form one or more third vias.

[0100] The first epitaxial layer and the second epitaxial layer can be formed on the first surface and the second surface of the substrate 101 by any one or more existing known methods such as vapor deposition or evaporation.

[0101] like Figure 4As shown, a first current spreading layer 108 is formed on the second semiconductor layer 104. The first current spreading layer 108 covers a portion of the second semiconductor layer 104 and has a first opening 116 that exposes a portion of the second semiconductor layer 104.

[0102] A first current spreading layer material is grown on the second semiconductor layer 104, and a layer of photoresist is uniformly coated on the first current spreading layer material. A corresponding photomask is then placed on the first current spreading layer material, and the photoresist is exposed using ultraviolet light. A developing solution is applied to the first current spreading layer material to remove the photoresist from the corresponding pattern on the photomask. The patterned areas on the first current spreading layer material are treated using a plasma scanner to remove residual photoresist. A backing adhesive is coated on the fourth semiconductor layer 107, and then the first current spreading layer material is etched using a corresponding etching solution to pattern the first current spreading layer material, forming the first opening 116. Residual photoresist is removed using a resist remover. It should be noted that the backing adhesive on the fourth semiconductor layer 107 can be removed after the formation of the first passivation layer 111.

[0103] like Figure 5 As shown, the first epitaxial layer is partially etched to form a first PN step in the first epitaxial layer. The first upper step surface of the first PN step is the second semiconductor layer 104, and the first lower step surface is the first semiconductor layer 102. The first upper step surface and the first lower step surface are connected to form the side surface 109a of the first PN step.

[0104] A layer of photoresist is uniformly coated onto the first current spreading layer 108 and the exposed second semiconductor layer 104. A corresponding photomask is then placed on the first current spreading layer 108 and the exposed second semiconductor layer 104, and the photoresist is exposed using ultraviolet light. A developer is applied to the first current spreading layer 108 and the exposed second semiconductor layer 104 to remove the photoresist from the corresponding pattern on the photomask. The patterned areas on the first current spreading layer 108 and the exposed second semiconductor layer 104 are treated with a plasma etching machine to remove residual photoresist. The workpiece is placed in an etching machine, where plasma is used to bombard the etching gas, followed by etching of the first epitaxial layer with ionized gas to a depth exceeding the first light-emitting layer 103, exposing the first semiconductor layer 102. From the side, this etched platform forms the first PN step. Residual photoresist is removed using a photoresist remover.

[0105] like Figure 6 As shown, a first electrode 110a is formed on the first semiconductor layer 102 and is electrically connected to the first semiconductor layer 102; a second electrode 110b is formed on the first current spreading layer 108 and is isolated from the first electrode 110a, and is electrically connected to the second semiconductor layer 104 through the first opening 116.

[0106] A layer of photoresist is uniformly coated onto the first current spreading layer 108, the exposed first semiconductor layer 102, and the second semiconductor layer 104. Subsequently, a corresponding photomask is placed on the first current spreading layer 108, the exposed first semiconductor layer 102, and the second semiconductor layer 104, and the photoresist is exposed using ultraviolet light. A developer is then applied to the first current spreading layer 108, the exposed first semiconductor layer 102, and the second semiconductor layer 104 to remove the photoresist from the corresponding pattern on the photomask. A plasma scanner is used to remove residual photoresist from the developed pattern areas on the first current spreading layer 108, the exposed first semiconductor layer 102, and the second semiconductor layer 104. A metal layer (such as titanium (Ti), platinum (Pt), silver (Ag), aluminum (Al), nickel (Ni), chromium (Cr), gold (Au), or gold-tin alloy (AuSn) or one or more metals) is grown on the first current spreading layer 108, the exposed first semiconductor layer 102, and the second semiconductor layer 104 using processes such as physical vapor deposition, electron beam evaporation, and sputtering. The metal on the photoresist is then removed using a stripping process, leaving the first electrode 110a and the second electrode 110b. Subsequently, the remaining photoresist is removed using a photoresist remover.

[0107] like Figure 7 As shown, a first passivation layer 111 is formed on the first electrode 110a and the second electrode 110b. The first passivation layer 111 covers the exposed first current spreading layer 108, the second semiconductor layer 104, the first semiconductor layer 102, and the first PN step side 109a. The first passivation layer 111 includes a third opening 117 and a fourth opening 118. The first electrode 110a is exposed through the third opening 117, and the second electrode 110b is exposed through the fourth opening 118.

[0108] A first passivation layer material 111 is grown on the first electrode 110a and the second electrode 110b, and a layer of photoresist is uniformly coated on the first passivation layer material. A corresponding photomask is then placed on the first passivation layer material, and the photoresist is exposed using ultraviolet light. A developer is applied to the photoresist to remove the photoresist from the corresponding pattern on the photomask. The patterned areas on the first passivation layer material are treated using a plasma scanner to remove residual photoresist. The first passivation layer material is etched using a corresponding etching solution to pattern the first passivation layer material, forming the third opening 117 and the fourth opening 118. Residual photoresist is removed using a photoresist remover. After forming the first passivation layer 111 on the first electrode 110a and the second electrode 110b, the backing adhesive on the fourth semiconductor layer 107 is removed. At this point, the fabrication of the first LED structure 110a is complete.

[0109] like Figure 8As shown, a bonding protective layer 112 is formed on the first passivation layer 111, covering the first electrode 110a, the second electrode 110b, and the first passivation layer 111. The material of the bonding protective layer 112 in this embodiment includes silicon dioxide polymer, high-temperature resistant adhesive, etc. The material of the bonding protective layer 112 is applied to the upper surface of the first LED structure 100a by coating, homogenization, or other methods to protect the upper surface of the first LED structure 100a from the influence of subsequent processes.

[0110] like Figure 9 As shown, according to Figures 4 to 7 The process steps shown form a second LED structure 100b on the second surface of the substrate 101.

[0111] like Figure 10 As shown, debonding process is used to remove Figure 8 and Figure 9 The bonding protective layer 112 shown provides the LED chip 100 in the first embodiment of the present invention. In some embodiments, electrical connection lines can be led out from the first electrode 110a and the second electrode 110b, and from the third electrode 114a and the fourth electrode 114b, for controlling the two LED structures respectively.

[0112] The first embodiment of this invention provides an LED chip and a method for manufacturing an LED chip. The LED chip includes a first LED structure and a second LED structure, which share a common substrate. The first epitaxial layer of the first LED structure and the second epitaxial layer of the second LED structure can be controlled to emit light separately or simultaneously. Simultaneous emission of the first and second LED structures increases the emission angle of the LED chip and improves its brightness. The LED chip has six emitting surfaces, achieving uniform emission across the entire circumference in both the vertical and horizontal directions of the sidewalls, thus improving the uniformity of light emission. The emitting surfaces can be applied laterally to address and improve issues such as excessive frontal emission, noticeable bright spots, and uneven surface emission in display / backlight applications.

[0113] In addition, compared with existing LED chips, in order to achieve the preset brightness required for the application scenario, the LED chip in the embodiment of the present invention has two light-emitting epitaxial layers, which can use fewer LED chips to achieve the preset brightness required for the application scenario, thereby reducing the cost of using LED chips to emit light in the application scenario.

[0114] Figure 11 A cross-sectional schematic diagram of an LED chip according to a second embodiment of the present invention is shown. Figure 11 As shown, the LED chip 200 includes:

[0115] Substrate 201; First LED structure 200a and second LED structure 200b, both sharing a substrate 201. First LED structure 200a includes: a first epitaxial layer located on a first surface of substrate 201; the first epitaxial layer includes a first semiconductor layer 202, a first light-emitting layer 203, and a second semiconductor layer 204, sequentially disposed from bottom to top; the first semiconductor layer 202 is located above substrate 201 and is an N-type semiconductor layer. The first light-emitting layer 203 is located above the first semiconductor layer 202 and is constructed as a quantum well layer. The second semiconductor layer 204 is located above the first light-emitting layer 203 and is a P-type semiconductor layer. A first PN step is located in the first epitaxial layer. The first upper step surface of the first PN step is the second semiconductor layer 204, and the first lower step surface is the first semiconductor layer 202. The first upper step surface and the first lower step surface are connected to form the side surface 209a of the first PN step. A first current spreading layer 208 is located on the second semiconductor layer 204 and covers a portion of the second semiconductor layer 204. The first current spreading layer 208 has a first opening 216, which exposes a portion of the second semiconductor layer 204.

[0116] The first via 217 is located on the first lower step surface of the first PN step and penetrates the first semiconductor layer 202, the substrate 201 and the third semiconductor 205; the second via 218 is located in the first opening 216 and penetrates the first semiconductor layer 202, the first light-emitting layer 203, the second semiconductor layer 204, the first current spreading layer 208, the substrate 201, the third semiconductor layer 205, the second light-emitting layer 206, the fourth semiconductor layer 207 and the second current spreading layer 213.

[0117] A first passivation layer 210 is located on the first current spreading layer 208, covering a portion of the first current spreading layer 208, the exposed second semiconductor layer 204, a portion of the first semiconductor layer 202, the side surface of the first PN step 209a, and a portion of the inner wall of the first via 217 and the second via 218. The first passivation layer 210 includes a seventh opening 219, an eighth opening 220, a ninth opening 221, and a tenth opening 222. The first semiconductor layer 202 is exposed through the seventh opening 219 and the eighth opening 220, and the first current spreading layer 208 is exposed through the ninth opening 221 and the tenth opening 222.

[0118] The first electrode 211a is located on the first passivation layer 210. The first electrode 211a covers the exposed first semiconductor layer 202 and the first passivation layer 210 on the inner wall of the first via 217. The first electrode 211a is electrically connected to the first semiconductor layer 202 through the seventh opening 219 and the eighth opening 220. The second electrode 211b is isolated from the first electrode 211a and is located on the first passivation layer 210. The second electrode 211b covers the exposed first current spreading layer 208 and the first passivation layer 210 on the inner wall of the second via 218. The second electrode 211b is electrically connected to the first current spreading layer 208 through the ninth opening 221 and the tenth opening 222.

[0119] The second LED structure 200b includes: a second epitaxial layer located on the second surface of a substrate 201; the second epitaxial layer includes a third semiconductor layer 205, a second light-emitting layer 206, and a fourth semiconductor layer 207 disposed sequentially from top to bottom; the third semiconductor layer 205 is located below the substrate 201 and is an N-type semiconductor layer; the second light-emitting layer 206 is located below the third semiconductor layer 205 and is a quantum well layer; and the fourth semiconductor layer 207 is located below the second light-emitting layer 206 and is a P-type semiconductor layer. The second PN step is located in the second epitaxial layer. The second upper step surface of the second PN step is the third semiconductor layer 205, and the second lower step surface is the fourth semiconductor layer 207. The second upper step surface and the second lower step surface are connected to form the side surface 209b of the second PN step. The first via 217 is located on the second upper step surface of the second PN step. The second current spreading layer 213 is located below the fourth semiconductor layer 207 and covers part of the fourth semiconductor layer 207. The second current spreading layer 213 has a second opening (located in the opposite position to the first opening 216). The second opening exposes part of the fourth semiconductor layer 207, and the second via 218 is located in the second opening.

[0120] The second passivation layer 214 is located below the second current spreading layer 213, covering a portion of the second current spreading layer 213, the exposed fourth semiconductor layer 207, a portion of the third semiconductor layer 205, the side surface 209b of the second PN step, and a portion of the inner wall of the first via 217 and the second via 218. The second passivation layer 214 and the first passivation layer 210 together cover the entire inner wall of the first via 217 and the second via 218. The second passivation layer 214 includes an eleventh opening (located relative to the seventh opening 219), a twelfth opening (located relative to the eighth opening 220), a thirteenth opening (located relative to the ninth opening 221), and a fourteenth opening (located relative to the tenth opening 222). The third semiconductor layer 205 is exposed through the eleventh and twelfth openings, and the second current spreading layer 213 is exposed through the thirteenth and fourteenth openings.

[0121] The third electrode 215a is located below the second passivation layer 214. The third electrode 215a covers the exposed third semiconductor layer 205 and the second passivation layer 214 on the inner wall of the first via 217. The third electrode 215a is electrically connected to the third semiconductor layer 205 through the eleventh and twelfth openings. The first electrode 211a and the third electrode 215a together cover the first passivation layer 210 and the second passivation layer 214 on the inner wall of the first via 217. The fourth electrode 215b is isolated from the third electrode 215a and located below the second passivation layer 214. The fourth electrode 215b covers the exposed second current spreading layer 213 and the second passivation layer 214 on the inner wall of the second via 218. The fourth electrode 215b is electrically connected to the second current spreading layer 213 through the thirteenth and fourteenth openings. The second electrode 211b and the fourth electrode 215b together cover the first passivation layer 210 and the second passivation layer 214 on the inner wall of the second via 218. The first electrode 211a is electrically connected to the third electrode 215a, and the second electrode 211b is electrically connected to the fourth electrode 215b. The first electrode 211a and the third electrode 215a are N-type electrodes, and the second electrode 211b and the fourth electrode 215b are P-type electrodes.

[0122] Figures 12 to 21 Cross-sectional views of different stages of the LED chip manufacturing method according to the second embodiment of the present invention are shown. (Reference) Figures 12-21 The method for manufacturing the LED chip includes the following steps.

[0123] like Figure 12 and Figure 13 As shown, a first epitaxial layer is formed on the first surface of the substrate 201, and a second epitaxial layer is formed on the second surface of the substrate 201. The first epitaxial layer includes a first semiconductor layer 202, a first light-emitting layer 203 and a second semiconductor layer 204 arranged sequentially from bottom to top. The second epitaxial layer includes a third semiconductor layer 205, a second light-emitting layer 206 and a fourth semiconductor layer 207 arranged sequentially from top to bottom.

[0124] like Figure 14 As shown, a first current spreading layer 208 is formed on the second semiconductor layer 204. The first current spreading layer 208 covers a portion of the second semiconductor layer 204 and has a first opening 216 that exposes a portion of the second semiconductor layer 204.

[0125] like Figure 15 As shown, the first epitaxial layer is partially etched to form a first PN step in the first epitaxial layer. The first upper step surface of the first PN step is the second semiconductor layer 204, and the first lower step surface is the first semiconductor layer 202. The first upper step surface and the first lower step surface are connected to form the side surface 209a of the first PN step.

[0126] likeFigures 12 to 15 The manufacturing method of the second embodiment shown is the same as Figures 2 to 5 The method for manufacturing the LED chip shown in the first embodiment of the present invention is the same, and will not be repeated here.

[0127] like Figure 16 As shown, a first via 217 is formed on the first lower step surface of the first PN step, and the first via 217 penetrates the first semiconductor layer 202, the substrate 201, the third semiconductor 205, the second light-emitting layer 206 and the fourth semiconductor layer 207; a second via 218 is formed in the first opening 216, and the second via 218 penetrates the first semiconductor layer 202, the first light-emitting layer 203, the second semiconductor layer 204, the first current spreading layer 208, the substrate 201, the third semiconductor layer 205, the second light-emitting layer 206 and the fourth semiconductor layer 207.

[0128] On the first lower step surface, a small hole is made in the area to be covered by the first electrode 211a using a laser or etching process to form a first through hole 217. Inside the first opening 216, a small hole is made in the area to be covered by the second electrode 211b using a laser or etching process to form a second through hole 218.

[0129] like Figure 17 As shown, a first passivation layer 210 is formed on the first current spreading layer 208. The first passivation layer 210 covers a portion of the first current spreading layer 208, the exposed second semiconductor layer 204, a portion of the first semiconductor layer 202, the side surface of the first PN step 209a, and a portion of the inner wall of the first via 217 and the second via 218. The first passivation layer 210 includes a seventh opening 219, an eighth opening 220, a ninth opening 221, and a tenth opening 222. The first semiconductor layer 202 is exposed through the seventh opening 219 and the eighth opening 220, and the first current spreading layer 208 is exposed through the ninth opening 221 and the tenth opening 222.

[0130] A first passivation layer material is grown on the first current spreading layer 208, covering the first current spreading layer 208, the exposed second semiconductor layer 204, the first semiconductor layer 202, the side surface of the first PN step 209a, and part of the inner wall of the first via 217 and the second via 218. A layer of photoresist is uniformly coated on the first passivation layer material. Subsequently, a corresponding photomask is placed on the first passivation layer material, and the photoresist is exposed using ultraviolet light. A developer is applied to the photoresist to remove the photoresist of the corresponding pattern on the photomask. The developed pattern on the first passivation layer material is treated with a plasma scanner to remove residual photoresist. The first passivation layer material is etched using a corresponding etching solution to pattern the material, exposing the seventh opening 219, the eighth opening 220, the ninth opening 221, and the tenth opening 222. These openings serve as pre-reserved openings for the first electrode 211a and the second electrode 211b, used for metal vapor deposition. Residual photoresist is then removed using a photoresist remover.

[0131] like Figure 18 As shown, a first electrode 211a and a second electrode 211b are formed on the first passivation layer 210. The first electrode 211a covers the exposed first semiconductor layer 202 and the first passivation layer 210 on the inner wall of the first via 217, and is electrically connected to the first semiconductor layer 202 through a seventh opening 219 and an eighth opening 220. The second electrode 211b is isolated from the first electrode 211a and covers the exposed first current spreading layer 208 and the first passivation layer 210 on the inner wall of the second via 218, and is electrically connected to the first current spreading layer 208 through a ninth opening 221 and a tenth opening 222.

[0132] A layer of photoresist is uniformly coated onto the exposed first semiconductor layer 202, first current spreading layer 208, and first passivation layer 210. Then, a corresponding photomask is placed on the exposed first semiconductor layer 202, first current spreading layer 208, and first passivation layer 210, and the photoresist is exposed using ultraviolet light. A developer is applied to the exposed first semiconductor layer 202, first current spreading layer 208, and first passivation layer 210 to remove the photoresist from the corresponding pattern on the photomask. The patterned areas on the exposed first semiconductor layer 202, first current spreading layer 208, and first passivation layer 210 are then treated using a plasma analyzer to remove residual photoresist. A metal layer (such as titanium (Ti), platinum (Pt), silver (Ag), aluminum (Al), nickel (Ni), chromium (Cr), gold (Au), or gold-tin alloy (AuSn) or one or more metals) is grown on the exposed first semiconductor layer 202, first current spreading layer 208, and first passivation layer 210 using processes such as physical vapor deposition, electron beam evaporation, and sputtering. The metal on the photoresist is then removed using a stripping process, leaving the first electrode 211a and the second electrode 211b. Residual photoresist is then removed using a photoresist remover.

[0133] like Figure 19 As shown, a bonding protective layer 212 is formed on the first electrode 211a and the second electrode 211b, covering the first electrode 211a, the second electrode 211b, the first current spreading layer 208, and the first passivation layer 210. The material of the bonding protective layer 212 in this embodiment includes silicon dioxide polymer, high-temperature resistant adhesive, etc. The material of the bonding protective layer 212 is applied to the upper surface of the first LED chip 200a by coating, spin coating, or other methods to protect the upper surface of the first LED structure 200a from the influence of subsequent processes.

[0134] like Figure 20 As shown, according to Figures 14 to 18 The process steps shown form a second LED structure 200b on the second surface of the substrate 201.

[0135] like Figure 21 As shown, debonding process is used to remove Figure 19 and 20 The bonding protective layer 212 shown above yields the LED chip 200 in the second embodiment of the present invention.

[0136] The LED chip and its manufacturing method provided in the second embodiment of the present invention involve a first electrode and a third electrode jointly covering the first passivation layer and the second passivation layer on the inner wall of a first via, and a second electrode and a fourth electrode jointly covering the first passivation layer and the second passivation layer on the inner wall of a second via. The first electrode and the third electrode are electrically connected, and the second electrode and the fourth electrode are also electrically connected. By simply energizing the first electrode (or the third electrode) and the second electrode (or the fourth electrode), the first and second epitaxial layers of the LED chip can emit light simultaneously, which is convenient and reduces the complexity of powering the LED chip.

[0137] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An LED chip, wherein, include: The substrate allows the LED chip to be connected in series with other LED chips through a perforated area in the substrate. A first LED structure and a second LED structure, wherein the first LED structure and the second LED structure share the substrate; The first LED structure includes: a first epitaxial layer located on a first surface of the substrate, the first epitaxial layer including a first semiconductor layer, a first light-emitting layer and a second semiconductor layer disposed sequentially from bottom to top; a first PN step located in the first epitaxial layer, the first upper step surface of the first PN step being the second semiconductor layer, the first lower step surface being the first semiconductor layer, and the first upper step surface and the first lower step surface being connected to form a side surface of the first PN step; and a first current spreading layer located on the second semiconductor layer, covering a portion of the second semiconductor layer. The second LED structure includes: a second epitaxial layer located on a second surface of the substrate, the second epitaxial layer including a third semiconductor layer, a second light-emitting layer and a fourth semiconductor layer disposed sequentially from top to bottom; a second PN step located in the second epitaxial layer, the second upper step surface of the second PN step being the third semiconductor layer, the second lower step surface being the fourth semiconductor layer, and the second upper step surface and the second lower step surface being connected to form a side surface of the second PN step; and a second current spreading layer located below the fourth semiconductor layer, covering a portion of the fourth semiconductor layer. The first via is located on the first lower step surface of the first PN step and the second upper step surface of the second PN step, penetrating the first semiconductor layer, the substrate, and the third semiconductor layer; the second via is located in the first opening of the first current spreading layer and the second opening of the second current spreading layer, penetrating the first semiconductor layer, the first light-emitting layer, the second semiconductor layer, the first current spreading layer, the substrate, the third semiconductor layer, the second light-emitting layer, the fourth semiconductor layer, and the second current spreading layer. The first passivation layer is located on the first current spreading layer, and the second passivation layer is located below the second current spreading layer. The first passivation layer and the second passivation layer together cover the entire inner wall of the first via and the second via. The first and second electrodes are located on the first passivation layer, and the third and fourth electrodes are located below the second passivation layer. The first and second electrodes are isolated from each other, and the fourth electrode is isolated from the third electrode. The first electrode is electrically connected to the first semiconductor layer, the second electrode is electrically connected to the second semiconductor layer through the first current spreading layer, the third electrode is electrically connected to the third semiconductor layer, and the fourth electrode is electrically connected to the fourth semiconductor layer through the second current spreading layer. The first and third electrodes together cover the first and second passivation layers on the inner wall of the first via, and the second and fourth electrodes together cover the first and second passivation layers on the inner wall of the second via.

2. The LED chip according to claim 1, wherein, The first opening exposes a portion of the second semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer through the first opening. The second opening exposes a portion of the fourth semiconductor layer, and the fourth electrode is electrically connected to the fourth semiconductor layer through the second opening.

3. The LED chip according to claim 2, wherein, The first electrode is electrically connected to the third electrode, and the second electrode is electrically connected to the fourth electrode.

4. The LED chip according to claim 3, wherein, The first passivation layer covers a portion of the first current spreading layer, the exposed second semiconductor layer, a portion of the first semiconductor layer, the side surface of the first PN step, the first via, and a portion of the inner wall of the second via. The first passivation layer includes a seventh opening, an eighth opening, a ninth opening, and a tenth opening. The first semiconductor layer is exposed through the seventh opening and the eighth opening, and the first current spreading layer is exposed through the ninth opening and the tenth opening. The second passivation layer covers a portion of the second current spreading layer, the exposed fourth semiconductor layer, a portion of the third semiconductor layer, the side surface of the second PN step, the first via, and a portion of the inner wall of the second via. The second passivation layer includes an eleventh opening, a twelfth opening, a thirteenth opening, and a fourteenth opening. The third semiconductor layer is exposed through the eleventh and twelfth openings, and the second current spreading layer is exposed through the thirteenth and fourteenth openings.

5. The LED chip according to claim 4, wherein, The first electrode covers the exposed first semiconductor layer and the first passivation layer on the inner wall of the first via, and the first electrode is electrically connected to the first semiconductor layer through the seventh opening and the eighth opening; The second electrode covers the exposed first current spreading layer and the first passivation layer on the inner wall of the second via, and the second electrode is electrically connected to the first current spreading layer through the ninth opening and the tenth opening; The third electrode covers the exposed third semiconductor layer and the second passivation layer on the inner wall of the first via, and the third electrode is electrically connected to the third semiconductor layer through the eleventh opening and the twelfth opening; The fourth electrode covers the exposed second current spreading layer and the second passivation layer on the inner wall of the second via, and the fourth electrode is electrically connected to the second current spreading layer through the thirteenth opening and the fourteenth opening.

6. The LED chip according to claim 5, wherein, The first semiconductor layer is an N-type semiconductor layer, the first light-emitting layer is constructed as a quantum well layer, and the second semiconductor layer is a P-type semiconductor layer; The third semiconductor layer is an N-type semiconductor layer, the second light-emitting layer is a quantum well layer, and the fourth semiconductor layer is a P-type semiconductor layer.

7. The LED chip according to claim 6, wherein, The substrate includes patterned substrates and non-patterned substrates.

8. The LED chip according to claim 7, wherein, The substrate includes: a first substrate layer, a perforated area, and a second substrate layer, wherein the perforated area is located between the first substrate layer and the second substrate layer, and the perforated area includes a third via.

9. A method for manufacturing an LED chip, wherein, include: A first LED structure is fabricated on a first surface of a substrate, wherein the LED chip can be connected in series with other LED chips through a perforated area in the substrate; A second LED structure is fabricated on the second surface of the substrate, wherein the first LED structure and the second LED structure share the substrate. The first LED structure includes: a first epitaxial layer located on a first surface of the substrate, the first epitaxial layer including a first semiconductor layer, a first light-emitting layer and a second semiconductor layer disposed sequentially from bottom to top; a first PN step located in the first epitaxial layer, the first upper step surface of the first PN step being the second semiconductor layer, the first lower step surface being the first semiconductor layer, and the first upper step surface and the first lower step surface being connected to form a side surface of the first PN step; and a first current spreading layer located on the second semiconductor layer, covering a portion of the second semiconductor layer. The second LED structure includes: a second epitaxial layer located on a second surface of the substrate, the second epitaxial layer including a third semiconductor layer, a second light-emitting layer and a fourth semiconductor layer disposed sequentially from top to bottom; a second PN step located in the second epitaxial layer, the second upper step surface of the second PN step being the third semiconductor layer, the second lower step surface being the fourth semiconductor layer, and the second upper step surface and the second lower step surface being connected to form a side surface of the second PN step; and a second current spreading layer located below the fourth semiconductor layer, covering a portion of the fourth semiconductor layer. The first via is located on the first lower step surface of the first PN step and the second upper step surface of the second PN step, penetrating the first semiconductor layer, the substrate, and the third semiconductor layer; the second via is located in the first opening of the first current spreading layer and the second opening of the second current spreading layer, penetrating the first semiconductor layer, the first light-emitting layer, the second semiconductor layer, the first current spreading layer, the substrate, the third semiconductor layer, the second light-emitting layer, the fourth semiconductor layer, and the second current spreading layer. The first passivation layer is located on the first current spreading layer, and the second passivation layer is located below the second current spreading layer. The first passivation layer and the second passivation layer together cover the entire inner wall of the first via and the second via. The first and second electrodes are located on the first passivation layer, and the third and fourth electrodes are located below the second passivation layer. The first and second electrodes are isolated from each other, and the fourth electrode is isolated from the third electrode. The first electrode is electrically connected to the first semiconductor layer, the second electrode is electrically connected to the second semiconductor layer through the first current spreading layer, the third electrode is electrically connected to the third semiconductor layer, and the fourth electrode is electrically connected to the fourth semiconductor layer through the second current spreading layer. The first and third electrodes together cover the first and second passivation layers on the inner wall of the first via, and the second and fourth electrodes together cover the first and second passivation layers on the inner wall of the second via.

10. The manufacturing method according to claim 9, wherein, The first epitaxial layer and the second epitaxial layer are manufactured simultaneously.

11. The manufacturing method according to claim 10, wherein, The fabrication of the first LED structure on the first surface of the substrate includes: The first current spreading layer is formed on the second semiconductor layer, and the first opening exposes a portion of the second semiconductor layer; The first PN step is formed in the first epitaxial layer.

12. The manufacturing method according to claim 11, wherein, The fabrication of the first LED structure on the first surface of the substrate further includes: The first through hole is formed on the first lower step surface of the first PN step; The second through hole is formed within the first opening.

13. The method for manufacturing an LED chip according to claim 12, wherein, The fabrication of the first LED structure on the first surface of the substrate further includes: A first passivation layer is formed on the first current spreading layer. The first passivation layer covers a portion of the first current spreading layer, the exposed second semiconductor layer, a portion of the first semiconductor layer, the side surface of the first PN step, the first via, and a portion of the inner wall of the second via. The first passivation layer includes a seventh opening, an eighth opening, a ninth opening, and a tenth opening. The first semiconductor layer is exposed through the seventh opening and the eighth opening, and the first current spreading layer is exposed through the ninth opening and the tenth opening.

14. The manufacturing method according to claim 13, wherein, The fabrication of the first LED structure on the first surface of the substrate further includes: A first electrode and a second electrode are formed on the first passivation layer. The first electrode covers the exposed first semiconductor layer and the first passivation layer on the inner wall of the first via. The first electrode is electrically connected to the first semiconductor layer through the seventh opening and the eighth opening. The second electrode covers the exposed first current spreading layer and the first passivation layer on the inner wall of the second via. The second electrode is electrically connected to the first current spreading layer through the ninth opening and the tenth opening.

15. The manufacturing method according to claim 14, wherein, After fabricating the first LED structure on the first surface of the substrate, the fabrication of the second LED structure on the second surface of the substrate further includes: A second passivation layer is formed under the second current spreading layer. The second passivation layer covers a portion of the second current spreading layer, the exposed fourth semiconductor layer, a portion of the third semiconductor layer, the side surface of the second PN step, the first via, and a portion of the inner wall of the second via. The second passivation layer includes an eleventh opening, a twelfth opening, a thirteenth opening, and a fourteenth opening. The third semiconductor layer is exposed through the eleventh opening and the twelfth opening, and the second current spreading layer is exposed through the thirteenth opening and the fourteenth opening.

16. The manufacturing method according to claim 15, wherein, After fabricating the first LED structure on the first surface of the substrate, the fabrication of the second LED structure on the second surface of the substrate further includes: The third electrode and the fourth electrode are formed under the second passivation layer. The third electrode covers the exposed third semiconductor layer and the second passivation layer on the inner wall of the first via. The third electrode is electrically connected to the third semiconductor layer through the eleventh opening and the twelfth opening. The fourth electrode covers the exposed second current spreading layer and the second passivation layer on the inner wall of the second via. The fourth electrode is electrically connected to the second current spreading layer through the thirteenth opening and the fourteenth opening.

17. The manufacturing method according to claim 16, wherein, Before fabricating the second LED structure on the second surface of the substrate, the manufacturing method further includes: A bonding protective layer is formed above the first LED structure; After fabricating the second LED structure on the second surface of the substrate, the manufacturing method further includes: Remove the bonding protective layer above the first LED structure.

18. The manufacturing method according to claim 17, wherein, The substrate includes: a first substrate layer, a perforated area, and a second substrate layer, wherein the perforated area is located between the first substrate layer and the second substrate layer. The manufacturing method further includes, before fabricating the first LED structure on the first surface of the substrate or after fabricating the second LED structure on the second surface of the substrate: A third through hole is formed in the punching area.

19. A lamp, wherein, include: The LED chip according to any one of claims 1 to 8.

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