Pseudo-random logical-physical core assignment at boot time for age averaging

Abstract

A computing device (100) includes a processor (100) having a plurality of cores (111-114), a core translation component (616), and a core assignment component (617). The core translation component provides a set of registers (405), one register for each of the plurality of processor cores. The core assignment component includes a component for providing a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transmitted to the corresponding core based on the core index.

Description

Background Art

[0001] In a conventional processing system having a processor with multiple cores, one core is designated as a default core that is used to implement the boot process of the processing system and remains in an active state to process various tasks, while the other cores of the processor are in a power saving state. This default core assignment is static and permanent across boot processes and state changes. The core that is permanently designated as this default core therefore shares the processor's computational workload unevenly. As a result, the operating life of the default core is reduced relative to the other cores, and once the default core is no longer operational within the minimum specification, the entire processor is typically scrapped or discarded. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] By referring to the accompanying drawings, the present disclosure can be better understood, and its numerous features and advantages will be apparent to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0003] Figure 1 is a block diagram of a computing device having a multi-core processor with a dynamically assigned default core, according to some embodiments.

[0004] Figure 2 is a block diagram of a computing device having a multi-core processor with rotating default core assignments, according to some embodiments.

[0005] Figure 3 is a flow chart illustrating a method for assigning logical cores of a multi-core processor to an operating system, according to some embodiments.

[0006] Figure 4 is a block diagram of a computing device with a multi-core processor, according to some embodiments, where the cores are specified through Advanced Configuration and Power Interface (ACPI) persistent storage.

[0007] Figure 5 is a flow chart illustrating a method for assigning logical cores of a multi-core processor through ACPI persistent memory, according to some embodiments.

[0008] Figure 6 is a block diagram of a computing device with a multi-core processor that specifies core assignments to an operating system, according to some embodiments.

[0009] Figure 7 is a flow chart illustrating a method for causing a multi-core processor to assign cores of the multi-core processor, according to some embodiments.

[0010] Figure 8is a block diagram of a computing device for specifying a core of a multi-core processor via one or more boot components according to some embodiments.

[0011] Fig. 9 is a flow chart illustrating a method for specifying a core of a multi-core processor through a boot loader according to some embodiments. DETAILED DESCRIPTION

[0012] Typically, an operating system (OS) of a computing device logically enumerates the cores of a multi-core processor according to pin numbers, where the core at the first pin position or number is numbered C(0) (or "C0") by the operating system as the default core for handling processes assigned to the processor for execution. This assignment is maintained as long as the operating system remains active, often with weeks or even months between reboots or boots. In addition, when computing demand decreases, one or more cores of the multi-core processor are placed in a power saving state, while the default core C(0) is maintained in an active state (or a more active state) so that at least one core is available to accept a process for execution. Therefore, even when idle, the OS generally tends to favor assigning the execution of a process to the default core C(0). However, between assigning boot tasks, low-level kernel tasks, and user space program processes to the default core C(0), the default core C(0) wears out faster than other cores, especially when the other cores of the processor are frequently set to an idle state or a power saving state. Thus, without evenly distributing the workload across all cores of the processor, the operating life of the processor is reduced as the default core C(0) wears out. Once one core fails or wears out, the processor (and possibly the device implementing the processor) becomes non-operational because processors are generally not designed to operate without all cores of the processor remaining active to accept process tasks from the OS.

[0013] Therefore, according to some embodiments, during the boot process, a computing device implementing a processor having multiple processor cores is configured to non-permanently select one of the multiple cores as the default core for process execution, so that the computing device and the OS do not default to always assigning the same core as the default core. Other cores are assigned based on this selection. The assignment of the default core C(0) is performed according to one of the multiple techniques as further described. Since this selection of a core as the default core is temporary, the computing device is able to dynamically reassign a different core as the default core C(0) at some point after the process is started. Therefore, the responsibility for operating as the default core C(0) is more evenly distributed among the cores of the processor. This more evenly distributes the wear on the cores and thus extends the operating life of the processor.

[0014] Figure 11 is a block diagram of a computing device with a multi-core processor at two different times, according to some embodiments, where core assignments have been reassigned between a first time and a second time. For example, the two times are after two executions of a boot process. Computing device 100 includes motherboard 101 that provides power and support for at least system memory 102 and multi-core processor 110. Processor 110 includes four cores 111-114 arranged adjacent to an L3 cache of memory 115. OS 103 in system memory 102 has become active during the boot process.

[0015] At a first time ("time 1"), a core assignment component 104 operable in the device 100 has assigned or designated the first core in the upper left corner ("core 1") as the default core C(0) to the OS 103 - where the core index is numbered starting from zero. The second core ("core 2") 112 has been assigned as the second core C(1). The third core ("core 3") 113 has been assigned as the third core C(2). The fourth core ("core 4") 114 has been assigned as the fourth core C(3). At a second time ("time 2") before or after the first time, the cores 111-114 have been assigned differently by one or more components of the computing device 100 (such as the core assignment component 104) according to some embodiments. The same physical cores are still in their same physical locations in the processor 110. However, the core assignments have changed. At the second time, the cores 111-114 are respectively designated as C(3), C(2), C(1), and C(0).

[0016] According to some embodiments, the fourth core 114 is randomly selected and designated as the default core C(0), and the remaining cores are designated according to the pin order in the processor 110 encountered during the boot process. Other embodiments assign core names by other methods. For example, according to other embodiments, the third core 113 and the fourth core 114 are randomly selected and designated as the second core C(1) and the default core C(0), respectively, and the remaining cores are designated according to the pin order in the processor 110 encountered during the boot process. In other embodiments, the second, third, and fourth cores 112-114 are randomly selected and designated as the third core C(2), the second core C(1), and the default core C(0), respectively, and the remaining cores are designated according to the pin order in the processor 110 encountered during the boot process. Other examples of embodiments and other illustrative details are provided herein with respect to other figures.

[0017] Regardless of whether the computing device 100 is operating at a first time or a second time, the OS 103 sends process instructions to the cores 111-114 according to the core index. For example, the process instruction passed from the OS 103 to the processor 110 is completed according to the index (e.g., 1 in hexadecimal notation corresponds to the second core 112 or the third core 113) and the hardware identifier (e.g., HID=LNXCPU:00 corresponds to the processor 110). Therefore, when a reference to a process of the OS 103 needs to be passed from the system memory 102 to the processor 110 so that the process instruction can be executed, the mechanism calls the core index. The core index allows the device 100 to deliver the processor instruction to the appropriate core without the OS 103 passing the specific pin number of the processor 110 relative to the motherboard 101. Therefore, the OS 103 can be written, compiled, and operated across various types of processors without changing the operating system for each hardware change across various devices. Various embodiments are now described as examples of how to assign processor core indexes for use by an OS (such as OS 103).

[0018] Figure 2 2 is a block diagram of a computing device 200 having a multi-core processor with a rotating default core assignment according to some embodiments. The computing device 200 includes, for example, a desktop computer, a notebook computer, a server, a tablet computer, a game console, or a mobile phone. The computing device 200 includes a motherboard 201 for operating various hardware elements, including a boot memory 202, a multi-core processor 210, a hard disk drive 220 or other storage device, and a system memory 230. According to some embodiments, the system memory 230 includes a read-only memory (ROM) or a random access memory (RAM).

[0019] Processor 210 includes multiple cores, including a first core 211, a second core 212, a third core 213, and a fourth core 214. These cores include, for example, a central processing unit (CPU) core, a graphics processing unit (GPU) core, or a combination thereof. According to some embodiments, cores 211-214 include their own corresponding memory structures, such as L1 cache memory and L2 cache memory, which are described in detail for ease of description. Figure 2215. The cache memory is not shown in FIG. 216. The cores 211-214 also share an L3 cache memory 215. The cores 211-214 and the associated cache memory form a cluster 216 of cores. The processor 210 may have other core clusters. According to some embodiments, the cores 211-214 are physical cores that can support hyperthreading so that each of the cores 211-214 provides two "cores" or processors to the OS 232 for receiving processor instructions. In this case, the number of cores in the processor 210 will be eight, so as to select the default core C(0). In addition, according to some embodiments, the cores 211-214 may be placed in a low power state or an idle state individually without affecting the power state of other cores. The cluster 216 may also be placed in a lower power or idle state, thereby placing the cores 211-214 in a low power state and allowing the device 200 to assign processes to other available (powered) cores of the processor 210.

[0020] According to some embodiments, the boot memory 202 is implemented as a ROM that stores boot code for execution during the boot process, which is started after a power-on reset on the motherboard. The boot memory 202 includes boot services such as an Advanced Configuration and Power Interface (ACPI) framework 203 and a Basic Input Output System (BIOS) 204. The ACPI framework 203 provides hardware registers to components powered by the motherboard 201 to implement power management and device operations without directly calling each component such as by a hardware address. The ACPI framework 203 serves as an interface layer between the BIOS 204 and the OS 232 of the device 200.

[0021] At a power-on reset or other boot initialization event, power is supplied to the motherboard 201. When the motherboard 201 first receives power, the boot memory 202 is activated and completes its setup, initialization, and self-tests, including the power-on self-test (POST). The BIOS 204 then uses the information obtained during firmware initialization to create or update a table of the ACPI framework 203 having various platform and device configurations, including power interface data. During the boot process, the processor 210 generates core information 205, which provides data about cores 211-214 to the OS 232. Specifically, the core information 205 includes a designation of one of the cores 211-214 as the default core C(0), and in the case where the default core C(0) is so designated, the other cores are listed accordingly as C(1) to C(N-1).

[0022] During the boot process, BIOS 204 identifies all available storage devices for potential boot devices, which may have an OS for device 200. BIOS 204 uses the boot order specified in the permanent storage device available to motherboard 201. On some motherboards, the permanent storage device is a separate chip. In many cases, the BIOS permanent storage device is integrated with a real-time clock (RTC) or with an integrated circuit (IC) on motherboard 201, which is responsible for hard drive controllers, I / O controllers, and integrated components. In some embodiments, the BIOS permanent storage device has its own power supply in the form of a battery, so that even if the motherboard 201 of device 200 loses main power, the BIOS permanent storage device is allowed to save the boot order, core assignment 207, etc.

[0023] BIOS 204 expects the OS to be loaded sequentially into the first sector of each storage device in the boot order. Figure 2 In the present invention, BIOS 204 identifies hard disk drive 220 as a potential boot device. The first magnetic area stores at least one of two items: a master boot record (MBR) 221, or a volume boot record (VBR) if multiple partitions exist in hard disk drive 220. BIOS 204 copies MBR 221 to system memory 230. The copied MBR 231 is configured to point to the active partition 222 where the OS is located. Hard disk drive 220 may include one or more other inactive partitions, such as a second partition 223 where programs and program data may be located.

[0024] The copied MBR 231 includes a boot loader for OS 232. The boot loader includes an executable code that loads OS 232 into system memory 230 and starts OS 232. At this point, BIOS 204 activates the boot loader and stops controlling motherboard 201 and device 200. The boot loader loads and executes various components of OS 232 in system memory 230. During its initialization, OS 232 starts and initializes kernel 233 to allow kernel 233 to provide tasks in the form of processor instructions to processor cores 211-214. Kernel 233 manages the execution of processes on cores 211-214. During initialization, kernel 233 is configured to access cores 211-214 by reference indexes corresponding to core assignment 207. According to some embodiments, core assignment 207 is implemented as a set of registers or a table of ACPI framework 203, and kernel 233 operates according to conventional practices. In other embodiments, the core assignment 207 is provided to the kernel 233 via the boot loader of the MBR 231, and the kernel 233 uses the new core assignment 207 to effectively shift the default core designation of C(0) to one of the second core 212, the third core 213, or the fourth core 214. In other embodiments, the processor 210 provides the core assignment 207 to the boot loader or to the kernel 233 during initialization of the OS 232. According to other embodiments, after the boot process, during operation of the OS 232, periodically or upon demand, the core assignment 207 is updated to a new index value to spread wear among the cores 211-214 during the life of the processor 210. After the reassignment, processes are assigned to the various processor cores 211-214 according to the new core assignments.

[0025] According to some embodiments, when the OS schedules a process to execute at a core 211-214, the OS references the core 211-214 by an affinity mask. The affinity mask is a set of N bytes, one byte for each of the N cores of the processor 210 in the device 200. The core information 205 translates to the OS 232 the physical core 211-214 that actually receives the task or thread of the particular process that is scheduled to execute.

[0026] Figure 3 3 is a flow chart illustrating a method 300 for assigning logical cores to an operating system, according to some embodiments. At block 301, the cores of a processor are enumerated, such as part of a CPU initialization step during a boot or start process. At block 302, core assignments are generated to change the physical enumeration of each core to an assigned enumeration of each core. At block 303, the core assignments are provided to a kernel of an OS, such as Figure 2A kernel 233 of the OS 232 .

[0027] According to some embodiments, core assignment is provided to the OS by making the index available by permanently storing the index in a hardware component of boot memory. An exemplary hardware component is Figure 2 The non-volatile complementary metal oxide semiconductor (CMOS) memory of the boot memory 202 of the CMOS memory. For example, the current set of core indexes are stored in the boot memory 202, and the core indexes are thereby made available to the kernel 233 of the OS 232 in the CMOS memory. As another example, the current set of core indexes are stored in a table, and both the indexes and the table are generated by ACPI machine language (AML) byte codes, which are generated in the CMOS memory as known to those skilled in the art. Figure 2 207. To rotate the core assignments 207 from time to time, as needed, the current set of core indexes is reordered and made available to the kernel 233 of the OS 232. Reordering the core indexes spreads out the core wear so that the cores 211-214 of the multi-core processor 210 wear more evenly over time than might have previously occurred when the OS was operating the device.

[0028] Figure 4 is a block diagram of a computing device with a multi-core processor according to some embodiments, wherein the core is specified through a persistent boot memory, such as an Advanced Configuration and Power Interface (ACPI) persistent memory. Computing device 400 includes a motherboard 401 for operating various hardware elements. For ease of illustration, Figure 4 Some elements of a general purpose processing device are omitted, such as system memory (e.g., ROM) and a hard disk drive. Motherboard 401 operates boot memory 402 and multi-core processor 410. Boot memory 402 includes a permanent boot memory, such as ACPI permanent memory or BIOS CMOS memory. According to some embodiments, processor 410 is a CPU and includes multiple cores, including a first core 411, a second core 412, a third core 413, and a fourth core 414. According to some embodiments, cores 411-414 include their own corresponding memory structures and can share a shared memory (e.g., an L3 cache memory), where for ease of description, in Figure 4 Such memory structures are not shown. Cores 411-414 form core cluster 415. Processor 410 may have other core clusters.

[0029] Boot memory 402 includes ACPI framework 403 and BIOS 404, which allows the OS of computing device 400 to use processor 410 by scheduling processing instructions to be executed on processor 410. ACPI framework 403 includes ACPI persistent memory, which can store values ​​for the operation of components of computing device 400. According to some embodiments, as known to those skilled in the art, ACPI persistent memory takes the form of ACPI tables, a set of ACPI registers, or a set of ACPI registers 405. Processor 410 is declared in the ACPI namespace of ACPI framework 403. In general, ACPI namespace includes ACPI tables for operating components of motherboard 401 (including processor 410). During its initialization, the OS of computing device 400 establishes a namespace for itself according to the ACPI table. The device definition of processor 410 is declared in the OS of computing device 400 using a hardware identifier, which is used by the OS to schedule processes to execute on cores 411-414 of processor 410.

[0030] The OS uses the set of registers 405 to schedule processes on the processor 410. The ACPI framework 403 includes registers for each of the cores 411-414 of the processor 410 in the form of core assignments 407. According to some embodiments, the core assignments 407 correspond to the bus numbers of the cores 411-414 (e.g., 0x4C, 0x10), but for convenience, the core assignments 407 are shown in the following table. Figure 4 As the OS operates and executes a process, the OS kernel schedules the process based on its conventional core index 0 to N-1. The index of the OS scheduler of the OS kernel corresponds to Figure 44. The core index 406 in 406 is shown in FIG. 4 (e.g., an executing process with PID 0123 executes on core (2) of a processor with processor index (0)). However, as part of a configurable interface between the OS and processor 410, core assignment 407 allows scheduled processes to be passed to cores 411-414 according to the contents of register 405, specifically core assignment 407. For example, a process scheduled by the OS to execute at core index (0) at 406 (i.e., default core C(0)) is actually passed to the physical core with index (3) at 407 (i.e., C(3), the fourth core 414). In this way, the first core 411, which was originally and permanently hardwired or configured as the default core C(0) in a conventional system, has been transformed into the fourth core C(3), and processes assigned to execute on the default core C(0) (from the perspective of the OS) are actually sent to C(3). This scheduling is repeated using core assignment 407 until core assignment 407 is regenerated. From the perspective of the OS scheduler, the process is executed on the default core C(0), and in reality, the process is apparently passed to and executed on the fourth core C(3) 414. Thus, the process is passed to the respective core 411-414 corresponding to the index of the core assignment 407, thereby creating a configurable interface between the OS and the processor cores 411-414. Thus, Figure 4 It is illustrated that the configurable core interface is generated by the ACPI framework 403 and is permanently stored in the ACPI framework 403 .

[0031] According to some embodiments, the assignment 407 is performed during the boot process by executing a generic event of ACPI 403, as is known in the art. According to one illustrative embodiment, the core assignment 407 corresponding to each of the physical core indexes 406 (0-3) is generated by using a core arrangement table 408 in which each row corresponds to one of the N factorial number of permutations of the N number of cores in the processor 410. For example, Figure 4 The indexes shown in core assignment 407 are "3", "2", "0", and "1" for physical core 406, which correspond to indexes "0", "1", "2", and "3" for cores 411-414. A new core assignment 407 is generated each time device 400 is restarted or each time ACPI framework 403 is initialized or modified.

[0032] As an example, during the boot process, a row index 409 is obtained, such as from a permanent memory register 405. The row index 409 corresponds to a row in a core permutation table 408. The permutation table 408 includes a series of rows, one row for each permutation of the indexes of the cores 411-414. According to one embodiment, the permutation table 408 is an ACPI table permanently stored in the boot memory 402 even if power is no longer provided to the motherboard 401. According to another embodiment, the permutation table 408 is generated whenever the motherboard 401 of the device 400 is booted, wherein the permutation table 408 is generated based on the answer to a query of the number of cores in the request processor 410. During the boot process, the query is executed as AML byte code. The row index 409 is permanently stored from boot to boot. During any given boot process, the row index 409 is incremented by one, and then the core assignment 407 is generated by referencing the row corresponding to the new row index 409 in the permutation table 408. As another exemplary implementation, row index 409 is selected based on a random or pseudo-random algorithm operable as AML byte code in ACPI framework 403. In this manner, each of cores 411-414 receives a process for execution based on its corresponding core assignment 407.

[0033] Other mechanisms are possible for generating core assignments 407. As another example of a mechanism for generating core assignments 407, a random number generator algorithm that is programmed, compiled, and executed as AML byte code during the boot process assigns each of core assignments 407 until all assignments are completed, one for each of cores 411-414 of processor 410.

[0034] Figure 5 1 is a flowchart illustrating a method 500 for assigning logical cores of a multi-core processor through ACPI persistent memory according to some embodiments. At box 501, the cores of the processor are enumerated. Enumeration includes identifying the number of cores in the processor or in all processors in the computing device. According to other embodiments, enumeration includes obtaining an identifier, address, bus address, or bus number of each of the cores, and the operating system sends the process to the core for execution. The core can be made available by supporting hyperthreading at the physical core, thereby allowing processor instructions to be executed at two or more cores or "processors" at each physical core. According to some embodiments, enumeration is performed by AML byte code provided for this function. According to other embodiments, enumeration is performed by a BIOS function programmed and compiled into the BIOS for this purpose.

[0035] At block 502, core assignments are generated for the listed cores. According to some embodiments, one of a plurality of rows of an assignment table is accessed and a new core index number is provided to each of the listed cores. For example, for a quad-core processor where the cores are physically numbered 0, 1, 2, and 3, each of the four cores has a new index number. Figure 4 As shown at 407 in FIG. 1 , an example of a new core index number is: "3" for the first physical core 411, "2" for the second physical core 412, "0" for the third physical core 413, and "1" for the fourth physical core 414. According to some embodiments, core assignment is performed by an AML byte code provided for this function. According to other embodiments, core assignment is performed by a BIOS function programmed and compiled into the BIOS for this purpose.

[0036] At block 503, method 500 includes permanently storing the core assignments for use in passing processes to processor cores. For example, the permanent storage includes storing an address (e.g., bus address, bus number) or identifier of each of the processor cores in a permanent boot memory (such as a Figure 4 The stored row index is used to point to identify the core assignments for each of the respective cores of the processor. According to some embodiments, permanently storing the core assignments is performed by AML byte code provided for this function. According to other embodiments, permanently storing the core assignments is performed by a BIOS function programmed and compiled into the BIOS for this purpose.

[0037] Figure 6 600 is a block diagram of a computing device with a multi-core processor that specifies core assignments to an operating system according to some embodiments. Computing device 600 includes motherboard 601 for operating various hardware elements. Figure 6 Some elements of a general purpose processing device are omitted, such as system memory (e.g., ROM) and a hard disk drive. Motherboard 601 operates boot memory 602 and multi-core processor 610. Boot memory 602 includes a permanent boot memory, such as an ACPI permanent memory or a BIOS CMOS memory. Boot memory 602 includes an ACPI framework 603 and BIOS 604, which allows the OS of computing device 600 to use processor 610. ACPI framework 603 includes an ACPI permanent memory, which can store values ​​for the operation of components of computing device 600.

[0038] According to some embodiments, processor 610 is a CPU and includes multiple cores, including a first core 611, a second core 612, a third core 613, and a fourth core 614. One of cores 611-614 is designated as a default core C(0). Cores 611-614 include their own respective memory structures and may share a shared memory (e.g., an L3 cache memory), wherein for ease of illustration, in Figure 6 Such memory structures are not shown in FIG. Cores 611-614 form a first cluster of cores 620. Processor 610 may have other clusters of cores.

[0039] The processor 610 also includes a core translation component 615 and a core translation component 616. These modules 615, 616 are designed and operated according to one of a plurality of core assignment schemes. Two core assignment schemes are described herein as examples of a plurality of schemes for the structural components of the processor 610. The components shuffle the names of the cores 611-614 of the processor 610, and the components provide interfaces to allow the cores to interoperate with other components of the device 600 (including the OS).

[0040] According to some embodiments, and as an exemplary approach, during a processor configuration or initialization process (e.g., during a boot process), the core translation component 615 uses the core assignment component 617 to configure the core translation component 616 by providing a core index 618 (e.g., in the form of a core index, a core address, or a bus number) to the core translation component 616. After the boot process, during operation of the computing device 600, the OS routes process instructions by referencing the same set of bus numbers of the processor 610 as in a conventional scheduling mechanism, as if no bus number change occurred at the bus of the processor 610. The OS and the ACPI framework 603 interoperate in a conventional manner. However, based on the core assignment component 617 that is operable during the boot process inside the processor 610, the process instructions from the OS are routed to the cores 611-614 based on the index 618 of the core translation component 616. The processor 610 routes instructions to the cores 611-614 internally via the core translation component 616 according to a specific core indexing scheme represented as the core index 618. Each time the processor 610 is initialized, the order or sequence of these core indexes 618 changes. For example, the first process scheduled to execute on the default core C(0) is actually delivered to the core addressed at the first core index 618, which is in Figure 6610 is "3". This process is repeated for each process passed to processor 610 for execution at one of cores 611-614. From the perspective of the OS, nothing has changed because the process instructions are executed at one of the cores 611-614 of processor 610 and the results are returned to operating memory and the OS. From the perspective of processor 610, processor instructions are spread to the various cores 611-614 in a more even manner over the life of processor 610.

[0041] According to some embodiments, the processor 610 or the core translation component 615 of the processor 610 includes a pseudo-random number generator (PRNG) 619 or a component for implementing core index number generation. The core translation component 615 can call or activate PRNG 619 to provide an index value to be placed in each register, thereby providing an index 618 according to a pseudo-random scheme. A core assignment component 617 can be provided to check to ensure that an illegal index 618 is not provided (for example, when only 0-3 is possible for the four cores 611-614 of the processor 610, a value of "5"). Optionally, the core translation component 615 can call or activate PRNG 619 to select which register is designated as the default core C (0). Subsequently, the address or core bus number is provided to the specific register in the processor 610. This process can be repeated until all cores 611-614 have been assigned indexes 618.

[0042] Optionally, once the C(0) register is identified and filled, the other registers may be filled in order without regard to any randomness, such that C(0) is at least pseudo-randomly selected for processor 610. According to some embodiments, motherboard 601 includes a real-time clock (RTC) operating therein, and PRNG 619 communicates with the RTC when providing core index 618 to registers of the core translation component, PRNG 619 basing its operation on the value of the RTC. According to such embodiments, PRNG 619 uses the RTC to obtain entropy for assigning at least the C(0) name to a register corresponding to one of cores 611-614.

[0043] According to a variation of this exemplary scheme, during the processor configuration process, the core translation component 615 uses the core assignment component 617 to configure the registers of the core translation component 616 according to a polling scheme. As used herein, during the processor initialization step of the boot sequence, the polling scheme shifts the core index of each core by one position. The position is shifted each time the device operating the processor undergoes a boot process or each time the processor 610 detects a reassignment signal at the bus of the processor 610.

[0044] As an example of operation, when the processor 610 detects a reassignment signal, the core assignment component 617 pseudo-randomly selects a first register and a second register in the set of registers that hold index 618. The core assignment component 617 then switches the index 618 of the first selected register and the second selected register. The reassignment signal may be sent by a scheduler of a kernel of an OS functioning in the device 600 after exceeding a predetermined core wear target time, which is specified by the manufacturer or OS programmer based on typical life estimates of the cores 611-614. For example, the core wear target time may be predetermined and may be set to operate for a few hours or days under a particular core assignment configuration.

[0045] According to other embodiments, and as another exemplary approach, during a processor configuration or initialization process (e.g., during a boot process), the core translation component 615 uses the core assignment component 617 to configure the ACPI registers or ACPI tables (corresponding to the cores 611-614 of the processor 610) of the ACPI framework 603 by providing a core index 618 (e.g., in the form of a core index, a core address, or a bus number) to the ACPI framework 603. According to some embodiments, the core index 618 corresponds to the bus number (e.g., 0x4C, 0x10) of the core 611-614. As an example of an implementation, the core translation component 615 reads the core index 618 from the core translation component 616 and passes the index 618 to the ACPI framework 603. According to another exemplary implementation, the core translation component 616 includes an arranged table of sets of core indexes 618 or values ​​that can be used in subsequent configuration or initialization steps. During an initialization step in processor 610 , core translation component 615 randomly selects a row from the arranged table of the set of core indexes 618 and passes the index 618 to ACPI framework 603 via core assignment component 617 .

[0046] In operation, according to the second exemplary scheme, process instructions are routed from the OS via information provided to the ACPI framework 603 by the core translation component 615. The scheduler and kernel of the OS of the computing device 600 operate using conventional core calls and core dispatches, but instructions are routed to one of the various cores 611-614 indicated by core index 618 rather than by hardwired names as in conventional operation. For example, a first process scheduled to execute on C(0) is actually passed to the core whose address is at the first index in Figure 6is "3" in . This method is repeated for each process passed to processor 610 for execution. In this way, the first core 611, which is permanently hardwired or configured as C(0) in a conventional system, is transformed into C(3), and processes assigned to execute on C(0) are actually sent to C(3).

[0047] This scheduling scheme is repeated using core assignments 607 until core assignments 607 are regenerated from time to time. Core reassignment is performed at each restart or from time to time as needed based on a schedule or trigger by the OS or by some other component or combination of components in the computer device 600. In brief, as with respect to Figure 6 As illustrated, from the perspective of the OS scheduler, each process is executed on one of C(0), C(1), C(2), and C(3), and in reality, each process is explicitly passed to and executed on the core specified by core index 618. Core index 618, core translation component 616, and core translation component 615 are part of the configurable interface between the OS and processor cores 611-614. Figure 6 The configurable core interface may exist between the OS and the cores 611-614 of the processor 610. From the perspective of the OS, nothing has changed because the process instructions are successfully executed and the results are returned to the memory for access by the OS. From the perspective of the processor 610, the processor instructions are spread to the various cores 611-614 in a more even manner over the life of the processor 610.

[0048] According to another embodiment, as another exemplary scheme, during a processor configuration or initialization process (e.g., during a boot process), a core translation component of a first processor (e.g., an ARM processor) provides a first core assignment, and provides its core assignment output to a second processor, such as Figure 6Processor 610. In this embodiment, the second processor is a processor type that is the same or different from the first processor, such as a second processor configured to use a different instruction set (e.g., an x86 instruction set). In this embodiment, during the first or earlier execution of the BIOS sequence, the first processor is instructed to use the core translation component of the first processor and use the core of the first processor according to the translation scheme until the first processor is no longer needed or the first processor is no longer in use. Afterwards, during the second or later execution of the BIOS sequence, the BIOS operable in the memory or the first processor instructs the first processor to use its core translation component and provide the second or another core assignment to the second processor--the second core reassignment. The second processor includes a storage register for receiving and saving its new core assignment (e.g., in the form of a core index, a core address, or a bus number). Optionally, the first processor provides the new core assignment to the operating system (OS) of the second processor. In this way, the core of the second processor is renumbered so that the OS assigns the process to the core of the second processor.

[0049] Figure 7 701. A core reassignment scheme is created. The reassignment scheme uses the number of cores in the processor or in all processors in the computing device to randomly or pseudo-randomly provide new index numbers to each of the available cores. This scheme can be described as a pseudo-random assignment scheme. This scheme may include obtaining an identifier, address, bus address, or bus number for each of the cores to which the operating system sends a process for execution. According to some embodiments, this reassignment scheme is performed by a portion of the processor (such as in Figure 6 According to some embodiments, the core is a core of a multi-core CPU or a multi-core GPU, and the reassignment scheme is applied to each multi-core processor in the device.

[0050] At block 702, the core reassignment plan created at block 701 is permanently stored. The storage may take the form of passing an address, such as a bus address, to another element in the computing device, such as boot memory, a memory structure of an ACPI framework, or system RAM.

[0051] At block 703, the process instructions for execution on the cores of the processor are delivered to one of the corresponding cores based on the reassignment scheme. For example, as shown at 618, a process scheduled and delivered to core C(0) is actually sent to C(3), or to the core to which C(0) is reassigned.

[0052] Figure 8 800 is a block diagram of a computing device for specifying a core of a multi-core processor through one or more boot components according to some embodiments. The computing device 800 includes a motherboard 801 for operating various hardware elements. The motherboard 801 operates various components, including a boot memory 802, a storage memory such as a hard drive 808, a multi-core processor 810, and a system memory 820. The hard drive 808 includes an active partition 809 having instructions therein.

[0053] According to some embodiments, the processor 810 includes a plurality of cores, including a first core 811, a second core 812, a third core 813, and a fourth core 814. The cores 811-814 include their own respective memory structures and share a shared memory (e.g., an L3 cache memory), wherein for ease of description, the cores 811-814 are described in detail in the following sections. Figure 8 Such memory structures are not depicted in FIG. Cores 811-814 form a first cluster 815 of cores. Processor 810 may have other clusters of cores, and cores in any other clusters of the same or different sockets are treated similarly to those in first cluster 815.

[0054] The boot memory 802 includes an ACPI framework 803 and a BIOS 804, which allows the OS of the computing device 800 to provide processes to the cores 811-814 of the processor 810 for execution thereon. The ACPI framework 803 includes an ACPI memory within the boot memory 802 or as part of the boot memory. The ACPI memory stores values ​​for the operation of components of the computing device 800. According to some embodiments, as known to those skilled in the art, the ACPI memory takes the form of an ACPI table, a set of ACPI registers, or a set of ACPI registers. During the boot process, the processor 810 is declared in the ACPI namespace of the ACPI framework 803. The ACPI namespace includes ACPI tables for operating components of the motherboard 801 (including the processor 810 and its cores 811-814). During its initialization, the OS of the computing device 800 establishes a namespace for itself according to the ACPI table. The device definition of the processor 810 is declared in the OS of the computing device 800 using a hardware identifier, and the OS uses the hardware identifier to schedule processes to execute on the cores 811-814 of the processor 810.

[0055] The OS uses the information in the set of ACPI registers to schedule processes on the cores 811-814 of the processor 810. The ACPI framework 803 includes registers for each of the cores 811-814 of the processor 810 in the form of core assignments 807. According to some embodiments, the core assignments 807 correspond to the bus numbers of the cores 811-814 (e.g., 0x4C, 0x10), but are not shown for convenience. Figure 8 822 is represented as an index because the bus number varies according to the architecture and layout of the components of the processor 810. When the OS 822 operates and executes a process, the kernel 823 of the OS 822 schedules the process based on its conventional core index 0 to N-1. The index of the OS scheduler of the kernel 823 corresponds to Figure 8 806 in the core index 806 in (e.g., the executing process with PID 0123 executes on core (2) of the processor with processor index (0)). However, as part of the configurable interface between the OS and processor 810, core assignment 807 allows scheduled processes to be delivered to cores 811-814 according to core assignment 807 and not according to conventional core numbers and static bus numbers.

[0056] For example, a process scheduled to execute at core index (0) at 806 (i.e., the default core C(0)) is actually passed to the core with index (3) at 807 (i.e., the fourth core 414C(3)). In this way, the first core 811 that was initially and permanently hardwired or configured as the default core C(0) in a conventional system has been transformed into the fourth core C(3), and the process assigned to execute on the first core 811 is actually sent to the fourth core 814. This scheduling is repeated using all corresponding core assignments 807 until the core assignments 807 are regenerated. From the perspective of the OS scheduler, the process is executing on the default core C(0), and in fact, the process is apparently passed to the fourth core 814 or C(3) and executed on the fourth core. Therefore, the process is passed to the corresponding core 811-814 corresponding to the index of the core assignment 807, thereby creating a configurable interface between the OS and the processor cores 811-814. In short, Figure 8 It is described that the configurable core interface is permanently stored in ACPI 803.

[0057] According to some embodiments, core assignment 807 is performed by a boot component during execution of a master boot record (MBR) 821 during the boot process. Certain BIOS instructions are executed from boot memory 802 before executing MBR 821. BIOS 804 eventually activates the boot loader of MBR 821, and BIOS 804 stops directly controlling motherboard 801 and device 800. MBR 821 includes a boot loader for OS 822. The boot loader executes a boot thread (e.g., thread (0) in core (0) of processor (0)), which starts retrieval code. The retrieval code pulls additional instructions from the first magnetic sector of the active partition 809 of the hard disk drive 808 starting from a specific address. The additional instructions include instructions for performing core assignment 807. The additional instructions also include instructions for loading the OS into system memory 820 and initializing OS 822 after core assignment has been performed.

[0058] Thus, according to some embodiments, core assignment 807 is performed prior to loading a portion or all of OS 822 and operating the OS. Once initialized, the boot loader's instructions start OS 822 by placing OS 822 in certain conditions to execute user-defined instructions on computing device 800. During its initialization, OS 822 starts and initializes kernel 823. Kernel 823 uses core assignment 807 to provide process instructions to processor cores 811-814.

[0059] At once Figure 8 For example, core assignments 807 are generated by instructions of ACPI 803, instructions of a boot loader, instructions of MBR 821, instructions of OS 822, or a combination thereof. According to one illustrative embodiment, core assignments 807 are provided by instructions triggered by execution of instructions of a boot loader after BIOS 804 stops controlling motherboard 801. According to some embodiments, instructions operable in system memory 820 read physical core addresses (e.g., bus numbers) from ACPI registers of an ACPI framework 803 in boot memory 802, as represented by core indexes 806. The instructions determine a set of core assignments 807 according to one of a plurality of available assignment schemes, one core assignment for each of the physical cores 811-814 indicated as core indexes 806 in registers 805. As shown in FIG. Figure 8 As shown in , register 805 is in system memory 820 as part of MBR 821. Subsequent instructions use the information in register 805 to generate core assignments.

[0060] The instructions for determining the core assignment 807 take one of a variety of forms. For example, the instructions utilize a core arrangement table, where each row corresponds to one of the N factorial number arrangements of the N number of cores in the processor 810. The number of cores can be determined by the instructions of the MBR 821 or the boot loader of the MBR 821 during the boot process by reading one or more registers of the ACPI framework 803 during the boot process. As another example, the instructions of the MBR 821 include a random number generator algorithm that is called to perform some or all of the core assignments 807. According to a first variant, a first random or pseudo-random assignment is made for the default core C(0) among the available cores 811-814. Subsequently, each of the other cores is sequentially assigned in bus order to perform the remaining core assignments 807. According to a second variant for performing the core assignment 807, each of the cores (C(0) to C(3)) is randomly or pseudo-randomly assigned. The instructions for making the core assignment 807 include persisting or otherwise making the assignment 807 available to the kernel 823 of the OS 822. One mechanism for doing so includes executing instructions to write or rewrite one or more ACPI entries in certain registers of the ACPI framework 803 or one or more corresponding ACPI tables. According to some embodiments, the MBR 821 includes instructions for persisting the core assignment 807.

[0061] Fig. 9 The invention discloses a method 900 for specifying the core of a multi-core processor by a boot loader instruction, a master boot record instruction, a kernel instruction, an OS instruction, or a combination thereof according to some embodiments. At box 901, an instruction in a system memory reads a core address of a processor from a boot memory. For example, the boot loader instruction reads a bus number from a set of ACPI registers corresponding to a set of cores of a multi-core processor. At box 902, a core assignment is performed for each core in the set of cores of the multi-core processor. The core assignment is performed according to one of the various methods described with respect to other figures. At box 903, based on the core assignment, the core address is written to a memory, such as to a boot memory. The newly generated core assignment is then used by a scheduler of a kernel of an operating system when a process is scheduled for execution. According to some embodiments, the use of this method 900 allows an operating system to execute processes in a conventional manner without substantially changing the configuration, programming, or execution of the operating system, and extends the life of a multi-core processor by rotating at least a default core C(0) as a first core name to the core of the multi-core processor over the life of the multi-core processor so that all cores age approximately the same.

[0062] In some embodiments, the apparatus and techniques described above are implemented in a device or system (such as described above with reference to FIG. 1 ) that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips). Figures 1 to 9 The multi-core processor described in the specification and the invention is implemented in the electronic design automation (EDA) and computer-aided design (CAD) software tools can be used for the design and manufacture of these IC devices. These design tools are usually represented as one or more software programs. The one or more software programs include codes, which can be executed by a computer system to manipulate the computer system to operate the code representing the circuit of one or more IC devices, so as to perform at least a part of the process for designing or adapting the manufacturing system to manufacture the circuit. This code may include instructions, data, or a combination of instructions and data. Software instructions representing design tools or manufacturing tools are usually stored in a computer-readable storage medium that can be accessed by a computing system. Similarly, codes representing one or more stages of the design or manufacture of IC devices can be stored in the same computer-readable storage medium or different computer-readable storage media, and accessed from the same computer-readable storage medium or different computer-readable storage media.

[0063] Computer-readable storage media may include any non-transitory storage media or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache memory), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical system (MEMS)-based storage media. The computer-readable storage media may be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disc or flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage (NAS)).

[0064] In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system that executes software. The software includes one or more executable instruction sets stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that manipulate the one or more processors to perform one or more aspects of the above-mentioned techniques when executed by one or more processors. A non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device (such as a flash memory), a cache memory, a random access memory (RAM), or one or more other non-volatile memory devices, etc. The executable instructions stored on a non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats interpreted or otherwise executed by one or more processors.

[0065] It should be noted that not all activities or elements described above in the general description are required, a portion of a particular activity or device may not be required, and one or more other activities may be performed, or elements other than those described may be included. In addition, the order in which the activities are listed is not necessarily the order in which the activities are performed. In addition, concepts have been described with reference to specific embodiments. However, it will be appreciated by those of ordinary skill in the art that various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the appended claims. Therefore, this specification and the accompanying drawings will be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0066] The benefits, other advantages, and problem solutions have been described above with respect to specific embodiments. However, the benefits, advantages, problem solutions, and any features that may make any benefit, advantage, or problem solution appear or become more prominent should not be interpreted as being key, essential, or necessary features of any or all claims. In addition, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter may be modified and practiced in different but equivalent ways that are obvious to those skilled in the art who understand the teachings of this article. Except as described in the appended claims, it is not intended to limit the details of the construction or design shown herein. Therefore, it is obvious that the specific embodiments disclosed above may be changed or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A processor, comprising: a plurality of processor cores accessible based on a plurality of changeable core indexes; a core translation component having a set of registers, wherein each register is associated with a corresponding processor core of the plurality of processor cores; as well as A core assignment component, the core assignment component being configured to: When the processor is powered on during a boot process, a core index of the plurality of changeable core indexes is assigned to each of the set of registers of the core translation component according to a core assignment scheme during processor initialization, the core assignment component being configured to route processor instructions to corresponding processor cores based on the corresponding assigned core indexes, wherein: A processor core of the plurality of processor cores is randomly or pseudo-randomly assigned from among the plurality of processor cores of the processor as a default core for execution of a process by the processor; as well as When remaining processor cores of the plurality of processor cores become active during the boot process, the remaining processor cores are assigned to the set of registers based on a bus order in the processor during the boot process.

2. The processor of claim 1, wherein each core index provided to a corresponding register of the set of registers is a bus number of a corresponding core of the plurality of processor cores.

3. A processor as claimed in any one of claims 1 to 2, wherein: At least two of the processor cores are coupled as a core cluster; and The core assignment scheme provides respective core indexes for the at least two of the processor cores of the core clusters based on the cluster coupling, such that only the core indexes of the clusters are reordered relative to each other.

4. The processor of claim 1, wherein: The core assignment component includes a pseudo-random number generator (PRNG) based on operation of a real time clock operatively associated with a motherboard supporting the processor to provide the plurality of changeable core indexes to the set of registers of the core translation component.

5. The processor of claim 4, wherein the pseudo-random number generator communicates with a motherboard having a real-time clock (RTC) when providing the plurality of changeable core indexes to the set of registers of the core translation component.

6. The processor of claim 1 , wherein the core assignment component is configured to: A row of an order permutation table of the processor cores in the plurality of processor cores is identified, wherein the row of the table is the core assignment scheme for the default core that is randomly or pseudo-randomly assigned.

7. A processor, comprising: Multiple processor cores; a first register for a default processor core among the plurality of processor cores; and Core designation components, which are used to: pseudo-randomly or randomly assigning a bus number of a processor core among the plurality of processor cores to the first register during a boot process, the first register being designated as the default processor core of the processor for scheduling execution of a process by the processor through a scheduler of an operating system; When the remaining processor cores become active through the boot process, based on the bus order in the processor during the boot process, the bus numbers of the remaining processor cores are assigned to a scheduler of an operating system that provides processor instructions to the processor, wherein the processor routes the processor instructions to the multiple processor cores based on the assigned bus numbers.

8. The processor of claim 7, wherein: The pseudo-random or randomly assigned bus number of the processor core is provided based on a real time clock (RTC) value obtained by the processor during the boot process.

9. The processor of claim 7, wherein the core assignment component is further configured to: detecting a reassignment signal at a bus of the processor; pseudo-randomly or randomly selecting the first register of a set of registers in response to detecting the reassignment signal; pseudo-randomly or randomly selecting a second register of the set of registers in response to detecting the reassignment signal; switching the bus number of the first selected register to the second selected register after selecting the first register and the second register; and The bus number of the second selected register is switched to the first selected register after the first register and the second register are selected.

10. The processor of claim 9, wherein the reassignment signal is generated by the scheduler of the operating system that provides the processor instructions to the processor, wherein the reassignment signal is sent after a predetermined core wear target time.

11. A method comprising: A core index is assigned to each of the plurality of cores of the processor according to a core assignment scheme in the following manner: randomly or pseudo-randomly assigning a core from the plurality of cores of the processor as a default core for execution of a process by the processor; as well as when remaining processor cores of the plurality of cores become active during a boot process, assigning the remaining processor cores based on a bus order among the processors during the boot process; as well as Processor instructions with core bus numbers received at the processor are routed from an operating system to corresponding cores in the processor based on the assigned core indexes of the cores in the processor.

12. The method of claim 11, wherein the core assignment scheme is a round-robin scheme whereby the default core is shifted by one core during processor initialization of the boot process.

13. The method of claim 11, wherein each core index is a bus number of another core.

14. The method of any one of claims 11 to 13, wherein: At least two of the cores in the plurality of cores are coupled as a core cluster; and The core assignment scheme provides respective core indexes for the at least two of the cores of the cluster based on the cluster coupling, such that only the core indexes of the at least two of the cores of the cluster are reordered relative to each other.

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