Organic Light-Emitting Diode Display

Abstract

An organic light emitting diode display according to an exemplary embodiment is provided. The organic light emitting diode display includes: data wirings including data lines disposed in a display area and first data lines disposed in a peripheral area; driving voltage wirings including driving voltage lines disposed in the display area and first driving voltage lines disposed in the peripheral area and extending in a first direction; and driving low voltage wirings including a cathode covering the display area and formed to the peripheral area and a first driving low voltage connection part connected to the cathode and disposed in the peripheral area, wherein the first driving low voltage connection part includes a first part and a second part having a different width compared to the first part.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0002678, filed with the Korean Intellectual Property Office on January 9, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to an organic light emitting diode display, and more particularly, to a voltage line applied to a pixel of an organic light emitting diode display. Background Art

[0003] A display device is a device that displays an image. Recently, organic light emitting diode displays have received attention.

[0004] Unlike a liquid crystal display device, an organic light emitting diode display has a self-emission characteristic and does not require a separate light source, and thus it is possible to reduce the thickness and weight of the organic light emitting diode display. In addition, the organic light emitting diode display has high-quality characteristics such as low power consumption, high brightness, and high response speed.

[0005] An organic light emitting diode (OLED) display has a complex pixel structure compared to a liquid crystal display device, and many wirings are connected to each pixel, so that the wiring structure in the peripheral region surrounding the display region is relatively complex.

[0006] The above information disclosed in this background art section is only for enhancing the understanding of the background of the invention, and thus it may include information that does not constitute the prior art already known to those of ordinary skill in the art in this country. Summary of the Invention

[0007] Exemplary embodiments are intended to have the same or smaller parasitic capacitance compared to the prior art, which occurs when a plurality of signal lines provided in a fan-out region overlap with a wiring for applying a driving low voltage ELVSS or a driving voltage ELVDD. In addition, the exemplary embodiments are intended to minimize the voltage drop of the driving voltage ELVDD and the driving low voltage ELVSS.

[0008] An organic light emitting diode display according to an exemplary embodiment includes: data wirings including data lines provided in a display region and first data lines provided in a peripheral region; driving voltage wirings including driving voltage lines provided in the display region and first driving voltage lines provided in the peripheral region and extending in a first direction; and driving low voltage wirings including a cathode covering the display region and formed to the peripheral region and a first driving low voltage connection portion connected to the cathode and provided in the peripheral region, wherein the first driving low voltage connection portion includes a first portion and a second portion having a different width compared to the first portion.

[0009] The first driving low-voltage connection part may include a wiring part and pad parts provided on both sides thereof, and the wiring part includes parts having the different widths.

[0010] The wiring part of the first driving low-voltage connection part may have a triangular shape.

[0011] The wiring part of the first driving low-voltage connection part may include a first part having a first thickness and a second part having a second thickness.

[0012] It may further include a first additional metal layer provided in the peripheral area and stacked with the first driving low-voltage connection part, and the first additional metal layer may be electrically connected to the first driving low-voltage connection part.

[0013] The first additional metal layer may be provided under the semiconductor layer.

[0014] The first driving voltage line may further include a pad part electrically connected to one side.

[0015] The first driving voltage line and the driving voltage line may be formed on the same layer.

[0016] It may further include a second additional metal layer provided in the peripheral area and stacked with the first driving voltage line, and the second additional metal layer may be electrically connected to the first driving voltage line.

[0017] The second additional metal layer may be provided under the semiconductor layer.

[0018] The first data line may be formed in the gate conductive layer.

[0019] An organic light-emitting diode display according to an exemplary embodiment includes: data wirings including data lines provided in a display area and first data lines provided in a peripheral area; driving voltage wirings including driving voltage lines provided in the display area and first driving voltage lines provided in the peripheral area and including connection parts extending in a first direction; and driving low-voltage wirings including cathodes provided in the display area and first driving low-voltage connection parts connected to the cathodes and provided in the peripheral area, wherein at least one of the first driving voltage line and the first driving low-voltage connection part is connected to an additional metal layer, and the additional metal layer is provided in the peripheral area and has a lower resistance than at least one of the first driving voltage line and the first driving low-voltage connection part connected to the additional metal layer.

[0020] The additional metal layer connected to the first driving low-voltage connection part may be the first additional metal layer, and the first additional metal layer may include parts having different widths.

[0021] The first additional metal layer may have a triangular shape.

[0022] The first additional metal layer may include a first portion having a first thickness and a second portion having a second thickness.

[0023] The first driving low voltage connection portion may include pad portions disposed on both sides thereof.

[0024] The connection portion of the first driving low voltage connection portion may have a straight shape.

[0025] The first driving voltage line may have a pad portion extending in a first direction and electrically connected thereto.

[0026] The first driving voltage line and the driving voltage line may be formed on the same layer.

[0027] The first data line may be formed in the gate conductive layer.

[0028] An organic light emitting diode display according to an exemplary embodiment includes: data wirings including a first data line and a second data line disposed in a peripheral area, wherein the first data line is longer than the second data line; driving voltage wirings including a driving voltage line disposed in a display area and a first driving voltage line disposed in the peripheral area and extending in a first direction; and driving low voltage wirings including a cathode covering the display area and formed to the peripheral area and a first driving low voltage connection portion connected to the cathode and disposed in the peripheral area, wherein a first portion of the first driving low voltage connection portion that overlaps with the first data line is smaller than a second portion of the first driving low voltage connection portion that overlaps with the second data line.

[0029] In some examples, in the above organic light emitting diode display, by making the first portion of the first driving low voltage connection portion smaller than the second portion of the first driving low voltage connection portion, the parasitic capacitance of the first data line is made substantially equal to the parasitic capacitance of the second data line.

[0030] According to an exemplary embodiment, when a plurality of signal lines disposed in a fan-out area overlap wirings to which a driving low voltage (ELVSS) or a driving voltage (ELVDD) is applied, the parasitic capacitance generated is the same as or smaller than that in the prior art. In addition, when the driving voltage ELVDD and the driving low voltage ELVSS are applied, a relatively low voltage drop may occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a layout diagram of an organic light emitting diode display according to an exemplary embodiment.

[0032] Figure 2 is an enlarged view of a peripheral area of an organic light emitting diode display according to an exemplary embodiment.

[0033] Figure 3is a cross-sectional view taken along line III-III of Figure 2 .

[0034] Figure 4 is an enlarged view of a peripheral region of an organic light emitting diode display according to an exemplary embodiment.

[0035] Figure 5 is a cross-sectional view taken along lines V-V', V'-V'' and V-V''' of Figure 4 .

[0036] Figure 6 and Figure 7 are enlarged views of a peripheral region of an organic light emitting diode display according to an exemplary embodiment.

[0037] Figure 8 is a circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0038] Figure 9 and Figure 10 are cross-sectional views of a pixel of an organic light emitting diode display according to an exemplary embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, the present invention will be described more fully with reference to the accompanying drawings in which exemplary embodiments of the invention are shown. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention.

[0040] Descriptions of components irrelevant to the present invention are omitted, and throughout the specification, like reference numerals denote like elements.

[0041] In addition, since the dimensions and thicknesses of the constituent elements shown in the drawings are arbitrarily given for better understanding and ease of description, the present invention is not limited to the illustrated dimensions and thicknesses. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0042] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, no intervening elements are present. Further, in the specification, the words "on" or "above" mean being located on or under the target part, and do not necessarily mean being located on the upper side of the target part based on the direction of gravity.

[0043] Additionally, unless there is an express contrary description, the word "comprising" and its variants will be understood to mean including the stated elements, without excluding any other elements.

[0044] Furthermore, in the specification, the phrase "in a plane" means viewing the target portion from the top, and the phrase "in a cross-section" means viewing the cross-section of the target portion vertically cut from the side.

[0045] Now, refer to Figure 1 the structure of the organic light-emitting diode display is described.

[0046] Figure 1 is a layout diagram of an organic light-emitting diode display according to an exemplary embodiment.

[0047] The organic light-emitting diode display according to the present exemplary embodiment includes a display panel 100 in which pixels PX are formed, a printed circuit board (PCB) 300 in which voltage application units 310 and 320 are formed, and a flexible printed circuit substrate 200 that connects the display panel 100 and the printed circuit board (PCB) 300 and in which a driving chip 250 is formed.

[0048] The display panel 100 includes a display area 110 in which pixels PX are formed to display an image and a peripheral area 120 that surrounds the display area 110 and includes a fan-out area.

[0049] A data line 171 to which a data voltage is applied, a driving voltage line 181 to which a driving voltage ELVDD is applied, and a driving low voltage line 182 to which a driving low voltage ELVSS is applied are connected to the pixels PX formed in the display area 110. Here, the driving low voltage line 182 may be a cathode 410 having a one-piece structure that completely covers the display area 110. In addition, the pixels PX are applied with an initialization voltage and are also connected to a detection signal line 173 and a detection signal line extension 173', and the detection signal line 173 and the detection signal line extension 173' sense the voltage of a specific node in the pixels PX when the initialization voltage is not applied.

[0050] The signal lines connected to the pixels PX may include various other lines, and they are omitted in Figure 1 In Figures 8 to 10 the pixels PX according to an exemplary embodiment are shown in detail.

[0051] In Figure 1In [the structure shown in the figure], regarding the pixel PX, the data line 171 is disposed on the left side, the driving voltage line 181 is disposed on the right side, and the driving low voltage line 182 passes above the pixel PX. However, the present invention is not limited thereto. On the other hand, the detection signal line 173 and the detection signal line extension 173' are not formed for each pixel PX in a column. One longitudinal detection signal line 173 is formed for each column of a plurality of pixels PX and is connected to the plurality of pixels PX through the detection signal line extension 173' extending in the horizontal direction. In the present exemplary embodiment, one longitudinal detection signal line 173 is formed for every three pixel PX columns, and three pixels PX and the longitudinal detection signal line 173 are connected through the detection signal line extension 173'. In addition, according to the exemplary embodiment, the driving voltage line 181 may not be formed for each pixel PX column.

[0052] In the peripheral region 120 of the display panel 100, a peripheral data line 171-1 (hereinafter referred to as the first data line) connected to the data line 171, a peripheral detection signal line 173-1 connected to the longitudinal detection signal line 173, a peripheral driving voltage line 181-1 (hereinafter referred to as the first driving voltage line) connected to the driving voltage line 181, and a peripheral driving low voltage connection portion 182-1 (hereinafter referred to as the first driving low voltage connection portion) connected to the driving low voltage line 182 are formed.

[0053] The peripheral data line 171-1 and the peripheral detection signal line 173-1 form a structure in which they converge from both sides in the fan-out region of the peripheral region 120. This structure enables signals from a single driving chip 250 to be applied in a predetermined region. The peripheral data line 171-1 and the peripheral detection signal line 173-1 have a structure in which they converge toward the center of the fan-out region while being bent (folded). Therefore, pads (also known as "bonding pads") provided at the ends of the peripheral data line 171-1 and the peripheral detection signal line 173-1 can be arranged to converge near the driving chip 250. In addition, the peripheral data line 171-1 and the peripheral detection signal line 173-1 have different lengths due to the bent structure. As a result, the peripheral data line 171-1 may have different resistances. To eliminate the difference in resistance values, the peripheral data line 171-1 may further include a portion (not shown) for forming an additional resistor to have a predetermined resistance. Similar to the peripheral data line 171-1, each peripheral detection signal line 173-1 may also include a portion (not shown) for forming an additional resistance. The conductive layer (in the present exemplary embodiment, the data conductive layer) in which the data line 171 and the detection signal line 173 are formed in the display region 110 may be a different conductive layer from the conductive layer (in the present exemplary embodiment, the gate conductive layer) in which the peripheral data line 171-1 and the peripheral detection signal line 173-1 are formed in the peripheral region 120.

[0054] The peripheral driving voltage line 181-1 extends in the horizontal direction and has a structure including connection lines for connecting a plurality of driving voltage lines 181. The connection lines of the peripheral driving voltage line 181-1 can be integrally formed in the entire peripheral area 120, thus having a structure in which all the driving voltage lines 181 are connected to one connection line. However, according to a typical embodiment, a plurality of connection lines of the peripheral driving voltage line 181-1 can be formed such that one connection line can be connected to only some of the driving voltage lines 181.

[0055] On the other hand, a plurality of peripheral driving low-voltage connection portions 182-1 are formed and the plurality of peripheral driving low-voltage connection portions 182-1 are separated from each other. Although Figure 1 a wiring structure extending in one horizontal direction is shown, Figure 2 it is shown that each separate connection portion can be connected through the cathode 410 to be connected in the circuit structure. That is, each separate peripheral driving low-voltage connection portion 182-1 is connected to the driving low-voltage line 182 of the cathode 410 covering the display area 110. The cathode 410 not only completely covers the display area 110, but also is partially formed in the peripheral area 120 and is connected to the peripheral driving low-voltage connection portion 182-1 at the peripheral area 120. The driving low voltage ELVSS applied to the peripheral driving low-voltage connection portion 182-1 is transmitted to the cathode 410, and the portion where the driving low voltage ELVSS is applied to the cathode 410 can have a plurality of positions.

[0056] The peripheral data line 171-1 formed in the peripheral area 120 can be formed in a different conductive layer from the peripheral driving voltage line 181-1 and the peripheral driving low-voltage connection portion 182-1, thus having a stacked structure in the layout diagram. On the contrary, the peripheral driving voltage line 181-1 and the peripheral driving low-voltage connection portion 182-1 can be formed on the same conductive layer, thus having a separate structure in the layout diagram. The peripheral driving voltage line 181-1 and the peripheral driving low-voltage connection portion 182-1 are formed in the same conductive layer (the data conductive layer in this embodiment) as the driving voltage line 181.

[0057] The data line 171 provided in the display area 110 and the peripheral data line 171-1 provided in the peripheral area 120 are also referred to as data wirings hereinafter.

[0058] The driving voltage line 181 provided in the display area 110 and the peripheral driving voltage line 181-1 provided in the peripheral area 120 are also referred to as driving voltage wirings hereinafter.

[0059] The cathode 410 that covers the display area 110 and forms to the peripheral area 120 and the peripheral driving low-voltage connection part 182-1 disposed in the peripheral area 120 are hereinafter also referred to as driving low-voltage wirings. Here, the driving low-voltage wiring may include driving low-voltage lines 182.

[0060] The flexible printed circuit substrate 200 includes a driving chip 250 that applies a data voltage to the data lines 171, an input wiring 2171 that transmits signals to the driving chip 250, and an output wiring 1171-1 that outputs the data voltage from the driving chip 250.

[0061] The output wiring 1171-1 is connected to the peripheral data lines 171-1 disposed in the peripheral area 120. The input wiring 2171 has a structure for receiving signals from the printed circuit board (PCB) 300 side.

[0062] On the other hand, in the flexible printed circuit substrate 200, there are also included a driving voltage transmission line 1181 for applying a driving voltage ELVDD and a driving low-voltage transmission line 1182 for applying a driving low voltage ELVSS.

[0063] The driving voltage transmission line 1181 is connected to the peripheral driving voltage line 181-1 in the peripheral area 120, and the driving low-voltage transmission line 1182 is connected to the peripheral driving low-voltage connection part 182-1 in the peripheral area 120.

[0064] The printed circuit board (PCB) 300 includes a driving voltage application unit 310 that generates and transmits a driving voltage ELVDD and a driving low-voltage application unit 320 that generates and transmits a driving low voltage ELVSS. The printed circuit board (PCB) 300 includes a driving voltage output line 2181 connected to the driving voltage application unit 310. The driving voltage output line 2181 is connected to the driving voltage transmission line 1181 of the flexible printed circuit substrate 200. As a result, the driving voltage ELVDD is transmitted to the display panel 100. The printed circuit board (PCB) 300 further includes a driving low-voltage output line 2182 connected to the driving low-voltage application unit 320. The driving low-voltage output line 2182 is connected to the driving low-voltage transmission line 1182 of the flexible printed circuit substrate 200. As a result, the driving low voltage ELVSS is transmitted to the display panel 100.

[0065] The printed circuit board (PCB) 300 may further include an image driver that divides an image signal applied from the outside and transmits the image signal to each driving chip 250 disposed on the flexible printed circuit substrate 200. The image driver is connected to the input wiring 2171 of the flexible printed circuit substrate 200 through an image signal transmission line. As a result, the image signal is transmitted to the driving chip 250.

[0066] In the above organic light emitting diode display, the structure of the peripheral region 120 is described in detail by Figure 2 and Figure 3 .

[0067] Figure 2 is an enlarged view of the peripheral region of the organic light emitting diode display according to an exemplary embodiment, Figure 3 and Figure 2 is a cross-sectional view taken along line III-III of

[0068] Figure 2 shows the peripheral region 120 provided at the lower part of the display panel 100, and a fan-out region where the peripheral data lines 171-1 converge will be focused on.

[0069] First, each data line 171 has such a structure: extending in the vertical direction in the display region 110, connected to the peripheral data line 171-1 in the peripheral region 120, and bent in the fan-out region to converge to the center of the fan-out region.

[0070] The different peripheral data lines 171-1 are bent differently. For example, the peripheral data lines 171-1 near the center of the fan-out region may have a relatively small curvature (or no curvature at all), while the peripheral data lines 171-1 near the edge of the fan-out region may have a relatively large curvature (i.e., bent at a large angle, extending for a relatively long length in the changed direction, or both). This results in different total lengths of the different peripheral data lines 171-1, and as a result, different electrical characteristics such as resistance or parasitic capacitance.

[0071] Therefore, a compensation part can be constructed to reduce the difference in the electrical characteristics of the different peripheral data lines 171-1 (for example, including the structure of the peripheral driving low voltage connection part 182-1 described below). The compensation part can achieve this equalization effect by overlapping the different peripheral data lines 171-1 by different amounts. That is, when two conductors at different potentials are close to each other, they are affected by each other's electric fields and store opposite charges like a capacitor. Therefore, the proximity of the peripheral data lines 171-1 to the compensation part (i.e., the structure including the peripheral driving low voltage connection part 182-1) results in a parasitic capacitance, which increases with the overlapping length between the two elements. Therefore, making the overlapping lengths different for the different peripheral data lines 171-1 can reduce or eliminate the difference in parasitic capacitance caused by the fan-out structure (i.e., the different bending of the peripheral data lines 171-1). As a result, the signals passing through the different peripheral data lines 171-1 can be synchronized more effectively, which can bring about improved performance of the display.

[0072] Referring to Figure 3, the peripheral data lines 171-1 are formed in the layer (gate conductive layer) in which the gate lines are formed, rather than in the layer (data conductive layer) in which the data lines 171 are formed. As a result, each data line 171 has a structure that passes through the display area 110, forms a partial area in the data conductive layer to the peripheral area 120, and is electrically connected to the peripheral data line 171-1 formed in the gate conductive layer through a contact structure. Here, the gate conductive layer is formed closer to the semiconductor layer than the data conductive layer, and has a position set away from the anode layer and the cathode layer.

[0073] The peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1 are formed in the data conductive layer of the peripheral area 120. Since the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1 are formed on the same layer, they are separated from each other in the plan view.

[0074] In other words, the gate conductive layer is the layer in which the peripheral data lines 171-1 are formed, and the data conductive layer is the layer in which the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1 are formed.

[0075] The peripheral driving voltage line 181-1 provided in the peripheral area 120 extends in the horizontal direction (first direction), and includes a pad portion that protrudes downward to be electrically connected. The pad portion of the peripheral driving voltage line 181-1 is provided between adjacent fan-out areas. The pad portion of the peripheral driving voltage line 181-1 is connected to the driving voltage transmission line 1181 of the flexible printed circuit substrate 200 to receive the driving voltage ELVDD. The driving voltage ELVDD transmitted to the peripheral driving voltage line 181-1 is then transmitted to the driving voltage line 181. As the number of pad portions protruding from the peripheral driving voltage line 181-1 increases, the driving voltage ELVDD has a constant characteristic in the display area 110. Since the driving voltage line 181 is formed on the data conductive layer and the peripheral driving voltage line 181-1 is formed on the data conductive layer, the driving voltage line 181 and the peripheral driving voltage line 181-1 can have an overall structure in which they are directly connected without a separate contact structure.

[0076] The peripheral driving low voltage connection part 182-1 provided in the peripheral area 120 has a plurality of separate structures. In one connection part, pad portions are provided on both sides and a wiring part connecting the two pad portions is formed. That is, the peripheral driving voltage line 181-1 has a structure that is integrally connected through a connection line, but the peripheral driving low voltage connection part 182-1 has a plurality of separate connection parts.

[0077] In addition, the wiring portion of the peripheral drive low-voltage connection portion 182-1 has a structure in which the width increases toward the center of the fan-out region. This structure makes the parasitic capacitance generated in the peripheral data lines 171-1 and the peripheral detection signal lines 173-1 due to the peripheral drive low-voltage connection portion 182-1 constant or almost constant for all the peripheral data lines 171-1 and the peripheral detection signal lines 173-1. This structure (equal-capacitance structure) reduces or eliminates the difference in signal delay caused by the fact that the data lines 171 may have differential parasitic capacitance in the fan-out region due to the peripheral data lines 171-1. In addition, the difference in signal delay caused by the detection signal lines 173 that may have differential parasitic capacitance in the fan-out region due to the peripheral detection signal lines 173-1 can be reduced or removed.

[0078] At the edge of the fan-out region, the wiring portion of the peripheral drive low-voltage connection portion 182-1 has a narrow width h2 to slightly overlap only with the wiring (i.e., the wiring of the peripheral data lines 171-1 and the peripheral detection signal lines 173-1). At the center of the fan-out region, the wiring portion of the peripheral drive low-voltage connection portion 182-1 has a wide width h1 to be mostly overlapped. As a result, all the peripheral data lines 171-1 and the peripheral detection signal lines 173-1 have the same or almost the same parasitic capacitance.

[0079] If the equal-capacitance structure according to an exemplary embodiment of the present invention is used together with the structure of the peripheral data lines 171-1 having equal resistance, the RC delay value generated in the peripheral data lines 171-1 can be kept constant or almost constant. As a result, the RC delay values generated in all the data lines 171 become the same, so that there is no problem due to the delay difference generated by each wiring.

[0080] In addition, in all the peripheral detection signal lines 173-1, the parasitic capacitance generated by overlapping with the wiring portion of the peripheral drive low-voltage connection portion 182-1 is the same or almost the same. In addition, the peripheral detection signal lines 173-1 may include a structure having an equal resistance such as the equal resistance of the peripheral data lines 171-1.

[0081] Each peripheral drive low-voltage connection portion 182-1 forms a contact structure in the peripheral region 120 that contacts the drive low-voltage line 182. That is, the drive low-voltage line 182 is formed as the cathode 410 covering the region of the display region 110, and the cathode 410 extends to the peripheral region 120. In addition, since the peripheral drive low-voltage connection portion 182-1 in the fan-out region is formed of a data conductive layer, it can be electrically connected to the cathode 410 located thereon through the opening 405.

[0082] In some embodiments, the cathode 410 not only covers the area of the display region 110, but also is formed in the peripheral region 120, and according to Figure 2 In the embodiment shown in, the cathode 410 covers the peripheral driving low voltage connection part 182-1 and the peripheral driving voltage line 181-1. However, according to an exemplary embodiment, the cathode 410 may have a structure that only overlaps with a part of the peripheral driving low voltage connection part 182-1 or the peripheral driving voltage line 181-1.

[0083] Figure 3 The positional relationship of certain wirings is shown through a cross-sectional view.

[0084] According to Figure 3 , the buffer layer 11 is stacked on the substrate 10. The substrate 10 may be a glass substrate or a flexible substrate such as plastic. A metal layer may be formed on the substrate 10, but the metal layer is not shown in the Figure 3 cross-sectional view. Additionally, a semiconductor layer is formed on the buffer layer 11, although the semiconductor layer may not be formed in the peripheral region 120. The gate insulating layer 12 is stacked on the buffer layer 11. A gate conductive layer is formed on the gate insulating layer 12, and the peripheral data line 171-1 is formed in the peripheral region 120. The interlayer insulating layer 14 covering the peripheral data line 171-1 and the gate insulating layer 12 is stacked on the peripheral data line 171-1 and the gate insulating layer 12. According to an exemplary embodiment, the layer for constructing the pixel PX may include a second gate conductive layer. In this case, a second gate insulating layer (not shown) may also be formed between the interlayer insulating layer 14 and the gate insulating layer 12. Additionally, according to an exemplary embodiment, the peripheral data line 171-1 may be formed by the second gate conductive layer.

[0085] A data conductive layer is formed on the interlayer insulating layer 14, and the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1 are formed in the peripheral region 120. Since the driving voltage line 181 of the display region 110 is formed in the data conductive layer, the peripheral driving voltage line 181-1 may have a directly connected structure.

[0086] An organic insulator 15 covering the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1 is formed on the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1. An anode layer may be formed on the organic insulator 15. A spacer 20 covering the organic insulator 15 is formed on the organic insulator 15. The cathode 410 is formed on the spacer 20, and the cathode 410 and the peripheral driving low voltage connection part 182-1 are electrically connected through an opening 405 formed in the organic insulator 15 and the spacer 20.

[0087] In the foregoing, an exemplary embodiment having an equal-capacitance structure was described, the equal-capacitance structure being formed of a structure in which the width of the peripheral driving low-voltage connection portion 182-1 gradually changes. This structure is also referred to hereinafter as a triangular structure or a triangular shape. Referring to Figure 2 , since the portion connected to the pad portion has a narrow width h2, the structure of the wiring portion of the peripheral driving low-voltage connection portion 182-1 has a triangular shape, and for convenience, in this specification, this structure is sometimes referred to as a triangle.

[0088] Hereinafter, in addition to the equal-capacitance structure, a structure in which a peripheral driving voltage line 181-1 and a peripheral driving low-voltage connection portion 182-1 having low resistance are formed by additional wiring formed in the peripheral region 120 is described.

[0089] Figure 4 is an enlarged view of a peripheral region of an organic light-emitting diode display according to an exemplary embodiment, Figure 5 is a cross-sectional view taken along the lines V-V', V'-V'' and V-V''' of Figure 4 .

[0090] Referring to Figure 4 and Figure 5 , compared with Figure 3 , additional metal layers C1 and C2 may be formed between the substrate 10 and the buffer layer 11. Each of the additional metal layers C1 and C2 has a structure that overlaps with the peripheral driving voltage line 181-1 and the peripheral driving low-voltage connection portion 182-1, respectively, and is electrically connected to the peripheral driving voltage line 181-1 and the peripheral driving low-voltage connection portion 182-1, but the present invention is not limited thereto, and at least one of the peripheral driving voltage line 181-1 and the peripheral driving low-voltage connection portion 182-1 may be connected to the additional metal layer C1 / C2.

[0091] Figure 4 shows an opening OC1, which may refer to an opening in, for example, the buffer layer 11, the gate insulating layer 12, and the interlayer insulating layer 14, so that the wiring in the data conductive layer can be connected to the additional metal layer C1.

[0092] Specifically, the peripheral driving voltage line 181-1 is formed in the data conductive layer and is connected to the additional metal layer C1 in the metal layer formed under the buffer layer 11 to reduce the total resistance. That is, the peripheral driving voltage line 181-1 provided in the data conductive layer is electrically connected to the additional metal layer C1 through the opening OC1, and the additional metal layer C1 may be formed to have a lower resistance than the data conductive layer, thereby reducing the overall resistance.

[0093] Figure 4 Differences from Figure 2 also lie in that:Figure 4 An embodiment is shown in which the peripheral drive low-voltage connection portion 182-1 can be connected to the additional metal layer C2 through the opening OC2. In the example shown, the opening OC2 is located at the edge of the fan-out structure. That is, the peripheral drive low-voltage connection portion 182-1 is connected to the additional metal layer C2 in the metal layer formed under the buffer layer 11 to reduce the total resistance. That is, the peripheral drive low-voltage connection portion 182-1 provided in the data conductive layer is electrically connected to the additional metal layer C2 through the opening OC2, and the additional metal layer C2 can be formed to have a lower resistance than the data conductive layer, thereby reducing the overall resistance. By Figure 4 In the embodiment shown, unlike the structure of the peripheral drive low-voltage connection portion 182-1 (which has a triangular structure), the additional metal layer C2 has a quadrilateral structure. However, according to an exemplary embodiment, the additional metal layer C2 may also have a structure in which the width gradually changes (i.e., a triangular shape) the same as the structure of the peripheral drive low-voltage connection portion 182-1. Refer to Figure 6 This is described below.

[0094] Figure 6 is an enlarged view of the peripheral area of an organic light emitting diode display according to an exemplary embodiment.

[0095] In Figure 6 the peripheral drive low-voltage connection portion 182-1 has a quadrilateral structure, and the additional metal layer C2 has a triangular structure.

[0096] In other words, Figure 4 an embodiment is shown in which the peripheral drive low-voltage connection portion 182-1 has a triangular structure and the additional metal layer C2 has a rectangular (or quadrilateral) structure, while in Figure 6 the structure is reversed such that the peripheral drive low-voltage connection portion 182-1 has a quadrilateral structure and the additional metal layer C2 has a triangular structure.

[0097] However, in both figures, the aspect that the peripheral drive low-voltage connection portion 182-1 is formed in the data conductive layer and the additional metal layer C2 is formed in the metal layer provided on the substrate 10 is the same.

[0098] In Figure 4 the structure of Figure 6 and

[0099] The wirings for applying a driving low voltage ELVSS (e.g., the peripheral driving low voltage connection part 182-1 and the additional metal layer C2) are formed above and below the peripheral data line 171-1 and the peripheral detection signal line 173-1. Since the peripheral driving low voltage connection part 182-1 or the additional metal layer C2 has a triangular structure, parasitic capacitance is generated based on the overlapping area, and thus there are differences in the areas overlapping with each of the peripheral data line 171-1 or the peripheral detection signal line 173-1. When the length of the peripheral data line 171-1 or the peripheral detection signal line 173-1 is long, the overlapping area is small, and when the length is short, the overlapping area is large, such that the overall parasitic capacitance is formed to be uniform in the peripheral data line 171-1 or the peripheral detection signal line 173-1.

[0100] According to an exemplary embodiment, the peripheral driving low voltage connection part 182-1 and the additional metal layer C2 may both have a structure in which the width gradually changes (e.g., a triangular shape). In this case, compared with Figure 4 and Figure 6 the exemplary embodiment, the width difference between the overlapping low voltage layers will be small.

[0101] According to an exemplary embodiment, the parasitic capacitance generated in the peripheral data line 171-1 and the peripheral detection signal line 173-1 may not be completely constant, and the difference may be generated within a range where problems do not occur due to the difference in parasitic capacitance.

[0102] Refer to Figure 7 to describe an example structure in which the parasitic capacitance generated in the peripheral data line 171-1 and the peripheral detection signal line 173-1 is not constant.

[0103] Figure 7 is an enlarged view of the peripheral area of an organic light emitting diode display according to an exemplary embodiment. Except for the shape of the peripheral driving low voltage connection part 182-1, Figure 7 the embodiment shown in Figure 2 is similar to the embodiment of Figure 7 For example, Figure 4 and Figure 6 the embodiment shown in does not include the additional metal layer C1 or C2 shown in

[0104] In Figure 7 the peripheral driving low voltage connection part 182-1 does not have a triangular structure, but is formed of a structure having different parts with two different widths from each other (i.e., h3 and h4). The part having a thick width h3 is provided at the central part of the fan-out area, and the part having a thin width h4 is provided on both sides of the fan-out area. As a result, Figure 7The similarity between the embodiment shown and the previous exemplary embodiments is that when the length of the peripheral data line 171-1 is long, the overlapping region (i.e., the overlapping region between the peripheral driving low voltage connection part 182-1 and the peripheral data line 171-1) is small, and when the length is short, the overlapping region is large. However, the difference is that the width of the peripheral driving low voltage connection part 182-1 does not gradually increase. Still, according to Figure 7 's exemplary embodiment, the difference in parasitic capacitance caused by the peripheral data line 171-1 and the peripheral detection signal line 173-1 can be reduced. According to other exemplary embodiments, the width of the peripheral driving low voltage connection part 182-1 can be formed to have three or more different widths instead of being formed to have two widths as shown in Figure 7 . In the exemplary embodiment, the thickest width can be set at the central part of the fan-out region, and the thinner parts are arranged toward both sides.

[0105] In some embodiments, Figure 7 's exemplary embodiment does not include the additional metal layers C1 and C2, however it can have the additional metal layers C1 and C2 as in Figure 4 . Additionally, as shown in Figure 6 , the additional metal layer C2 can have an Figure 7 equal-capacitance structure. Similarly, the peripheral driving low voltage connection part 182-1 can be in a structure with a constant width.

[0106] In the above exemplary embodiments, the structure in which the display panel 100 is connected to the flexible printed circuit substrate 200 through the lower part is mainly described. Additionally or alternatively, the fan-out region can be formed at the upper part of the display panel 100.

[0107] The peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1 can be formed in the part of the peripheral region 120 where the fan-out region is not formed. The peripheral driving low voltage connection part 182-1 can have an equal-capacitance structure in the corresponding part.

[0108] Hereinafter, the structure of the pixel described in the exemplary embodiment is described through the Figure 8 circuit diagram.

[0109] Figure 8 is the circuit diagram of the pixel of the organic light emitting diode display according to the exemplary embodiment.

[0110] The pixel PX according to the present exemplary embodiment includes three transistors T1, T2, and T3, one organic light emitting diode OLED, and two capacitors C st and C oledIn addition, the signal lines include a gate line SC, a previous gate line SS, a data line Data, a driving voltage line, a detection signal line SL / INT, and a driving low voltage line. The detection signal line SL / INT also serves as an initialization voltage line for applying an initialization voltage.

[0111] According to Figure 8 An exemplary embodiment of the pixel PX includes a driving transistor T1, a switching transistor (i.e., a second transistor T2) connected to the gate line SC, and an initialization transistor (i.e., a third transistor T3 (hereinafter referred to as a sensing transistor)) connected to the previous gate line SS. The third transistor T3 may be connected to a signal line that applies a gate-on voltage at a timing different from that of the previous gate line SS.

[0112] The gate line SC is connected to a gate driver (not shown) to transmit a scan signal to the second transistor T2 and extends in the horizontal direction.

[0113] The previous gate line SS is connected to the gate driver to transmit a previous scan signal applied to the pixel PX disposed in the previous stage to the third transistor T3. The previous gate line SS extends in the horizontal direction as does the gate line SC.

[0114] The data line Data (171) extends in the vertical direction and is a wiring for receiving a data voltage from the driving chip 250 and transferring it to the pixel PX.

[0115] The detection signal line SL / INT also extends in the vertical direction, and one detection signal line SL / INT may be formed for each of the plurality of pixels PX.

[0116] The driving voltage line 181 applies a driving voltage ELVDD, and the driving low voltage line 182 applies a driving low voltage ELVSS. The driving voltage line 181 extends in the vertical direction. According to the exemplary embodiment, the driving voltage line 181 may be formed of a grid structure by further including a portion extending in the horizontal direction.

[0117] The driving low voltage line 182 may be formed to cover the cathode 410 of the entire pixel PX in the display area 110. However, when the cathode 410 is formed of a single plate structure, a difference in voltage value may occur based on the position. To prevent this, the driving low voltage line 182 may also include a grid structure including a portion extending in an additional horizontal direction and a portion extending in the vertical direction.

[0118] Hereinafter, a plurality of transistors will be described.

[0119] First, the driving transistor T1 is a transistor that adjusts the magnitude of the current output according to the data voltage applied to the gate electrode, and the output driving current is applied to the organic light-emitting diode OLED so that the brightness of the organic light-emitting diode OLED is controlled. For this purpose, the first electrode (input-side electrode) of the driving transistor T1 is set to receive the driving voltage ELVDD, and the second electrode (output-side electrode) is connected to the anode of the organic light-emitting diode OLED. In addition, the gate electrode of the driving transistor T1 is connected to the second electrode (output-side electrode) of the second transistor T2 to receive the data voltage.

[0120] On the other hand, the gate electrode of the driving transistor T1 is connected to one electrode of the storage capacitor C st . The storage capacitor C st ensures that the data voltage transmitted to the gate electrode of the driving transistor T1 is maintained for one frame. Therefore, the voltage of the gate electrode of the driving transistor T1 changes based on the voltage stored in the storage capacitor C st , and the driving current output from the driving transistor T1 changes and is constantly output during one frame.

[0121] On the other hand, according to an exemplary embodiment, a metal layer M1 may be additionally formed under the semiconductor layer in which the channel of the driving transistor T1 is provided. The metal layer M1 overlaps with the channel and the gate electrode of the driving transistor T1 to improve the performance of the driving transistor T1 and maintain the voltage of the gate electrode. The second electrode of the driving transistor T1 may be electrically connected to the metal layer M1, and this is the structure of the voltage connected to the anode. However, according to an exemplary embodiment, the driving voltage ELVDD may be transmitted to the metal layer M1.

[0122] The second transistor T2 (hereinafter referred to as the switching transistor) is a transistor that receives the data voltage into the pixel PX. The gate electrode is connected to the gate line SC, the first electrode is connected to the data line 171, and the second electrode (output-side electrode) is connected to the gate electrode of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal transmitted through the gate line SC, the data voltage transmitted through the data line 171 is transmitted to the gate electrode of the driving transistor T1 and stored in the storage capacitor C st .

[0123] The third transistor T3 (hereinafter referred to as the initialization transistor or the sensing transistor) is used to initialize the second electrode of the driving transistor T1, the storage capacitor C stOne electrode of and the anode of the organic light-emitting diode OLED. The gate electrode of the third transistor T3 is connected to the previous gate line SS, and the first electrode is connected to the initialization voltage line SL / INT. The second electrode of the third transistor T3 is electrically connected to the second electrode (output side electrode) of the driving transistor T1, and as a result, is also connected to the anode of the organic light-emitting diode OLED.

[0124] The detection signal line SL / INT is used to sense the voltage of the anode connected to the second electrode of the third transistor T3, or to transmit the initialization voltage according to the period. As a result, the third transistor T3 is called a sensing transistor.

[0125] Describe the operation of the third transistor T3. The voltage of the anode when the organic light-emitting diode OLED emits light (emission period) is applied to one electrode of the storage capacitor C st In this case, the data voltage is applied to the other electrode of the storage capacitor C st When the gate conduction voltage is applied to the gate electrode of the third transistor T3, the detection signal line 173 also operates as an initialization voltage line, so that the voltage of the anode is transmitted to the sensing unit (not shown) through the sensing line. Hereinafter, this is called the detection period. Then, in the remaining periods among the periods in which the gate conduction voltage is applied to the gate electrode of the third transistor T3, the detection signal line 173 applies the initialization voltage Vint to initialize the voltage of the anode. Hereinafter, this is called the initialization period.

[0126] If the voltage sensed in the sensing period is different from the expected anode voltage determined based on the applied data voltage, the data voltage can be modified and provided to the pixel PX. In other words, the state of the driving transistor T1 can be changed, and the state of the driving transistor T1 can be sensed, so that the organic light-emitting diode OLED can emit light normally by sensing the corresponding data voltage.

[0127] The anode voltage of the organic light-emitting diode OLED is stored by two capacitors C st and C oled and is maintained for one frame.

[0128] According to other embodiments, pixels other than the pixel PX shown in Figure 8 can be used.

[0129] Having the same circuit structure as Figure 8 The pixel PX can simultaneously form various layer structures having the same as Figure 9 and Figure 10 the same.

[0130] First, describe Figure 9 the structure of.

[0131] Figure 9 is a cross-sectional view of a pixel of an organic light-emitting diode display according to an exemplary embodiment.

[0132] Figure 9 The cross-sectional view mainly shows Figure 8 the driving transistor T1, the storage capacitor C st and the organic light-emitting diode OLED in

[0133] A metal layer M1 is formed on a substrate 10, and a buffer layer 11 is stacked on the metal layer M1 and the substrate 10.

[0134] A semiconductor layer (S1, ch, and S2) is formed on the buffer layer 11. The semiconductor layer (S1, ch, and S2) includes a first region S1, a channel region ch, and a second region S2 of the driving transistor T1. A gate insulating layer 12 is formed on the semiconductor layer (S1, ch, and S2).

[0135] A gate conductive layer is formed on the gate insulating layer 12, and the gate electrode Gate and the first electrode cap-1 of the storage capacitor C Figure 9 are shown in st The gate insulating layer 12 is only disposed under the gate electrode Gate and the first electrode cap-1 of the storage capacitor C st below.

[0136] A second gate insulating layer 13 covering the first electrode cap-1 of the storage capacitor C st and the gate insulating layer 12 is disposed thereon. A second gate conductive layer is disposed on the second gate insulating layer 13, Figure 9 showing connection electrodes S1-1, S2-1, and Gate-1 electrically connected to each electrode of the driving transistor T1 and the second electrode cap-2 of the storage capacitor C st Among the connection electrodes, the output-side connection electrode S2-1 connected to the second electrode of the driving transistor T1 is also electrically connected to the metal layer M1. The storage capacitor C st is formed by the first electrode cap-1, the second electrode cap-2, and the second gate insulating layer 13 disposed between the first electrode cap-1 and the second electrode cap-2.

[0137] The second gate conductive layer is covered by an interlayer insulating layer 14.

[0138] A data conductive layer is formed on the interlayer insulating layer 14, and in Figure 9Among them, a driving voltage line 181 for transmitting a driving voltage ELVDD to a first electrode of a driving transistor T1, an output electrode DD of the driving transistor T1 connected to an output side connection electrode S2-1, and a peripheral driving low voltage connection part 182-1 provided in a peripheral area 120 are formed. The output electrode DD of the driving transistor T1 is also connected to a second electrode cap-2 of a storage capacitor C st of the storage capacitor C

[0139] The data conductive layer is covered by an organic insulator 15. An anode is formed on the organic insulator 15, and the anode is also connected to the output electrode DD of the driving transistor T1 to receive the output of the driving transistor T1.

[0140] A separator 20 is provided on the anode. The separator 20 is provided with an opening, and an organic emission layer OL is provided in a part where the anode is exposed. A cathode 410 is provided on the organic emission layer OL and the separator 20.

[0141] The cathode 410 is connected to the peripheral driving low voltage connection part 182-1 exposed through an opening provided in the separator 20 and the organic insulator 15, and receives a driving low voltage ELVSS.

[0142] Figure 9 The exemplary embodiment has a metal layer, a semiconductor layer, a gate conductive layer, a second gate conductive layer, a data conductive layer, an anode layer, and a cathode layer. However, such a layer structure can be changed for each exemplary embodiment, and another exemplary embodiment is shown in Figure 10 the following figure.

[0143] Figure 10 is a cross-sectional view of a pixel of an organic light emitting diode display according to an exemplary embodiment.

[0144] A metal layer M1 is formed on a substrate 10, and a buffer layer 11 is stacked on the metal layer M1 and the substrate 10.

[0145] A semiconductor layer (S1, ch, and S2) is formed on the buffer layer 11. The semiconductor layer (S1, ch, and S2) includes a first region S1, a channel region ch, and a second region S2 of the driving transistor T1. A gate insulating layer 12 is formed on the semiconductor layer (S1, ch, and S2).

[0146] A gate conductive layer is formed on the gate insulating layer 12, Figure 10 showing a gate electrode Gate and a first electrode cap-1 of a storage capacitor C st of the storage capacitor C. The gate insulating layer 12 is only provided under the gate electrode Gate and the first electrode cap-1 of the storage capacitor C st of the storage capacitor C.

[0147] covering the storage capacitor C stThe first electrode cap-1 of and the interlayer insulating layer 14 of the gate insulating layer 12 are formed thereon.

[0148] The data conductive layer is formed on the interlayer insulating layer 14. Among Figure 10 them, the driving voltage line 181 that transmits the driving voltage ELVDD to the first electrode of the driving transistor T1, the output electrode DD of the driving transistor T1, the peripheral driving low-voltage connection part 182-1 provided in the peripheral area 120, and the storage capacitor C st The second electrode cap-2 of is formed in the data conductive layer. The output electrode DD of the driving transistor T1 is connected to the metal layer M1. In addition, although not shown in Figure 10 it, the output electrode DD of the driving transistor T1 is also electrically connected to the second electrode cap-2 of the storage capacitor C st as well.

[0149] The data conductive layer is covered with a second interlayer insulating layer 14-1 (also referred to as a passivation layer). The second interlayer insulating layer 14-1 has an opening that exposes the peripheral driving low-voltage connection part 182-1, and an interlayer low-voltage connection part C-PXL electrically connected to the exposed peripheral driving low-voltage connection part 182-1 is formed on the second interlayer insulating layer 14-1. The layer formed on the second interlayer insulating layer 14-1 is referred to as a second data conductive layer (also referred to as a pixel electrode layer according to an exemplary embodiment).

[0150] The organic insulator 15 covering the second data conductive layer is formed on the second data conductive layer. The anode is formed on the organic insulator 15, and the anode is connected to the output electrode DD of the driving transistor T1 to receive the output of the driving transistor T1.

[0151] The spacer 20 is provided on the anode, and the organic emission layer OL is provided in the part where the spacer 20 has an opening and the anode is exposed. The cathode 410 is provided on the organic emission layer OL and the spacer 20.

[0152] The cathode 410 is connected to the interlayer low-voltage connection part C-PXL exposed by the openings provided in the spacer 20 and the organic insulator 15, thereby receiving the driving low voltage ELVSS from the peripheral driving low-voltage connection part 182-1.

[0153] Figure 10 The exemplary embodiment of has a metal layer, a semiconductor layer, a gate conductive layer, a data conductive layer, a second data conductive layer, an anode layer, and a cathode layer.

[0154] Figure 9 The exemplary embodiment of and Figure 10 The exemplary embodiment of are distinguished by the presence or absence of the second gate conductive layer and the presence or absence of the second data conductive layer.

[0155] With Figure 9 and Figure 10 the same, as the layer structure forming each pixel PX changes, Figures 2 to 7 the structure can be composed of different layers.

[0156] That is, in Figures 2 to 7 the gate conductive layer is described as the layer in which the peripheral data line 171-1 is formed, and the data conductive layer is described as the layer in which the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1 are formed. Additionally, the additional metal layers C1 and C2 are described as the metal layers provided under the semiconductor layer. However, various combinations of layer positions are possible. Furthermore, the gate conductive layer can be formed of two or more layers, and the data conductive layer can be formed of two or more layers, so that combinations of various exemplary embodiments are possible. Additionally, a pixel electrode layer provided on the data conductive layer can also be used.

[0157] Although the present invention has been described in connection with currently considered practical exemplary embodiments, it will be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the claims.

[0158] <Description of reference numerals>

[0159] 100: Display panel

[0160] 110: Display area

[0161] 120: Peripheral area

[0162] 200: Flexible printed circuit substrate

[0163] 250: Driving chip

[0164] 300: Printed circuit board (PCB)

[0165] 310: Driving voltage application unit

[0166] 320: Driving low voltage application unit

[0167] 10: Substrate

[0168] 11: Buffer layer

[0169] 12: Gate insulating layer

[0170] 13: Second gate insulating layer

[0171] 14: Interlayer insulating layer

[0172] 14-1: Second interlayer insulating layer

[0173] 15: Organic insulator

[0174] 20: Spacer

[0175] 171: Data line

[0176] 2171: Output wiring

[0177] 171-1: Peripheral data line (first data line)

[0178] 173: Detection signal line

[0179] 173': Detection signal line extension

[0180] 173-1: Peripheral detection signal line

[0181] 181: Drive voltage line

[0182] 1181: Drive voltage transmission line

[0183] 1182: Drive low voltage transmission line

[0184] 2181: Drive voltage output line

[0185] 182: Drive low voltage line

[0186] 181-1: Peripheral drive voltage line (first drive voltage line)

[0187] 182-1: Peripheral drive low voltage connection part (first drive low voltage connection part)

[0188] 2182: Drive low voltage output line

[0189] 405, OC1, OC2: Opening

[0190] 410: Cathode

[0191] C1, C2: Additional metal layer

[0192] M1: Metal layer

[0193] OL: Organic emission layer

[0194] SC: Gate line

[0195] SS: Previous gate line

[0196] C-PXL: Interlayer low voltage connection part

Claims

1. An organic light emitting diode display, the organic light emitting diode display comprising: A display panel, including a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out area located at one side of the display area; Data wirings, including data lines disposed in the display area and first data lines disposed in the peripheral area; Drive voltage wirings, including drive voltage lines disposed in the display area and first drive voltage lines disposed in the peripheral area and extending in a first direction; And Drive low voltage wirings, including a cathode covering the display area and formed to the peripheral area and a first drive low voltage connection portion connected to the cathode and disposed in the peripheral area, Wherein, the first drive low voltage connection portion includes a wiring portion, and the wiring portion includes a first portion at an edge of the fan-out area and overlapping with the first data line and a second portion at a center of the fan-out area and overlapping with the first data line, and Wherein, the width of the first portion is less than the width of the second portion.

2. The organic light emitting diode display according to claim 1, wherein, The first drive low voltage connection portion further includes pad portions disposed on both sides of the wiring portion.

3. The organic light emitting diode display according to claim 1, the organic light emitting diode display further comprising: A first additional metal layer, disposed in the peripheral area and overlapping with the first drive low voltage connection portion, Wherein, the first additional metal layer is electrically connected to the first drive low voltage connection portion, and Wherein, the first additional metal layer is disposed under a semiconductor layer.

4. The organic light emitting diode display according to claim 1, wherein, The first drive voltage line further includes a pad portion electrically connected to one side, and The first drive voltage line and the drive voltage line are formed on the same layer.

5. The organic light emitting diode display according to claim 4, the organic light emitting diode display further comprising: A second additional metal layer, disposed in the peripheral area and overlapping with the first drive voltage line, and The second additional metal layer is electrically connected to the first drive voltage line, Wherein, the second additional metal layer is disposed under a semiconductor layer.

6. The organic light emitting diode display according to claim 1, wherein, The first data line is formed in a gate conductive layer.

7. An organic light emitting diode display, the organic light emitting diode display comprising: A display panel, including a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out area located at one side of the display area; Data wirings, including data lines disposed in the display area and first data lines disposed in the peripheral area; Drive voltage wirings, including drive voltage lines disposed in the display area and first drive voltage lines disposed in the peripheral area and including a connection portion extending in a first direction; And The driving low-voltage wiring includes a cathode provided in the display area and a first driving low-voltage connection portion connected to the cathode and provided in the peripheral area. Wherein, at least one of the first driving voltage line and the first driving low-voltage connection portion is connected to an additional metal layer. The additional metal layer is provided in the peripheral area and has a lower resistance than at least one of the first driving voltage line and the first driving low-voltage connection portion connected to the additional metal layer. Wherein, the first driving low-voltage connection portion includes a wiring portion, and the wiring portion includes a first portion at the edge of the fan-out area and overlapping with the first data line and a second portion at the center of the fan-out area and overlapping with the first data line, and wherein, the width of the first portion is smaller than the width of the second portion.

8. The organic light-emitting diode display according to claim 7, wherein, the additional metal layer connected to the first driving low-voltage connection portion is a first additional metal layer, and the first additional metal layer includes a first portion and a second portion having a different width compared to the first portion.

9. The organic light-emitting diode display according to claim 8, wherein, the first driving low-voltage connection portion further includes pad portions provided on both sides of the wiring portion.

10. The organic light-emitting diode display according to claim 7, wherein, the first driving voltage line and the driving voltage line are formed on the same layer, and the first data line is formed in the gate conductive layer.

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