Oscillator calibration structure and method

Abstract

This document discloses an oscillator calibration structure and method. A short-range data link receiver includes: an edge detector configured to generate pulses on the edges of a data input; a first clock data recovery path coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; a second clock data recovery path coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; and a controller configured to alternate between the first and second clock data recovery paths to use one path to recover clock and data while calibrating the other path. The controller can switch paths whenever calibration of one path is complete. This can include starting calibration of the next path immediately after switching paths. Alternatively, power consumption can be reduced by delaying calibration of the next path after switching paths.

Description

Technical Field

[0001] This disclosure relates to the calibration of oscillators in receivers for short-range data links. More specifically, this disclosure relates to the structure and method for calibrating an injection-locked oscillator in a clock data recovery circuit in a receiver for a short-range data link. Background Technology

[0002] The background description provided herein is for the purpose of generally presenting the context of this disclosure. The work of the inventors with respect to the work described in this background section, as well as aspects that may otherwise not qualify as prior art at the time of filing, are neither expressly nor implied to be considered prior art to this disclosure.

[0003] Short-range data links are sometimes used for chip-to-chip communication when a reliable, high-speed, low-power serial interface is required. For example, as semiconductor process nodes evolve, the cost of semiconductor devices increases. Consequently, electronic devices comprising multiple interconnect chips are becoming increasingly popular. In some cases, more advanced process nodes are used only on integrated circuit chips that implement functions requiring fast processing and high power consumption. Conversely, less demanding features such as traditional input / output features and other peripheral features can be implemented on one or more integrated circuit chips at older process nodes. One or more short-range data links are then used to interconnect the separate integrated circuit chips.

[0004] One advantage of short-range data links is low channel loss (~-12dB). Due to such low channel loss, clock data recovery (CDR) based on injection-locked oscillators (ILO) is practical. However, for ILO-based CDR to function correctly, the ratio of the oscillator free-running frequency (FRF) to the data rate must be kept constant. Summary of the Invention

[0005] A short-range data link receiver according to an implementation of the subject matter of the present invention comprises: an edge detector configured to generate pulses on the edges of a data input; a first clock data recovery path coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; a second clock data recovery path coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; and a controller configured to alternate between the first clock data recovery path and the second clock data recovery path to recover clock and data using one of the paired first clock data recovery paths and the second clock data recovery path, while calibrating the other of the first clock data recovery path and the second clock data recovery path.

[0006] In a first implementation of this short-range data link receiver, the controller can be configured to exchange the first path of the first clock data recovery path and the second path of the second clock data recovery path with a predetermined time interval.

[0007] In a first variant of this first implementation, the predetermined time interval can be selected to be at most equal to the operation duration during which temperature drift will cause the first path of the first clock data recovery path and the second clock data recovery path to lose calibration.

[0008] In a second variant of the first implementation, the controller may be configured to swap the first path of the first clock data recovery path with the second path of the second clock data recovery path whenever calibration of the second path of the first clock data recovery path and the second clock data recovery path is completed.

[0009] In a second variant of this first implementation, the controller may be configured to begin calibration of the next path to be calibrated in the first and second clock data recovery paths immediately after the first and second clock data recovery paths are swapped. Alternatively, in the second variant of this first implementation, the controller may be configured to delay the calibration of the next path to be calibrated in the first and second clock data recovery paths for a portion of the predetermined time interval following the swapping of the first and second clock data recovery paths.

[0010] In a second implementation of this short-range data link receiver, each of the first clock data recovery path and the second clock data recovery path may include: an injection-locked oscillator configured to recover the clock by injecting a reference frequency locked to the output of the edge detector; and a demultiplexer configured to operate on the data input and the recovered clock to recover the data.

[0011] In a first variant of this second implementation, each of the first clock data recovery path and the second clock data recovery path may further include: circuitry configured to compare the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path, and to adjust the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path when the corresponding polarities of the signals in the first clock data recovery path and the second clock data recovery path are different.

[0012] In a first variant of this second implementation, the circuit configured to compare the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path may include: an XOR circuit having a corresponding signal from each of the first clock data recovery path and the second clock data recovery path as input, and the circuit configured to adjust the polarities of the signals in the first clock data recovery path and the second clock data recovery path when the polarities of the signals in the first clock data recovery path and the second clock data recovery path are different; the circuit may include: at least one multiplexer controlled by the output of the XOR circuit.

[0013] In a second variant of this second implementation, the injection-locked oscillator may include a ring oscillator having a transistor configured to receive the output of the edge detector and to connect two opposite poles of the ring oscillator components together upon receiving a pulse in the output of the edge detector.

[0014] A third variant of the second implementation may further include a delay line on the data input at the demultiplexer to compensate for clock recovery delay in the injected locked oscillator.

[0015] A method for operating a short-range data link receiver according to an implementation of the subject matter of the present invention, the short-range data link receiver comprising: an edge detector configured to generate a pulse on an edge of a data input; a first clock data recovery path coupled to the output of the edge detector for recovering a clock from the output of the edge detector; and a second clock data recovery path coupled to the output of the edge detector for recovering a clock from the output of the edge detector, the method comprising: using a first path of the first clock data recovery path and the second clock data recovery path to recover the clock from the output of the edge detector; using the first path of the first clock data recovery path and the second clock data recovery path to recover data from the data input using the recovered clock; and calibrating a second path of the first clock data recovery path and the second clock data recovery path while using the first path of the first clock data recovery path and the second clock data recovery path.

[0016] A first implementation of this method may further include: exchanging the first path and the second path of the first clock data recovery path and the second clock data recovery path at predetermined time intervals.

[0017] A first variant of the first implementation may further include: selecting the predetermined time interval as at most equal to the operation duration, during which temperature drift will cause the first path of the first clock data recovery path and the second clock data recovery path to lose calibration.

[0018] In a second variant of the first implementation, the swap may include: swapping the first path of the first clock data recovery path with the second path of the second clock data recovery path whenever calibration of the second path of the first clock data recovery path and the second clock data recovery path is completed.

[0019] A second variant of the first implementation may include: immediately after swapping the first clock data recovery path and the second clock data recovery path, initiating calibration of the next path to be calibrated in the first and second clock data recovery paths. Alternatively, a second variant of the first implementation may include: reducing power consumption by delaying the calibration of the next path to be calibrated in the first and second clock data recovery paths for a portion of the predetermined interval following the swapping of the first and second clock data recovery paths.

[0020] A second implementation of this method may further include: comparing the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path, and adjusting the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path when the corresponding polarities of the signals in the first clock data recovery path and the second clock data recovery path are different.

[0021] In a variant of this second implementation, comparing the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path may include performing an XOR operation on the corresponding signals from each of the first clock data recovery path and the second clock data recovery path, and adjusting the polarities of the signals in the first clock data recovery path and the second clock data recovery path when the corresponding polarities of the signals in the first clock data recovery path and the second clock data recovery path are different may include multiplexing the signals under the control of the output of the XOR operation.

[0022] A third implementation of this method may further include delaying the data input to compensate for clock recovery delay.

[0023] In a fourth implementation of this method, recovering the clock from the output of the edge detector using the first path of the first clock data recovery path and the second clock data recovery path may include: injecting a reference frequency into the output of the edge detector in the first path of the first clock data recovery path and the second clock data recovery path.

[0024] In a variant of this fourth implementation, calibrating the second path of the first clock data recovery path and the second clock data recovery path while using the first path of the first clock data recovery path and the second clock data recovery path may include calibrating the oscillator in the second path of the first clock data recovery path and the second clock data recovery path to the reference frequency. Attached Figure Description

[0025] Other features, nature, and various advantages of this disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which the same reference numerals throughout refer to the same parts, and in the drawings:

[0026] Figure 1 It is a block diagram of the various parts of a corresponding integrated circuit device for a corresponding transceiver used in a short-range data link that includes an implementation of the subject matter of this disclosure;

[0027] Figure 2 yes Figure 1 A schematic diagram illustrating the implementation of the receiver in the transceiver;

[0028] Figure 3 This is a schematic diagram of an injection-locked oscillator used in the implementation of the subject matter of this disclosure;

[0029] Figure 4 The figure shows Figure 2 Two different cases of the relative polarity of the signals in the two data paths of the receiver;

[0030] Figure 5 and Figure 6 It is used for regulation Figure 2 A schematic diagram of a circuit with different signal polarities between two data paths of a receiver;

[0031] Figure 7 It is shown Figure 2 Timing diagram of the operation of the two data paths of the receiver;

[0032] Figure 8 It is a timing diagram of the calibration operation; and

[0033] Figure 9 This is a flowchart illustrating the operation of a method for implementing the subject matter of this disclosure. Detailed Implementation

[0034] As noted above, short-range data links are suitable for use between different integrated circuit chips in certain scenarios, such as when different parts of a system are implemented on different integrated circuit chips. Furthermore, as mentioned above, the low channel loss in short-range data links allows for the use of ILO-based CDRs. However, for an ILO-based CDR to function correctly, the ratio of the free-running frequency (FRF) of the injected locked oscillator to the data rate must be kept constant. Otherwise, large FRF errors caused by PVT drift (especially temperature variations) will degrade tracking performance and make it difficult to support data patterns with long-term continuous identical digits (CID).

[0035] Some known ILO-based CDR solutions use a phase-locked loop (PLL) and an ILO for frequency tracking. However, this solution requires a significant amount of additional die area and increases power consumption.

[0036] Other known ILO-based CDR solutions use a phase detector (PD) to estimate the FRF error. The falling edge of the data is used for injection, and the rising edge of the data is used for FRF error sampling. However, the residual phase error sampled by the phase detector consists of three components:

[0037] ΔPtot =ΔP FRF_ERR +ΔP DCD +ΔP ISI

[0038] Where ΔP tot It is the total phase difference, ΔP FRF_ERR It is the integral of the FRF error, ΔP DCD It's due to data duty cycle distortion, plus the sampling setup time difference between the rising and falling edges, and ΔP ISI This refers to inter-symbol interference (ISI) between the injected data edge and the FRF error sampling data edge. Because the phase difference includes components other than the FRF error, using phase detection to measure the FRF error can lead to poor FRF tracking accuracy. Such an implementation might be able to support, for example, PRBS9 8-bit / 10-bit modes, but not random data modes with long-term CIDs.

[0039] For designs requiring phase drift due to FRF error to be no more than 10% of the unit interval (UI) after 100 CIDs, an FRF tracking accuracy better than 1,000 parts per million (ppm) is required.

[0040] According to implementations of the subject matter of this disclosure, transceivers for short-range data links include receiver structures using ILO-based CDRs with two injection-locked paths. One injection-locked path operates in clock data recovery mode, while the other operates in calibration mode, in which its oscillator is calibrated to a constant ratio with a reference clock, which (because the data rate is constant with the reference clock) is constant with the data rate. In some such implementations, the system is designed to switch paths after one path has operated in clock data recovery mode for no more than the duration of operation, based on a target frequency and a target margin for the FRF error (examples provided below). As discussed in more detail below, after the switch, the path already operating in calibration mode immediately switches to clock data recovery mode. However, calibration may take less time than the operation duration of each injection-locked path. Therefore, a path already operating in clock data recovery mode may not immediately enter calibration mode after ending operation in clock data recovery mode, but may instead enter an idle mode or low-power mode for a period of operation before entering calibration mode.

[0041] Figure 1Two integrated circuit devices are shown, each including a corresponding transceiver 100, and connected via a short-range data link incorporating an implementation of the subject matter of this disclosure. Each integrated circuit device includes a corresponding transceiver 100 and other operating circuitry (not shown). Each transceiver 100 includes a receiver 101 and a transmitter 102. A clock standard circuit 112 (as depicted, the clock standard is a PLL, but can be any other type of clock standard, such as a digital PLL or a delay-locked loop (DLL)) is provided to control the transmit clock / frequency of the transmitter 102. An (N+1) bit data signal 122 originating from the integrated circuit chip on which the transceiver 100 resides is input to the transmitter 102 and transmitted at 113 onto channel 103 of the short-range data link between the integrated circuit chips on which the corresponding transceiver 100 resides. Figure 1 As described, channel 103 uses differential signaling, but can also provide a single-ended channel.

[0042] Receiver 101 receives (N+1) bits of signal 123 on channel 103 and recovers data 121. The same reference clock signal 104 is provided to both clock standard circuit 112 and receiver 101. Receiver 101 does not require a clock / frequency signal from clock standard circuit 112 because it recovers the clock from signal 123 as part of an ILO-based CDR process. However, the reference clock is used as a timer to correct the oscillator FRF in receiver 101, as discussed below.

[0043] Based on the subject matter of this disclosure, Figure 2 The implementation 200 of receiver 101 is shown. Receiver 200 includes an analog front-end (AFE) 201 that converts the analog differential signal 123 into a digital data_in (DIN) signal 211. An edge detector 202 provides a pulse signal 212, wherein a pulse exists for each rising or falling edge of the DIN signal 211. The pulse signal 212 is input to each of two ILO-based CDR paths 203, 204. Each ILO-based CDR path 203, 204 includes a corresponding half-rate ILO 223, 224. By applying the corresponding INJ_DIS_PATHn (n = 1, 2) to the corresponding gates 213, 214, the corresponding gates 213, 214 are used to open or close the CDR operation in the corresponding ILO-based CDR path 203, 204.

[0044] At any given time, one of the ILO-based CDR paths 203 and 204 will operate in clock data recovery mode. In clock data recovery mode, pulse signal 212 is input to the corresponding half-rate ILO 223 or 224, which in some implementations may have Figure 3The structure 300 seen in the diagram includes a corresponding two-stage ring oscillator 301 and a corresponding transistor switch 302. When pulse signal 212 equals "0", the two-stage ring oscillator 301 operates as a voltage-controlled oscillator. Increasing or decreasing the oscillator supply voltage VDD of the ring oscillator 301 will increase or decrease the FRF of the ring oscillator 301 (FRF calibration is discussed below). At the occurrence of each pulse, a pulse of pulse signal 212 is injected into the corresponding switch 302, causing the two tracks 313, 323 of the corresponding ring oscillator 301 to short-circuit together, ultimately causing the corresponding ILOs 223, 224 to be injected and locked to the clock of DIN signal 211.

[0045] The two-stage ILO 300 provides an ILO edge clock ECK1 / 2_RING locked to the rising or falling edge of the DIN signal 211 for each corresponding path 203, 204. A second ILO clock signal CCK1 / 2_RING, 90° out of phase with the ILO edge clock ECK1 / 2_RING, is also provided for sampling each corresponding path 203, 204, since data should be sampled in the middle between the rising and falling edges, rather than on the rising and falling edges.

[0046] The following will be combined. Figure 5 and Figure 6Following the corresponding clock multiplexers CLK_MUX_1 (233) and CLK_MUX_2 (234) that describe their functions, the corresponding ILO clock signals CCK1 / 2_PATH1 and CCK1 / 2_PATH2 can be used to sample the DATA signal 221 in the corresponding demultiplexers DEMUX1_1 (243) and DEMUX1_2 (244). The DATA signal 221 is the DIN signal 211, which is delayed by the delay line 205 to take into account the time for deriving CCK1 / 2_PATH1 and CCK1 / 2_PATH2 (in this implementation, these signals, specified as "1 / 2", are differential signals) by the corresponding ILOs 223 and 224. Because sampling occurs based on rising and falling edges, the corresponding demultiplexers DEMUX1_1 (243) and DEMUX1_2 (244) have two-bit input signals, which are demultiplexed into corresponding four-bit signals DOUT_PATH1[3:0](253) and DOUT_PATH2[3:0](254) in the implementation shown. The multiplexer DATA_MUX (206) selects the appropriate one of signals 253 and 254 as the output signal DOUT[3:0](226) based on which path 203 or 204 indicated by signal DOUT_PATH_SEL (216) is in CDR operation mode. In the implementation shown, the second demultiplexer DEMUX2 (207) demultiplexes the four-bit signal 226 into a 20-bit output signal DOUT[19:0](217).

[0047] When controller 208 releases the INJ_DIS_PATH1 disable signal and selects path 203 using the DOUT_PATH_SEL signal 216, the ILO-based CDR path 203 is active. When controller 208 releases the INJ_DIS_PATH2 disable signal and selects path 204 using the DOUT_PATH_SEL signal 216, the ILO-based CDR path 204 is active. The following will combine... Figure 7 The timing implementation of the exchange between paths 203 and 204 is discussed. However, during any path exchange, it may be necessary to adjust the polarity of the signal in the activated path to match the polarity of the signal in the deactivated path to avoid discontinuities, as described below.

[0048] like Figure 4As shown, in case 1 or case 2, paths 203 and 204 can operate according to the conditions when pulse signal 212 closes switch 302. In case 1, CCK1_RING2, CCK2_RING2, ECK1_RING2, and ECK2_RING2 have the same polarity as CCK1_RING1, CCK2_RING1, ECK1_RING1, and ECK2_RING1. In case 2, CCK1_RING2, CCK2_RING2, ECK1_RING2, and ECK2_RING2 have the opposite polarity to CCK1_RING1, CCK2_RING1, ECK1_RING1, and ECK2_RING1. If case 2 is true, then when a path exchange occurs, there will be a 180° phase difference between paths with opposite polarities. To prevent this phase shift discontinuity during path switching, clock multiplexers CLK_MUX_1 (233) and CLK_MUX_2 (234) are used to adjust the polarity of the signal in the path 203, 204 that is about to enter active CDR mode. Each clock multiplexer CLK_MUX_1 (233) and CLK_MUX_2 (234) has CCK1 signals from its own path (CCK1_PATH1 or CCK1_PATH2, respectively) and from another path (CCK1_PATH2 or CCK1_PATH1, respectively) as inputs, which are used to sense the polarity. Each clock multiplexer CLK_MUX_1(233) and CLK_MUX_2(234) also has CCK1_RING and CCK2_RING signals as inputs from its own paths (i.e., CCK1_RING_PATH1 and CCK2_RING_PATH1, or CCK1_RING_PATH2 and CCK2_RING_PATH2, respectively), which outputs with different polarities depending on the polarity sensed using the CCK1 signal.

[0049] Specifically, Figure 5An implementation 500 of CLK_MUX_1(233) is shown, which corrects the polarity in path 203 when path 203 is about to enter active CDR mode. Before switching the DOUT_PATH_SEL signal 216 to path 203 and establishing INJ_DIS_PATH2 to shut down path 204, controller 208 de-establishes INJ_DIS_PATH1 to allow path 203 to produce output, and then establishes the path 203 polarity detection enable signal EN_CLK_POL_DET_PATH1 to turn on CLK_MUX_1(233). At XOR gate 501, CCK1_PATH2 is compared with CCK1_PATH1. If CCK1_PATH2 is the same as CCK1_PATH1, the CLK_SWAP signal 502 remains low. Therefore, the CLK_SWAP signal 502 will not cause the trigger 506 to switch, so the CLK_POL_SEL signal 503 will retain its value, and the selection of multiplexers 504 and 505 will not change. If CCK1_PATH2 is different from CCK1_PATH1, the CLK_SWAP signal 502 goes high, causing the trigger 506 to switch, which changes the polarity of the CLK_POL_SEL signal 503, causing multiplexers 504 and 505 to swap the polarities of CCK1_PATH1 and CCK2_PATH1 to match the polarities of CCK1_PATH2 and CCK2_PATH2. At this time, the DOUT_PATH_SEL signal 216 is set to path 203 and INJ_DIS_PATH2 is established to turn off path 204.

[0050] Similarly, Figure 6An implementation 600 of CLK_MUX_2(234) is shown, which corrects the polarity in path 204 when path 204 is about to enter active CDR mode. Before switching the DOUT_PATH_SEL signal 216 to path 204 and establishing INJ_DIS_PATH1 to shut down path 203, controller 208 de-establishes INJ_DIS_PATH2 to allow path 204 to produce output, and then establishes the path 204 polarity detection enable signal EN_CLK_POL_DET_PATH2 to turn on CLK_MUX2(234). At XOR gate 501, CCK1_PATH2 is compared with CCK1_PATH1. If CCK1_PATH2 is the same as CCK1_PATH1, the CLK_SWAP signal 502 remains low. Therefore, the CLK_SWAP signal 502 will not cause the trigger 506 to switch, so the CLK_POL_SEL signal 503 will retain its value, and the selection of multiplexers 504 and 505 will not change. If CCK1_PATH2 is different from CCK1_PATH1, the CLK_SWAP signal 502 goes high, causing the trigger 506 to switch, which changes the polarity of the CLK_POL_SEL signal 503, causing multiplexers 504 and 505 to swap the polarities of CCK1_PATH2 and CCK2_PATH2 to match the polarities of CCK1_PATH1 and CCK2_PATH1. At this time, the DOUT_PATH_SEL signal 216 is set to path 204, and INJ_DIS_PATH1 is established to turn off path 203.

[0051] Figure 7 The timing of the operation and path exchange for each path 203, 204 in CDR operation mode is shown, as well as the timing of the background oscillator FRF calibration for the path 203, 204 that is not in operation. In implementations where background oscillator FRF calibration does not need to be as long as the operation duration, it can be expected that the path of the operation in paths 203, 204 has drifted after the operation duration.

[0052] like Figure 7As shown, from time t0 to time t2, path 1 203 is in normal CDR operation mode. The duration from time t0 to time t2 is equal to the operation duration determined based on the target frequency and target margin of the FRF error (see below). However, the background oscillator FRF calibration of one of paths 203 and 204 can be completed during the duration from time t1 to time t2. Therefore, the background oscillator FRF calibration of path 2 204 is performed between time t1 and time t2. When the required calibration time is less than the normal operation period, then between time t0 and time t1, path 2 204 is turned off (i.e., in low-power mode), which is achieved by the controller 208 releasing the ring oscillator enable signal VCOEN_PATH2, so that the ring oscillator 224 is neither used for CDR operation mode nor for calibration. However, there may be implementations where the background oscillator FRF calibration of one path takes longer, and therefore occurs during the entire time the other path is in CDR operation mode.

[0053] Once the background oscillator FRF calibration of path 2 204 is completed at time t2, path 2 204 is immediately selected for CDR operating mode to prevent delay before path 2 204 has a chance to begin drifting. Path 2 204 operates in CDR operating mode from time t2 to time t4. In the implementation shown, the background oscillator FRF calibration of path 1 203 is performed between time t3 and time t4. Between time t2 and time t3, path 1 203 is turned off (i.e., in low-power mode), which is achieved by controller 208 deactivating the ring oscillator enable signal VCOEN_PATH1, so that ring oscillator 223 is neither used for CDR operating mode nor for calibration.

[0054] In addition, when the system is powered on for the first time, both ring oscillators 223 and 224 are calibrated before either of the CDR paths 203 and 204 begins operation.

[0055] To calibrate either ring oscillator 223 or 224, the corresponding INJ_DIS_PATH1 / INJ_DIS_PATH2 signals are established to disconnect the corresponding ring oscillator 223 or 224 from the injection of pulse signal 212. At startup, both signals INJ_DIS_PATH1 and INJ_DIS_PATH2 are established. Therefore, disconnected from pulse signal 212, the calibrated oscillator or ring oscillator operates freely at the oscillator FRF determined by VDD (…). Figure 3 The oscillator FRF can be compared with the signal derived from the reference clock 104, and VDD can be adjusted to adjust the oscillator FRF so that the oscillator FRF has the desired relationship with the reference clock 104.

[0056] Figure 8 An example 800 of the actions during a background calibration operation is shown. In this case, the example is a background oscillator FRF calibration of path 2 204 performed between time t1 and time t2. However, a background oscillator FRF calibration of path 1 203 performed between time t3 and time t4 is similar. In this example, the signals on path 2 204 are shown as solid lines, while the signals on path 1 203 are shown as dashed lines.

[0057] In this example of calibration operation 800, path 2 204 to be calibrated is already in low-power mode. Therefore, at the start of operation 800, the ring oscillator enable signal VCOEN_PATH2 for path 2 is low, but is established to allow ring oscillator 224 to produce output. During this time, path 1 203 is operating, so the ring oscillator enable signal VCOEN_PATH1 for path 1 is high. However, at the end of operation 800, after path 2 204 has started operating and path 1 203 has stopped operating, the ring oscillator enable signal VCOEN_PATH1 for path 1 goes low. Note that in implementations where calibration takes longer and therefore low-power mode is not present, both ring oscillator enable signals VCOEN_PATH1 and VCOEN_PATH2 will remain high.

[0058] After VCOEN_PATH2 is established to allow ring oscillator 224 to generate output, the INJ_DIS_PATH2 signal is established to disconnect ring oscillator 224 from the injection of pulse signal 212. Thus disconnected from pulse signal 212, ring oscillator 224 operates freely at the oscillator FRF determined by VDD, which is adjusted until the oscillator FRF is calibrated to the reference clock. The INJ_DIS_PATH2 signal is de-established to reconnect ring oscillator 224 to pulse signal 212, and by injection locking, the intersection of ECK1_RING2 signals (323) and ECK2_RING2 signals (313) will be aligned with the midpoint of pulse signal 212. Next, the path 204 polarity detection enable signal EN_CLK_POL_DET_PATH2 is established, so that the polarity of path 204 signals can be reversed if needed, as combined with the above. Figure 6 (and for path 1 203 in) Figure 5As described in (the Chinese text). At this point, path 2 204 is ready to operate, and DOUT_PATH_SEL is set to path 2 204 to select path 2 204 at DATA_MUX206 to swap paths. As noted above, at some point after the swap, in this example where calibration occurs quickly enough to allow low-power mode, the ring oscillator enable signal VCOEN_PATH1 for path 1 goes low to turn off ring oscillator 223.

[0059] According to the method 900 for implementing the subject matter of this disclosure, Figure 9 The diagram illustrates the process. At 901, the first path of the first clock data recovery path and the second clock data recovery path is used to recover the clock from the output of the edge detector. Then, at 902, the first path of the first clock data recovery path and the second clock data recovery path is used to recover data from the data input using the recovered clock. At 903, while the first path of the first clock data recovery path and the second clock data recovery path are used to recover the clock from the output of the edge detector and recover data from the data input, the second path of the first clock data recovery path and the second clock data recovery path are calibrated. At 904, at predetermined time intervals, the first path of the first clock data recovery path and the second path of the second clock data recovery path are swapped, and the process returns to 901 and 903.

[0060] Therefore, it can be seen that a receiver structure using an ILO-based CDR is provided, which has two injection-locked paths to maintain calibration, so that the ratio of the free-running frequency (FRF) of the injection-locked oscillator to the data rate can be kept constant.

[0061] As used herein and in the appended claims, the construction of "one of A and B" should mean "A or B". It should be understood that the foregoing is merely illustrative of the principles of the invention, and the invention can be practiced in ways other than those described, which are presented for illustrative purposes and not for limitation, and the invention is limited only by the appended claims.

Claims

1. A short-range data link receiver, comprising: An edge detector is configured to generate pulses on the edges of the data input; A first clock data recovery path is coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; A second clock data recovery path is coupled to the output of the edge detector for recovering the clock and data from the output of the edge detector. and The controller is configured to alternate between the first clock data recovery path and the second clock data recovery path to recover the clock and data using the first path of the pair of the first clock data recovery path and the second clock data recovery path, while calibrating the second path of the pair of the first clock data recovery path and the second clock data recovery path; The controller is further configured to exchange the first path of the first clock data recovery path and the second clock data recovery path, and the second path of the first clock data recovery path and the second clock data recovery path, at a predetermined time interval. as well as The predetermined time interval is selected to be at most equal to the operation duration, during which temperature drift will cause the first path of the first clock data recovery path and the second clock data recovery path to lose calibration, wherein the operation duration is determined based on the target frequency and the target margin of the frequency error of the first clock data recovery path and the second clock data recovery path.

2. The short-range data link receiver of claim 1, wherein the controller is configured to swap the first path of the first clock data recovery path and the second path of the second clock data recovery path, and the second path of the first clock data recovery path and the second clock data recovery path, whenever calibration of the second path of the first clock data recovery path and the second clock data recovery path is completed.

3. The short-range data link receiver of claim 2, wherein the controller is configured to immediately begin calibration of the next path to be calibrated in the first clock data recovery path and the second clock data recovery path after exchanging the first clock data recovery path and the second clock data recovery path.

4. The short-range data link receiver of claim 2, wherein the controller is configured to delay the calibration of the next path to be calibrated in the first clock data recovery path and the second clock data recovery path for a portion of the predetermined time interval following the exchange of the first clock data recovery path and the second clock data recovery path.

5. The short-range data link receiver according to claim 1, wherein each corresponding path in the first clock data recovery path and the second clock data recovery path comprises: An injection-locked oscillator is configured to recover the clock by injecting a reference frequency locked to the output of the edge detector; and A demultiplexer is configured to operate on the data input and the recovered clock to recover the data.

6. The short-range data link receiver of claim 5, wherein each of the first clock data recovery path and the second clock data recovery path further includes circuitry configured to compare the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path, and to adjust the corresponding polarities of the signals in the first clock data recovery path and the second clock data recovery path when the corresponding polarities of the signals in the first clock data recovery path and the second clock data recovery path are different.

7. The short-range data link receiver according to claim 6, wherein: The circuit configured to compare the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path includes an XOR circuit having a corresponding signal from each of the first clock data recovery path and the second clock data recovery path as input; as well as The circuit configured to adjust the polarity of the signals in the first clock data recovery path and the second clock data recovery path when the polarities of the signals in the first clock data recovery path and the second clock data recovery path are different includes at least one multiplexer controlled by the output of the XOR circuit.

8. The short-range data link receiver of claim 5, wherein the injection-locked oscillator comprises a ring oscillator having a transistor configured to receive the output of the edge detector and to connect two opposite poles of the ring oscillator components together after receiving a pulse in the output of the edge detector.

9. The short-range data link receiver of claim 5, further comprising a delay line at the data input of the multiplexer to compensate for clock recovery delay in the injected locked oscillator.

10. A method of operating a short-range data link receiver, the short-range data link receiver comprising: an edge detector configured to generate a pulse on an edge of a data input; and a first clock data recovery path coupled to the output of the edge detector for recovering a clock from the output of the edge detector; and a second clock data recovery path, coupled to the output of the edge detector, for recovering the clock from the output of the edge detector, the method comprising: The clock is recovered from the output of the edge detector using the first path of the first clock data recovery path and the second clock data recovery path; Data is recovered from the data input using the recovered clock via the first path of the first clock data recovery path and the second clock data recovery path; While using the first path of the first clock data recovery path and the second clock data recovery path, calibrate the second path of the first clock data recovery path and the second clock data recovery path; The first path in the first clock data recovery path and the second clock data recovery path, and the second path in the first clock data recovery path and the second clock data recovery path are exchanged at predetermined time intervals. The predetermined time interval is selected to be at most equal to the operation duration, during which temperature drift will cause the first path of the first clock data recovery path and the second clock data recovery path to lose calibration, wherein the operation duration is determined based on the target frequency and the target margin of the frequency error of the first clock data recovery path and the second clock data recovery path.

11. The method of claim 10, wherein the exchange comprises: Whenever the calibration of the second path in the first clock data recovery path and the second clock data recovery path is completed, the first path in the first clock data recovery path and the second path in the second clock data recovery path are swapped.

12. The method of claim 11, comprising: After swapping the first clock data recovery path and the second clock data recovery path, calibration of the next path to be calibrated in the first clock data recovery path and the second clock data recovery path shall begin immediately.

13. The method of claim 11, comprising: Power consumption is reduced by delaying the calibration of the next path to be calibrated in the first and second clock data recovery paths for a portion of the predetermined time interval after the first and second clock data recovery paths are swapped.

14. The method of claim 10, further comprising: The polarities of the signals in the first clock data recovery path and the second clock data recovery path are compared, and when the polarities of the signals in the first clock data recovery path and the second clock data recovery path are different, the polarities of the signals in the first clock data recovery path and the second clock data recovery path are adjusted.

15. The method of claim 14, wherein: Comparing the corresponding polarities of signals in the first clock data recovery path and the second clock data recovery path includes: performing an XOR operation on the corresponding signals from each of the first and second clock data recovery paths; and When the polarities of the signals in the first clock data recovery path and the second clock data recovery path are different, adjusting the polarities of the signals in the first clock data recovery path and the second clock data recovery path includes: multiplexing the signals under the control of the output of the XOR operation.

16. The method of claim 10, further comprising: The data input is delayed to compensate for clock recovery delay.

17. The method of claim 10, wherein using the first path of the first clock data recovery path and the second clock data recovery path to recover the clock from the output of the edge detector comprises: In the first path of the first clock data recovery path and the second clock data recovery path, the reference frequency is injected and locked to the output of the edge detector.

18. The method of claim 17, wherein calibrating the second path of the first clock data recovery path and the second clock data recovery path while using the first path of the first clock data recovery path and the second clock data recovery path comprises: The oscillator in the second path of the first clock data recovery path and the second clock data recovery path is calibrated to the reference frequency.

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