Clock and data recovery circuit and source driver comprising the same

Abstract

A clock and data recovery circuit is disclosed. The clock and data recovery circuit can include a clock recovery unit configured to output a recovered clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit according to a phase difference between the recovered clock signal and a clock of an input signal, and a data recovery unit configured to sample data from the input signal and output recovered data.

Description

Technical Field

[0001] This disclosure relates to display devices, and more specifically, to a clock and data recovery circuit capable of easily recovering clock and data during high-speed operation, and a source driver including the clock and data recovery circuit. Background Technology

[0002] Typically, a display device may include a display panel, a source driver, a timing controller, etc.

[0003] The source driver converts the image data provided by the timing controller into a data voltage and supplies the data voltage to the display panel. Source drivers can be integrated as a chip and multiple can be configured in the display panel, taking into account the screen size and resolution.

[0004] The source driver may include clock and data recovery circuitry for recovering clock signals and data. This clock and data recovery circuitry is used to receive input signals from the timing controller, in which the clock has been embedded in the data, and to recover the clock signals and data from the input signals.

[0005] Typical clock and data recovery circuits may include bang-bang phase detectors, and the phase of the clock signal can be controlled by using bang-bang phase detectors.

[0006] However, if conventional clock and data recovery circuits are used to recover data transmitted at high speeds, the jitter characteristics of the bang-bang phase detector may degrade. Furthermore, the problem with conventional clock and data recovery circuits is that the circuitry is complex due to the mixture of digital and analog circuitry, and the chip area increases due to passive components. Summary of the Invention

[0007] Various implementations relate to providing clock and data recovery circuitry capable of easily recovering clock signals and data during high-speed operation, and a source driver including the clock and data recovery circuitry.

[0008] In an implementation, the clock and data recovery circuit may include a clock recovery unit and a data recovery unit. The clock recovery unit is configured to perform a first time-to-digital conversion or a second time-to-digital conversion on the first phase difference based on whether the first phase difference between the recovered clock signal and the clock of the input signal is greater than a preset reference phase difference, and output a recovered clock signal, a first clock signal, and a second clock signal corresponding to the first time-to-digital conversion or the second time-to-digital conversion. The second phase difference between the first clock signal and the recovered clock signal is different from the third phase difference between the second clock signal and the recovered clock signal. The data recovery unit is configured to sample data from the input signal using the first clock signal and the second clock signal and output recovered data.

[0009] In an implementation, the source driver may include: a clock and data recovery circuit configured to generate a recovered clock signal and recovered data from an input signal; and a data driving circuit configured to generate a data voltage using the recovered clock signal and recovered data, and to provide the data voltage to a display panel. The clock and data recovery circuit may include: a first time-to-digital converter configured to receive an input signal having a clock training mode and output a first digital signal corresponding to a first phase difference between the recovered clock signal and the clock of the input signal; a second time-to-digital converter configured to receive an input signal in which the clock has been embedded in the data and output a second digital signal corresponding to the first phase difference; a digital loop filter configured to output a control signal corresponding to the first digital signal or the second digital signal; and a digitally controlled oscillator configured to output a recovered clock signal, a first clock signal, and a second clock signal having a phase controlled in response to the control signal, wherein the second phase difference between the first clock signal and the recovered clock signal is different from a third phase difference between the second clock signal and the recovered clock signal.

[0010] According to the implementation, since a time-to-digital converter circuit capable of comparing the clock signal of the recovery clock signal with the clock of the input signal is used, the clock signal and data can be easily recovered even in the operation of recovering high-speed transmitted data.

[0011] Furthermore, according to the implementation method, digital circuitry is used to implement the circuitry for recovering clock signals and data. Therefore, its configuration can be simplified, and it can facilitate scalability for process changes.

[0012] Furthermore, according to the implementation, since the clock signal and the clock of the input signal can be compared and recovered even when the position of the clock changes according to the protocol of the input signal, the clock embedded in the data can be easily recovered. Attached Figure Description

[0013] Figure 1 This is a block diagram of the clock and data recovery circuit according to the implementation method.

[0014] Figure 2 This is a flowchart describing the operation of the clock and data recovery circuit according to an embodiment.

[0015] Figure 3 yes Figure 1 The circuit diagram of the sampler shown is shown.

[0016] Figure 4 This is a block diagram showing an example of a time-to-digital conversion circuit.

[0017] Figure 5 yes Figure 4The block diagram of the second time-to-digital converter circuit shown is shown.

[0018] Figure 6 The timing diagram of the recovery clock signal and the clock of the input signal is shown.

[0019] Figure 7 A timing diagram showing a comparison between the phases of the recovered clock signal and a first clock signal having a phase difference of 0.5 UI relative to the recovered clock signal is shown.

[0020] Figure 8 It is used to describe Figure 5 The flowchart shown illustrates the operation of the second time-to-digital converter circuit.

[0021] Figure 9 yes Figure 5 The circuit diagram of the flip-flop array shown is shown.

[0022] Figure 10 This is a circuit diagram showing a time-to-digital converter. Detailed Implementation

[0023] The implementation may provide a clock and data recovery circuit capable of easily recovering clock and data during high-speed operation, and a source driver including the clock and data recovery circuit.

[0024] Implementations may provide a time-to-digital converter circuit for clock and data recovery circuitry, and a source driver including the time-to-digital converter circuit.

[0025] In the early stages of operation, an input signal is provided to have a clock training mode, followed by data in which a clock is already embedded. The clock training mode refers to a clock pattern that includes a clock for recovery. An input signal with a clock training mode can be provided during a clock training cycle set in the early stages of operation to stabilize the clock signal, etc.

[0026] In the implementation, it is understood that the clock and data recovery circuit can receive an input signal with a clock training mode in the early stages of operation, and after the coarse locking stabilizes within a preset range, the clock and data recovery circuit compares the recovered clock signal with the clock of the input signal and receives an input signal with data in which the clock has been embedded. Image data and control data may be included in the data.

[0027] Coarse locking can be enabled when the time difference between the recovered clock signal and the input signal's clock is equal to or less than the reference time, and coarse locking can be disabled when the time difference between the recovered clock signal and the input signal's clock is greater than the reference time. In this case, the recovered clock signal can be limited to a clock signal recovered using the input signal's clock.

[0028] As described above, time difference refers to the phase difference between the recovered clock signal and the clock of the input signal. In the following text, it can be understood that phase difference corresponds to time difference. A reference time difference can be understood as a reference phase difference. For example, assuming one period of the recovered clock signal comprises two unit intervals (2UI) and the duty cycle of the recovered clock signal is 50:50, in embodiments of this disclosure, the reference phase difference can be set to 0.5UI. It can be understood that a reference phase difference of 0.5UI corresponds to a phase difference of 90°.

[0029] Furthermore, it can be understood that coarse locking is enabled when the phase difference between the recovery clock signal and the input signal clock is equal to or less than the reference phase difference of 0.5UI, and coarse locking is disabled when the phase difference between the recovery clock signal and the input signal clock is greater than the reference phase difference of 0.5UI.

[0030] In an implementation, a coarse cycle can be defined to align the clocks of the recovery clock signal and the input signal such that when the phase difference is greater than the reference phase difference, the clocks of the recovery clock signal and the input signal have a phase difference within the reference phase difference.

[0031] In an implementation, a fine cycle can be defined to align the clocks of the recovered clock signal and the input signal such that when the phase difference is equal to or less than the reference phase difference, the clocks of the recovered clock signal and the input signal have a smaller phase difference within the reference phase difference.

[0032] In implementation, terms such as first and second may be used to distinguish various elements. These elements are not limited by terms such as first and second.

[0033] Figure 1 This is a block diagram of the clock and data recovery circuit 100 according to the embodiment.

[0034] The clock and data recovery circuit 100 may include a clock recovery unit 110 and a data recovery unit 120.

[0035] The clock recovery unit 110 is configured to perform a first time-to-digital conversion or a second time-to-digital conversion on the phase difference based on whether the phase difference between the recovered clock signal and the clock of the input signal DIN is greater than a preset reference phase difference.

[0036] Furthermore, the clock recovery unit 110 is configured to output a recovered clock signal, a first clock signal, and a second clock signal corresponding to the first time-to-digital conversion or the second time-to-digital conversion. In this case, preferably, the phase difference between the first clock signal and the recovered clock signal is different from the phase difference between the second clock signal and the recovered clock signal.

[0037] In addition, the data recovery unit 120 is configured to sample data from the input signal DIN using a first clock signal and a second clock signal and output the recovered data R_DATA.

[0038] The clock recovery unit 110 can receive the input signal DIN and can generate a recovery clock signal corresponding to the phase of the clock of the input signal DIN, a first clock signal having a phase difference of 0.5UI relative to the recovery clock signal, and a second clock signal having a phase difference of 1.5UI relative to the recovery clock signal. For the purpose of describing the implementation, the recovery clock signal is represented as CK0°, the first clock signal is represented as CK90°, and the second clock signal is represented as CK270°.

[0039] The clock recovery unit 110 may include a first time-to-digital converter (CTDC) for a first time-to-digital conversion and a second time-to-digital converter (DTDC) for a second time-to-digital conversion. The CTDC and DTDC can be operated such that they are alternately enabled and disabled in response to a coarse lock signal C_LOCK.

[0040] For example, when the phase difference between the recovery clock signal and the clock of the input signal DIN is greater than the reference phase difference of 0.5UI, the level of the coarse lock signal C_LOCK can be switched to a low logic level to disable coarse lock. In this case, the first time-to-digital converter (CTDC) is enabled, and the second time-to-digital converter (DTDC) is disabled.

[0041] Furthermore, when the phase difference between the recovery clock signal and the clock of the input signal DIN is equal to or less than the reference phase difference of 0.5UI, the level of the coarse lock signal C_LOCK can be shifted to a high logic level to enable coarse lock. In this case, the first time-to-digital converter (CTDC) is disabled, and the second time-to-digital converter (DTDC) is enabled.

[0042] The clock recovery unit 110 can output a recovery clock signal CK0°, a first clock signal CK90°, and a second clock signal CK270°, which have an oscillation frequency and phase controlled by using the first digital signal COUT of the first time-to-digital converter circuit CTDC or the second digital signal DOUT of the second time-to-digital converter circuit DTDC.

[0043] In this configuration, the recovered clock signal CK0° can be fed back to the first time-to-digital converter (CTDC) and the second time-to-digital converter (DTDC). Furthermore, the first clock signal CK90° can be fed back to the second time-to-digital converter (DTDC). Feeding back the recovered clock signal CK0° and the first clock signal CK90° can be used to align the phases of the recovered clock signal CK0° and the clock of the input signal DIN.

[0044] The first clock signal CK90° and the second clock signal CK270° can be provided to the data recovery unit 120 and can be used to recover data from the input signal DIN.

[0045] The clock recovery unit 110 may include a first time-to-digital converter (CTDC), a second time-to-digital converter (DTDC), a digital cyclic filter (40), a digitally controlled oscillator (50), and a clock divider (30).

[0046] The first-time digital converter (CTDC) can receive the input signal DIN from the timing controller and output a first digital signal COUT corresponding to the phase difference between the recovery clock signal and the clock of the input signal DIN. The timing controller can send the input signal DIN, including a clock training mode, in the early stages of operation.

[0047] When the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is greater than the reference phase difference of 0.5UI, the first time-to-digital converter circuit CTDC can be used as a coarse loop to align the clocks of the recovery clock signal CK0° and the input signal DIN.

[0048] The first-time digital conversion circuit CTDC can be operated to reduce the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN to within a reference phase difference of 0.5UI through phase alignment. The first-time digital conversion circuit CTDC can be disabled by the coarse lock signal C_LOCK when the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is equal to or less than the reference phase difference of 0.5UI.

[0049] When the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is equal to or less than the reference phase difference of 0.5UI through the first time-to-digital converter circuit CTDC, the second time-to-digital converter circuit DTDC can be enabled by the coarse lock signal C_LOCK.

[0050] The second time-to-digital converter (DTDC) can receive an input signal DIN containing data with an embedded clock from the timing controller, and can output a second digital signal DOUT corresponding to the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN.

[0051] The second time-to-digital converter circuit (DTDC) can be used as a fine loop to align the clock of the recovery clock signal CK0° and the clock of the input signal DIN, so that the clock of the recovery clock signal CK0° and the clock of the input signal DIN have a smaller phase difference within a reference phase difference of 0.5UI.

[0052] When the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is greater than the reference phase difference of 0.5UI, or when no clock is detected in the input signal DIN, the second time-to-digital converter (DTDC) can be disabled by the coarse lock signal C_LOCK, or it can output a second digital signal DOUT that retains the previous value. The case where no clock is detected in the input signal DIN corresponds to the case where continuous data holds logic "0" and no clock shift occurs.

[0053] The second time-to-digital converter circuit DTDC can receive the recovery clock signal CK0° and the first clock signal CK90° from the digitally controlled oscillator 50, and can output the second digital signal DOUT when the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is equal to or less than the phase difference between the recovery clock signal CK0° and the first clock signal CK90°.

[0054] When the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is greater than the phase difference between the recovery clock signal CK0° and the first clock signal CK90°, the second time-to-digital converter (DTDC) can output a second digital signal DOUT that retains its previous value. This corresponds to the case where the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is greater than a reference phase difference of 0.5UI.

[0055] The digital loop filter 40 can convert the first digital signal COUT or the second digital signal DOUT into a control signal VCON with an input range in which the digitally controlled oscillator 50 can operate, and can provide the control signal VCON to the digitally controlled oscillator 50.

[0056] The digitally controlled oscillator 50 can generate recovery clock signals CK0°, a first clock signal CK90°, and a second clock signal CK270° with different phases by controlling the oscillation frequency and phase in response to the control signal VCON.

[0057] Clock divider 30 can provide the first-time digital converter (CTDC) with a divided clock signal obtained by dividing the recovered clock signal CK0° by the division ratio N. In this case, N is a natural number, and the value of N can be determined according to the protocol configured between the timing controller and the source driver. Clock divider 30 can increase the output frequency and decrease the comparison frequency.

[0058] The first-time digital converter circuit CTDC can output a first digital signal COUT corresponding to the phase difference between the divided clock signal and the clock of the input signal.

[0059] The data recovery unit 120 can sample image data from the input signal DIN using a first clock signal CK90° and a second clock signal CK270°, and can provide the recovered image data R_DATA to the data drive circuit 130. The data drive circuit 130 can convert the recovered image data R_DATA into a data voltage and provide the data voltage to the display panel.

[0060] The data recovery unit 120 may include a sampler 10 and a series-parallel circuit 20.

[0061] Sampler 10 can receive input signal DIN, can sample odd-numbered data DATA_ODD in response to first clock signal CK90°, and can sample even-numbered data DATA_EVEN in response to second clock signal CK270°.

[0062] The series-parallel circuit 20 can respond to the first clock signal CK90° and the second clock signal CK270° respectively to convert the serial odd-numbered data DATA_ODD and the serial even-numbered data DATA_EVEN into parallel data, and output the parallel data as the recovered image data R_DATA.

[0063] The source driver may include clock and data recovery circuitry 100 and data drive circuitry 130.

[0064] The source driver can receive an input signal DIN from the timing controller, which has a clock training mode or data in which a clock is already embedded.

[0065] In this configuration, the clock and data recovery circuit 100 can recover the clock signal and data from the input signal DIN and can provide the clock signal and data to the data drive circuit 130.

[0066] The data driving circuit 130 can convert image data into data voltage and provide the data voltage to the display panel.

[0067] Figure 2This is a flowchart describing the operation of the clock and data recovery circuit 100 according to an embodiment.

[0068] First, when the power is turned on, the value of the division ratio N of the clock divider 30 can be determined according to the preset protocol (S10).

[0069] The first-time digital conversion circuit (CTDC) can receive the input signal DIN(S20) with clock training mode in the early stages of operation.

[0070] Furthermore, the recovery clock signal CK0° of the digitally controlled oscillator 50 can be input to the first time-to-digital converter circuit CTDC (S30). In this case, the recovery clock signal CK0° can be a divided clock signal that has been divided by the clock divider 30, and can be input to the first time-to-digital converter circuit CTDC.

[0071] The first-time digital conversion circuit (CTDC) can be operated as a coarse loop for phase alignment.

[0072] The first-time digital conversion circuit CTDC compares the recovered clock signal CK0°, which is input in the form of a divided clock signal, with the clock of the input signal DIN (S30).

[0073] When the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is equal to or less than the reference phase difference of 0.5UI, a coarse lock can be generated in the first-time digital conversion circuit CTDC (S35). In this case, the generation of the coarse lock means the activation of the coarse lock. The level of the coarse lock signal C_LOCK is moved to a high logic level.

[0074] Furthermore, when coarse locking occurs, the first time-to-digital converter (CTDC) can be disabled and its operation can be stopped, and the value of the first digital signal COUT of the CTDC can be fixed. Combined with the operation of the first time-to-digital converter (CTDC), the second time-to-digital converter (DTDC) can be enabled and operated (S40).

[0075] More specifically, the first time-to-digital converter (CTDC) can be disabled when the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is equal to or less than the reference phase difference of 0.5UI through phase alignment. In this case, the second time-to-digital converter (DTDC) can be enabled.

[0076] In addition, the second time-to-digital converter circuit DTDC can receive an input signal DIN(S50) containing data in which a clock has already been embedded.

[0077] The second time-to-digital converter circuit DTDC compares the recovered clock signal CK0° with the clock signal of the input signal DIN (S60).

[0078] When the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is equal to or less than the reference phase difference of 0.5UI, the second time-to-digital converter circuit DTDC can convert this phase difference into a second digital signal DOUT (S70).

[0079] In this case, when the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is greater than the reference phase difference of 0.5UI, the second time-to-digital converter circuit DTDC can output a second digital signal DOUT (S70) that retains the previous value.

[0080] In addition, when the clock is not detected in the input signal DIN, the second time-to-digital converter circuit DTDC can output a second digital signal DOUT that retains the previous value.

[0081] Furthermore, sampler 10 can sample odd-numbered data DATA_ODD in response to the first clock signal CK90°, and can sample even-numbered data DATA_EVEN in response to the second clock signal CK270° (S80).

[0082] Furthermore, the series-parallel circuit 20 can convert the serial odd-numbered data DATA_ODD and the serial even-numbered data DATA_EVEN into parallel data in response to the first clock signal CK90° and the second clock signal CK270° respectively, and can output the recovered image data R_DATA (S90).

[0083] Figure 3 yes Figure 1 The circuit diagram of sampler 10 shown is shown.

[0084] The sampler 10 may include a first D flip-flop (D-FF) 12 and a second D flip-flop (D-FF) 14.

[0085] The first D flip-flop 12 can receive an input signal DIN with data in which a clock has been embedded, and can output data DATA_ODD with an odd number of the input signal DIN in response to a first clock signal CK90°.

[0086] The second D flip-flop 14 can receive an input signal DIN with data in which a clock has been embedded, and can output data DATA_EVEN with an even number of the input signal DIN in response to the second clock signal CK270°.

[0087] Figure 4This is a block diagram of the time-to-digital conversion circuit 35 of the clock and data recovery circuit 100 according to the embodiment.

[0088] The time-to-digital converter circuit 35 may include a first time-to-digital converter circuit CTDC, a second time-to-digital converter circuit DTDC, and a multiplexer 42.

[0089] refer to Figure 1 Understandable Figure 4 The operation of the first time-to-digital converter circuit CTDC and the second time-to-digital converter circuit DTDC is described, but their detailed description is omitted.

[0090] Multiplexer 42 can be configured to select the first digital signal COUT when the coarse lock signal C_LOCK is disabled, select the second digital signal DOUT when the coarse lock signal C_LOCK is enabled, and output the selected digital signal to digital loop filter 40 as digital signal SOUT.

[0091] Figure 4 The time-to-digital conversion circuit 35 is shown as including a multiplexer 42. For another example, the multiplexer 42 may be included in... Figure 1 In the digital loop filter 40.

[0092] Figure 5 yes Figure 4 The block diagram of the second time-to-digital converter circuit DTDC shown is illustrated.

[0093] The second time-to-digital converter (DTDC) circuit may include a first time-to-digital converter (TDC1), a second time-to-digital converter (TDC2), a comparator (60), a flip-flop array (70), and an encoder (80).

[0094] The first time-to-digital converter TDC1 can output a digital value corresponding to the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN, that is, the first output signal OUT1.

[0095] The second time-to-digital converter TDC2 can output a digital value corresponding to the phase difference between the recovery clock signal CK0° and the first clock signal CK90°, i.e., the second output signal OUT2.

[0096] Comparator 60 can compare the values ​​of the first output signal OUT1 and the second output signal OUT2, and can output a digital value, i.e., the comparison signal COMP, based on the comparison result.

[0097] For example, when the value of the first output signal OUT1 (i.e., the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN) is equal to or less than the value of the second output signal OUT2 (i.e., the phase difference between the recovery clock signal CK0° and the first clock signal CK90°), the comparator 60 can output an enabled comparator signal COMP.

[0098] The trigger array 70 can update and store the first output signal OUT1 in response to the enabled comparison signal COMP, and can output the updated value as the trigger signal FOUT in response to the disabled comparison signal COMP, or can output the unupdated trigger signal FOUT that retains the previous value.

[0099] For example, when the value of the first output signal OUT1 is equal to or less than the value of the second output signal OUT2, the flip-flop array 70 can output the nth first output signal OUT1 as the nth flip-flop signal FOUT in response to the enabled comparison signal COMP.

[0100] Conversely, when the value of the first output signal OUT1 is greater than the value of the second output signal OUT2, the flip-flop array 70 can respond to the disabled comparison signal COMP to hold the (n-1)th first output signal OUT1 and output the (n-1)th first output signal OUT1 as the nth flip-flop signal FOUT.

[0101] Encoder 80 can convert the trigger signal FOUT into a second digital signal DOUT.

[0102] Therefore, encoder 80 can convert the trigger signal FOUT, which corresponds to the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN, into a second digital signal DOUT.

[0103] As described above, when the value of the first output signal OUT1 is equal to or less than the value of the second output signal OUT2, the second time-to-digital converter circuit DTDC can convert the first output signal OUT1 into the second digital signal DOUT.

[0104] Furthermore, when the value of the first output signal OUT1 is greater than the value of the second output signal OUT2, the second time-to-digital converter (DTDC) can output a second digital signal DOUT that retains the previous value.

[0105] For example, when the value of the nth first output signal OUT1 is greater than the value of the second output signal OUT2, the second time-to-digital converter circuit DTDC can output the nth second digital signal DOUT that maintains the value of the (n-1)th second digital signal DOUT.

[0106] In addition, when the clock is not detected in the input signal DIN, the second time-to-digital converter circuit DTDC can output a second digital signal DOUT that retains the previous value.

[0107] Figure 6 The timing diagram for the recovery clock signal CK0° and the input signal DIN is shown.

[0108] refer to Figure 6 The clock signal DIN can be periodically input. The phase of the restored clock signal CK0° and the clock signal DIN can be aligned by the coarse cycle operation of the first time-to-digital converter circuit CTDC and the fine cycle operation of the second time-to-digital converter circuit DTDC.

[0109] In this situation, when the clock is not detected in the input signal DIN, the time-to-digital converter 35 can maintain the previous value of the second digital signal DOUT, so that neither coarse nor fine loop operation is performed.

[0110] For example, when the clock is not detected in the nth input signal DIN, the time-to-digital converter 35 can retain the value of the nth second digital signal DOUT as the value of the (n-1)th second digital signal DOUT.

[0111] This is to prevent the output of the digitally controlled oscillator 50 from changing, because when the difference between the recovery clock signal CK0° and the clock of the input signal DIN is not determined, the output of the time-to-digital converter 35 becomes the maximum value.

[0112] Figure 7 The timing diagrams for the recovery clock signal CK0° and the first clock signal CK90° are shown.

[0113] Figure 7 The phase difference between the recovery clock signal CK0° and the first clock signal CK90° is shown as a reference phase difference of 0.5UI.

[0114] The second time-to-digital converter (DTDC) can restore the phase difference between the clock signal CK0° and the clock signal DIN, and... Figure 7 The fixed phase difference between the recovery clock signal CK0° and the first clock signal CK90° shown is compared.

[0115] Figure 8 It is used to describe Figure 5 A flowchart of the operation of the time-to-digital converter circuit 35.

[0116] refer to Figure 8When the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN is equal to or less than the reference phase difference of 0.5UI, the second time-to-digital converter circuit DTDC (S11) can be operated.

[0117] The second time-to-digital converter TDC2 can convert a reference phase difference of 0.5UI corresponding to the phase difference between the recovery clock signal CK0° and the first clock signal CK90° into a digital value, and can output the digital value as the second output signal OUT2 (S12).

[0118] The first-time digital converter TDC1 can convert the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN into a digital value, and can output the digital value as the first output signal OUT1 (S13).

[0119] Comparator 60 can compare the values ​​of the first output signal OUT1 and the second output signal OUT2, and can output a comparison signal COMP (S14) based on the comparison result.

[0120] When the value of the first output signal OUT1 is equal to or less than the value of the second output signal OUT2, comparator 60 can output the comparison signal COMP in the enabled state (i.e., at a high logic level). When the value of the first output signal OUT1 is greater than the value of the second output signal OUT2, comparator 60 can output the comparison signal COMP in the disabled state (i.e., at a low logic level).

[0121] The trigger array 70 can respond to the comparison signal COMP to update the first output signal OUT1 and output the updated value as the trigger signal FOUT, or it can output the trigger signal FOUT that retains the previous value (S15).

[0122] The encoder 80 can output a second digital signal DOUT (S16) obtained by converting the number of "H" in the trigger signal FOUT into a binary number.

[0123] Therefore, encoder 80 can convert the phase difference between the recovery clock signal CK0° and the clock of the input signal DIN into a second digital signal DOUT.

[0124] Figure 9 yes Figure 5 The circuit diagram of the flip-flop array 70 shown is shown.

[0125] The flip-flop array 70 may include D flip-flops D-FF corresponding to the output signals OUT1[0] to OUT1[n], respectively.

[0126] The D flip-flop (D-FF) can update its output signals OUT1[0] to OUT1[n] in response to the comparator signal COMP, and output the updated flip-flop signal FOUT, or it can output the flip-flop signal FOUT that retains its previous value. When the value of the first output signal OUT1 is equal to or less than the value of the second output signal OUT2, the level of the comparator signal COMP, which is a high logic level, can be input to control the update of the D flip-flop (D-FF) and the output of the flip-flop signal FOUT. Furthermore, when the value of the first output signal OUT1 is greater than the value of the second output signal OUT2, the level of the comparator signal COMP, which is a low logic level, can be input to control the output of the flip-flop signal FOUT and the retention of the previous value of the D flip-flop (D-FF).

[0127] Figure 10 This is the circuit diagram of a Time-to-Digital Converter (TDC).

[0128] refer to Figure 10 The time-to-digital converter (TDC) can output output signals OUT[0] to OUT[n] corresponding to the phase difference between the signals input to the reference terminal REF and the feedback terminal FEB, respectively.

[0129] For example, the time-to-digital converter (TDC) can output the output signals OUT[0] to OUT[n] as "HHHLLLLL..." or "LLLHHHHH..." depending on which signal has an earlier phase between the signals input to the reference terminal REF and the feedback terminal FEB.

[0130] In this case, the number of "H"s can be determined as "HHHLLLLL....", where H is located sequentially from the least significant bit (LSB). The encoder 80 can convert the bits corresponding to the number of "H"s into binary numbers.

[0131] As described above, the clock and data recovery circuit according to this embodiment, as well as the source driver including the clock and data recovery circuit, can use a time-to-digital converter circuit capable of comparing the recovered clock signal with the clock of the input signal, thereby enabling easy recovery of the clock and data even during high-speed data transmission operations.

[0132] Furthermore, according to the implementation method, since the circuit is implemented as a digital circuit, the circuit can be simplified, and it can facilitate the flexibility of process changes.

[0133] Furthermore, according to the implementation, since clock signals and data can be compared even if the position of the clock changes according to the protocol, the clock embedded in the data can be recovered.

Claims

1. Clock and data recovery circuitry, including: A clock recovery unit is configured to perform a first time-to-digital conversion or a second time-to-digital conversion on the first phase difference based on whether the first phase difference between the recovered clock signal and the clock of the input signal is greater than a preset reference phase difference, and output the recovered clock signal, the first clock signal, and the second clock signal corresponding to the first time-to-digital conversion or the second time-to-digital conversion, wherein the second phase difference between the first clock signal and the recovered clock signal is different from the third phase difference between the second clock signal and the recovered clock signal; and The data recovery unit is configured to sample data from the input signal using the first clock signal and the second clock signal and output recovered data. The clock recovery unit includes: A first-time digital conversion circuit is configured to output a first digital signal corresponding to the first phase difference when the first phase difference is greater than the reference phase difference. The second time-to-digital converter circuit is configured to output a second digital signal corresponding to the first phase difference when the first phase difference is equal to or less than the reference phase difference.

2. The clock and data recovery circuit according to claim 1, wherein, The clock recovery unit includes: A digital loop filter, configured to output a control signal corresponding to either the first digital signal or the second digital signal; and A digitally controlled oscillator configured to output the recovered clock signal, the first clock signal, and the second clock signal, each having a phase controlled in response to the control signal.

3. The clock and data recovery circuit according to claim 2, wherein, When the first phase difference is equal to or less than the reference phase difference, the first time-to-digital conversion circuit is disabled.

4. The clock and data recovery circuit according to claim 2, wherein, When the first phase difference is equal to or less than the reference phase difference, the second time-to-digital conversion circuit is activated.

5. The clock and data recovery circuit according to claim 4, wherein, When the clock is not detected in the input signal, the second time-to-digital converter outputs the second digital signal that retains the previous value.

6. The clock and data recovery circuit according to claim 2, wherein, Second time-to-digital converter circuit Receive the input signal, the recovery clock signal, and the first clock signal, and When the first phase difference is equal to or less than the second phase difference, the second digital signal is output.

7. The clock and data recovery circuit according to claim 6, wherein, When the first phase difference is greater than the second phase difference, the second time-to-digital converter outputs the second digital signal that retains the previous value.

8. The clock and data recovery circuit according to claim 2, further comprising: A clock divider is configured to provide the first time-to-digital converter with a divided clock signal obtained by dividing the recovered clock signal by a division ratio N, where N is a natural number. The first time-to-digital converter outputs a first digital signal corresponding to the first phase difference between the frequency-divided clock signal and the clock of the input signal.

9. The clock and data recovery circuit according to claim 2, wherein: The first time-to-digital converter and the second time-to-digital converter receive a coarse locking signal. When the first phase difference is equal to or less than the reference phase difference, the coarse locking signal is activated. In response to the disabling of the coarse locking signal, the first time-to-digital conversion circuit is enabled and the second time-to-digital conversion circuit is disabled. In response to the activation of the coarse locking signal, the first time-to-digital conversion circuit is disabled and the second time-to-digital conversion circuit is enabled.

10. The clock and data recovery circuit according to claim 1, wherein, The data recovery unit includes a sampler configured to receive the input signal, control a first sampling of odd-numbered data in response to a first clock signal, and control a second sampling of even-numbered data in response to a second clock signal.

11. The clock and data recovery circuit according to claim 10, wherein, The data recovery unit further includes a series-parallel circuit, which is configured to convert the sampled odd-numbered data and even-numbered data into parallel data in response to the first clock signal and the second clock signal, respectively, and output the parallel data as the recovered data.

12. Source driver, including: The clock and data recovery circuit is configured to generate a recovery clock signal and recover data from the input signal; as well as The data driving circuit is configured to generate a data voltage using the recovery clock signal and the recovery data, and to provide the data voltage to the display panel. The clock and data recovery circuit includes: A first-time digital conversion circuit is configured to receive the input signal having a clock training mode and output a first digital signal corresponding to a first phase difference between the recovered clock signal and the clock of the input signal. The second time-to-digital converter circuit is configured to receive the input signal in which the clock has been embedded in the data, and to output a second digital signal corresponding to the first phase difference; A digital loop filter, configured to output a control signal corresponding to either the first digital signal or the second digital signal; and A digitally controlled oscillator is configured to output a recovered clock signal, a first clock signal, and a second clock signal having a phase controlled in response to the control signal, wherein a second phase difference between the first clock signal and the recovered clock signal is different from a third phase difference between the second clock signal and the recovered clock signal.

13. The source driver according to claim 12, wherein, When the first phase difference is equal to or less than the preset reference phase difference, the first time-to-digital conversion circuit is disabled.

14. The source driver according to claim 12, wherein, When the first phase difference is equal to or less than the preset reference phase difference, the second time-to-digital conversion circuit is activated.

15. The source driver according to claim 14, wherein, When the clock is not detected in the input signal, the second time-to-digital converter outputs the second digital signal that retains the previous value.

16. The source driver according to claim 12, wherein, Second time-to-digital converter circuit Receive the input signal, the recovery clock signal, and the first clock signal, and When the first phase difference is equal to or less than the second phase difference, the second digital signal is output.

17. The source driver according to claim 16, wherein, When the first phase difference is greater than the second phase difference, the second time-to-digital converter outputs the second digital signal that retains the previous value.

18. The source driver according to claim 12, further comprising: A clock divider is configured to provide the first time-to-digital converter with a divided clock signal obtained by dividing the recovered clock signal by a division ratio N, where N is a natural number. The first time-to-digital converter outputs a first digital signal corresponding to the first phase difference between the frequency-divided clock signal and the clock of the input signal.

19. The source driver according to claim 12, further comprising: The sampler is configured to receive the input signal, control a first sampling of odd-numbered data in response to a first clock signal, and control a second sampling of even-numbered data in response to a second clock signal.

20. The source driver according to claim 19, further comprising: A series-parallel circuit is configured to convert the sampled odd-numbered data and even-numbered data into parallel data in response to the first clock signal and the second clock signal, respectively, and output the parallel data as the recovered data.

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