A clock data recovery circuit and a method of preventing lock-up or non-lock-up thereof

Abstract

The application discloses a clock data recovery circuit and a method for preventing false locking or non-locking of the clock data recovery circuit. The method uses a locking detector in the clock data recovery circuit to judge four kinds of information, i.e. clock advance, clock lag, clock error 1 and clock error 2, detected by a phase detector in the clock data recovery circuit, so that whether the input data rate of the current clock recovery circuit matches the sampling clock can be effectively judged. When the input data rate is high, the clock data recovery circuit is prevented from running off-center and being non-locked, and when the input data rate is low, the clock data recovery circuit is prevented from being false-locked. Meanwhile, the upper protocol layer is rapidly informed. Compared with a traditional speed negotiation mechanism based on the upper protocol layer, the efficiency is improved, and the clock data recovery circuit is effectively prevented from being non-locked.

Description

TECHNICAL FIELD

[0001] The present application relates to a clock recovery circuit, in particular to a clock data recovery circuit and a method for preventing the clock data recovery circuit from being locked or unlocked. BACKGROUND

[0002] With the continuous progress of integrated circuit technology, various high-speed serial interface specifications such as SATA (Serial Advanced Technology Attachment) are constantly upgraded, and the interface rate is constantly improved. From the initial 1.0 specification (1.5 Gbps), 2.0 specification (3 Gbps) to the current 3.0 specification (6 Gbps). Although the specification interface rate is constantly improved, each generation of specification must be downward compatible, such as SATA 3.0 devices must be downward compatible with SATA 2.0 and SATA 1.0 devices. Thus, in practical applications, there is inevitably a problem that the speed levels supported by the SATA host and the SATA slave are inconsistent, and when they are interconnected, speed negotiation must be performed.

[0003] The clock data recovery circuit is widely used in the receiving end of the high-speed serial interface to extract clock information from the input serial data stream and to retime (recover) the data. Figure 1 For the traditional phase interpolation-based clock data recovery circuit (half-rate architecture), clk0 and clk180 in the four-phase sampling clock are data bit edge sampling clocks, and clk90 and clk270 are data bit center sampling clocks. When the loop is locked, the rising edges of clk0 and clk180 are aligned with the data bit edges, and the rising edges of clk90 and clk270 are aligned with the data bit centers. The data sampled by clk90 and clk270 is the re-timed (recovered) data.

[0004] When the input data rate matches the four-phase sampling clock frequency (the frequency difference is very small, generally less than 1 / 1000), the phase detector compares the phase relationship between the input data transition edge and the four-phase sampling clock to obtain clock advance or clock lag information. The loop filter filters the clock advance or clock lag information to control the phase interpolator to shift the phase of the four-phase sampling clock. Finally, when the clock advance and clock lag information are uniformly distributed in a certain time, it can be considered that the loop is locked.

[0005] When the input data rate does not match the frequency of the four-phase sampling clock, if the SATA host is a 3.0 specification device (6Gbps) and the SATA slave is a 2.0 specification device (3Gbps). For the clock data recovery circuit of the host (assuming a half-rate architecture, i.e. the normal sampling clock frequency is half of the input data rate), the input data rate is 3Gbps, and the local four-phase sampling clock is 3GHz, which is equivalent to each bit of input data being sampled twice. In this case, the loop can still obtain useful clock advance or clock lag information from the edge transition of the input data, and the loop can be locked, but the re-timed data is incorrect (each bit is sampled twice), i.e. the clock data recovery circuit is mislocked at this time. Usually, this situation is determined by the protocol upper layer according to the recovered data content to determine that an error has occurred, and then the local clock frequency is reduced to the next level to complete speed negotiation. If the mislock is determined by the clock data recovery circuit, the protocol upper layer is directly notified, which can obviously improve the efficiency.

[0006] When the input data rate does not match the frequency of the four-phase sampling clock, if the SATA host is a 2.0 specification device (3Gbps) and the SATA slave is a 3.0 specification device (6Gbps). For the clock data recovery circuit of the host (assuming a half-rate architecture, i.e. the normal sampling clock frequency is half of the input data rate), the input data rate is 6Gbps, and the local four-phase sampling clock is 1.5GHz, which is equivalent to 1 bit of every 2 consecutive bits of input data not being sampled. At this time, the clock advance or clock lag information is incorrect, the loop cannot be locked, and instead the stored frequency deviation in the loop digital filter of the clock data recovery circuit of the SATA host can run to the boundary (the boundary value is generally designed to exceed the maximum frequency deviation allowed by the clock data recovery circuit). Since the loop cannot be locked, in this case, the protocol upper layer usually negotiates to control the SATA slave to switch to the next speed level, such as from 6Gbps mode to 3Gbps mode in this example. However, at this time, the stored frequency deviation in the loop digital filter of the clock data recovery circuit of the SATA host has run to the boundary, and even when the input data (3Gbps) matches the speed, the loop is difficult to recover to normal, and thus the speed negotiation fails. If this non-locking condition is determined by the clock data recovery circuit, the protocol upper layer is directly notified, and the clock data recovery circuit is forcibly reset, which can avoid the problem of speed negotiation failure. SUMMARY

[0007] The purpose of the present application is to overcome the shortcomings of the prior art and provide a clock data recovery circuit and a method for preventing mislock or non-lock of the clock data recovery circuit

[0008] To achieve the above-mentioned purpose, the technical solution of the present application is:

[0009] In a first aspect, the present application provides a method for preventing false lock or no lock of a clock data recovery circuit, comprising the following steps:

[0010] The clock data recovery circuit is reset and then released, and the clock data recovery circuit works again;

[0011] The phase detector samples the input data by using the four-phase sampling clock, and determines which one of the clock leading, the clock lagging, the clock error 1 and the clock error 2 the phase relationship between the input data and the sampling clock belongs to;

[0012] The lock detector analyzes the continuous Nbit determination results output by the phase detector, and counts the number of bits of the clock error 1 and the number of bits of the clock error 2 which appear continuously;

[0013] If the number of bits of the clock error 1 which appear continuously exceeds Mbit, the lock detector determines that the input data rate is higher than the sampling clock frequency, and then resets the clock data recovery circuit once, and the clock data recovery circuit works again after being released, and the protocol upper layer is informed at the same time;

[0014] If the number of bits of the clock error 2 which appear continuously exceeds Mbit, the lock detector determines that the input data rate is lower than the sampling clock frequency, and then resets the clock data recovery circuit once, and the clock data recovery circuit works again after being released, and the protocol upper layer is informed at the same time;

[0015] If the number of bits of the clock error 1 which appear continuously or the number of bits of the clock error 2 which appear continuously does not exceed Mbit, the lock detector counts the number of bits of the clock leading and the number of bits of the clock lagging in a period of time, and when the difference between them is within a set range, a loop lock indication signal is given, and the protocol upper layer is informed at the same time;

[0016] N and M are integers and M < N.

[0017] Further, the clock error 1 refers to the case that one of the two continuous bits is not sampled by the data bit center clock.

[0018] Further, the clock error 2 refers to the case that one bit is sampled twice by the data bit center clock.

[0019] Further, N is 20 and M is 6.

[0020] In a second aspect, the present application provides a clock data recovery circuit, comprising a phase-locked loop, a phase interpolator, a phase detector, a digital filter and a lock detector,

[0021] The phase detector is used for comparing the phase of the edge of the input data and the four-phase sampling clock, and outputting four kinds of phase information of the clock leading, the clock lagging, the clock error 1 and the clock error 2.

[0022] When the input data rate and the quadrature sampling clock frequency match, the clock advance and clock lag information is valid, the digital filter outputs the phase control signal after filtering, the phase-locked loop outputs the quadrature clock with fixed frequency and phase according to the reference clock, the phase interpolator interpolates the quadrature clock according to the phase control signal to adjust the phase of the quadrature sampling clock, when the sampling clock clk0 and clk180 are aligned with the data bit edge, the sampling clock clk90 and clk270 are aligned with the data bit center, the data sampled by clk90 and clk270 is the re-timed data, at this time, the clock advance information and the clock lag information output by the phase detector balance in a period, at this time, the lock detector outputs the lock signal and notifies the upper protocol layer at the same time;

[0023] When the input data rate is higher than the quadrature sampling clock frequency, the clock error 1 information output by the phase detector is valid at this time, the lock detector analyzes the continuous Nbit judgment results output by the phase detector, if the number of bits with continuous clock error 1 is more than Mbit, the lock detector determines that the input data rate is higher than the sampling clock frequency, then resets the clock data recovery circuit once, and after the reset is released, the clock data recovery circuit starts to work again, and at the same time, the upper protocol layer is notified;

[0024] When the input data rate is lower than the quadrature sampling clock frequency, the clock error 2 information output by the phase detector is valid at this time, the lock detector analyzes the continuous Nbit judgment results output by the phase detector, if the number of bits with continuous clock error 2 is more than Mbit, the lock detector determines that the input data rate is lower than the sampling clock frequency, at this time, the clock data recovery circuit is mislocked, then resets the clock data recovery circuit once, and after the reset is released, the clock data recovery circuit starts to work again, and at the same time, the upper protocol layer is notified;

[0025] N and M are integers and M is less than N.

[0026] Further, the input data rate higher than the quadrature sampling clock frequency means that the input data rate is more than twice the quadrature sampling clock frequency, and the input data rate lower than the quadrature sampling clock frequency means that the input data rate is less than half the quadrature sampling clock frequency.

[0027] Compared with the prior art, the present application has the beneficial effects that:

[0028] The method for preventing the clock data recovery circuit from being locked or unlocked in the application adopts the lock detector in the clock data recovery circuit to judge the clock advance, clock lag, clock error 1 and clock error 2 information detected by the phase detector in the clock data recovery circuit, which can effectively judge whether the input data rate of the current clock recovery circuit matches the sampling clock, prevent the clock data recovery circuit from being unlocked when the input data rate is high, prevent the clock data recovery circuit from being locked when the input data rate is low, and quickly inform the upper protocol layer. Compared with the traditional speed negotiation mechanism based on the upper protocol layer, the efficiency is improved and the clock data recovery circuit is effectively prevented from being unlocked. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is a traditional clock data recovery circuit principle diagram based on phase interpolation;

[0030] Figure 2 It is a flow chart of the method for preventing the clock data recovery circuit from being locked or unlocked provided by the embodiment of the application;

[0031] Figure 3 It is a clock data recovery circuit principle diagram provided by the embodiment of the application;

[0032] Figure 4 It is an example of the phase detector outputting the clock advance information when the input data rate matches the four-phase sampling clock frequency;

[0033] Figure 5 It is an example of the phase detector outputting the clock lag information when the input data rate matches the four-phase sampling clock frequency;

[0034] Figure 6 It is an example of the phase detector outputting the clock error 1 information when the input data rate is higher than the four-phase sampling clock frequency;

[0035] Figure 7 It is an example of the phase detector outputting the clock error 2 information when the input data rate is lower than the four-phase sampling clock frequency. DETAILED DESCRIPTION

[0036] Embodiment:

[0037] The technical solutions of the application will be further described below in combination with the drawings and embodiments.

[0038] Referring to Figure 2 The method for preventing the clock data recovery circuit from being locked or unlocked provided by the embodiment mainly includes the following steps:

[0039] Step 1: The clock data recovery circuit is reset and released, and the clock data recovery circuit works;

[0040] Step 2: the phase detector samples the input data with a four-phase sampling clock, and determines which of the following four kinds of phase relationship between the input data and the sampling clock: clock leading, clock lagging, clock error 1, and clock error 2;

[0041] Step 3: the lock detector analyzes the continuous 20-bit judgment results (each bit judgment result is one of the following four kinds: clock leading, clock lagging, clock error 1, and clock error 2) output by the phase detector, and counts the number of bits of the continuous clock error 1 and the number of bits of the continuous clock error 2;

[0042] Step 4-1: if the number of bits of the continuous clock error 1 exceeds 6 bits, the lock detector determines that the input data rate is higher than the sampling clock frequency, at this time the clock data recovery circuit may be skewed and unable to lock, so the clock data recovery circuit is reset once, and after the reset is released, it starts to work again, and the protocol upper layer is notified at the same time;

[0043] Step 4-2: if the number of bits of the continuous clock error 2 exceeds 6 bits, the lock detector determines that the input data rate is lower than the sampling clock frequency, at this time the clock data recovery circuit may be mislocked, so the clock data recovery circuit is reset once, and after the reset is released, it starts to work again, and the protocol upper layer is notified at the same time;

[0044] Step 4-3: if the number of bits of the continuous clock error 1 or the number of bits of the continuous clock error 2 does not exceed 6 bits, the lock detector counts the number of clock leading bits and the number of clock lagging bits within a period of time, and when the difference between them is within a certain range, a loop locking indication signal is given, and the protocol upper layer is notified at the same time.

[0045] As can be seen, the method for preventing the clock data recovery circuit from being mislocked or unlocked, by using the lock detector in the clock data recovery circuit, determines the four kinds of information of clock leading, clock lagging, clock error 1, and clock error 2 detected by the phase detector in the clock data recovery circuit, which can effectively determine whether the input data rate of the current clock recovery circuit matches the sampling clock, prevent the clock data recovery circuit from being skewed and not locked when the input data rate is high, prevent the clock data recovery circuit from being mislocked when the input data rate is low, and quickly notify the protocol upper layer. Compared with the traditional speed negotiation mechanism based on the protocol upper layer, the efficiency is improved and the clock data recovery circuit is effectively prevented from being unlocked.

[0046] Figure 3 An example of a clock data recovery circuit using the above method is given, and the following will be described in combination with Figure 3 The above method is further described.

[0047] Figure 3In the clock data recovery circuit, the phase detector, the digital filter, the phase interpolator, the lock detector and the phase-locked loop are included. The basic working principle is as follows:

[0048] The phase detector compares the phase of the edge of the input data and the four-phase sampling clock, and outputs four kinds of phase information, i.e., clock advance, clock lag, clock error 1 and clock error 2.

[0049] When the input data rate and the four-phase sampling clock frequency match (the frequency difference is very small, generally less than 1 / 1000), the clock advance and clock lag information is valid, the digital filter outputs the phase control signal after filtering, the phase-locked loop outputs the four-phase clock with fixed frequency and phase according to the reference clock, and the phase interpolator interpolates the four-phase clock according to the phase control signal to adjust the phase of the four-phase sampling clock (clk0 / clk90 / clk180 / clk270). When the sampling clock clk0 and clk180 are aligned with the data bit edge, the sampling clock clk90 and clk270 are aligned with the data bit center, the data sampled by clk90 and clk270 is the re-timed (recovered) data, at this time, the clock advance information and the clock lag information output by the phase detector balance in a period, that is, the difference between the number of clock advance bits and the number of clock lag bits in a period is within a certain range, at this time, the lock detector outputs the lock signal and notifies the upper protocol layer at the same time.

[0050] When the input data rate is higher than the four-phase sampling clock frequency (here, the input data rate is more than twice the four-phase sampling clock frequency), at this time, the clock error 1 information output by the phase detector is valid, the lock detector analyzes the continuous 20-bit judgment result (each bit judgment result is one of clock advance, clock lag, clock error 1 and clock error 2) output by the phase detector, if the number of bits of continuous clock error 1 is more than 6 bits, the lock detector determines that the input data rate is higher than the sampling clock frequency, at this time, the clock data recovery circuit may be deviated and unable to lock, then the clock data recovery circuit is reset once, and after the reset is released, the work is restarted again, and the upper protocol layer is notified at the same time.

[0051] When the input data rate is lower than the four-phase sampling clock frequency (here, it refers to the input data rate is 1 / 2 of the four-phase sampling clock frequency or less), the clock error 2 information outputted by the phase detector is valid at this time, the lock detector analyzes the continuous 20bit judgment results (each bit judgment result is one of the clock advance, clock lag, clock error 1, clock error 2) outputted by the phase detector, if the number of bits of the continuous clock error 2 is counted, more than 6 bits, the lock detector determines that the input data rate is lower than the sampling clock frequency, at this time, the clock data recovery circuit will be mislocked, then the clock data recovery circuit is reset once, after the reset is released, it starts to work again, and informs the upper protocol layer at the same time.

[0052] Figure 4 An example is given when the input data rate matches the four-phase sampling clock frequency, the phase detector outputs the clock advance information.

[0053] Figure 5 An example is given when the input data rate matches the four-phase sampling clock frequency, the phase detector outputs the clock lag information.

[0054] The principle of the phase detector and the principle of outputting the clock advance and lag information will be explained below. Figure 4 Figure 5

[0055] Figure 4 Figure 5 In the above, Data_in is the input data (continuous 0, 1 transition, that is, clock data), clk0, clk90, clk180, clk270 are four-phase sampling clocks, data_clk0, data_clk90, data_clk180, data_clk270 are the sampling data of clk0, clk90, clk180, clk270 respectively. Define clk0, clk180 as the data bit edge clock, clk90, clk270 as the data bit center clock, then when the clock data recovery circuit loop is locked, clk0 and clk180 are aligned with the data bit edge, clk90 and clk270 are aligned with the data bit center.

[0056] Figure 4 In the above, data_clk90, data_clk180, data_clk270 are 0, 0, 1 respectively, which indicates that there is a data transition from 0 to 1 between clk90 and clk270, and clk180 leads the edge, that is, the clock advance.

[0057] Figure 5 ​​​In the figure, data_clk90, data_clk180, data_clk270 are 0, 1, 1 respectively, which indicates that there is a data jump from 0 to 1 between clk90 and clk270, and clk180 lags behind the edge, i.e. clock lag.

[0058] Figure 6 An example is given in which the phase detector outputs clock error 1 information when the input data rate is higher than the four-phase sampling clock frequency.

[0059] Figure 7 An example is given in which the phase detector outputs clock error 2 information when the input data rate is lower than the four-phase sampling clock frequency.

[0060] The principle of the phase detector and the principle of outputting clock error 1 and clock error 2 information will be explained below. Figure 6 、 Figure 7 The principle of the phase detector and the principle of outputting clock error 1 and clock error 2 information will be explained below.

[0061] Figure 6 、 Figure 7 In the figure, data_clk90, data_clk180, data_clk270 are 0, 1, 1 respectively, which indicates that there is a data jump from 0 to 1 between clk90 and clk270, and clk180 lags behind the edge, i.e. clock lag.

[0062] Figure 6 In the figure, data_clk90, data_clk180, data_clk270 are 0, 1, 1 respectively, which indicates that there is a data jump from 0 to 1 between clk90 and clk270, and clk180 lags behind the edge, i.e. clock lag.

[0063] Figure 7In the middle, data_clk90, data_clk180, data_clk270 are 0, 0, 0 respectively, which indicates that there is no data transition between clk90 and clk270, which is not consistent with the assumption that the input data is continuous 0, 1 transition. Obviously, the sampling clock frequency is unreasonable here, and is higher than the input data rate, and a bit is sampled twice by the data bit center clock clk90, clk270. Here, this situation is defined as clock error 2.

[0064] In order to prevent misjudgment, the lock detector analyzes the continuous 20-bit judgment results (each bit judgment result is one of clock advance, clock lag, clock error 1, clock error 2) output by the phase detector, and if the number of bits with continuous clock error 1 exceeds 6 bits or the number of bits with continuous clock error 2 exceeds 6 bits, the entire clock data recovery circuit is reset and starts working again, and the protocol upper layer is notified.

[0065] The above embodiments are only for illustrating the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and to implement it, and cannot limit the protection scope of the present application. Any equivalent changes or modifications made according to the essence of the present application should be covered within the protection scope of the present application.

Claims

1. A method for preventing clock data recovery circuits from accidentally locking or not locking, characterized in that, Includes the following steps: The clock data recovery circuit reset is released, and the clock data recovery circuit starts working; The phase detector samples the input data using a four-phase sampling clock and determines whether the phase relationship between the input data and the sampling clock belongs to clock lead, clock lag, clock error 1, or clock error 2. The lock detector analyzes the continuous N-bit judgment results output by the phase detector and counts the number of bits that continuously occur clock error 1 and the number of bits that continuously occur clock error 2. If the number of consecutive clock error 1 bits exceeds Mbit, the lock detector determines that the input data rate is higher than the sampling clock frequency, and resets the clock data recovery circuit once. After the reset is released, it restarts and notifies the upper layer of the protocol. If the number of consecutive clock errors 2 bits exceeds Mbit, the lock detector determines that the input data rate is lower than the sampling clock frequency, and resets the clock data recovery circuit once. After the reset is released, it restarts and notifies the upper layer of the protocol. If the number of consecutive clock error 1 bits or consecutive clock error 2 bits does not exceed Mbit, the lockout detector counts the number of clock ahead bits and clock lag bits within a certain period of time. When their difference is within the set range, a loop lockout indication signal is given, and the upper layer of the protocol is notified at the same time. N and M are integers and M < N; Clock error 1 refers to a situation where one of two consecutive bits is not sampled by the center clock of the data bit; Clock error 2 refers to a situation where a bit is sampled twice by the data bit center clock.

2. The method for preventing clock data recovery circuit from erroneously locking or not locking as described in claim 1, characterized in that, The value of N is 20.

3. The method for preventing clock data recovery circuit from erroneously locking or not locking as described in claim 1 or 2, characterized in that, The value of M is 6.

4. A clock data recovery circuit, comprising a phase-locked loop, a phase interpolator, a phase detector, a digital filter, and a lock detector, characterized in that, The phase detector is used to compare the edge of the input data with the phase of the four-phase sampling clock, and outputs four types of phase information: clock leading, clock lagging, clock error 1, and clock error 2. When the input data rate and the four-phase sampling clock frequency match, the clock lead and clock lag information are valid. The digital filter filters it and outputs a phase control signal. The phase-locked loop outputs a four-phase clock with a fixed frequency and phase according to the reference clock. The phase interpolator interpolates the four-phase clock according to the phase control signal to adjust the phase of the four-phase sampling clock. When the sampling clocks clk0 and clk180 are aligned with the edge of the data bit, the sampling clocks clk90 and clk270 are aligned with the center of the data bit. The data sampled by clk90 and clk270 is the retiming data. At this time, the clock lead and clock lag information output by the phase detector are balanced within a certain period of time. At this time, the lock detector outputs a lock signal and notifies the upper layer of the protocol. When the input data rate is higher than the four-phase sampling clock frequency, the clock error 1 information output by the phase detector is valid. The lock detector analyzes the continuous N-bit judgment results output by the phase detector. If the number of consecutive clock error 1 bits exceeds M bits, the lock detector determines that the input data rate is higher than the sampling clock frequency, and then resets the clock data recovery circuit once. After the reset is released, it starts working again and notifies the upper layer of the protocol. When the input data rate is lower than the four-phase sampling clock frequency, the clock error 2 information output by the phase detector is valid. The lock detector analyzes the continuous N-bit judgment results output by the phase detector. If the number of consecutive clock error 2 bits exceeds M bits, the lock detector determines that the input data rate is lower than the sampling clock frequency. At this time, the clock data recovery circuit will be falsely locked. The clock data recovery circuit will be reset once, and after the reset is released, it will start working again. At the same time, the upper layer of the protocol is notified. N and M are integers and M < N; Clock error 1 refers to a situation where one of two consecutive bits is not sampled by the center clock of the data bit; Clock error 2 refers to a situation where a bit is sampled twice by the data bit center clock.

5. The clock data recovery circuit as described in claim 4, characterized in that, The input data rate being higher than the four-phase sampling clock frequency means that the input data rate is more than twice the four-phase sampling clock frequency; the input data rate being lower than the four-phase sampling clock frequency means that the input data rate is less than half the four-phase sampling clock frequency.

6. The clock data recovery circuit as described in claim 4, characterized in that, N is 20 and M is 6.

Images