Phase-locked loop circuit and method of operation thereof, and sub-range control circuit
By introducing TDC, loop filter, DCO, feedback circuit, SDM and prediction circuit into the phase-locked loop circuit, and combining it with sub-range control circuit, the nonlinearity problem of traditional TDC circuit is solved, and higher resolution time interval and system stability are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MEDIATEK INC
- Filing Date
- 2021-11-08
- Publication Date
- 2026-05-29
AI Technical Summary
In the existing technology, traditional time-to-digital converters have nonlinearity problems and cannot meet the requirements of high-speed systems, especially the nonlinearity of the phase detector and the integral nonlinearity of the traditional TDC circuit.
By introducing a time-to-digital converter (TDC), loop filter, digitally controlled oscillator (DCO), feedback circuit, Σ-Δ modulator (SDM), and prediction circuit into the phase-locked loop circuit, combined with a sub-range control circuit, a phase detector and processing circuit are used to limit the voltage range, and the prediction circuit predicts the future voltage level and performs voltage folding, the nonlinearity problem of the analog-to-digital converter (ADC) is compensated.
Higher resolution time intervals were achieved, reducing nonlinearity issues in the phase-locked loop circuit and improving the system's accuracy and stability.
Smart Images
Figure CN114499504B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to phase-locked loop (PLL) circuits, and more specifically, to improvements on the nonlinearity problems caused by conventional time-to-digital converter (TDC) circuits in PLL circuits. Background Technology
[0002] Generally, conventional time-to-digital converter (TDC) circuits, such as R-interpolation TDCs or phase-shift TDCs, can reduce their performance (e.g., the average time interval corresponding to the resolution) to 0.9 picoseconds or 0.5 picoseconds. However, it is difficult to further reduce it to 0.3 picoseconds to meet the new requirements of high-speed systems. Furthermore, conventional TDCs suffer from integral nonlinearity (INL) problems caused by their phase detectors. Summary of the Invention
[0003] Therefore, one of the objectives of this invention is to provide a phase-locked loop (PLL) circuit, a sub-range control circuit, and a method for operating the PLL circuit to solve the above-mentioned problems.
[0004] According to an embodiment of the present invention, a phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a time-to-digital converter (TDC), a loop filter, a digitally controlled oscillator (DCO), a feedback circuit, a sum-Δ modulator (SDM), and a prediction circuit. The TDC includes a phase detector and a processing circuit. The phase detector generates a charging current signal based on an input frequency signal and a feedback signal. The processing circuit is coupled to the phase detector and limits the voltage level corresponding to the charging current signal within a specific voltage range based on the prediction signal to generate a digital output. The loop filter is coupled to the TDC and performs a low-pass filtering operation based on the digital output. The DCO is coupled to the loop filter and generates a DCO frequency signal based on the output of the loop filter. The feedback circuit is coupled to the DCO and the phase detector and generates a feedback signal based on the DCO frequency signal. The sum-Δ modulator (SDM) is coupled to the feedback circuit and generates a phase signal representing accumulated phase shift information to the prediction circuit based on information from the feedback circuit and fractional frequency information. The prediction circuit is coupled to the SDM and generates a prediction signal based on the phase signal.
[0005] According to an embodiment, a sub-range control circuit is disclosed. The sub-range control circuit is disposed between a charge pump and an analog-to-digital converter (ADC) in a phase-locked loop (PLL) circuit. The sub-range control circuit includes multiple capacitor banks and control logic circuitry. Each capacitor bank includes multiple capacitor cells and multiple switching cells. A first terminal of each capacitor cell is coupled to the output of the charge pump and to the input of the ADC. A first terminal of each switching cell is coupled to a second terminal of the corresponding capacitor cell, and the second terminal of each switching cell is selectively coupled to one of a reference voltage and ground. The control logic circuitry is coupled to the multiple capacitor banks and, by controlling the states of the multiple switching cells in at least one capacitor bank, limits the voltage level corresponding to the output of the charge pump within a specific voltage range to dynamically lower the voltage level once or multiple times to generate an adjusted voltage level for the ADC.
[0006] According to an embodiment, a method for operating a phase-locked loop (PLL) circuit is disclosed. The method includes: generating a charging current signal using a phase detector based on an input frequency signal and a feedback signal generated by a feedback circuit; limiting a voltage level corresponding to the charging current signal within a specific voltage range based on a prediction signal to generate a digital output; performing a low-pass filtering operation using a loop filter based on the digital output; generating a DCO frequency signal using a digitally controlled oscillator (DCO) based on the output of the loop filter; generating the feedback signal using the feedback circuit based on the DCO frequency signal; generating a phase signal indicating accumulated phase shift information using a sum-Δ modulator (SDM) based on information from the feedback circuit and fractional frequency information; and generating the prediction signal based on the phase signal.
[0007] According to the present invention, the performance of the phase-locked loop circuit can achieve an average time interval corresponding to a small resolution, which greatly reduces the nonlinearity problem caused by the traditional TDC in the phase-locked loop circuit.
[0008] These and other objects of the invention will become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description
[0009] Figure 1 This is a simplified block diagram of a phase-locked loop (PLL) circuit according to an embodiment of the present invention.
[0010] Figure 2 This is illustrated in the embodiments of the present invention. Figure 1 A schematic diagram of an example of a processing circuit.
[0011] Figure 3 According to an embodiment of the present invention, the output voltage level of the PD is lowered multiple times (e.g., four times, but not limited thereto) to achieve the desired effect. Figure 2 The diagram shows an example of a sawtooth waveform of the input voltage generated at the input terminal of a SARADC.
[0012] Figure 4 This is a simplified block diagram of a PLL circuit according to another embodiment of the present invention.
[0013] Figure 5 This is according to an embodiment of the present invention. Figure 4 Detailed circuit diagrams of the neutron range converter, SARADC, and compensator unit. Detailed Implementation
[0014] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components by differences in name, but rather by differences in function. The term "comprising" throughout the specification and subsequent claims is an open-ended term and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if the text describes a first device electrically connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.
[0015] Figure 1 This is a simplified block diagram of a phase-locked loop (PLL) circuit 100 according to an embodiment of the present invention. The PLL circuit 100 can be, for example, an all-digital PLL (ADPLL) circuit. See also... Figure 1 The PLL circuit 100 includes a time-to-digital converter (TDC) 103, a loop filter 130 such as a low-pass filter, a digitally controlled oscillator (DCO) 135, and a feedback circuit 140 incorporating a sigma-delta modulator (SDM) 145 and a prediction circuit 150. The TDC 103 includes an error detector (e.g., a phase detector (PD) 105) and processing circuitry 107. Based on phase / time difference (or offset / error) information on the feedback path of the PLL 100, the TDC 103 generates a digital output to the loop filter 130.
[0016] PD 105 is coupled to an input frequency signal, such as a reference frequency signal REF, and a feedback signal FB generated from a feedback circuit 140, which may be, for example, a clock / edge generator or a multi-modulus divider (MMD). PD 105 generates a PD output signal, such as a charging current signal (or current signal) I_pump, based on the reference frequency signal REF and the feedback signal FB, and then pumps the current signal I_pump to the processing circuit 107.
[0017] Feedback circuit 140 generates a feedback signal FB based on the output frequency signal F_DCO of DCO 135. SDM 145 generates a phase signal PS to indicate the accumulated phase shift information based on the information signal INFO from feedback circuit 140 and the fractional frequency information represented by ".f". Prediction circuit 150 predicts and generates a prediction signal S_P based on the phase signal PS, and transmits the information of prediction signal S_P to TDC 103. PLL 100 is used to track / lock the phase of frequency signal REF to generate the output frequency signal F_DCO by tracking the phase difference between the two signals.
[0018] For high-performance synthesizers, a high-resolution TDC is required. However, phase detectors can degrade the nonlinearity of the signal and introduce nonlinearity issues into subsequent circuitry (e.g., the analog-to-digital converter (ADC) included in processing circuitry 107). To avoid or mitigate the nonlinearity of the input dynamic range of circuit components such as the ADC used in processing circuitry 107, TDC 103 limits the output voltage range of PD 105 (e.g., limits the input voltage range of the ADC) by lowering the output voltage level of PD 105 once or multiple times based on the prediction signal S_P generated by prediction circuitry 150 (e.g., folding the output voltage curve of PD 105).
[0019] The SDM 145 obtains a phase signal PS based on fractional frequency information ".f". To generate a prediction signal S_P, the prediction circuit 150 can predict the future voltage level of the ADC at the Nth time point after the first time point (or the start time of the PLL's tracking operation) based on the phase signal PS generated by the SDM 145 at the first time point. This prediction is made because the future voltage level increases or decreases due to the current signal I_pump. The phase signal PS indicates the accumulated phase generated based on a specific step size, which is related to the voltage change of the ADC's input voltage level. The prediction circuit 150 can predict the future voltage level of the ADC at different future time points, and then generate and output the prediction signal S_P to the TDC 103 (or processing circuit 107) to control the TDC 103 to automatically lower the ADC's input voltage level at future time points (e.g., fold the voltage curve of the ADC input voltage level), automatically compensate for the ADC digital output caused by voltage folding, and / or automatically compensate for quantization noise caused by voltage folding.
[0020] The information carried by the prediction signal S_P will be used to lower the input voltage level of the ADC at a future time point and to provide corresponding bit information for compensating for the ADC's digital output after voltage folding. TDC 103 (or processing circuit 107) can precisely control the ADC's input voltage level within a voltage range with good linearity, and then compensate the ADC's digital output to produce a more accurate digital output signal. This prediction method is more useful in high-speed systems because it is difficult to achieve instantaneous voltage detection to detect the PD's output voltage (or the ADC's input voltage) in high-speed systems. This prediction method can be easily implemented in high-speed systems to achieve a linear voltage domain TDC.
[0021] Figure 2 This is illustrated in the embodiments of the present invention. Figure 1 A schematic diagram of an example of processing circuitry 107 is provided. Processing circuitry 107 includes a SARADC 110 with a successive approximation register (SAR) algorithm / circuit, a compensator unit 115 represented by adder notation (but not limited to), an amplifier unit 120 with a specific gain K1, and a noise cancellation unit 125, such as a quantization noise canceller represented by subtraction notation (but not limited to). In other embodiments, noise cancellation unit 125 may be optional and may be excluded from processing circuitry 107.
[0022] In this embodiment, the prediction signal S_P is transmitted to the SARADC 110, the compensator unit 115, and the noise cancellation unit 125, respectively. The SARADC 110 is used to lower the output voltage level of PD 105 based on the prediction signal S_P as the output voltage level of PD 105 increases and reaches a future voltage level, and then performs SARADC operation to convert the output voltage level of PD 105 into a digital output. The compensation unit 115 is coupled to the SARADC 110 and is used to compensate the digital output of the SARADC 110 based on the information carried by the prediction signal S_P.
[0023] In practice, in one embodiment, the prediction signal S_P can indicate the most significant bit (MSB) information corresponding to the voltage amplitude to be adjusted by the SARADC 110. After the output voltage level of PD 105 (i.e., the input voltage level of SARADC 110) is adjusted once or multiple times by SARADC 110, the SARADC can perform ADC operation using the SAR algorithm based on the adjusted input voltage level to produce a digital output associated with the least significant bit (LSB) of the original digital output, which has not been voltage-folded. The compensator unit 115 is used to combine the MSB information with the LSB information to produce a combined digital output that is equivalent to or approximates the original digital output.
[0024] Amplifier unit 120 amplifies the combined digital output at a specific gain Kl to produce an amplified digital output, and noise cancellation unit 125 performs quantization noise cancellation on the amplified digital output based on information from the prediction signal S_P to produce a final digital output to loop filter 130. It should be noted that in some embodiments, noise cancellation unit 125 may perform this quantization noise cancellation on the amplified digital output without referring to information from the prediction signal S_P.
[0025] Figure 3 According to an embodiment of the present invention, the output voltage level of the PD is lowered multiple times (e.g., four times, but not limited thereto) to achieve the desired effect. Figure 2 The diagram shows an example of a sawtooth waveform generated at the input terminal of the SAR ADC 110. Figure 2 As shown, based on the predicted signal S_P, the SAR ADC 110 can, for example, use... Figure 3Multiple adjustable delay units or delay elements (e.g., four delay units, but not limited to) sequentially delay the charging start signal by the same or different delay amounts (i.e., as shown below) Figure 4 or Figure 5 The charge pump's charging start signal (e.g., control signal EN) generates four different control signals S0, S1, S2, and S3 at four different time points. These signals sequentially trigger / execute voltage folding operations at specific predicted time points t0-t3, sequentially adjusting or folding down the initial waveform W1 of the SARADC 110's input voltage level to produce a sawtooth waveform W2, thereby maintaining the input voltage level within a linear voltage range / region. The voltage folding operation can be achieved by using... Figure 5 This can be achieved using multiple capacitor banks (but not limited to), as detailed later; voltage folding can also be implemented using other circuit components. The adjustment of the delay amount and / or the execution of the voltage folding operation can be performed by the SARADC 110 based on... Figure 2 The prediction signal S_P is used to determine this. Alternatively, in one embodiment, four delay units can be used to generate four control signals S0-S3 to sequentially trigger voltage folding operations within a time interval, which can be, for example, set between a rising / falling edge of the input reference frequency signal REF and a rising / falling edge of the feedback signal FB. For example, this time interval can be between two rising edges of signals REF and FB, i.e., one CKV. However, this is not a limitation of the invention.
[0026] In other embodiments, this application provides a sub-range control circuit disposed between the phase detector and the ADC to mitigate or avoid nonlinearity problems caused by the phase detector. Figure 4This is a simplified block diagram of a PLL circuit 200 according to another embodiment of the present invention. In practice, the PLL circuit 200 is, for example, an ADPLL circuit and includes a subrange converter 205 (e.g., a subrange time-voltage converter (TVC)), a SAR ADC 210, a compensator unit 115, a loop filter 130, a DCO 135, a feedback circuit 140, an SDM 145, and a prediction circuit 150. The subrange converter 205 includes a phase frequency detector (PFD) 2051, a charge pump (CP) 2052, and a subrange control circuit 2053. The prediction signal S_P is transmitted to the subrange control circuit 2052 and the compensator unit 115. The PFD 2015 generates a corresponding voltage signal based on the reference frequency signal REF and the feedback signal FB. Then, the CP 2052 generates a current signal I_pump based on this corresponding voltage signal. The DC value of this current signal I_pump is linearly proportional to the difference between the phases of the two inputs (i.e., the reference frequency signal REF and the feedback signal FB). The sub-range control circuit 2053 adjusts the increased voltage level corresponding to the current signal I_pump downwards one or more times based on the prediction signal S_P. The voltage adjustment / folding operation is similar to that described above. V1 indicates the sawtooth waveform adjusted by the sub-range control circuit 2053 and transmitted to the input of the SARADC 210. Figure 4 As shown, the voltage adjustment / folding operation can be performed during the rising edges of the two signals REF and FB, and can be performed a different number of times, for example, four times during time interval T1, twice during time interval T2, and three times during time interval T3; this does not imply limitation on the invention. After the SARADC 210 generates and outputs the LSB information, the compensator unit 115 combines the LSB information with the MSB information indicated by the prediction signal S_P to produce a combined digital output as the digital output provided to the loop filter 130.
[0027] Figure 5 This is according to an embodiment of the present invention. Figure 4 Detailed circuit diagrams of the neutron range converter 205, SAR ADC 210, and compensator unit 115 are shown below. Figure 5 As shown, CP 2052 includes a current source I1 for providing the charging current signal I_pump, and also includes two switching units SWA and SWB controlled by control signals EN and RST generated by PFD 2051, respectively. SAR ADC 210 includes operational amplifier 2101 and SAR circuitry 2102. Sub-range control circuitry 2053 includes control logic circuitry 2054 and multiple capacitor banks (e.g., 2...).N (Several capacitor banks). For example, the value of N is equal to 3 (but not limited to), i.e., capacitor banks C0-C7. Each capacitor bank may include 2 N One capacitor unit and the corresponding 2 M A switching unit (for simplicity, Figure 5 Only one of the multiple switching units (SW0-SW7) is shown in the diagram, where 2 M For example, it can be 64 (but is not limited to this). It should be noted that N and M are different positive integers, or they can be the same positive integer. The first terminal of each capacitor cell in each capacitor bank is coupled to the intermediate node Nd1 (located between switching units SWA and SWB), i.e., the output terminal of CP 2052. The second terminal of each capacitor cell is coupled to one end of the corresponding switching unit, and the other end of the corresponding switching unit can be selectively coupled to either ground level or a reference voltage level (e.g., power supply level VDD). Equivalently, the capacitor banks are connected in parallel, and the capacitor cells of the corresponding switching units are also connected in parallel. The switching units in each capacitor bank are controlled by the control logic circuit 2054.
[0028] Prediction circuit 150 generates a prediction signal S_P to control logic circuit 2054 and compensator unit 115. In practice, prediction signal S_P may include, for example, signals THPS, S_Fold, and LSF. Signal THPS indicates the amount of delay used by control logic circuit 2054, which uses this delay amount to control adjustable delay units (such as...). Figure 3 The control signals are generated respectively (as shown in the diagram). The signal S_Fold indicates which (or which) capacitor banks are used to perform the voltage folding operation. The signal LSF indicates which input dynamic range of the SARADC 210 is used; the signal LSF may be optional. The prediction signal S_P transmitted to the compensator unit 115 may include a signal RR with MSB information, which may be, for example, three MSB bits represented by RR[2:0] (but is not limited to this).
[0029] The control logic circuit 2054 may include the connection methods described above, such as... Figure 3The adjustable delay unit shown is not limited in number. Control logic circuit 2054 generates control signals based on the prediction signal S_P to control the switching units of each capacitor bank to turn on / off (i.e., close / open). According to an embodiment, initially, before charging begins, all switching units of each capacitor bank are selectively connected to ground, and PFD 2051 generates signals EN and RST to control switch unit SWA to open and switch unit SWB to close, resetting the charge of all switching units. After reset, PFD 2051 generates signals EN and RST to control switch unit SWA to close and switch unit SWB to open, and control logic circuit 2054 generates control signals to control all switching units of each capacitor bank to connect to a reference level (e.g., power supply voltage level VDD). Accordingly, charging begins, and current source I1 charges the level at intermediate node Nd1 (i.e., the input voltage level of SARADC 210) using its charging current, and the input voltage level increases linearly with time within a linear voltage range. The control logic circuit 2054 then generates control signals at different times by utilizing a circuit design with delay units, for example... Figure 3 The figures S0-S3 represent voltage curves that fold the input voltage level of the ADC at time points t0-t3. It should be noted that these time points are determined based on the delay indicated by the signal THPS of the prediction signal S_P generated by the prediction circuit 150.
[0030] Furthermore, for example, the signal S_Fold can indicate the capacitor bank number to be switched at time points t0-t3. For instance, based on the information from the signal S_Fold, the control logic circuit 2054 can sequentially send control signals S0-S3 to control all switching units represented by SW0-SW3 respectively at time points t0-t3. Figure 3 The different time points t0-t3 shown switch from the reference level VDD to ground level. Accordingly, the voltage curve of the input voltage level is folded four times to produce a sawtooth waveform. The SAR ADC 210 determines and generates a digital output S_ADC associated with the LSB information (e.g., seven LSB bits) represented by S_ADC[6:0] based on the adjusted input voltage level. The compensator unit 115 combines the MSB bits RR[2:0] with the LSB bits S_ADC[6:0] to produce a final digital output with nine-bit resolution as the digital output signal S_TDC[8:0] of the TDC.
[0031] In one embodiment, the control logic circuit 2054 can finely control at least some (or all) of the switching units of two capacitor banks (e.g., C6 and C7) to switch between ground level and reference level VDD to generate digital output signals UP[5:0] and DN[5:0]. The SAR ADC 210 can then overlap the digital output signals UP[5:0] and DN[5:0] to compensate for voltage errors or residual voltage levels, thereby generating LSB bits S_ADC[6:0] more accurately. However, this is not a limitation of the invention.
[0032] In another embodiment, the prediction circuit 150 may generate a control signal to CP 2052 to control the current source I1 to provide a charging current I_pump, which gradually increases from a lower current to a specific current level. For example, when the prediction circuit 150 determines that the initial phase shift is large, it may control the charging current I_pump to gradually or linearly increase from a lower current level to a specific current level to avoid prediction errors. When the prediction circuit 150 determines that the phase shift is not large, it may control the charging current I_pump at a specific current level. Accordingly, if the charging current I_pump is controlled by the prediction circuit 150, the compensation unit 115 compensates the digital output of the ADC accordingly using a prediction signal S_P corresponding to the information of the adjusted charging current I_pump, to accurately generate the final digital output for the loop filter 130.
[0033] Those skilled in the art will readily recognize that many modifications and changes can be made to the apparatus and method while retaining the teachings of the invention. Therefore, the above disclosure should be construed as being limited only by the scope and limits of the appended claims.
Claims
1. A phase-locked loop circuit, comprising: Time-to-Digital Converter (TDC), including: A phase detector is used to generate a charging current signal based on the input frequency signal and the feedback signal; and A processing circuit, coupled to the phase detector, is used to limit the analog voltage level provided to the analog-to-digital converter (ADC) of the processing circuit and corresponding to the charging current signal within a specific voltage range based on a predicted signal, in order to generate a digital output. A loop filter, coupled to the TDC, is used to perform a low-pass filtering operation based on the digital output; A digitally controlled oscillator (DCO) is coupled to the loop filter to generate a DCO frequency signal based on the output of the loop filter. A feedback circuit, coupled to the DCO and the phase detector, is used to generate the feedback signal based on the DCO frequency signal; A Σ-Δ modulator (SDM), coupled to the feedback circuit, is used to generate a phase signal representing the accumulated phase shift information to the prediction circuit based on information from the feedback circuit and fractional frequency information; and The prediction circuit is coupled to the SDM to generate the prediction signal based on the phase signal.
2. The phase-locked loop circuit as described in claim 1, wherein the processing circuit is used for: By dynamically lowering the voltage level according to the predicted signal, the voltage level corresponding to the charging current signal is limited to the specific voltage range to generate an adjusted voltage level; A digital output with least significant bit (LSB) information is generated based on the adjusted voltage level. as well as The LSB information is combined with the most significant bit (MSB) information carried by the prediction signal to generate a combined digital output as the digital output.
3. The phase-locked loop circuit as described in claim 2, wherein the adjusted voltage level is associated with a sawtooth waveform signal.
4. The phase-locked loop circuit as described in claim 1, wherein the processing circuit comprises: Multiple adjustable delay units connected in series are used to generate multiple control signals, which are respectively used to lower the voltage level; The delay amount of the plurality of adjustable delay units is determined by the prediction signal to determine the time point at which the plurality of control signals are generated.
5. The phase-locked loop circuit of claim 4, wherein the plurality of control signals are generated during a time interval specified by the signal edge of the input frequency signal and the signal edge of the feedback signal.
6. The phase-locked loop circuit as described in claim 5, wherein the signal edge of the input frequency signal is a rising edge or a falling edge, and the signal edge of the feedback signal is another rising edge or another falling edge.
7. The phase-locked loop circuit as described in claim 5, wherein the signal edge of the input frequency signal is a rising edge, and the signal edge of the feedback signal is another rising edge.
8. The phase-locked loop circuit of claim 2, wherein the processing circuit is used to generate the LSB information by overlapping one bit of information from one capacitor bank with another bit of information from another capacitor bank.
9. A sub-range control circuit, disposed between a charge pump and an analog-to-digital converter (ADC) in a phase-locked loop circuit, the sub-range control circuit comprising: Multiple capacitor banks, each capacitor bank comprising: Multiple capacitor units, each capacitor unit having its first end coupled to the output of the charge pump and coupled to the input of the ADC; Multiple switching units, each with a first terminal coupled to the second terminal of a corresponding capacitor unit, and each switching unit's second terminal selectively coupled to either a reference level or ground level; and A control logic circuit, coupled to the plurality of capacitor banks, limits the voltage level corresponding to the output terminal of the charge pump within a specific voltage range by controlling the state of a plurality of switching units in at least one capacitor bank, so as to dynamically lower the voltage level once or multiple times to generate an adjusted voltage level for the ADC.
10. The sub-range control circuit of claim 9, wherein the control logic circuit is configured to control all switching units in each capacitor bank to become connected to the reference level and disconnected from the ground level when charging of the charge pump begins.
11. The sub-range control circuit of claim 10, wherein the control logic circuit is configured to control the switching unit of a specific capacitor bank among the plurality of capacitor banks to become connected to the ground level and disconnected from the reference level at a specific time point, so as to reduce the voltage level.
12. A method for operating a phase-locked loop circuit, comprising: A phase detector is used to generate a charging current signal based on the input frequency signal and the feedback signal generated by the feedback circuit. The processing circuitry uses a predicted signal to limit the analog voltage level provided to the ADC and corresponding to the charging current signal to a specific voltage range in order to generate a digital output. A low-pass filtering operation is performed using a loop filter based on the digital output; A digitally controlled oscillator (DCO) generates a DCO frequency signal based on the output of the loop filter. The feedback circuit is used to generate the feedback signal based on the DCO frequency signal; Using a Σ-Δ modulator (SDM), a phase signal indicating the accumulated phase shift is generated based on the information from the feedback circuit and the fractional frequency information; and The prediction signal is generated based on the phase signal.
13. The method of claim 12, wherein limiting the analog voltage level provided to the ADC and corresponding to the charging current signal to a specific voltage range based on the predicted signal to generate a digital output comprises: By dynamically lowering the voltage level according to the predicted signal, the voltage level corresponding to the charging current signal is limited to the specific voltage range to generate an adjusted voltage level; A digital output with least significant bit (LSB) information is generated based on the adjusted voltage level. as well as The LSB information is combined with the most significant bit (MSB) information carried by the prediction signal to generate a combined digital output as the digital output.
14. The method of claim 13, wherein the adjusted voltage level is associated with a sawtooth waveform signal.
15. The method of claim 12, wherein the step of generating digital output comprises: Multiple adjustable delay units connected in series are used to generate multiple control signals, which are respectively used to lower the voltage level. The delay amount of the plurality of adjustable delay units is determined by the prediction signal to determine the time point at which the plurality of control signals are generated.
16. The method of claim 15, wherein the plurality of control signals are generated during a time interval specified by the signal edge of the input frequency signal and the signal edge of the feedback signal.
17. The method of claim 16, wherein the signal edge of the input frequency signal is a rising edge or a falling edge, and the signal edge of the feedback signal is another rising edge or another falling edge.
18. The method of claim 16, wherein the signal edge of the input frequency signal is a rising edge, and the signal edge of the feedback signal is another rising edge.
19. The method of claim 13, wherein the processing circuitry is configured to generate the LSB information by overlapping one bit of information from one capacitor bank with another bit of information from another capacitor bank.