A distributed wiring harness testing device and method thereof

Abstract

The present invention provides a distributed wiring harness testing device and method thereof, wherein the device comprises: a test node array, which comprises a plurality of test nodes, the test nodes comprise a microprocessor, a signal generating unit, a signal sampling unit and a plurality of test terminals, the signal acquisition end of the signal sampling unit is connected to all the test terminals, each test terminal is connected to a selection switch, the signal generating unit comprises a plurality of signal generating devices, the signal output end of the signal generating device is connected to the selection end of all the selection switches, the selection end of the selection switch is connected to the signal generating device, the signal generating unit, the signal sampling unit and the selection switch are all connected to the microprocessor; all the test nodes share a global common line, all the test nodes are respectively provided with an internal common line, and in a single test node, the test terminal can be connected to the internal common line through the selection switch; a control system, which sends a command signal to the test node and receives the acquisition signal sent by the test node.

Description

Technical Field

[0001] The present invention relates to the field of line detection, and in particular to a distributed wire harness testing device and a method thereof. Background Art

[0002] In the fields of automobile, aviation, industrial control, etc., various types of wiring harnesses are used in large quantities. The correctness of the connection of the wiring harness and the correctness of the parameters of the functional components in the wiring harness are related to whether a system can work reliably.

[0003] The wiring harness test is to test the wiring components that connect the electrical components in the system and the functional components such as resistors, capacitors, diodes, etc. contained in the wiring harness. Generally, it is necessary to measure the conductivity of the wiring harness, the parameters of the functional components, etc.

[0004] The traditional wiring harness test device adopts the method of cascading multiple wiring motherboards, and is composed of a wiring motherboard, wiring harness connectors, test circuits and methods to form an integrated test device. After the wiring harness to be tested is converted through multiple wiring harness connectors, the wiring harness is arranged in groups according to the connectors and connected to the IO array of the wiring motherboard in sequence. The number of pins of the IO array is generally 128. The IO arrays of multiple wiring motherboards are cascaded together to form a larger IO array.

[0005] The traditional way is to manually assemble the wiring harness. During the assembly process, it is necessary to find the correspondence between the pin position on the IO array and the wiring harness connector. The installation process is time-consuming and labor-intensive, prone to errors, and seriously affects production efficiency. The traditional wiring harness testing method is based on the traditional wiring harness test circuit. The IO array is serially scanned through the test circuit to establish the correspondence between the wiring harness connectors in the test algorithm one by one. This process is also time-consuming and labor-intensive, prone to errors, and seriously affects production efficiency. Summary of the invention

[0006] The main purpose of the present invention is to provide a distributed wire harness testing device and method thereof, so as to solve the problems that the wire harness testing installation is time-consuming and labor-intensive, and the testing process is complicated.

[0007] In order to achieve the above object, according to one aspect of the present invention, the distributed wiring harness testing device comprises:

[0008] A test node array, comprising a plurality of test nodes, wherein the test nodes comprise a microprocessor, a signal generating unit, a signal sampling unit and a plurality of test terminals, wherein a signal acquisition end of the signal sampling unit is connected to all the test terminals, each test terminal is connected to a selection switch, the signal generating unit comprises a plurality of signal generating devices, a signal output end of the signal generating device is connected to the selection ends of all the selection switches, a selection end of the selection switch is connected to at most one signal generating device, and the signal generating unit, the signal sampling unit and the selection switch are all connected to the microprocessor;

[0009] Common lines include global common lines and internal common lines. All test nodes share the global common lines. All test nodes are respectively provided with internal common lines. In a single test node, the test terminal can be connected to the internal common line through a selection switch.

[0010] The control system sends command signals to the test nodes and receives acquisition signals sent by the test nodes.

[0011] By arranging the test nodes in an array, each test node has the same structure, and each test terminal in the test node has the same structure, so the wiring harness to be tested is connected to the test terminals in sequence, and the wiring harness can be tested by simply switching different signal generating devices.

[0012] The above-mentioned wiring harness sequence is installed on the test terminal, which means that the wiring harness is topological. The wiring harness generally numbers each point, and each point is connected to the test terminal in the order of numbering. The wiring priority of the test terminal is also set. First, in the matrix composed of test nodes, the order of columns first and rows later is used, that is, starting from the first column and the first row, the first column and the first row, the first column and the second row, and so on. After all the test terminals in the test node in the first column are used up, the second column is used, and the rules are the same as above, until the last column. The priority of using the test terminals in the test node is that the test terminals in the test node are generally 32 or 64. The test terminals are numbered 0-31 or 0-63, and they can be used in the order of numbers.

[0013] Furthermore, the signal generating unit includes an analog signal generating device, a reference voltage generating device and a ground signal device. The input end of the analog signal generating device is connected to the microprocessor, and the control end of the reference voltage generating device is connected to the microprocessor.

[0014] The test terminal connected to one end of the wire to be tested is connected to the reference voltage, and the test terminal connected to the other end is grounded. Then, by collecting the voltage values ​​at the two terminals, the conduction condition of the wire can be determined, so the detection method of the device is simple. When wiring, it is not necessary to consider the particularity of each test point of the wire harness to be tested. If some need to consider the test capacitance, it needs to be connected to a test terminal with a signal input device, but in the present invention, all test terminals can be connected to the analog signal generating device, which greatly simplifies the wiring steps.

[0015] Moreover, the traditional test circuit tests all wiring harnesses together, and the algorithm is relatively complex, and problems often occur. In the present invention, some test terminals can be put in neutral by selecting switches, so that the line speed test points connected to them do not enter the test circuit, so it is completely possible to test in steps, but if each line is tested separately, the speed is also very slow. Usually, the same type of lines are tested at the same time, such as the connectivity settings can be tested at the same time, such as all resistors can be tested at the same time, etc., which can speed up the test speed, and the present invention can greatly reduce the difficulty of calculation through a distributed testing method.

[0016] In the present invention, the control system sends commands to the microprocessor in each test node, and the microprocessor sends commands to the signal generating unit, the signal sampling unit and the selection switch. The signal collected by the signal sampling unit is also sent to the control system through the microprocessor, and the control system can analyze the signal to make a result.

[0017] The common line is mainly used to build a loop between the test terminals.

[0018] Furthermore, the analog signal generating device is a digital-to-analog converter, which mainly converts digital signals into analog signals, and the digital signals are sent by the microprocessor.

[0019] Furthermore, a current limiting resistor is provided between the above-mentioned test terminal and the selection switch, and the reference voltage is directly grounded via a diode, which often breaks down the diode.

[0020] Furthermore, the sampling unit is an analog-to-digital converter, which is used to convert the collected analog signal into a digital signal, and then transmit it to the control system via the microprocessor.

[0021] Furthermore, the test nodes in the test node array are arranged in a matrix, and the test nodes in the same column are connected to the control system through the same bus. The same column uses one bus, such as the first column uses the first bus, and the second column uses the second bus, so that a signal can be sent to the first bus to control the test nodes on the first column, further realizing a distributed control method, and avoiding too many collected signals. The signals are transmitted through different buses and are not easily lost.

[0022] Furthermore, the control system includes an FPGA controller and an embedded processor, the FPGA controller and the embedded processor are electrically connected, and the FPGA controller is also connected to a bus driver array, the bus driver is used to connect the bus accessed from the test node. The FPGA is used to send test commands and receive test data, and the embedded processor is used to perform data calculations.

[0023] In order to achieve the above object, according to another aspect of the present invention, a distributed wiring harness testing method is provided. The method comprises:

[0024] A. Input the topological structure information of the wiring harness to be tested and the configuration information of the test machine into the control system;

[0025] B. Obtain connection information of the test terminal in each test node on the test machine, and map the test terminal to the topological structure of the wiring harness to be tested according to the connection information of the test terminal;

[0026] C. First test the wiring harness connectivity within the test node, and then test the wiring harness connectivity between test nodes;

[0027] D. Perform parameter tests on functional components in the wiring harness;

[0028] E. Analyze the test content and generate test results.

[0029] The test terminal connection information is obtained in step B as follows: the test nodes are arranged in a matrix, with a total of m rows and n columns. In the first column, the test nodes are test node 1-1, test node 1-2, ..., test node 1-m, and in the second column, the test nodes are test node 2-1, test node 2-2, ..., test node 2-m, and so on. In the nth column, the test nodes are test node n-1, test node n-2, ..., test node nm.

[0030] If a test node contains a test terminals, they are named as test terminal 1, test terminal 2, ..., test terminal a. In the same test node, the smaller the test terminal is, the higher the priority is. The priority of the test node is first listed and then arranged;

[0031] The first test point of the wiring harness to be tested is connected to any test terminal in any test node, and the pin information of the test terminal is recorded. The second test point of the wiring harness to be tested is connected to a test terminal whose priority follows the test terminal corresponding to the first test point. The third test point of the wiring harness to be tested is connected to a test terminal whose priority follows the test terminal corresponding to the second test point. And so on. All the test points of the wiring harness to be tested are connected to the test terminals. When the pin information of the terminal to be tested corresponding to the first test point of the wiring harness to be tested is obtained, the pin information of the terminals to be tested corresponding to all other test points of the wiring harness to be tested can be obtained, and the connection information of the test terminals in each test node on the test machine is obtained.

[0032] The present invention has at least the following beneficial effects:

[0033] (1) The test terminals of all test nodes of the present invention have the same physical structure and can meet the different input requirements of different wiring harnesses. Therefore, the installation of the present invention before testing only requires the wiring harness and the test terminals to be installed in sequence, so that the test terminals and the wiring harness can be easily mapped, which is convenient for the subsequent testing process;

[0034] (2) In the test of the present invention, the test can also be performed in a distributed manner, such as first testing the connectivity of the line in the test node, then testing the connectivity of the line between the test nodes, and finally testing the parameters of the line with functional elements. The functional elements can also be tested in a distributed manner, which can speed up the test while reducing the amount of calculation.

[0035] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0037] Figure 1 It is a schematic diagram of the overall structure of the distributed wiring harness testing device of the present invention;

[0038] Figure 2 It is a structural schematic diagram of a test node of a distributed wiring harness test device of the present invention;

[0039] Figure 3 A schematic diagram of circuit connections of test terminals of a distributed wiring harness test device of the present invention;

[0040] Figure 4 is a flow chart of the distributed wiring harness testing method of the present invention;

[0041] Figure 5 A node line test diagram of a distributed wiring harness test device and method thereof of the present invention;

[0042] Figure 6 It is a node-to-node line test diagram of the distributed wiring harness test device and method thereof of the present invention;

[0043] Figure 7 A diagram showing the node internal resistance test of the distributed wiring harness test device and method of the present invention;

[0044] Figure 8 It is a graph of the capacitance test within a node of the distributed wiring harness test device and method of the present invention;

[0045] Fig. 9 The invention discloses a distributed wiring harness test device and a method for testing diodes in nodes. Figure 1 ;

[0046] Fig.10 The invention discloses a distributed wiring harness test device and a method for testing diodes in nodes. Figure 2 . DETAILED DESCRIPTION

[0047] The specific embodiments of the present invention are described in detail below. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0048] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", "A", "B", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. In addition, unless otherwise clearly specified and limited, the terms "set", "layout", "installation", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances and in combination with the prior art. And one or more of the components in the figure may be necessary or non-necessary, and the relative positional relationship between the components in the above figure can be adjusted according to actual needs.

[0051] See also Figures 1 to 3As shown, the distributed wiring harness test device provided by the present invention comprises: a test node array, which comprises several test nodes, wherein the test node comprises a microprocessor, a signal generating unit, a signal sampling unit and several test terminals, wherein the signal acquisition end of the signal sampling unit is connected to all the test terminals, and each test terminal is connected to a selection switch, and the signal generating unit comprises an analog signal generating device, a reference voltage generating device and a grounding signal device, wherein the input end of the analog signal generating device is connected to the microprocessor, and the control end of the reference voltage generating device is connected to the microprocessor. The signal output ends of the analog signal generating device, the reference voltage generating device and the grounding signal device are connected to the selection ends of all the selection switches, and at most one signal generating device is connected to one selection end of the selection switch, that is, in the test node, the test terminals can be connected to a signal generating device through the selection switch, such as a certain test terminal only needs to be grounded, that is, it is connected to the grounding signal device through the selection switch, and the signal generating unit, the signal sampling unit and the selection switch are all connected to the microprocessor.

[0052] The above-mentioned signal sampling unit is an analog-to-digital converter, which converts the collected analog signal into a digital signal and then transmits it to the microprocessor; the analog generating device is a digital-to-analog converter, which converts the collected data signal into an analog signal. The microprocessor mainly transmits the digital signal to the analog generating device, and then converts it into an analog signal and sends it to the test terminal to test the wiring harness; the reference voltage generating device is made of a voltage reference to provide a reference voltage; the grounding signal device refers to an ordinary grounding setting; the selection switch is made of a thyristor switch, which responds quickly, and its control end is connected to the microprocessor, and the switching is controlled by the microprocessor.

[0053] Common line, all test terminals can be connected to this common line through the selection switch, which is used for auxiliary testing and building a test loop;

[0054] The control system sends command signals to the test nodes and receives the acquisition signals sent by the test nodes. The control system includes an FPGA controller and an embedded processor. The FPGA controller and the embedded processor are electrically connected. The FPGA controller is also connected to a bus driver array, and the bus driver is used to connect the bus connected from the test node. The FPGA is used to send test commands and receive test data, and the embedded processor is used to perform data calculations. The control system is also provided with necessary memories, which are respectively connected to the FPGA controller and the embedded processor, and a display interface is set on the FPGA controller for connecting to a display to display the test object to the staff and view the test status; a USB interface is set on the FPGA controller for connecting to operating devices such as a mouse and a keyboard to input commands.

[0055] In this embodiment, the test nodes are arranged in an array, and an m*n square array is formed, with a total of m rows and n columns of test nodes, which are installed on a test table. Since each test node has the same structure and each test terminal in the test node has the same structure, the wiring harness to be tested is connected to the test terminal in sequence, so the wiring harness can be tested by simply switching different signal generating devices. The test nodes in the same column share a bus, so a total of n buses are set, and these buses are connected to the bus driver.

[0056] Before the harness is installed, the harness topology will be performed first to obtain the harness topology structure, and then the numbers of each point on the harness will be marked. The harness generally numbers each point, and each point is connected to the test terminal in the order of the numbering, and the wiring priority of the test terminal is also set. First, in the matrix composed of the test nodes, the columns are arranged first and then the rows are arranged, that is, starting from the first row of the first column, the first row of the first column, the second row of the first column, and so on. After all the test terminals in the test nodes in the first column are used up, the second column will be used, and the rules are the same as above, until the last column. The test terminals in the test nodes have a priority of use. The test terminals in the test nodes are generally 32, which can be expanded to 64. This embodiment uses 32, and the test terminals are numbered 0-31. When used, they can also be used in the order of the numbers, that is, the first test point of the harness is connected to the test terminal numbered 0 in the test node of the first row of the first column, the second test point is connected to the test terminal numbered 1 in the test node of the first row of the first column, and the third test point is connected to the test terminal numbered 2 in the test node of the first row of the first column, and so on.

[0057] The test terminal connected to one end of the wire to be tested is connected to the reference voltage, and the test terminal connected to the other end is grounded. Then, by collecting the voltage values ​​at the two terminals, the conduction condition of the wire can be determined, so the detection method of the device is simple. When wiring, it is not necessary to consider the particularity of each test point of the wire harness to be tested. If some need to consider the test capacitance, it needs to be connected to a test terminal with a signal input device, but in the present invention, all test terminals can be connected to the analog signal generating device, which greatly simplifies the wiring steps.

[0058] The present invention adopts distributed testing, specifically step-by-step testing. Usually, the same type of circuits are tested simultaneously. For example, connectivity settings can be tested simultaneously, all resistors can be tested simultaneously, etc., which can speed up the testing speed. In addition, the present invention can greatly reduce the calculation difficulty through a distributed testing method.

[0059] In a preferred embodiment, a current limiting resistor is provided between the test terminal and the selection switch. The reference voltage is directly grounded via a diode, which often breaks down the diode. Therefore, the current limiting resistor is provided to protect the diode.

[0060] like Figure 2 , Figure 3 In the figure, ADC is analog-to-digital converter, DAC is digital-to-analog converter, Vref is reference voltage generator, IO is test terminal, R is current limiting resistor, and K is selection switch.

[0061] like Figure 4 As shown, according to the distributed wiring harness testing device described in the above embodiment, this embodiment also matches a distributed wiring harness testing method, including the following steps:

[0062] A. Input the topological structure information of the wiring harness to be tested and the configuration information of the test machine into the control system;

[0063] B. Obtain connection information of the test terminal in each test node on the test machine, and map the test terminal to the topological structure of the wiring harness to be tested according to the connection information of the test terminal;

[0064] C. First test the wiring harness connectivity within the test node, and then test the wiring harness connectivity between test nodes;

[0065] D. Perform parameter tests on functional components in the wiring harness;

[0066] E. Analyze the test content and generate test results.

[0067] The test terminal connection information is obtained in step B as follows: the test nodes are arranged in a matrix, with a total of m rows and n columns. In the first column, the test nodes are test node 1-1, test node 1-2, ..., test node 1-m, and in the second column, the test nodes are test node 2-1, test node 2-2, ..., test node 2-m, and so on. In the nth column, the test nodes are test node n-1, test node n-2, ..., test node nm.

[0068] If a test node contains a test terminals, they are named as test terminal 1, test terminal 2, ..., test terminal a. In the same test node, the smaller the test terminal is, the higher the priority is. The priority of the test node is first listed and then arranged;

[0069] The first test point of the wiring harness to be tested is connected to any test terminal in any test node, and the pin information of the test terminal is recorded. The second test point of the wiring harness to be tested is connected to a test terminal whose priority follows the test terminal corresponding to the first test point. The third test point of the wiring harness to be tested is connected to a test terminal whose priority follows the test terminal corresponding to the second test point. And so on. All the test points of the wiring harness to be tested are connected to the test terminals. When the pin information of the terminal to be tested corresponding to the first test point of the wiring harness to be tested is obtained, the pin information of the terminals to be tested corresponding to all other test points of the wiring harness to be tested can be obtained, and the connection information of the test terminals in each test node on the test machine is obtained.

[0070] The mapping relationship between the test terminal and the topological structure of the harness to be tested has been easily obtained through the above content. The topological structure of the circuit is a prior art, that is, the connection relationship between the components in the circuit. All the connection points in the circuit are numbered in sequence, and the components between the points are recorded, which forms the topological structure of the circuit.

[0071] Now let's explain the testing process. Figure 5 , is the connectivity of the test line. Take a single test node 1-1 as an example: in the figure, test terminal No. 1 and test terminal No. 2 are connected through the line to be tested, that is, the connectivity of the line to be tested is tested. At this time, the selection switch of test terminal No. 1 is connected to the reference voltage output terminal, and test terminal No. 2 is grounded. The level signals of the two are measured by ADC as V1 and V2 respectively. When V1 and V2 are both half of the reference voltage, the line to be tested is connected; if V1 is equal to the reference voltage and V2 is equal to zero, the line to be tested is disconnected.

[0072] like Figure 6 It is a line connectivity test between test nodes. Take test nodes 1-1 and 1-2 as examples. In test node 1-1, the selection switch of test terminal 1 is connected to the reference voltage output terminal, the selection switch of test terminal 2 is grounded, and its test terminal is connected to the global common line. In test node 2-1, the test terminal 1 is connected to the test line between the test terminal 3 and the test terminal 4 of test node 1-1, so the selection switches of test terminals 3 and 4 in test node 2-1 are connected to the internal common line, and test terminal 4 is connected to the global common line. In this way, test terminal 1, test terminal 3, test terminal 4 and test terminal 2 are connected in sequence to form a loop. Through ADC testing, the level signal of test terminal 1 is V1, and the level signal of test terminal 2 is V2. If V1 is three quarters of the reference voltage and V2 is one quarter of the reference voltage, it means that the line to be tested is connected; if V1 is the reference voltage and V2 is zero, it means that the line to be tested is disconnected.

[0073] like Figure 7 , is the resistance parameter test. The layout of the resistor to be tested is consistent with the line. The level signal of the ADC test terminal No. 1 is V1, and the level signal of the test terminal No. 2 is V2. V1 and V2 are the level values ​​at both ends of the resistor to be tested. Because the value of the current limiting resistor R is known, the current value in the loop and the voltage value at both ends of the resistor to be tested can be calculated to obtain the resistance value of the resistor to be tested. The resistance test between nodes is similar to the line test between nodes. The test loop is realized through the global common line and the internal common line.

[0074] like Figure 8, for capacitor parameter testing, the selection switch of terminal 1 is connected to DAC, and DAC inputs a sinusoidal signal of a certain frequency to terminal 1, which forms a loop through the capacitor to be tested and terminal 2. ADC collects the level of terminals 1 and 2 for several cycles. The current limiting resistor R is known, and the current value in the loop and the voltage value across the resistor to be tested can be calculated to obtain the capacitance of the capacitor to be tested. The capacitance test between nodes is similar to the line test between nodes, and the test loop is realized through the global common line and the internal common line.

[0075] like Fig. 9 , Fig.10 , for diode measurement, it is divided into two steps: forward measurement and reverse measurement. First, the forward measurement is performed, such as Fig. 9 ,The terminal 1 selection switch is connected to the DAC, and the DAC outputs a triangle wave with a certain slope, which passes through the diode to be tested and the terminal 2 to form a test circuit. The level values ​​at the terminals 1 and 2 measured by the ADC can be used to calculate the forward voltage drop of the diode to be tested; Fig.10 , the selection switch of terminal 2 is connected to the DAC, and in the same way, the reverse voltage drop of the diode is obtained. Based on the two tests, it can be determined whether the connection of the diode is correct.

[0076] The above calculation process is processed and judged by the embedded processor, that is, the analysis test content in step E, and the obtained structure is sent to the display for display, that is, the generation test result in step E.

[0077] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is only limited by the claims and their full scope and equivalents. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0078] Those skilled in the art can understand that, in addition to implementing the system, device and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be regarded as structures within the hardware component; the modules for implementing various functions can also be regarded as both software programs for implementing the method and structures within the hardware component.

[0079] In addition, all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a single-chip microcomputer, a chip or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program codes.

[0080] In addition, various implementation modes of the embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the embodiments of the present invention, they should also be regarded as the contents disclosed by the embodiments of the present invention.

Claims

1. A distributed wiring harness test device, characterized in that: include: A test node array, comprising a plurality of test nodes, wherein the test nodes comprise a microprocessor, a signal generating unit, a signal sampling unit and a plurality of test terminals, wherein a signal acquisition end of the signal sampling unit is connected to all the test terminals, and each of the test terminals is connected to a selection switch, wherein the signal generating unit comprises a plurality of signal generating devices, and a signal output end of the signal generating device is connected to the selection ends of all the selection switches, and at most one signal generating device is connected to one selection end of the selection switch, and wherein the signal generating unit, the signal sampling unit and the selection switch are all connected to the microprocessor; The test nodes in the test node array are arranged in a matrix, and the test nodes in the same column are connected to the control system through the same bus; Common lines include global common lines and internal common lines. All test nodes share the global common lines. All test nodes are respectively provided with internal common lines. In a single test node, the test terminal can be connected to the internal common line through a selection switch. The test terminal can also be connected to the global common line, and the test loop is realized through the global common line and the internal common line. The control system sends command signals to the test nodes and receives acquisition signals sent by the test nodes.

2. The distributed wiring harness testing device according to claim 1, characterized in that: The signal generating unit comprises an analog signal generating device, a reference voltage generating device and a ground signal device. The input end of the analog signal generating device is connected to the microprocessor, and the control end of the reference voltage generating device is connected to the microprocessor.

3. The distributed wiring harness testing device according to claim 2, characterized in that: The analog signal generating device is a digital-to-analog converter.

4. The distributed wiring harness testing device according to claim 1, characterized in that: A current limiting resistor is arranged between the test terminal and the selection switch.

5. The distributed wiring harness testing device according to claim 1, characterized in that: The sampling unit is an analog-to-digital converter.

6. The distributed wiring harness testing device according to claim 1, characterized in that: The control system comprises: an FPGA controller and an embedded processor, the FPGA controller and the embedded processor are electrically connected, and the FPGA controller is also connected to a bus driver array, and the bus driver is used to connect a bus accessed from a test node.

7. A distributed wire harness testing method, used in the distributed wire harness testing device according to any one of claims 1 to 6, characterized in that: The steps include: Input the topological structure information of the wiring harness to be tested and the configuration information of the test machine into the control system; Acquire the connection information of the test terminal in each test node on the test machine, and map the test terminal to the topological structure of the wiring harness to be tested according to the test terminal connection information; First, test the connectivity of the wiring harness within the test node, and then test the connectivity of the wiring harness between test nodes; Conduct parameter tests on functional components in wiring harnesses; Analyze test content and generate test results.

8. The distributed wiring harness testing method according to claim 7, characterized in that: The test terminal connection information is obtained in the following manner: the test nodes are arranged in a matrix, with m rows and n columns in total. In the first column, the test nodes are test node 1-1, test node 1-2, ..., test node 1-m, respectively; in the second column, the test nodes are test node 2-1, test node 2-2, ..., test node 2-m, respectively; and in the nth column, the test nodes are test node n-1, test node n-2, ..., test node nm, respectively; If a test node contains a test terminals, they are named as test terminal 1, test terminal 2, ..., test terminal a. In the same test node, the smaller the test terminal is, the higher the priority is. The priority of the test node is first listed and then arranged; The first test point of the wiring harness to be tested is connected to any test terminal in any test node, and the pin information of the test terminal is recorded. The second test point of the wiring harness to be tested is connected to a test terminal whose priority follows the test terminal corresponding to the first test point. The third test point of the wiring harness to be tested is connected to a test terminal whose priority follows the test terminal corresponding to the second test point. And so on. All the test points of the wiring harness to be tested are connected to the test terminals. When the pin information of the terminal to be tested corresponding to the first test point of the wiring harness to be tested is obtained, the pin information of the terminals to be tested corresponding to all other test points of the wiring harness to be tested can be obtained, and the connection information of the test terminals in each test node on the test machine is obtained.

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