Display panel and method of manufacturing the same

Abstract

A display panel and a manufacturing method thereof are provided. The display panel includes an upper display substrate and a lower display substrate. The upper display substrate includes: a base substrate; a light shielding pattern including an opening portion corresponding to a pixel area defined in the light shielding pattern; a color filter overlapping the pixel area; an encapsulation layer disposed on the lower side of the light shielding pattern and the lower side of the color filter; a partition wall disposed on the lower side of the encapsulation layer, overlapping the light shielding area, and including a partition wall opening portion corresponding to the pixel area defined in the partition wall; and a quantum dot layer disposed inside the partition wall opening portion. The partition wall includes a first layer and a second layer, the first layer being directly disposed on the bottom surface of the encapsulation layer, and the second layer being directly disposed on the lower side of the first layer and having a greater optical density than the first layer.

Description

Technical Field

[0001] The present disclosure herein relates to a display panel and a method for manufacturing the same, and more particularly, to a display panel including a partition wall and a method for manufacturing the same. Background Art

[0002] The display panel includes a transmissive display panel that selectively transmits source light generated by a light source and an emissive display panel in which the source light is generated. The display panel may include different types of color control layers according to pixels to generate a color image. The color control layer may transmit only source light of some wavelength ranges or change the color of the source light. Some color control layers may change the characteristics of the source light without changing the color of the source light. Summary of the invention

[0003] The present disclosure provides a display panel in which brightness is increased and color mixing is prevented.

[0004] The present disclosure also provides a method of manufacturing a display panel in which material consumption is reduced.

[0005] An embodiment of the inventive concept provides a display panel, which includes an upper display substrate and a lower display substrate, the upper display substrate including a first pixel area, a second pixel area, and a third pixel area and a light shielding area in the periphery of the first pixel area, the second pixel area, and the third pixel area, and the lower display substrate including a first display element, a second display element, and a third display element corresponding to the first pixel area, the second pixel area, and the third pixel area, respectively, wherein the upper display substrate includes: a base substrate; a light shielding pattern, which is arranged on a bottom surface of the base substrate, overlaps with the light shielding area, and includes a first opening portion, a second opening portion, and a third opening portion defined therein, which correspond to the first pixel area, the second pixel area, and the third pixel area, respectively; a first color filter, a second color filter, and a third color filter, which are arranged on the bottom surface of the base substrate and overlap with the light shielding area The first pixel area, the second pixel area and the third pixel area are overlapped respectively; the partition wall is arranged on the lower side of the first color filter, the second color filter and the third color filter, overlaps with the shading area, and includes a first partition wall opening portion, a second partition wall opening portion and a third partition wall opening portion defined therein and corresponding to the first pixel area, the second pixel area and the third pixel area respectively; and the first color control layer, the second color control layer and the third color control layer are arranged in the first partition wall opening portion, the second partition wall opening portion and the third partition wall opening portion, respectively, wherein the partition wall includes a first layer and a second layer, the second layer is directly arranged on the lower side of the first layer and has an optical density greater than the optical density of the first layer, and in a cross-sectional view, a portion of the second layer protrudes downward from the first color control layer, the second color control layer and the third color control layer.

[0006] In an embodiment, when the thickness of the second layer is 1 μm, the optical density of the second layer may be from about 0.15 to about 0.5.

[0007] In an embodiment, the second layer may include a hydrophobic region and a hydrophilic region disposed between the hydrophobic region and the first layer.

[0008] In an embodiment, the second layer may have a thickness from about 7 μm to about 10 μm.

[0009] In an embodiment, the hydrophilic region includes a base resin and a black colorant mixed with the base resin, and the hydrophobic region includes a hydrophobic agent chemically bonded to the base resin.

[0010] In an embodiment, the hydrophobic region may have a thickness from about 30 nm to about 200 nm.

[0011] In an embodiment, each of the first color control layer, the second color control layer, and the third color control layer may have a thickness of about 15 μm or more.

[0012] In an embodiment, a height of the partition wall in the light shielding region may be higher than a height of each of the first color control layer, the second color control layer, and the third color control layer.

[0013] In an embodiment, the thickness of the first layer may be from about 5 μm to about 15 μm, and the thickness of the second layer may be from about 5 μm to about 10 μm.

[0014] In an embodiment, the width of the first layer may be from about 10 μm to about 15 μm.

[0015] In an embodiment, the second layer may completely overlap the first layer in plan view.

[0016] In an embodiment, the light shielding pattern may include a blue first light shielding layer and a black second light shielding layer, and the second light shielding layer at least covers a bottom surface of the first light shielding layer.

[0017] In an embodiment, each of the first display element, the second display element, and the third display element may include a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode, and the emission layers of the first display element, the second display element, and the third display element may have an integral shape and generate blue light.

[0018] In an embodiment, the first color control layer may include first quantum dots configured to convert blue light into red light, the second color control layer may include second quantum dots configured to convert blue light into green light, and the third color control layer may transmit blue light.

[0019] In an embodiment of the inventive concept, a display panel includes an upper display substrate and a lower display substrate, the upper display substrate including a pixel area and a peripheral area in the periphery of the pixel area, and the lower display substrate including a display element arranged to correspond to the pixel area, wherein the upper display substrate includes: a base substrate; a shading pattern, which is arranged on the bottom surface of the base substrate, overlapping with the peripheral area, and including an opening portion corresponding to the pixel area defined therein; a color filter, which is arranged on the bottom surface of the base substrate and overlapping with the pixel area; an encapsulation layer, which is arranged on the lower side of the shading pattern and the color filter; a partition wall, which is arranged on the lower side of the encapsulation layer, overlapping with the peripheral area, and including a partition wall opening portion corresponding to the pixel area defined therein; and a quantum dot layer, which is arranged in the partition wall opening portion, wherein the partition wall includes a first layer and a second layer, the first layer is directly arranged on the bottom surface of the encapsulation layer, and the second layer is directly arranged on the lower side of the first layer and has a greater optical density than the first layer.

[0020] In an embodiment of the inventive concept, a method for manufacturing a display panel includes manufacturing a first display substrate including a display element, manufacturing a second display substrate including a pixel area corresponding to the display element and a shading area in the periphery of the pixel area, and combining the first display substrate and the second display substrate, wherein the manufacturing of the second display substrate includes the following steps: forming a shading pattern on a base substrate to overlap with the shading area; forming a color filter overlapping with the pixel area; forming a first initial partition wall layer on the base substrate; exposing the first initial partition wall layer so that a first area of ​​the first initial partition wall layer overlapping with the shading pattern is separated from a second area arranged in the periphery of the first area; forming a second initial partition wall layer on the exposed first initial partition wall layer; exposing the second initial partition wall layer so that a third area of ​​the second initial partition wall layer corresponding to the first area is separated from a fourth area corresponding to the second area; developing the first initial partition wall layer and the second initial partition wall layer so that a partition wall and a partition wall opening portion surrounded by the partition wall are formed; and forming a quantum dot layer in the partition wall opening portion.

[0021] In an embodiment, the forming of the second preliminary partition wall layer may include forming a composition layer including a base resin, a black colorant, and a hydrophobic agent on the first preliminary partition wall layer; drying the composition layer; and primarily baking the composition layer to provide heat thereto.

[0022] In an embodiment, the primary baked composition layer may include a hydrophilic region including a matrix resin and a black colorant and a hydrophobic region including a hydrophobic agent chemically bonded to the matrix resin.

[0023] In an embodiment, the manufacturing method may further include: after the developing, second baking the partition wall to provide heat thereto, wherein a temperature in the second baking is higher than a temperature in the first baking.

[0024] In an embodiment, the forming of the first preliminary partition wall layer may include: forming a composition layer including a base resin on the base substrate; drying the composition layer; and baking the composition layer to provide heat thereto. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0026] Figure 1A is a perspective view of a display panel according to an embodiment of the inventive concept;

[0027] Figure 1B is a cross-sectional view of a display panel according to an embodiment of the inventive concept;

[0028] Figure 2 is a plan view of a display panel according to an embodiment of the inventive concept;

[0029] Figure 3A is a plan view of a pixel area of ​​a display panel according to an embodiment of the inventive concept;

[0030] Figure 3B is a cross-sectional view of a pixel region of a display panel according to an embodiment of the inventive concept;

[0031] Figure 3C is a cross-sectional view of a pixel region of an upper display substrate according to an embodiment of the inventive concept;

[0032] Figure 4 is a flow chart illustrating a method of manufacturing a display panel according to an embodiment of the inventive concept;

[0033] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E is a diagram illustrating a method of manufacturing an upper display substrate according to an embodiment of the inventive concept;

[0034] Fig. 6A and Figure 6B is a diagram illustrating a method of manufacturing an upper display substrate according to an embodiment of the inventive concept; and

[0035] Fig. 7A and Figure 7B is a cross-sectional view of a pixel region of an upper display substrate according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0036] The inventive concept can be modified in various ways and implemented in various forms, so specific embodiments will be illustrated in the drawings and described in detail below. However, it will be understood that the inventive concept is not intended to be limited to the specific form set forth herein, and includes all changes, equivalents and substitutions included in the technical scope and spirit of the inventive concept.

[0037] With reference to the accompanying drawings, the same reference numerals always represent the same components. In the accompanying drawings, the size of the structure may be exaggerated or reduced for clarity of illustration. Terms such as first, second, etc. may be used to describe various components, but these components should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component. The singular forms "one", "an", and "the (said)" are also intended to include plural forms unless the context clearly indicates otherwise.

[0038] It will be understood that the terms “including” or “having” when used in this specification are intended to specify the presence of the stated features, integers, steps, operations, components or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components or combinations thereof.

[0039] Figure 1A is a perspective view of a display panel DP according to an embodiment of the inventive concept. Figure 1B is a cross-sectional view of a display panel DP according to an embodiment of the inventive concept. Figure 2 is a plan view of a display panel DP according to an embodiment of the inventive concept.

[0040] Reference Figure 1A to Figure 2 The display panel DP may be any one of a liquid crystal display panel, an electrophoretic display panel, a micro-electromechanical system (MEMS) display panel, an electrowetting display panel, and an organic light emitting display panel, but is not particularly limited thereto.

[0041] Although not separately shown, the display panel DP may further include a frame member or a molding member, and may further include a backlight unit according to the type of the display panel DP.

[0042] The display panel DP may include a first display substrate 100 (or a lower display substrate) and a second display substrate 200 (or an upper display substrate) facing the first display substrate 100 and spaced apart from the first display substrate 100. A predetermined cell gap may be formed between the first display substrate 100 and the second display substrate 200. The cell gap may be maintained by a sealant SLM that combines the first display substrate 100 and the second display substrate 200. A grayscale display layer for image generation may be disposed between the first display substrate 100 and the second display substrate 200. Depending on the type of the display panel, the grayscale display layer may include a liquid crystal display layer, an organic light emitting display layer, and an electrophoretic display layer.

[0043] like Figure 1A As shown in , the display panel DP may display an image on a display surface DP-IS. The display surface DP-IS is parallel to a surface defined by a first direction axis DR1 and a second direction axis DR2. The display surface DP-IS may include a display area DA and a non-display area NDA. The pixel PX is disposed in the display area DA and the pixel PX is not disposed in the non-display area NDA. The non-display area NDA is defined along an edge of the display surface DP-IS. The display area DA may be surrounded by the non-display area NDA.

[0044] The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) is indicated by the third directional axis DR3. The front surface (or upper surface) and the rear surface (or lower surface) of each layer or unit to be described below are defined by the third directional axis DR3. However, the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3 shown in the present embodiment are only examples. Hereinafter, the first direction, the second direction, and the third direction are defined as the directions indicated by the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3, respectively, and refer to the same figure marks.

[0045] In an embodiment of the inventive concept, the display panel DP is shown to include a flat display surface DP-IS, but is not limited thereto. The display panel DP may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas facing different directions.

[0046] Figure 2 A planar arrangement relationship of the signal lines GL1 to GLn and DL1 to DLm and the pixels PX11 to PXnm is shown. The signal lines GL1 to GLn and DL1 to DLm may include a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm.

[0047] Each of the pixels PX11 to PXnm is connected to a corresponding gate line among a plurality of gate lines GL1 to GLn and a corresponding data line among a plurality of data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a display element. According to the configuration of the pixel driving circuit of the pixels PX11 to PXnm, the display panel DP may include an additional signal line.

[0048] The pixels PX11 to PXnm are exemplarily shown as having a matrix type, but the types of the pixels PX11 to PXnm are not limited thereto. The pixels PX11 to PXnm may be arranged in a PenTile type. The pixels PX11 to PXnm may be arranged in a diamond type. The gate drive circuit GDC may be integrated into the display panel DP by an oxide silicon gate driver circuit (OSG) process or an amorphous silicon gate driver circuit (ASG) process.

[0049] Figure 3A is a plan view of pixel areas PXA-R, PXA-G, and PXA-B of a display panel DP according to an embodiment of the inventive concept. Figure 3B is a cross-sectional view of a pixel area PXA-G of a display panel DP according to an embodiment of the inventive concept. Figure 3C is a cross-sectional view of a pixel area PXA-G of an upper display substrate 200 according to an embodiment of the inventive concept.

[0050] Figure 3A yes Figure 1A An enlarged view of a portion of the display area DA shown in FIG. In the figure, three types of pixel areas PXA-R, PXA-G, and PXA-B are mainly shown. Figure 3A The three types of pixel areas PXA-R, PXA-G, and PXA-B shown in FIG. 1 may be repeatedly disposed in the entire display area DA.

[0051] The light shielding area or peripheral area NPXA is disposed on the periphery of the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B. The light shielding area NPXA may be defined as a peripheral area. The light shielding area NPXA is disposed at the boundary of the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, and prevents color mixing between the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B.

[0052] In the present embodiment, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B are shown to have the same plane area, but are not limited thereto. The areas of at least two of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may be different. The first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B are shown in a plan view as having a rectangular shape with a rounded corner area, but are not limited thereto. In a plan view, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have another polygonal shape such as a rhombus or a pentagonal shape.

[0053] One of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B provides a first color light corresponding to the source light, another provides a second color light different from the first color light, and the remaining one provides a third color light different from the first color light and the second color light. In the present embodiment, the first pixel region PXA-R may provide red light, the second pixel region PXA-G may provide green light, and the third pixel region PXA-B may provide blue light.

[0054] The partition wall overlaps the light shielding area NPXA. A first partition wall opening portion OP-R, a second partition wall opening portion OP-G, and a third partition wall opening portion OP-B corresponding to the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, respectively, are defined in the partition wall.

[0055] Figure 3B It is along Figure 3A A cross-sectional view taken along line II′. Figure 3B A cross section of the display panel DP corresponding to the second pixel area PXA-G is shown. Figure 3B A cross section corresponding to a driving transistor TD and an organic light emitting element (hereinafter referred to as a light emitting element) OLED is exemplarily shown. The upper display substrate 200 and the lower display substrate 100 may provide a predetermined gap GP.

[0056] like Figure 3B As shown in FIG. 1 , the lower display substrate 100 includes a first base substrate BS1 , a circuit element layer DP-CL disposed on the first base substrate BS1 , and a display element layer DP-OLED disposed on the circuit element layer DP-CL.

[0057] The first base substrate BS1 may include a synthetic resin substrate or a glass substrate. The circuit element layer DP-CL includes a circuit element and at least one insulating layer. The circuit element includes a signal line and a driving circuit of a pixel, etc. The circuit element layer DP-CL may be formed by a process of providing an insulating layer, a semiconductor layer, and a conductive layer through coating, deposition, etc., and a process of patterning the insulating layer, the semiconductor layer, and the conductive layer through a photolithography process.

[0058] In the present embodiment, the circuit element layer DP-CL may include a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30. The first insulating layer 10 and the second insulating layer 20 may be inorganic layers, and the third insulating layer 30 may be an organic layer.

[0059] Figure 3B The arrangement relationship among the semiconductor pattern OSP, the control electrode GE, the input electrode DE, and the output electrode SE constituting the driving transistor TD is exemplarily shown. The first through hole CH1, the second through hole CH2, and the third through hole CH3 are also shown as examples.

[0060] The display element layer DP-OLED includes a light emitting element OLED. The light emitting element OLED can generate the source light described above. The light emitting element OLED includes a first electrode, a second electrode and an emission layer disposed between the first electrode and the second electrode. In the present embodiment, the display element layer DP-OLED may include an organic light emitting diode as a light emitting element. The display element layer DP-OLED includes a pixel defining layer PDL. For example, the pixel defining layer PDL may be an organic layer.

[0061] The first electrode AE ​​is disposed on the third insulating layer 30. The first electrode AE ​​is connected to the output electrode SE through a third through hole CH3 configured to penetrate through the third insulating layer 30. An opening portion OP is defined in the pixel defining layer PDL. The opening portion OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE.

[0062] The hole control layer HCL, the emission layer EML, and the electron control layer ECL may be commonly disposed in the second pixel region PXA-G and the light shielding region NPXA. The hole control layer HCL, the emission layer EML, and the electron control layer ECL may be commonly disposed in the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B (see Figure 3A )middle.

[0063] The hole control layer HCL may include a hole transport layer and may further include a hole injection layer. The emission layer EML may generate blue light. The blue light may include a wavelength of 410nm to 480nm. The emission spectrum of the blue light may have a maximum peak within 440nm to 460nm. The electron control layer ECL may include an electron transport layer and may further include an electron injection layer.

[0064] The second electrode CE is disposed on the electronic control layer ECL. The second electrode CE may be commonly disposed in the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. Therefore, the second electrode CE has an area larger than that of the first electrode AE. A cover layer CL configured to protect the second electrode CE may be further disposed on the second electrode CE. The cover layer CL may include an organic material or an inorganic material.

[0065] The lower display substrate 100 may include Figure 3A The first pixel region PXA-R, the second pixel region PXA-G and the third pixel region PXA-B shown in FIG. 1 correspond to the first display element, the second display element and the third display element respectively. The stacked structures of the first display element, the second display element and the third display element may be the same as each other and have the following structure: Figure 3B However, the stacked structures of the first display element, the second display element, and the third display element may be different from each other, for example, the emission layers EML in the first display element, the second display element, and the third display element may emit light of different colors.

[0066] like Figure 3B As shown in FIG. 1 , the upper display substrate 200 may include a second base substrate BS2 , a light blocking pattern BM disposed on a bottom surface of the second base substrate BS2 , a color filter CF-G, a partition wall WP, and a color control layer CCF-G.

[0067] The second base substrate BS2 may include a synthetic resin substrate or a glass substrate. The light shielding pattern BM is disposed on the bottom surface of the second base substrate BS2. The light shielding pattern BM is disposed in the light shielding area NPXA. The opening portions BM-OP corresponding to the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, respectively, are defined in the light shielding pattern BM. In the present embodiment, the second pixel area PXA-G is defined to correspond to the opening portion BM-OP of the light shielding pattern BM.

[0068] The color filter CF-G is arranged on the shading pattern BM on the bottom surface of the second base substrate BS2. The color filter CF-G includes a base resin and a dye and / or a pigment dispersed in the base resin. The base resin is a material in which the dye and / or the pigment are dispersed, and may be composed of various resin compositions generally referred to as a binder. The color filter CF-G is superimposed on the pixel area PXA-G. The edge area of ​​the color filter CF-G may overlap with the shading area NPXA. A portion of the shading pattern BM may be arranged between the color filter CF-G and the bottom surface of the second base substrate BS2.

[0069] about Figure 3A and Figure 3B , the first color filter CF-R, the second color filter CF-G, and the third color filter CF-B are arranged to correspond to the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, respectively. The first color filter CF-R, the second color filter CF-G, and the third color filter CF-B include dyes and / or pigments configured to absorb light of different wavelength bands. The first color filter CF-R may be a red color filter, the second color filter CF-G may be a green color filter, and the third color filter CF-B may be a blue color filter.

[0070] The first color filter CF-R, the second color filter CF-G, and the third color filter CF-B reduce the reflection ratio of external light. Each of the first color filter CF-R, the second color filter CF-G, and the third color filter CF-B transmits light within a specific wavelength range and absorbs or intercepts light having a wavelength other than the specific wavelength band. Each of the first color filter CF-R, the second color filter CF-G, and the third color filter CF-B can absorb light having a wavelength other than the specific wavelength range.

[0071] The first encapsulation layer ENL1 is disposed on the color filter CF-G. The first encapsulation layer ENL1 encapsulates the color filter CF-G. The first encapsulation layer ENL1 may be commonly disposed in the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B.

[0072] The first encapsulation layer ENL1 may include an inorganic layer. The first encapsulation layer ENL1 may include any one of silicon oxide, silicon nitride, and silicon oxynitride. The first encapsulation layer ENL1 may further include an organic layer configured to form a flat bottom surface.

[0073] The partition wall WP is disposed on the bottom surface of the first encapsulation layer ENL1. The partition wall WP may completely overlap the light shielding pattern BM disposed on the light shielding area NPXA. The partition wall WP defines Figure 3AThe first pixel area PXA-R, the second pixel area PXA-G and the third pixel area PXA-B correspond to the first internal area, the second internal area and the third internal area (or the first internal space, the second internal space and the third internal space) respectively.

[0074] The partition wall WP prevents the color control layers CCF-R, CCF-G and CCF-B from being formed. Figure 3A The first pixel area PXA-R, the second pixel area PXA-G and the third pixel area PXA-B are mixed.

[0075] The color control layer CCF-G is disposed inside the partition wall WP. In this embodiment, the color control layer CCF-G can absorb the first color light generated by the light emitting element OLED and then generate other color lights. The color control layer CCF-G can transmit and / or scatter the first color light.

[0076] The color control layer CCF-G may include a matrix resin and quantum dots mixed with the matrix resin (or dispersed in the matrix resin). In the present embodiment, the color control layer CCF-G may be defined as a quantum dot layer. The matrix resin is a material or medium in which the quantum dots are dispersed, and may include various resins generally referred to as binders. However, the matrix resin here is not limited thereto, and in this specification, the material in which the quantum dots can be uniformly dispersed may be referred to as a matrix resin, regardless of its name, other functions attached, materials, etc. The matrix resin may be a polymer resin. For example, the matrix resin may be an acrylic resin, a urethane resin, a silicone resin, an epoxy resin, etc. The matrix resin may be a transparent resin.

[0077] Quantum dots may be particles configured to convert the wavelength of incident light. Quantum dots are materials having a crystal structure with a size of several nanometers, composed of hundreds to thousands of atoms, and exhibit a quantum confinement effect in which the energy band gap increases due to its small size. When light of a wavelength having higher energy than the band gap is incident on the quantum dot, the quantum dot absorbs the light to become an excited state, and falls to a ground state while emitting light of a specific wavelength. The emitted light of a specific wavelength has a value corresponding to the band gap. When the size and composition of the quantum dot are adjusted, the emission characteristics can be adjusted due to the quantum confinement effect.

[0078] The quantum dots may be selected from Group II-VI compounds, Group I-III-VI compounds, Group III-V compounds, Group IV-VI compounds, Group IV elements, Group IV compounds, and combinations thereof.

[0079] The II-VI compound may include one selected from the group consisting of: a binary compound selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; a ternary compound selected from the group consisting of AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZn S, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; a quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof; and combinations thereof.

[0080] The I-III-VI group compound includes one selected from the group consisting of: a ternary compound selected from AgInS 2 、CuInS 2 、AgGaS 2 、CuGaS 2 and mixtures thereof; quaternary compounds selected from AgInGaS 2 、CuInGaS 2 and mixtures thereof; and combinations thereof.

[0081] The III-V compound includes one selected from the group consisting of the following substances: a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; a ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb and mixtures thereof; a quaternary compound selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof; and combinations thereof. At the same time, the III-V compound may also include a Group II metal. For example, InZnP or the like may be selected as the III-II-V group compound.

[0082] The IV-VI group compound includes one selected from the group consisting of the following substances: a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; a ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof; and combinations thereof. The IV group element may be selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe and mixtures thereof.

[0083] Here, the binary compound, the ternary compound, or the quaternary compound may exist in the interior of the particle at a uniform concentration, or may exist in the interior of the same particle at a concentration distribution divided into locally different states.

[0084] The quantum dot may have a core-shell structure including a core and a shell surrounding the core. In addition, a core-shell structure in which one quantum dot surrounds another quantum dot may be possible. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the core.

[0085] The quantum dots may be particles having a nanoscale size. The quantum dots may have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less (preferably, about 40 nm or less, more preferably, about 30 nm or less), and within this range, color purity or color gamut may be improved. In addition, light emitted by such quantum dots is emitted omnidirectionally, so that the viewing angle may be improved.

[0086] Furthermore, the type of quantum dots is not particularly limited to the one commonly used in the technical field, but more specifically, spherical, pyramidal, multi-armed, or cubic nanoparticles, nanotubes, nanowires, nanofibers or nanoplanar particles, etc. may be used.

[0087] about Figure 3A and Figure 3B , the first color control layer CCF-R, the second color control layer CCF-G, and the third color control layer CCF-B are arranged to correspond to the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B. The first color control layer CCF-R absorbs blue light to generate red light, and the second color control layer CCF-G absorbs blue light to generate green light. In other words, the first color control layer CCF-R and the second color control layer CCF-G may include quantum dots different from each other. The third color control layer CCF-B may transmit blue light.

[0088] The first color control layer CCF-R, the second color control layer CCF-G, and the third color control layer CCF-B may further include scattering particles. The scattering particles may be titanium oxide (TiO 2 ) or silica-based nanoparticles, etc.

[0089] The second encapsulation layer ENL2 is disposed on the partition wall WP and the color control layer CCF-G. The second encapsulation layer ENL2 encapsulates the partition wall WP and the color control layer CCF-G. The second encapsulation layer ENL2 may be commonly disposed in the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B (see Figure 3A )middle.

[0090] The second encapsulation layer ENL2 may include an inorganic layer configured to contact the partition wall WP and the color control layer CCF-G. The inorganic layer may include any one of silicon oxide, silicon nitride, and silicon oxynitride. The second encapsulation layer ENL2 may further include an organic layer disposed on the inorganic layer. The organic layer may form a flat bottom surface. The first encapsulation layer ENL1 may include silicon oxide, and the second encapsulation layer ENL2 may include silicon nitride.

[0091] Figure 3BThe color control layer CCF-G shown in FIG includes a base resin and quantum dots, and the weight % (weight percentage) of the quantum dots on the entire color control layer CCF-G is less than a reference value. When the weight % of the quantum dots is greater than the reference value, the bonding force of the color control layer CCF-G with the partition wall WP and the first encapsulation layer ENL1 is reduced, thereby causing defects.

[0092] In order to improve the photoelectric conversion efficiency, the weight of the quantum dots should be greater than the reference weight. By increasing the thickness of the color control layer CCF-G, the weight of the quantum dots can be adjusted to be greater than the reference weight. In the present embodiment, the thickness of the color control layer CCF-G may be 15 μm or greater. The upper limit value of the thickness of the color control layer CCF-G is not specifically limited, but is formed to have a height lower than that of the partition wall WP.

[0093] The height of the partition wall WP may be higher than the height of each of the first color control layer CCF-R, the second color control layer CCF-G, and the third color control layer CCF-B. The height of the color control layer CCF-G and the height of the partition wall WP are values ​​measured on the third directional axis DR3. The partition wall WP prevents the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B (see FIG. 2 ) from being formed. Figure 3A ) when different compositions are mixed.

[0094] The partition wall WP may include two layers. The first layer WP1 may be directly disposed on the first encapsulation layer ENL1. The second layer WP2 may be directly disposed on the first layer WP1. The first layer WP1 and the second layer WP2 are formed by different processes and thus have a boundary. In the cross-sectional view, a portion of the second layer WP2 protrudes downward from the first color control layer CCF-R, the second color control layer CCF-G, and the third color control layer CCF-B.

[0095] The first layer WP1 and the second layer WP2 may have different materials. The first layer WP1 and the second layer WP2 may commonly include a base resin, a coupling agent, and a photoinitiator. The base resin may include various resins that may be generally referred to as a binder. The first layer WP1 and the second layer WP2 may also include a dispersant. The second layer WP2 may also include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof.

[0096] The first layer WP1 may not include a black colorant, or may include a black colorant having a smaller weight % than the second layer WP2. Therefore, the optical density of the second layer WP2 may have a value greater than or equal to the optical density of the first layer WP1. In the present embodiment, when the thickness of the second layer WP2 is 1 μm, the optical density of the second layer WP2 may be from about 0.15 to about 0.5. The second layer WP2 may prevent the first color light generated in the light emitting element OLED from being incident on the adjacent pixel regions PXA-R and PXA-B (see Figure 3A ).

[0097] Each of the first layer WP1 and the second layer WP2 may be formed by an exposure process and a development process. The partition wall WP having an optical density of about 0.2 to about 0.5 in total has a low transmittance, and therefore, when the thickness of the partition wall WP is thicker than a reference value, the light exposure efficiency becomes lower. In a process of manufacturing a partition wall WP consisting only of the second layer WP2 having a thickness thicker than a reference value, a region adjacent to the first encapsulation layer ENL1 may be in an exposed state to cause a defect.

[0098] In the present embodiment, the thickness of the second layer WP2 may be from about 5 μm to about 10 μm so that exposure is sufficiently performed. The thickness of the first layer WP1 may be from about 5 μm to about 15 μm. Since the first layer WP1 has a lower optical density, the exposure efficiency of the first layer WP1 is high. In addition, double exposure may be performed when forming the partition wall WP, and defects in the partition wall WP may be reduced.

[0099] about Figure 3C , the light shielding pattern BM may include a first light shielding layer BM1 and a second light shielding layer BM2. The first light shielding layer BM1 may be directly formed on the bottom surface of the second base substrate BS2. The first light shielding layer BM1 may include the same material as the blue color filter.

[0100] The second light shielding layer BM2 may cover at least the bottom surface of the first light shielding layer BM1. Figure 3C As shown in FIG, the second light shielding layer BM2 may also cover the side surface of the first light shielding layer BM1.

[0101] The second light shielding layer BM2 may be a typical black matrix. The second light shielding layer BM2 has a black color. The second light shielding layer BM2 may include a matrix resin and a black colorant mixed with the matrix resin. When the thickness of the second light shielding layer BM2 is 1 μm, the optical density of the second light shielding layer BM2 may be from about 1 to about 3.

[0102] Since the refractive index difference between the first light shielding layer BM1 and the second base substrate BS2 is smaller than the refractive index difference between the second light shielding layer BM2 and the second base substrate BS2, the first light shielding layer BM1 having the same material as the blue color filter may reduce reflection of external light.

[0103] Reference Figure 3C , the first layer WP1 has a smaller width than the light shielding pattern BM. The width W1 of the first layer WP1 may be from about 10 μm to about 15 μm. The width W2 of the second layer WP2 may be smaller than the width W1 of the first layer WP1. The width W2 of the second layer WP2 and the width W1 of the first layer WP1 are measured in the second direction DR2. In a plan view, the second layer WP2 may completely overlap the first layer WP1. In a plan view, the first layer WP1 may completely overlap the light shielding pattern BM.

[0104] However, embodiments of the inventive concept are not limited to the above numerical range. The width of the light blocking area NPXA may be differently set according to the resolution of the display panel, and the width W1 of the first layer WP1 may be wider or narrower than the above range.

[0105] The corner region of the first layer WP1 is partially removed by the developer, and thus the corner may not be substantially defined in the first layer WP1. Figure 3C A corner area of ​​the above-mentioned first layer WP1 is shown. In cross section, the corner may not be substantially formed in the first layer WP1. A chamfer is arranged in the first layer WP1.

[0106] about Figure 3C , the second layer WP2 may include two regions with different properties in cross section. The second layer WP2 may include a hydrophilic region WP2-A1 and a hydrophobic region WP2-A2.

[0107] The hydrophobic region WP2-A2 is disposed farther from the first layer WP1 than the hydrophilic region WP2-A1. The hydrophilic region WP2-A1 is disposed between the hydrophobic region WP2-A2 and the first layer WP1. The hydrophobic region WP2-A2 prevents different color control layers CCF-R, CCF-G, and CCF-B from being formed in the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B (see FIG. Figure 3A ) at the boundaries between them.

[0108] The thickness of the second layer WP2 including the hydrophilic region WP2-A1 and the hydrophobic region WP2-A2 may be from about 7 μm to about 10 μm. The hydrophilic region WP2-A1 may include a base resin and a black colorant mixed with the base resin. The hydrophobic region WP2-A2 may include a base resin and a hydrophobic agent chemically bonded to the base resin. The hydrophobic agent is phase-separated in a process for setting the second layer WP2 and then densely concentrated on the bottom surface of the second layer WP2. The thickness of the hydrophobic region WP2-A2 may be from about 30 nm to about 200 nm.

[0109] The hydrophobic agent may include fluorine-based epoxy series materials and perfluoroether series system materials. Asahi Kasei Corporation's product name S-656, S-611, S-386 or S-243, DIC Corporation's product name RS-56 or RS-76NS, Daikin Industries' product name DAC-HP or Fluorotech's product name FS-7024 hydrophobic agent may be used to form the partition wall WP.

[0110] Figure 4 is a flowchart illustrating a method of manufacturing a display panel DP according to an embodiment of the inventive concept. FIG. 5A to FIG. 5E FIG. 2 shows a method for manufacturing an upper display substrate 200 according to an embodiment of the inventive concept. Figures 1A to 3C The components described are the same as the detailed descriptions of the components.

[0111] like Figure 4 As shown in FIG. 1 , a first display substrate including first to third display elements is manufactured (operation S10). The first display substrate may be a reference Figures 1A to 3B The lower display substrate 100 is described, that is, an array substrate. The first display substrate may be manufactured according to a typical manufacturing method.

[0112] In addition, the second display substrate is manufactured (operation S20). The manufacturing order of the first display substrate and the second display substrate is not particularly limited.

[0113] Then, the first display substrate and the second display substrate are combined (operation S30). A non-display area NDA (see FIG. 1 ) on one of the first display substrate and the second display substrate is formed. Figure 1A ), and then the first display substrate and the second display substrate may be combined. After the combination, the initial sealant may be cured.

[0114] Will refer to FIG. 5A to FIG. 5E The method of manufacturing the second display substrate 200 is described in more detail. FIG. 5A to FIG. 5E Shown with Figure 3C The accompanying drawings in FIG.

[0115] like Figure 5A As shown in the figure, a light shielding pattern BM is formed on the second base substrate BS2. In the present embodiment, the light shielding pattern BM can be formed by printing an inorganic material of a specific color on a specific area of ​​the second base substrate BS2. In an embodiment of the inventive concept, an organic layer of a specific color is formed on one surface of the second base substrate BS2, and then the organic layer is exposed and developed to form a first light shielding layer BM1.

[0116] After forming the first light shielding layer BM1, a second light shielding layer BM2 may be formed to form a light shielding pattern BM having a double-layer structure. A second preliminary partition wall layer may be formed and then exposed and developed to form a second light shielding layer BM2.

[0117] like Figure 5B As shown in , color filters CF-R, CF-G, and CF-B are formed on the second base substrate BS2. In the present embodiment of the inventive concept, an organic layer having a predetermined color is formed on one surface of the second base substrate BS2, and then the organic layer is exposed and developed to form color filters CF-R, CF-G, and CF-B. In order to form three color filters, one cycle process of forming an organic layer, exposing the organic layer, and developing the organic layer can be performed three times.

[0118] like Figure 5B As shown in FIG, a first encapsulation layer ENL1 is formed on the color filters CF-R, CF-G, and CF-B. An inorganic material is deposited to form the first encapsulation layer ENL1.

[0119] like Figure 5B As shown in , a first preliminary partition wall layer WPL1 is formed on the first encapsulation layer ENL1. A first composition may be applied to form the first preliminary partition wall layer WPL1. The first composition may include a base resin, a coupling agent, and a photoinitiator. The first composition may also include a black colorant. The first composition may also include a dispersant.

[0120] like Figure 5B As shown in , the first preliminary partition wall layer WPL1 may be exposed so that the first region W-A1 overlapped with the light shielding pattern BM is exposed to light. Since the first preliminary partition wall layer WPL1 exposed to light is not developed and other portions of the first preliminary partition wall layer WPL1 are developed, the second region W-A2 may be surrounded by the first region W-A1. The first preliminary partition wall layer WPL1 may be exposed using a first mask MSK1 formed with an opening region corresponding to the first region W-A1.

[0121] Before exposure, the second base substrate BS2 on which the first preliminary partition wall layer WPL1 is formed is disposed in a vacuum chamber to dry the first preliminary partition wall layer WPL1. The dried first preliminary partition wall layer WPL1 may be baked at a first temperature. The first temperature may be from about 90° C. to about 130° C. Then, the above-mentioned exposure process may be performed.

[0122] like Figure 5C As shown in, a second initial partition wall layer WPL2 is formed on the first initial partition wall layer WPL1 after exposure. The second initial partition wall layer WPL2 can be formed by coating with a second composition. The second composition may include a base resin, a coupling agent, and a photoinitiator. The second composition may also include a black colorant. The second composition may also include a dispersant. The weight % of the black colorant of the second composition may be greater than the weight % of the black colorant of the first composition.

[0123] like Figure 5C As shown in , the second initial partition wall layer WPL2 may be exposed so that the third region W-A10 overlapping the first region W-A1 of the first initial partition wall layer WPL1 is exposed to light. Since the second initial partition wall layer WPL2 exposed to light is not developed, the third region W-A10 may surround the fourth region W-A20 disposed to overlap the second region W-A2. The second initial partition wall layer WPL2 may be exposed using a second mask MSK2 formed with an opening region corresponding to the third region W-A10.

[0124] Using the second mask MSK2 including the third region W-A10 having a smaller width than the first region W-A1 can prevent the first layer WP1 from being misaligned with the second layer WP2 due to process errors. In other words, in a plan view, the second layer WP2 can completely overlap the first layer WP1.

[0125] In an embodiment of the inventive concept, the second preliminary partition wall layer WPL2 may be exposed using the first mask MSK1 instead of the second mask MSK2.

[0126] Before exposure, the second base substrate BS2 on which the second preliminary partition wall layer WPL2 is formed may be disposed in a vacuum chamber to dry the second preliminary partition wall layer WPL2. The dried second preliminary partition wall layer WPL2 may be baked at a second temperature. The second temperature may be set higher than the first temperature. The second temperature may be from about 100° C. to about 140° C. Then, the above-mentioned exposure process may be performed.

[0127] Although in Figure 5C Although not shown in detail, the third region W-A10 may include a hydrophilic region WP2-A1 (see Figure 3C) and the hydrophobic region WP2-A2 (see Figure 3C ). The second composition may further include a hydrophobic agent. Phase separation occurs after coating the second initial partition wall layer WPL2. The hydrophobic agent separates from the hydrophilic material and moves toward the top surface of the second initial partition wall layer WPL2. Such phase separation is accelerated by a baking process at a second temperature.

[0128] In order to form the hydrophobic area WP2-A2 having a thickness of from about 30 nm to about 200 nm, the second initial partition wall layer WPL2 is formed to have a thickness of about 7 μm or more. The maximum weight % of the hydrophobic agent is limited due to the adverse effect of the hydrophobic agent, which increases as the amount of the hydrophobic agent increases. Therefore, in order to increase the hydrophobic agent included in the entire second initial partition wall layer WPL2, the second initial partition wall layer WPL2 is formed to have a thickness equal to or greater than a predetermined thickness.

[0129] The polymer and monomer of the second composition are polymerized during the exposure process, and the hydrophobic agent may also be chemically combined with the polymer and / or monomer. In this way, a hydrophobic region WP2-A2 is formed in a region adjacent to the top surface of the third region W-A10.

[0130] like Figure 5D As shown in FIG. 1 , the first preliminary partition wall layer WPL1 and the second preliminary partition wall layer WPL2 may be developed to remove the second area W-A2 and the fourth area W-A20. The second area W-A2 and the fourth area W-A20 having the same base material may be developed in one development process by using the same developer.

[0131] After the developing process, the partition wall WP may be baked at a third temperature. The third temperature may be from about 200° C. to about 250° C. The partition wall WP is baked at a high temperature to increase its strength.

[0132] Reference FIG. 5A to FIG. 5D Because the second preliminary partition wall layer WPL2 is formed and then exposed before the first preliminary partition wall layer WPL1 is developed, the first region W-A1 overlapping the third region W-A10 may have a substantially flat surface.

[0133] like Figure 5E As shown in FIG. 1 , a second color control layer CCF-G is formed inside the second partition wall opening portion OP-G. Color control layers CCF-R, CCF-G, and CCF-B are sequentially formed to Figure 3AThe first partition wall opening portion OP-R, the second partition wall opening portion OP-G and the third partition wall opening portion OP-B shown in the figure correspond to each other, and hereinafter, a method of manufacturing a color control layer CCF-G will be described. A composition (hereinafter, color composition) for constituting the second color control layer CCF-G inside the second partition wall opening portion OP-G is formed.

[0134] The color composition may be formed inside the second partition wall opening portion OP-G using an inkjet process. The hydrophobic area WP2-A2 (see FIG. 2A ) formed on the top surface of the partition wall WP Figure 3C ) prevents the color composition from being formed on the partition wall WP, thereby forming the color composition only in the second partition wall opening portion OP-G.

[0135] The color composition includes a matrix resin and quantum dots. The matrix resin may include an epoxy polymer and / or a monomer. The color composition may also include scattering particles. The color composition is dried under vacuum. Then, a first baking process and a second baking process are performed.

[0136] The first baking temperature may be from about 90° C. to about 130° C. The second baking temperature may be from about 180° C. to about 240° C. The color control layer may be uniformly dried through the two-step baking process.

[0137] Then, a second encapsulation layer ENL2 is formed on the color control layers CCF-R, CCF-G, and CCF-B. An inorganic material is deposited to form an encapsulation inorganic layer. An organic material may be deposited or coated to form an encapsulation organic layer.

[0138] Although not separately shown, at least one of the processes for forming the color filter CF-G, the first encapsulation layer ENL1, and the second encapsulation layer ENL2 may be omitted.

[0139] Fig. 6A and Figure 6B 2 is a diagram illustrating a method of manufacturing the upper display substrate 200 according to an embodiment of the inventive concept.

[0140] Fig. 6A Shows that in the implementation Figure 5B The process and Figure 5B The second display substrate 200 after the developing process after the developing process. The first layer WP1 of the partition wall WP is formed on the first encapsulation layer ENL1.

[0141] Then, if Figure 6BAs shown in FIG. 1 , a second preliminary partition wall layer WPL2 may be formed on the first encapsulation layer ENL1 and the first layer WP1. Even when coating is performed so that the second composition has an upper surface as shown in the dotted line, the second composition flows after it is coated to form an upper surface as shown in the solid line due to the fluidity of the second composition. Figure 5C A second preliminary partition wall layer WPL2 having a thickness as shown in FIG. 1 requires a larger amount of the second composition.

[0142] The second preliminary partition wall layer WPL2 is exposed using a second mask MSK2, and the fourth region W-A20 is removed by a developing process. In this process, a larger amount of the second composition is required to form a film having the same FIG. 5A to FIG. 5E The second layer WP2 has the same thickness as disclosed in .

[0143] Fig. 7A and Figure 7B 2 is a cross-sectional view of a pixel region of an upper display substrate 200 according to an embodiment of the inventive concept. Figures 1A to 6B The construction described is the same as the detailed description of the construction.

[0144] like Fig. 7A As shown in , the first light shielding layer BM1 and the second light shielding layer BM2 may have the same width. After sequentially forming the first initial light shielding layer and the second initial light shielding layer, the first initial light shielding layer and the second initial light shielding layer may be patterned using a single exposure and a single development process. Alternatively, the first initial light shielding layer and the second initial light shielding layer may also be sequentially exposed.

[0145] like Figure 7B As shown in FIG. 1 , one side surface of the first layer WP1 and one side surface of the second layer WP2 can be aligned along a substantially straight line. Figure 3C Compared with the first layer WP1 in the embodiment of the present invention, the first layer WP1 has an inclined portion toward one side of the second layer WP2.

[0146] As described above, according to the embodiment, the color control layer may have a thickness greater than a reference value, so the amount of light changed in the color control layer increases. Therefore, the brightness of the display panel may increase.

[0147] The light shielding layer including the blue color filter and the black matrix can reduce the amount of reflection of external light.

[0148] The partition wall may have a two-layer structure and thus have a thickness greater than a reference value. Compared to the first layer of the double-layer structure, a second layer having greater absorbance than the first layer is disposed adjacent to the lower display substrate to prevent color mixing between pixels.

[0149] Before developing the first initial partition wall layer, the second initial partition wall layer is formed, and then the second initial partition wall layer is exposed to light. The development process is simplified by developing the first initial partition wall layer and the second initial partition wall layer substantially at the same time. The consumption of the composition used to make the second initial partition wall layer can be reduced.

[0150] Although the present invention has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and technical field of the invention as defined in the appended claims and their equivalents.

[0151] Thus, the scope of the inventive concepts should not be restricted or limited by the foregoing description, but should be determined by the broadest permissible interpretation of the following claims.

Claims

1. A display panel, the display panel include: an upper display substrate, comprising a first pixel region, a second pixel region, and a third pixel region and a light shielding region in the periphery of the first pixel region, the second pixel region, and the third pixel region; as well as a lower display substrate, comprising a first display element, a second display element and a third display element corresponding to the first pixel region, the second pixel region and the third pixel region respectively; Wherein, the upper display substrate comprises: base substrate; a light shielding pattern disposed on the bottom surface of the base substrate, overlapping the light shielding region, and comprising a first opening portion, a second opening portion, and a third opening portion defined in the light shielding pattern corresponding to the first pixel region, the second pixel region, and the third pixel region, respectively; A first color filter, a second color filter, and a third color filter are disposed on the bottom surface of the base substrate and overlap the first pixel region, the second pixel region, and the third pixel region, respectively; a partition wall disposed on lower sides of the first color filter, the second color filter, and the third color filter, overlapping the light shielding region, and including a first partition wall opening portion, a second partition wall opening portion, and a third partition wall opening portion defined in the partition wall corresponding to the first pixel region, the second pixel region, and the third pixel region, respectively; and A first color control layer, a second color control layer and a third color control layer are respectively disposed in the first partition wall opening portion, the second partition wall opening portion and the third partition wall opening portion, wherein the partition wall comprises a first layer and a second layer, the second layer being arranged directly on the underside of the first layer and having an optical density greater than that of the first layer, In a cross-sectional view, a portion of the second layer protrudes downward from the first color control layer, the second color control layer, and the third color control layer, and A side surface of the first layer of the partition wall is exposed and contacts the first color control layer in an opening portion of the first partition wall.

2. The display panel according to claim 1, in, When the thickness of the second layer is 1 μm, the optical density of the second layer is from 0.15 to 0.

5.

3. The display panel according to claim 1, in, The second layer includes a hydrophobic region and a hydrophilic region disposed between the hydrophobic region and the first layer.

4. The display panel according to claim 3, in, The second layer has a thickness from 7 μm to 10 μm.

5. The display panel according to claim 4, in, The hydrophilic region includes a base resin and a black colorant mixed with the base resin, and the hydrophobic region includes a hydrophobic agent chemically bonded to the base resin.

6. The display panel according to claim 3, in, The hydrophobic region has a thickness from 30 nm to 200 nm.

7. The display panel according to claim 1, in, Each of the first color control layer, the second color control layer, and the third color control layer has a thickness of 15 μm or more.

8. The display panel according to claim 7, in, The height of the partition wall in the light shielding region is higher than the height of each of the first color control layer, the second color control layer, and the third color control layer.

9. The display panel according to claim 7, in, The first layer has a thickness from 5 μm to 15 μm, and The second layer has a thickness from 5 μm to 10 μm.

10. The display panel according to claim 1, in, The width of the first layer is from 10 μm to 15 μm.

11. The display panel according to claim 1, in, In a plan view, the second layer completely overlaps the first layer.

12. The display panel according to claim 1, in, The light-shielding pattern includes a blue first light-shielding layer and a black second light-shielding layer, and the second light-shielding layer at least covers a bottom surface of the first light-shielding layer.

13. The display panel according to claim 1, in, Each of the first display element, the second display element, and the third display element includes a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode, and The emission layers of the first display element, the second display element, and the third display element have an integral shape and generate blue light.

14. The display panel according to claim 13, in, The first color control layer includes first quantum dots configured to convert the blue light into red light, The second color control layer includes second quantum dots configured to convert the blue light into green light, and The third color control layer transmits the blue light.

15. A display panel, the display panel include: an upper display substrate, comprising a pixel region and a peripheral region adjacent to the pixel region; as well as a lower display substrate, comprising a display element arranged to correspond to the pixel area, Wherein, the upper display substrate comprises: base substrate; a light shielding pattern disposed on the bottom surface of the base substrate, overlapping the peripheral area, and including an opening portion defined in the light shielding pattern corresponding to the pixel area; a color filter disposed on the bottom surface of the base substrate and overlapping the pixel area; an encapsulation layer disposed on a lower side of the light shielding pattern and a lower side of the color filter; a partition wall disposed on a lower side of the encapsulation layer, overlapping the peripheral region, and including a partition wall opening portion defined in the partition wall corresponding to the pixel region; and a quantum dot layer disposed in the partition wall opening portion, The partition wall includes a first layer and a second layer, wherein the first layer is directly disposed on the bottom surface of the encapsulation layer, and the second layer is directly disposed on the lower side of the first layer and has an optical density greater than that of the first layer.

16. A method for manufacturing a display panel, the manufacturing method The following steps are involved: manufacturing a first display substrate including a display element; manufacturing a second display substrate, the second display substrate including a pixel region corresponding to the display element and a light shielding region in the periphery of the pixel region; as well as combining the first display substrate and the second display substrate, Wherein, the manufacturing steps of the second display substrate include: forming a light shielding pattern on the base substrate to overlap the light shielding area; forming a color filter overlapping the pixel region; forming a first initial partition wall layer on the base substrate; exposing the first preliminary partition wall layer so that a first region of the first preliminary partition wall layer overlapping the light shielding pattern is separated from a second region disposed in a periphery of the first region; forming a second initial partition wall layer on the exposed first initial partition wall layer; exposing the second initial partition wall layer so that a third region of the second initial partition wall layer corresponding to the first region is separated from a fourth region corresponding to the second region; developing the first preliminary partition wall layer and the second preliminary partition wall layer so that a partition wall and a partition wall opening portion surrounded by the partition wall are formed; and A quantum dot layer is formed in the partition wall opening portion.

17. The manufacturing method according to claim 16, in, The step of forming the second initial partition wall layer comprises: forming a composition layer including a base resin, a black colorant, and a hydrophobic agent on the first preliminary partition wall layer; drying the composition layer; and The composition layer is primarily baked to provide heat to the composition layer.

18. The manufacturing method according to claim 17, in, The composition layer after primary baking includes a hydrophilic region including the base resin and the black colorant and a hydrophobic region including the hydrophobic agent chemically bonded to the base resin.

19. The manufacturing method according to claim 17, further comprising: The following steps are involved: After the developing, the partition walls are secondarily baked to provide heat to the partition walls. Wherein, the temperature in the secondary baking is higher than the temperature in the primary baking.

20. The manufacturing method according to claim 16, in, The step of forming the first initial partition wall layer comprises: forming a composition layer including a base resin on the base substrate; drying the composition layer; and The composition layer is baked to provide heat to the composition layer.

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