Semiconductor devices

Abstract

[Problem] To reduce the inter-wiring capacitance of a semiconductor device while maintaining mechanical strength and reliability. [Solution] A semiconductor device comprising: a multilayer wiring layer, in which a plurality of interlayer films and a plurality of diffusion prevention films are alternately stacked, and wiring is formed inside the interlayer film; a contact via formed to penetrate a via insulating layer and electrically connected to the wiring of the multilayer wiring layer, the via insulating layer being formed on one surface of the multilayer wiring layer; a through hole formed to penetrate at least one of the interlayer film and the diffusion prevention film from another surface of the multilayer wiring layer on the opposite side of the one surface of the multilayer wiring layer; and a void connected to the through hole and formed in at least one of the interlayer films to expose the contact via.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Recently, as the size of semiconductor devices has become smaller and smaller, wiring delays that reduce the operating speed of semiconductor devices have been increasing. Specifically, in semiconductor devices, wiring resistance increases due to a decrease in the cross-sectional area of ​​wiring, and therefore, a delay proportional to the product of capacitance between wirings and wiring resistance increases (this delay is also called RC delay).

[0003] In order to reduce this wiring delay, research has been conducted to reduce the dielectric constant of the interlayer film between the wirings. However, an interlayer film material that can achieve a sufficiently low dielectric constant has not yet been found.

[0004] In view of this, a method of further reducing the dielectric constant between wirings by removing material between wirings and forming a hollow layer (also referred to as a void) having a relative dielectric constant of 1 between wirings has been considered.

[0005] For example, Patent Document 1 mentioned below discloses provision of a structure that does not damage wirings when an insulating film between wirings is removed to form a void structure.

[0006] Reference List

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2006-19401 Summary of the invention

[0009] Problems to be solved by the present invention

[0010] However, with the technology disclosed in Patent Document 1, a thin film with low mechanical strength protrudes into the space where the void is formed, and therefore, there is a possibility that the thin film protruding into the void will collapse. In addition, with the technology disclosed in Patent Document 1, in the case where the distance between wirings is long, the mechanical strength of the entire semiconductor device is reduced due to the void, and therefore, there is a possibility that the reliability of the semiconductor device will decrease.

[0011] In view of the above circumstances, the present invention proposes an improved new semiconductor device capable of reducing the capacitance between wirings while maintaining mechanical strength and reliability.

[0012] Technical solutions to the problem

[0013] The present invention provides a semiconductor device, comprising: a multilayer wiring layer, in which a plurality of interlayer films and a plurality of diffusion prevention films are alternately stacked, and wiring is formed inside the interlayer film; a contact via, which is formed to penetrate a via insulating layer and is electrically connected to the wiring of the multilayer wiring layer, and the via insulating layer is formed on one surface of the multilayer wiring layer; a through hole, which is formed to penetrate at least one of the interlayer film and the diffusion prevention film from another surface of the multilayer wiring layer on the opposite side of the one surface; and a gap, which is connected to the through hole and is formed in at least one of the interlayer films to expose the contact via.

[0014] According to the present invention, the interlayer film is removed in predetermined regions in the stacking direction and the in-plane direction, so that a void can be formed in a region around a contact via for connecting a semiconductor substrate to a wiring.

[0015] Effects of the Invention

[0016] As described above, according to the present invention, the capacitance between wirings can be reduced while maintaining the mechanical strength and reliability of the semiconductor device.

[0017] It should be noted that the above-mentioned effects are not necessarily limitative, and together with or instead of the above-mentioned effects, any one of the effects described in this specification may be achieved, or other effects that are obvious from this specification may be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, taken along the stacking direction.

[0019] Figure 2A are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0020] Figure 2B are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0021] Figure 2C are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0022] Figure 2D are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0023] Figure 2E are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0024] Figure 2Fare cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0025] Figure 2G are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0026] Figure 3 is a cross-sectional view of a semiconductor device according to a first modification of the embodiment, taken along the stacking direction.

[0027] Figure 4 is a cross-sectional view of a semiconductor device according to a second modification of the embodiment, taken along the stacking direction.

[0028] Figure 5A is a cross-sectional view of a semiconductor device according to a third modification of the embodiment, taken along the stacking direction.

[0029] Figure 5B is a cross-sectional view of a semiconductor device according to a third modification of the embodiment, taken along the stacking direction.

[0030] Figure 5C is a cross-sectional view of a semiconductor device according to a third modification of the embodiment, taken along the stacking direction.

[0031] Figure 6 is a cross-sectional view of a semiconductor device according to a fourth modification of the embodiment, taken along the stacking direction.

[0032] Figure 7 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, taken along the stacking direction.

[0033] Fig. 8A are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0034] Figure 8B are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0035] Figure 8C are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0036] Fig.8D are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0037] Fig. 8E are cross-sectional views illustrating steps in a method of manufacturing a semiconductor device according to an embodiment.

[0038] Fig. 9 is a cross-sectional view of a semiconductor device according to a modification of the embodiment, taken along the stacking direction.

[0039] Fig.10 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention, taken along the stacking direction.

[0040] Fig.11 is a schematic diagram showing a stacked structure of respective wirings of the semiconductor device according to the embodiment.

[0041] Fig.12 is a schematic diagram showing a stacked structure of respective wirings of the semiconductor device according to the embodiment.

[0042] Fig.13A It shows that along Fig.11 A cross-sectional view of a section taken along line A-AA shown in FIG.

[0043] Fig. 13B It shows that along Fig.11 A cross-sectional view of a section taken along line B-BB shown in FIG.

[0044] Fig. 13C It shows that along Fig.12 A cross-sectional view of a section taken along line C-CC shown in FIG.

[0045] Fig.14 is a diagram schematically showing an example configuration of an endoscopic surgery system.

[0046] Fig.15 is a block diagram showing an example of the functional configuration of a camera and a CCU.

[0047] Fig.16 is a block diagram schematically showing an example configuration of an in-vivo information acquisition system.

[0048] Fig.17 is a block diagram schematically showing an example configuration of a vehicle control system.

[0049] Fig.18 : is an explanatory diagram showing an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0050] The following is a detailed description of preferred embodiments of the present invention with reference to the accompanying drawings. Note that in this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and description thereof will not be repeated.

[0051] In the various drawings used as references in the following description, for ease of explanation, the sizes of some components are shown as larger than their actual sizes in some cases. Therefore, the relative sizes of the components shown in the various drawings do not always accurately represent the dimensional relationships between the actual components. In addition, in the following description, the stacking direction of the substrate or layer is sometimes referred to as the upward direction.

[0052] Note that the description will be given in the following order.

[0053] 1. First Embodiment

[0054] 1.1. Example Construction

[0055] 1.2. Manufacturing method

[0056] 1.3. Modifications

[0057] 2. Second Embodiment

[0058] 2.1. Example Construction

[0059] 2.2. Manufacturing method

[0060] 2.3. Modifications

[0061] 3. Third embodiment

[0062] 4. Sample Application

[0063] 4.1. First application

[0064] 4.2. Second Application

[0065] 4.3. Third Application

[0066] <1. First Embodiment>

[0067] (1.1. Example construction)

[0068] First, refer to Figure 1 , describing the configuration of a semiconductor device according to a first embodiment of the present invention. Figure 1 is a cross-sectional view of the semiconductor device according to this embodiment taken along the stacking direction. It should be noted that Figure 1 A part of the cross section of the semiconductor device 1 according to the present embodiment is shown, and the semiconductor device 1 of course extends to a region not shown in the figure.

[0069] like Figure 1 As shown, the semiconductor device 1 includes a via insulating layer 600 and a multilayer wiring layer 101 in which first to third interlayer films 110, 120, and 130 and first to fourth diffusion prevention films 210, 220, 230, and 240 are alternately stacked.

[0070] The contact via 610 and the zero wiring 620 are formed in the via insulating layer 600, and the first to third wirings 310, 320 and 330 are respectively formed in the first to third interlayer films 110, 120 and 130. The first to third wirings 310, 320 and 330 are electrically connected to each other through the second and third through vias 420 and 430.

[0071] Hereinafter, the first to third interlayer films 110, 120, and 130 are also collectively referred to as the interlayer film 100, and the first to fourth diffusion prevention films 210, 220, 230, and 240 are also collectively referred to as the diffusion prevention film 200. In addition, the first to third wirings 310, 320, and 330 are also collectively referred to as the wirings 300, and the second and third through vias 420 and 430 are also collectively referred to as the through vias 400.

[0072] That is, the semiconductor device 1 includes a multilayer wiring layer 101 in which interlayer films 100 including wirings 300 and through vias 400 and diffusion prevention films 200 are alternately stacked.

[0073] Note that Figure 1 In the embodiment, the multilayer wiring layer 101 has a structure in which the first to third interlayer films 110, 120 and 130 and the first to fourth diffusion prevention films 210, 220, 230 and 240 are alternately stacked. However, the technology according to the present invention is not limited to this example. The multilayer wiring layer 101 may include, for example, 4 or at least 5 interlayer films 100. In addition, the multilayer wiring layer 101 may be formed by the same number of interlayer films 100 and diffusion prevention films 200.

[0074] The interlayer film 100 electrically insulates the wirings 300 from each other, and is a main layer member forming the semiconductor device 1. The interlayer film 100 is formed of an insulating material that can be easily etched (specifically, can be more easily etched than the diffusion prevention film 200 described later), and can be formed of, for example, an insulating material such as SiO2. Alternatively, the interlayer film 100 can be formed of an organic resin or a low-k material such as carbon-doped SiO2 or porous silicon.

[0075] The diffusion prevention film 200 is arranged to sandwich the respective interlayer films 100, reduce the surface diffusion of the metal forming the wiring 300, and acts as a barrier layer when processing the layers thereon. Specifically, the diffusion prevention film 200 is formed of an insulating material having higher corrosion resistance (for example, corrosion resistance to fluorine compounds) than the interlayer film 100, and can be made of, for example, SiN x , SiCN, SiON or SiC and other insulating materials.

[0076] It is to be noted that the materials forming the interlayer film 100 and the diffusion prevention film 200 only need to be selected so as to increase the etching selectivity of the interlayer film 100 relative to the diffusion prevention film 200, and various combinations are possible. Therefore, the materials forming the interlayer film 100 and the diffusion prevention film 200 are not limited to the above materials, and a combination of other materials may be used.

[0077] The wiring 300 transmits current or voltage between active elements or passive elements provided in the semiconductor device 1. The wiring 300 is formed of a conductive material and may be formed of a first metal or an alloy of the first metal, etc. For example, the first metal is a metal that is easy to handle with low resistance, such as copper (Cu), aluminum (Al), cobalt (Co), or an alloy of these metals (e.g., CoWB), etc. In the case where the wiring 300 is formed of Cu, the wiring 300 can be easily formed by using a damascene technique, etc. In addition, in the case where the wiring 300 is formed of Al, the wiring 300 can be easily formed by dry etching using a halogen gas.

[0078] The through via 400 electrically connects the wirings 300 formed in different interlayer films 100 to each other. Specifically, the second through via 420 electrically connects the first wiring 310 and the second wiring 320, and the third through via 430 electrically connects the second wiring 320 and the third wiring 330. Similar to the wiring 300, the through via 400 is formed of a conductive material and can be formed of a first metal or an alloy of the first metal. For example, the through via 400 can be formed of copper (Cu), aluminum (Al), cobalt (Co), or alloys of these metals (e.g., CoWB), etc.

[0079] The via insulating layer 600 is formed of an insulating material on one surface of the multilayer wiring layer 101, and the via insulating layer 600 electrically insulates each contact via 610. Similar to the interlayer film 100, the via insulating layer 600 can be formed of an insulating material that can be etched relatively easily (specifically, easier to etch than the diffusion prevention film 200). For example, the via insulating layer 600 can be formed of an insulating material such as SiO2, or can be formed of an organic resin or a low-k material such as carbon-doped SiO2 or porous silicon.

[0080] The contact via 610 penetrates the via insulating layer 600 and the first diffusion prevention film 210, and is formed to protrude into the first interlayer film 110, and electrically connects the semiconductor substrate (not shown) and the first wiring 310. Specifically, the contact via 610 electrically connects the first wiring 310 to a semiconductor substrate (not shown) or an electrode formed on a semiconductor substrate, etc., which is formed on the other surface of the via insulating layer 600 opposite to the surface on which the multilayer wiring layer 101 is formed. For example, the contact via 610 can be formed of a conductive material, and can be formed of a second metal or an alloy of a second metal different from the first metal forming the wiring 300, etc. The second metal is a metal having characteristics such as less diffusion of metal atoms into the semiconductor substrate, higher burying characteristics when forming the contact via 610, and higher heat resistance. For example, the metal can be tungsten (W) or the like.

[0081] Note that the contact via 610 may be formed in the via insulating layer 600 and the first interlayer film 110 in a floating state to ensure mechanical strength of the semiconductor device 1. In this case, the contact via 610 functions as a columnar member as a support between layers of the semiconductor device 1.

[0082] The zero wiring 620 is formed inside the first interlayer film 110 and on the first diffusion prevention film 210, and electrically connects the active element or the passive element provided in the semiconductor device 1 to the contact via 610. Similar to the contact via 610, the zero wiring 620 is formed of a conductive material and can be formed of a second metal or an alloy of the second metal. For example, the zero wiring 620 can be formed of tungsten (W) or a tungsten alloy, etc.

[0083] Since the contact via 610 and the zeroth wiring 620 are arranged at a position closer to the semiconductor substrate than the wiring 300, the contact via 610 and the zeroth wiring 620 can be formed by a second metal having a smaller impact on the semiconductor substrate than the first metal. In the case where the contact via 610 and the zeroth wiring 620 are formed by the second metal, a barrier metal layer formed by a metal having a high barrier property to atoms can be formed on the surface of the contact via 610 and the zeroth wiring 620. For example, the barrier metal layer can be formed by a metal such as tantalum (Ta), titanium (Ti), ruthenium (Ru), cobalt (Co) or manganese (Mn), or a nitride or oxide of these metals.

[0084] However, the barrier metal layer may be damaged when etching is performed to form the void 530 described later. Therefore, in the case where a barrier metal layer is formed on the surface of the contact via 610 and the zero wiring 620, a protective film formed of a material similar to the diffusion prevention film 200 may be provided to further cover the barrier metal layer.

[0085] The semiconductor device 1 according to the present embodiment further includes a through hole 510, a protective sidewall 520 and a void 530. The void 530 is formed in the first interlayer film 110 and the second interlayer film 120 so as to expose the contact via 610. The through hole 510 is formed to penetrate the fourth diffusion prevention film 240, the third interlayer film 130 and the third diffusion prevention film 230, and connects the void 530 to the external space. The protective sidewall 520 is formed on the side surface inside the through hole 510.

[0086] Note that although Figure 1 Although not shown in the figure, a sealing layer for covering the opening formed by the through hole 510 may be arranged on the fourth diffusion prevention film 240. For example, the sealing layer is made of a material such as SiO x 、SiN x , SiCN, SiON, SiC or other inorganic insulating materials or organic resins, and can prevent moisture and the like from entering the through hole 510 and the gap 530.

[0087] The through hole 510 is formed to penetrate the interlayer film 100 arranged on the other surface of the multilayer wiring layer 101 opposite to the surface provided with the via insulating layer 600 and the diffusion prevention film 200 sandwiching the interlayer film 100. Specifically, the through hole 510 is formed to penetrate the third interlayer film 130 and the third and fourth diffusion prevention films 230 and 240 sandwiching the third interlayer film 130. The opening of the through hole 510 can be formed in any appropriate planar shape. For example, the opening of the through hole 510 can be formed in a substantially square shape with a side of at least 50nm to 300nm, or a substantially circular shape with a diameter of at least 50nm to 300nm.

[0088] The protective sidewall 520 is formed on the side surface inside the through hole 510, and protects the side surface of the third interlayer film 130 exposed through the through hole 510. For example, the protective sidewall 520 is formed of an insulating material having higher corrosion resistance (for example, corrosion resistance to fluorine compounds) than the interlayer film 100, and the protective sidewall 520 can be made of, for example, SiN x , SiCN, SiON, SiOC or SiC. Alternatively, the protective sidewall 520 may be formed of a high-k material such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2) or lanthanum oxide (La2O3), or may be formed of a metal material. It should be noted that in the case where the protective sidewall 520 is formed of a metal material, the protective sidewall 520 is formed to be in a floating state.

[0089] The protective sidewall 520 plays a role in protecting the third interlayer film 130 from being etched when the void 530 is formed. Specifically, the void 530 is formed by introducing an etching solution or etching vapor through the through hole 510 and etching (wet etching or vapor etching) on ​​the first interlayer film 110 and the second interlayer film 120. At this time, the protective sidewall 520 protects the third interlayer film 130 from being etched using the etching solution or etching vapor. Due to the through hole 510 having an inner side surface covered by the protective sidewall 520 as described above, the semiconductor device 1 can form a void 530 in the interlayer film 100 inside the multilayer wiring layer 101. It should be noted that the protective sidewall 520 can be a thin film with a thickness of 5nm to 30nm, for example.

[0090] The void 530 is formed in at least one interlayer film 100 of the multilayer wiring layer 101 so as to expose the contact via 610, and the space between each contact via 610 or each wiring 300 is a hollow space with a relative dielectric constant of 1. Specifically, the void 530 is formed in the first interlayer film 110 and the second interlayer film 120, and each space between a portion of the contact via 610, the first wiring 310 and the second wiring 320 is a hollow space. With this arrangement, the void 530 can reduce the parasitic capacitance formed between each contact via 610 or each wiring 300.

[0091] In the semiconductor device 1 according to the present embodiment, the void 530 is formed in the first interlayer film 110 to expose at least the contact via 610. With this configuration, the semiconductor device 1 can reduce the capacitance between wirings in a region close to the semiconductor substrate where transistors etc. are formed. Therefore, basic performances such as signal conversion efficiency and switching characteristics of the semiconductor device 1 can be improved.

[0092] Note that the void 530 may be formed, for example, by introducing an etching solution or etching vapor through the through hole 510 and etching on the first interlayer film 110 and the second interlayer film 120 using wet etching or vapor etching.

[0093] At this stage, the region in which the void 530 is formed in the stacking direction of the multilayer wiring layer 101 is limited to the region surrounded by the diffusion prevention film 200. This is because the diffusion prevention film 200 has a higher corrosion resistance than the interlayer film 100 and is difficult to etch. In addition, the region in which the void 530 is formed in the in-plane direction of the multilayer wiring layer 101 is controlled by the etching amount. Specifically, the etching solution or etching vapor introduced from the through hole 510 diffuses isotropically from just below the through hole 510, thereby etching the interlayer film 100. Therefore, the region in the in-plane direction of the void 530 can be controlled by the etching amount.

[0094] It is to be noted that the etching of the interlayer film 100 is performed without etching the contact via 610, the through via 400, and the wiring 300. Therefore, in the case where the contact via 610, the through via 400, or the wiring 300 exists in the region where the void 530 is formed, these components remain in the void 530 without any change. In addition, in the case where the interlayer film 100 is spatially separated by the contact via 610, the through via 400, or the wiring 300, these components prevent the etching solution or the etching vapor from entering, and the region where the void 530 is formed is limited.

[0095] Here, in the case where the gaps 530 are formed in the plurality of interlayer films 100, openings are formed in the diffusion prevention film 200 between the plurality of interlayer films 100. Specifically, in the case where the gaps 530 are formed in the first interlayer film 110 and the second interlayer film 120, openings are formed in the second diffusion prevention film 220 between the first interlayer film 110 and the second interlayer film 120. Therefore, when an etching solution or etching vapor is introduced from the through hole 510, the etching solution or etching vapor diffuses from the second interlayer film 120 to the first interlayer film 110 via the openings. Therefore, the gaps 530 are formed to span across the plurality of interlayer films 100.

[0096] At this stage, the opening in the diffusion prevention film 200 is formed to protrude into the void 530 and is formed not to leave a region without a hole on the wiring 300. Therefore, after the void 530 is formed, the diffusion prevention film 200 protruding into the void 530 can be prevented from collapsing.

[0097] although Figure 1 The case where only one through hole 510 is formed is shown, but the technology according to the present invention is not limited to the above example. For example, a plurality of through holes 510 may be formed. In this case, the plurality of through holes 510 may form the same void 530, or the respective through holes 510 may form voids 530 different from each other.

[0098] In the semiconductor device 1 described above, each space between the wirings 300 can be made hollow by the gaps 530, so that the capacitance between the wirings can be reduced. Therefore, the semiconductor device 1 can achieve higher speed operation and lower power consumption by reducing the delay in the wirings 300. In addition, in the semiconductor device 1, the diffusion prevention film 200 does not protrude into the gaps 530. Therefore, the diffusion prevention film 200 having low mechanical strength can be prevented from collapsing.

[0099] (1.2. Manufacturing method)

[0100] Now, refer to Figures 2A to 2G A method of manufacturing the semiconductor device 1 according to the present embodiment is described. Figures 2A to 2Gare cross-sectional views respectively illustrating steps in the method for manufacturing the semiconductor device 1 according to the present embodiment.

[0101] First, if Figure 2A As shown, a via insulating layer 600, a first diffusion prevention film 210, a first interlayer film 110, and a second diffusion prevention film 220 are sequentially stacked on a semiconductor substrate (not shown) by chemical vapor deposition (CVD). In addition, a contact via 610 is formed in the via insulating layer 600, and a zero wiring 620 and a first wiring 310 are formed in the first interlayer film 110.

[0102] Specifically, first, a via insulating layer 600 is formed on a semiconductor substrate (not shown) including silicon (Si) or the like by CVD. Next, after forming a first diffusion prevention film 210 on the via insulating layer 600 by CVD, the via insulating layer 600 and the first diffusion prevention film 210 in a predetermined region are removed by etching. After forming a barrier metal layer such as a titanium nitride (TiN) layer or the like in an opening formed by etching by a sputtering technique, tungsten (W) is buried in the opening to form a contact via 610 and a zero wiring 620.

[0103] After the first interlayer film 110 is formed on the first diffusion prevention film 210 by CVD, the first interlayer film 110 in a predetermined region is removed by etching, and the resulting opening is filled with copper (Cu) or the like by a damascene technique, thereby forming the first wiring 310. Thereafter, the second diffusion prevention film 220 is formed on the entire surface of the first interlayer film 110 and the first wiring 310 by CVD.

[0104] It should be noted that the via insulating layer 600 and the first interlayer film 110 may be made of SiO2 which is easily etched by hydrofluoric acid. x etc., and the first diffusion prevention film 210 and the second diffusion prevention film 220 may be formed of SiC etc. having high corrosion resistance to hydrofluoric acid.

[0105] Next, if Figure 2B As shown, a portion of the second diffusion prevention film 220 is removed by photolithography or the like, thereby forming an opening 530A. The opening 530A serves as an opening for introducing an etching solution from the second interlayer film 120 to the first interlayer film 110 in a process of forming the space 530 at a later stage.

[0106] like Figure 2CAs shown, the second interlayer film 120, the third diffusion prevention film 230, the third interlayer film 130, and the fourth diffusion prevention film 240 are sequentially stacked on the second diffusion prevention film 220 by CVD. In addition, the second wiring 320 and the second through via 420 are formed in the second interlayer film 120, and the third wiring 330 and the third through via 430 are formed in the third interlayer film 130.

[0107] Specifically, after the second interlayer film 120 is formed on the second diffusion prevention film 220 by CVD, the second interlayer film 120 in a predetermined region is removed by etching, and the resulting opening is filled with copper (Cu) or the like by a damascene technique, thereby forming the second wiring 320 and the second through-via 420. Similarly, the third diffusion prevention film 230 and the third interlayer film 130 are then formed on the second wiring 320 and the second interlayer film 120 by CVD. Then, the third interlayer film 130 in a predetermined region is removed by etching, and the resulting opening is filled with copper (Cu) or the like by a damascene technique, thereby forming the third wiring 330 and the third through-via 430. Thereafter, the fourth diffusion prevention film 240 is formed on the third wiring 330 and the third interlayer film 130 by CVD.

[0108] It should be noted that the second interlayer film 120 and the third interlayer film 130 may be made of SiO2 which is easily etched by hydrofluoric acid. x etc., and the third diffusion prevention film 230 and the fourth diffusion prevention film 240 may be formed of SiC etc. having high corrosion resistance to hydrofluoric acid.

[0109] Next, if Figure 2D As shown, the fourth diffusion prevention film 240 and the third interlayer film 130 in a partial region are removed by etching or the like, thereby forming a through hole 510 for exposing the third diffusion prevention film 230. It should be noted that the region where the through hole 510 is formed is, for example, a region where the second wiring 320 and the third wiring 330 are not formed. The planar shape of the opening of the through hole 510 can be, for example, a square having a side of 50 nm to 300 nm. It should be noted that a plurality of through holes 510 can be formed, of course.

[0110] like Figure 2EAs shown, a protective film 520A is then formed on the fourth diffusion prevention film 240 and on the side surface inside the through hole 510 by atomic layer deposition (ALD). For example, the protective film 520A may be formed of SiC or the like, which has high corrosion resistance to hydrofluoric acid and can ensure sufficient etching selectivity for the interlayer film 100, and the protective film 520A may have a thickness of 5 nm to 30 nm. It should be noted that the protective film 520A is uniformly (conformally) formed on the fourth diffusion prevention film 240 and on the side surface inside the through hole 510 because it is formed by ALD.

[0111] Next, if Figure 2F As shown, etching back is performed on the entire surface of the protection film 520A, thereby removing the protection film 520A formed on the fourth diffusion prevention film 240 and the third diffusion prevention film 230 and exposing the fourth diffusion prevention film 240 and the second interlayer film 120 .

[0112] The etch-back on the entire surface is etched with high perpendicular anisotropy to remove the protective film 520A formed on the fourth diffusion prevention film 240 and the third diffusion prevention film 230 while leaving the protective film 520A formed inside the through hole 510. As a result, the protective sidewall 520 is formed to cover the inner side surface of the through hole 510. Since the fourth diffusion prevention film 240 is formed on the third interlayer film 130, the protective sidewall 520 can be formed without causing any damage to the third interlayer film 130 due to the etch-back on the entire surface.

[0113] like Figure 2G As shown, etching is then performed by introducing a solution or vapor of dilute hydrofluoric acid into the second interlayer film 120 and the first interlayer film 110 through the through hole 510. Thus, a gap 530 is formed.

[0114] Since the protective sidewall 520 and the first to fourth diffusion prevention films 210, 220, 230 and 240 are formed by SiC or the like having high corrosion resistance to hydrofluoric acid, it is difficult to etch at this stage. In addition, the contact via 610, the zero wiring 620, the first and second wirings 310 and 320, and the second through-hole 420 are formed by metal materials such as copper (Cu) or tungsten (W), and have high corrosion resistance to hydrofluoric acid. Therefore, it is difficult to etch. Therefore, only the first interlayer film 110 and the second interlayer film 120 can be removed by etching, and a gap 530 can be formed.

[0115] Therefore, the region where the void 530 is formed in the stacking direction of the semiconductor device 1 is limited to the region sandwiched between the first diffusion prevention film 210 and the third diffusion prevention film 230. In addition, the region where the void 530 is formed in the in-plane direction of the semiconductor device 1 is controlled by the etching amount. However, in the case where the contact via 610, the zero wiring 620, the first and second wirings 310 and 320, and the second through via 420 are formed as a wall surrounding a predetermined region, the region where the void 530 is formed can be limited to a predetermined region surrounded by these components. In this way, the semiconductor device 1 can form the void 530 only in the region where the capacitance between the wirings can be reduced.

[0116] Note that the second diffusion prevention film 220 is formed in a region whose end is located in a region where the first wiring 310 is formed and the second diffusion prevention film 220 does not protrude into the void 530. Therefore, in the semiconductor device 1, the second diffusion prevention film 220 can be prevented from collapsing after the void 530 is formed.

[0117] Through the above steps, the semiconductor device 1 according to the present embodiment can be manufactured. Note that in order to prevent moisture or the like from entering the gap 530 , a sealing layer made of an insulating material may be formed on the fourth diffusion prevention film 240 to close the opening of the through hole 510 .

[0118] According to the above manufacturing method, hydrofluoric acid is used for etching, and SiO2, which is a material that is easily etched by hydrofluoric acid, is used. x The interlayer film 100 is formed, and the diffusion prevention film 200 is formed of SiC having higher corrosion resistance to hydrofluoric acid. However, the technology according to the present invention is not limited to the above example. The combination of materials for the interlayer film 100 and the diffusion prevention film 200 can be any combination of appropriate materials as long as sufficient etching selectivity can be ensured for the interlayer film 100 relative to the diffusion prevention film 200.

[0119] (1.3. Modification)

[0120] Next, we will refer to Figures 3 to 6 A modification example of the semiconductor device 1 according to the present embodiment is described. Figure 3 is a cross-sectional view of a semiconductor device 11 according to a first modification example, taken along the stacking direction. Figure 4 is a cross-sectional view of a semiconductor device 12 according to a second modification example, taken along the stacking direction. FIG. 5A to FIG. 5C 2A and 2B are cross-sectional views of semiconductor devices 13A to 13C according to the third modification example, taken along the stacking direction. Figure 6 is a cross-sectional view of the semiconductor device 14 according to the fourth modification example taken along the stacking direction. Note that, Figures 3 to 6A portion of a cross section of a semiconductor device is respectively shown, and the semiconductor device of course extends to a region not shown in the figure.

[0121] (First Modification)

[0122] like Figure 3 As shown, in the semiconductor device 11 according to the first modification, a protective film 540 may be formed on the surface exposed by the gap 530. Specifically, the protective film 540 may be formed on each surface of the contact via 610, the zero wiring 620, the interlayer film 100, the diffusion prevention film 200, the wiring 300, and the through via 400 exposed by the gap 530. It should be noted that other components are the same as those in the reference Figure 1 The components described are the same and therefore, they will not be described here.

[0123] The protective film 540 is formed of, for example, any appropriate insulating material, and may be, for example, made of SiO x 、SiN x , SiCN, SiON, SiOC or SiC. The thickness of the protective film 540 can be, for example, 2 nm to 50 nm. The protective film 540 can improve the wiring reliability by preventing electromigration and time-dependent dielectric breakdown (TDDB) in the wiring 300 and the through-hole 400. For example, such a protective film 540 can be formed by introducing a source gas into the gap 530 through the through-hole 510 and performing ALD.

[0124] (Second Modification)

[0125] Next, if Figure 4 As shown, in the semiconductor device 12 according to the second modification, the interlayer film 100 can be formed of a plurality of different materials. Specifically, the via insulating layer 600, the first interlayer film 110 and the second interlayer film 120 can be formed of a first material, and the third interlayer film 131 can be formed of a second material different from the first material. For example, the via insulating layer 600, the first interlayer film 110 and the second interlayer film 120 can be made of a material such as SiO x The third interlayer film 131 may be made of SiO x It should be noted that the other components are similar to those of the reference Figure 1 The components described are the same and therefore, they will not be described here.

[0126] The gap 530 is formed in the interlayer film 100 formed of the first material having a higher relative dielectric constant than the second material, thereby effectively reducing the parasitic capacitance formed between the wirings 300. However, it goes without saying that the gap 530 may be formed in the interlayer film 100 formed of the second material having a lower relative dielectric constant than the first material.

[0127] Furthermore, when the combination of the first material and the second material is selected so that the etching selectivity of the first material with respect to the second material (the so-called low-k material described above) becomes high, the void 530 can be formed even without forming the protective sidewall 520. Specifically, since the third interlayer film 131 formed of the second material is not etched during the etching for forming the void 530, the void 530 can be formed without forming the protective sidewall 520.

[0128] (Third Modification)

[0129] Next, if FIG. 5A to FIG. 5C As shown, in the semiconductor devices 13A to 13C according to the third modification, at least four interlayer films 100 and at least four diffusion prevention films 200 may be stacked, and the void 530 may be formed in one to three interlayer films 100 .

[0130] Here, the fourth interlayer film 140 may be formed of a material similar to the first to third interlayer films 110, 120, and 130. The fifth diffusion prevention film 250 may be formed of a material similar to the first to fourth diffusion prevention films 210, 220, 230, and 240. The fourth wiring 340 may be formed of a material similar to the first to third wirings 310, 320, and 330. The fourth through via 440 may be formed of a material similar to the second and third through vias 420 and 430. In addition, the other components are the same as those of the reference Figure 1 The components described are the same and therefore, they will not be described here.

[0131] like Figure 5A As shown, the void 530 may be formed in a single interlayer film 100. Specifically, the void 530 may be formed in the first interlayer film 110. In this case, the through hole 510 is formed to penetrate the second to fifth diffusion prevention films 220, 230, 240 and 250 and the second to fourth interlayer films 120, 130 and 140.

[0132] Alternatively, if Figure 5B As shown, the void 530 may be formed in the two interlayer films 100. Specifically, the void 530 may be formed in the first interlayer film 110 and the second interlayer film 120. In this case, the through hole 510 is formed to penetrate the third to fifth diffusion prevention films 230, 240 and 250 and the third and fourth interlayer films 130 and 140.

[0133] In addition, if Figure 5C As shown, the void 530 may be formed in three interlayer films. Specifically, the void 530 may be formed in the first interlayer film 110, the second interlayer film 120, and the third interlayer film 130. In this case, the through hole 510 is formed to penetrate the fourth and fifth diffusion prevention films 240 and 250 and the fourth interlayer film 140.

[0134] However, in any case of the semiconductor devices 13A to 13C according to the present modification, the void 530 is formed at least in the first interlayer film 110 to expose the contact via 610 and the zeroth wiring 620. With this configuration, the semiconductor devices 13A to 13C can reduce the capacitance between the wirings in the region close to the semiconductor substrate where the transistors etc. are formed. Therefore, the basic performance of the semiconductor devices 13A to 13C such as the signal conversion efficiency and the switching characteristics can be improved.

[0135] It should be noted that in the semiconductor device 1 according to the present embodiment, the number of stacked layers as the interlayer film 100 and the diffusion prevention film 200 is not limited to any specific number. That is, the multilayer wiring layer 101 can be formed by stacking at least six interlayer films 100 and at least six diffusion prevention films 200. The greater the number of interlayer films 100 formed with the gaps 530, the more the capacitance between the wirings in the entire semiconductor device 1 can be reduced. However, the fewer the number of interlayer films 100 formed with the gaps 530, the greater the mechanical strength can be maintained in the entire semiconductor device 1. Therefore, considering the balance between the capacitance between the wirings and the mechanical strength, the number of interlayer films 100 formed with the gaps 530 can be appropriately adjusted.

[0136] (Fourth Modification)

[0137] In addition, if Figure 6 As shown, in the semiconductor device 14 according to the fourth modification, a diffusion prevention film 211 may be further formed in the first interlayer film 110. Specifically, the diffusion prevention film 211 may be further formed between the first wiring 310 and the contact via 610 in the first interlayer film 110.

[0138] It should be noted that the diffusion prevention film 211 may be formed of a material similar to that of the first to fourth diffusion prevention films 210, 220, 230, and 240. Figure 1 The components described are the same and therefore, they will not be described here.

[0139] In this configuration, the region where the void 530 is formed can be controlled in a finer manner by the diffusion prevention film 211. For example, the plane region where the void 530 is formed between the first wiring 310 and the contact via 610 can be changed.

[0140] <2. Second Embodiment>

[0141] (2.1. Example construction)

[0142] Now, refer to Figure 7 The configuration of a semiconductor device 2 according to a second embodiment of the present invention is described. Figure 7 is a cross-sectional view of the semiconductor device according to this embodiment taken along the stacking direction. It should be noted that Figure 7 A part of the cross section of the semiconductor device 2 according to the present embodiment is shown, and the semiconductor device 2 of course extends to a region not shown in the figure.

[0143] like Figure 7 As shown, in the semiconductor device 2 , a multilayer wiring layer 101 in which interlayer films 100 and diffusion prevention films 200 are alternately stacked is interposed between a pair of substrates 710 and 720 , and a through hole 510 is formed to penetrate the substrate 710 and the via insulating layer 600 .

[0144] Here, the fourth interlayer film 140 may be formed of a material similar to that of the first to third interlayer films 110, 120, and 130. Figure 1 The components described are the same and therefore, they will not be described here.

[0145] In the semiconductor device 2 according to the present embodiment, the multilayer wiring layer 101 in which the interlayer films 100 and the diffusion prevention films 200 are alternately stacked is interposed between the pair of substrates 710 and 720 , so that the mechanical strength of the entire semiconductor device 2 can be increased.

[0146] The substrate 710 is a semiconductor substrate and may be, for example, a silicon (Si) substrate. Specifically, the substrate 710 is a substrate on which various passive elements or active elements for realizing the main functions of the semiconductor device 2 are arranged. For example, a storage circuit, a logic circuit, an amplifier circuit, a color sensor, etc. may be arranged in the substrate 710.

[0147] As the substrate 720, a substrate of any material can be used as long as the multilayer wiring layer 101 alternately stacked with the interlayer film 100 and the diffusion prevention film 200 can be bonded to the substrate. For example, the substrate 720 may be a glass substrate such as quartz, a resin substrate such as polyimide or polyester, or a semiconductor substrate such as silicon (Si).

[0148] In addition, the thickness of the substrates 710 and 720 can be reduced by chemical mechanical polishing (CMP) or the like. Even in the case where the voids 530 are formed, the semiconductor device 2 according to the present embodiment can maintain mechanical strength as a whole. Therefore, even in the case where the thickness of the substrates 710 and 720 is reduced, sufficient mechanical strength can be maintained.

[0149] As shown in the semiconductor device 2 according to the present embodiment, the through hole 510 can be formed from any surface of the multilayer wiring layer 101 on which the interlayer film 100 and the diffusion prevention film 200 are alternately stacked. That is, the through hole 510 can be formed from the fourth interlayer film 140 side, or can be formed from the first interlayer film 110 side (which is the via insulating layer 600 side). In either case, in the semiconductor device 2, the gap 530 that exposes the contact via 610 or the zeroth wiring 620 through the through hole 510 can be formed in the multilayer wiring layer 101 as in the first embodiment.

[0150] (2.2. Manufacturing method)

[0151] Now, refer to FIG. 8A to FIG. 8E A method of manufacturing the semiconductor device 2 according to the present embodiment is described. FIG. 8A to FIG. 8E are cross-sectional views respectively illustrating steps in the method for manufacturing the semiconductor device 2 according to the present embodiment.

[0152] First, if Fig. 8A As shown, a via insulating layer 600, a first diffusion prevention film 210, a first interlayer film 110, and a second diffusion prevention film 220 are sequentially stacked by CVD. In addition, a contact via 610 is formed in the via insulating layer 600, and a zeroth wiring 620 and a first wiring 310 are formed in the first interlayer film 110.

[0153] Specifically, the via insulating layer 600 is first formed by CVD. Next, after the first diffusion prevention film 210 is formed on the via insulating layer 600 by CVD, the via insulating layer 600 and the first diffusion prevention film 210 in a predetermined region are removed by etching. Thereafter, a barrier metal layer such as a titanium nitride (TiN) layer is formed in the opening formed by etching by a sputtering technique, and then tungsten (W) is buried in the opening to form the contact via 610 and the zero wiring 620.

[0154] After the first interlayer film 110 is formed on the first diffusion prevention film 210 by CVD, the first interlayer film 110 in a predetermined region is removed by etching, and the resulting opening is filled with copper (Cu) or the like by a damascene technique, thereby forming the first wiring 310. Thereafter, the second diffusion prevention film 220 is formed on the entire surface of the first interlayer film 110 and the first wiring 310 by CVD.

[0155] It should be noted that the via insulating layer 600 and the first interlayer film 110 may be made of SiO2 which is easily etched by hydrofluoric acid. x etc., and the first diffusion prevention film 210 and the second diffusion prevention film 220 may be formed of SiC etc. having high corrosion resistance to hydrofluoric acid.

[0156] Then, if Figure 8B As shown, a portion of the second diffusion prevention film 220 is removed by photolithography or the like, thereby forming an opening 530A. The opening 530A serves as an opening for introducing an etching solution from the second interlayer film 120 to the first interlayer film 110 in a process of forming the space 530 at a later stage.

[0157] like Figure 8C As shown, the second interlayer film 120, the third diffusion prevention film 230, the third interlayer film 130, and the fourth diffusion prevention film 240 are sequentially stacked on the second diffusion prevention film 220 by CVD. In addition, the second wiring 320 and the second through via 420 are formed in the second interlayer film 120, and the third wiring 330 and the third through via 430 are formed in the third interlayer film 130.

[0158] Specifically, after the second interlayer film 120 is formed on the second diffusion prevention film 220 by CVD, the second interlayer film 120 in a predetermined region is removed by etching, and the resulting opening is filled with copper (Cu) or the like by a damascene technique, thereby forming the second wiring 320 and the second through-via 420. Similarly, the third diffusion prevention film 230 and the third interlayer film 130 are then formed on the second wiring 320 and the second interlayer film 120 by CVD. Then, the third interlayer film 130 in a predetermined region is removed by etching, and the resulting opening is filled with copper (Cu) or the like by a damascene technique, thereby forming the third wiring 330 and the third through-via 430. Thereafter, the fourth diffusion prevention film 240 is formed on the third wiring 330 and the third interlayer film 130 by CVD.

[0159] It should be noted that the second interlayer film 120 and the third interlayer film 130 may be made of SiO2 which is easily etched by hydrofluoric acid. x etc., and the third diffusion prevention film 230 and the fourth diffusion prevention film 240 may be formed of SiC etc. having high corrosion resistance to hydrofluoric acid.

[0160] Next, if Fig.8D As shown, after forming the fourth interlayer film 140 on the fourth diffusion prevention film 240 by CVD, the substrate 720 is bonded to the surface of the fourth interlayer film 140, and the substrate 710 is also bonded to the via insulating layer 600 side. As a result, the multilayer wiring layer 101 is inserted between the substrates 710 and 720. Thereafter, the through hole 510 and the protective film 520A are formed on the substrate 710 side.

[0161] The fourth interlayer film 140 may be made of SiO2 which is easily etched by hydrofluoric acid. x The substrates 710 and 720 may be silicon (Si) substrates. After the multilayer wiring layer 101 is bonded to the substrates 710 and 720, the thickness of the substrates 710 and 720 may be reduced by CMP or the like.

[0162] The through hole 510 is formed by etching away some areas of the substrate 710 and the via insulating layer 600. In addition, the protective film 520A is uniformly (conformally) formed on the substrate 710 and inside the through hole 510 by ALD. It should be noted that the planar shape of the opening of the through hole 510 can be a square with a side of 50nm to 300nm. The protective film 520A can be formed of SiC or the like having high corrosion resistance to hydrofluoric acid, and is designed to have a thickness of, for example, 5nm to 30nm.

[0163] Next, if Fig. 8E As shown, etching back is performed on the entire surface to remove the protective film 520A on the substrate 710 and to remove the protective film 520A and the first diffusion prevention film 210 on the first interlayer film 110. Thereafter, an etching solution or etching vapor is introduced through the through hole 510 to etch the first interlayer film 110 and the second interlayer film 120 to form the gap 530. It is to be noted that etching back on the entire surface can be performed by etching with high perpendicular anisotropy, for example.

[0164] Here, etching on the first interlayer film 110 and the second interlayer film 120 can be performed by wet etching or vapor etching using dilute hydrofluoric acid. Since the protective sidewall 520 and the first to third diffusion prevention films 210, 220 and 230 are formed of SiC or the like having high corrosion resistance to hydrofluoric acid, it is difficult to etch at this stage. In addition, the contact via 610, the zero wiring 620, the first wiring 310, the second wiring 320 and the second through-hole 420 are formed of metal materials such as copper (Cu) or tungsten (W), and have high corrosion resistance to hydrofluoric acid. Therefore, it is difficult to etch. Through this arrangement in the semiconductor device 2, selective etching can be performed on the first interlayer film 110 and the second interlayer film 120 to form a gap 530.

[0165] Through the above steps, the semiconductor device 2 according to the present embodiment can be manufactured. Note that in order to prevent moisture or the like from entering the gap 530 , a sealing layer made of an insulating material may be formed on the substrate 710 to close the opening of the through hole 510 .

[0166] By the method for manufacturing the semiconductor device 2 according to the present embodiment, the void 530 can be formed after reducing the thickness of the substrates 710 and 720 by CMP. Therefore, in the CMP step in which mechanical stress is applied to the semiconductor device 2, the semiconductor device 2 can reduce the formation of cracks and the like due to the void 530.

[0167] (2.3. Modification)

[0168] In addition, reference will be made to Fig. 9 A modification example of the semiconductor device 2 according to the present embodiment is described. Fig. 9 is a cross-sectional view of the semiconductor device 21 according to this modification example taken along the stacking direction. It should be noted that Fig. 9 A portion of a cross section of a semiconductor device is shown, and the semiconductor device of course extends to a region not shown in the drawing.

[0169] like Fig. 9 As shown, in the semiconductor device 21 according to this modification, the interlayer film 100 can be formed of a plurality of different materials. Specifically, a portion 110 of the first interlayer film and the via insulating layer 600 can be formed of a first material, and the remaining portion 111 of the first interlayer film, the second interlayer film 121, and the third interlayer film 131 can be formed of a second material different from the first material. For example, the portion 110 of the first interlayer film and the via insulating layer 600 can be made of a material such as SiO x The remaining portion 111 of the first interlayer film, the second interlayer film 121 and the third interlayer film 131 may be made of SiO having a relative dielectric constant greater than that of the first material. x It should be noted that the other components are similar to those of the reference Figure 7 The components described are the same and therefore, they will not be described here.

[0170] The gap 530 is formed in the interlayer film 100 formed of the first material having a higher relative dielectric constant than the second material, thereby effectively reducing the capacitance between the wirings 300. However, it goes without saying that the gap 530 may be formed in the interlayer film 100 formed of the second material having a lower relative dielectric constant than the first material.

[0171] In addition, in the case where a combination of the first material and the second material is selected so that the etching selectivity of the first material relative to the second material becomes high, the void 530 can be formed only in the interlayer film 100 formed of the first material. Specifically, the void 530 can be formed only in the portion 110 of the first interlayer film formed of the first material by etching for forming the void 530. In this case, in the semiconductor device 21, the region in which the void 530 is formed can be more easily controlled.

[0172] <3. Third embodiment>

[0173] Now, refer to Figures 10 to 13C The configuration of a semiconductor device 3 according to a third embodiment of the present invention is described. Fig.10 is a cross-sectional view of the semiconductor device according to the present embodiment, taken along the stacking direction.

[0174] like Fig.10 As shown, the semiconductor device 3 is a stacked solid-state imaging device formed by stacking a first substrate 1100 and a second substrate 1200 . Fig.10 The dotted line in represents a bonding plane between the first substrate 1100 and the second substrate 1200 .

[0175] For example, the first substrate 1100 is a pixel substrate on which pixel units are arranged, and the second substrate 1200 is a logic substrate on which circuits for performing various signal processing related to the operation of the semiconductor device 3 are arranged. The semiconductor device 3 performs photoelectric conversion on light entering from one surface of the first substrate 1100 in the pixel unit, and converts the photoelectrically converted signal charge into a pixel signal in the second substrate 1200. The semiconductor device 3 may be a so-called back-illuminated complementary metal oxide semiconductor (CMOS) image sensor.

[0176] The first substrate 1100 is mainly formed of, for example, a semiconductor substrate 1170 including silicon (Si) and a multilayer wiring layer 1101 formed on the semiconductor substrate 1170. A pixel unit and a pixel signal processing circuit for processing a pixel signal are arranged in the semiconductor substrate 1170, and in the pixel unit, pixels are arranged in a predetermined array. The pixel is mainly formed of a photodiode (PD), which receives light (observation light) from an observation target and performs photoelectric conversion, and a drive circuit including a transistor for reading a pixel signal corresponding to the observation light acquired by the PD, etc. In the pixel signal processing circuit, for example, various signal processing such as analog-to-digital conversion (AD conversion) is performed on the read pixel signal.

[0177] The interlayer film 1110 and the diffusion prevention film 1120 are alternately stacked on one surface of a semiconductor substrate 1170 on which a pixel unit and a pixel signal processing circuit are formed. Wiring 1130 for transmitting various signals such as pixel signals and driving signals for driving transistors of a driving circuit is formed in the interlayer film 1110. In this way, a multilayer wiring layer 1101 is formed. The wiring in the bottom layer (the layer closest to the semiconductor substrate 1170 side) of the multilayer wiring layer 1101 is electrically connected to an electrode 1180 or the like for extracting a signal from a pixel unit or a pixel signal processing circuit through a contact via 1160 formed of, for example, tungsten (W) or the like. In the semiconductor device 3 according to the present embodiment, a void 1153 and a through hole 1151 for forming the void 1153 are formed in the region where the contact via 1160 is exposed.

[0178] The second substrate 1200 is mainly formed of a semiconductor substrate 1270 including, for example, silicon, and a multilayer wiring layer 1201 formed on the semiconductor substrate 1270. A logic circuit for performing various signal processing related to the operation of the semiconductor device 3 is formed in the semiconductor substrate 1270. For example, in the logic circuit, control of a drive signal for driving a pixel unit of the first substrate 1100 (which is control of driving of the pixel unit) and control of signal exchange with the outside can be performed.

[0179] The interlayer film 1210 and the diffusion prevention film 1220 are alternately stacked on one surface of the semiconductor substrate 1270 on which the logic circuit is formed. The wiring layer 1230 for transmitting various signals related to the operation of the logic circuit is formed in the interlayer film 1210. In this way, a multilayer wiring layer 1201 is formed. The wiring in the lowermost layer (the layer closest to the semiconductor substrate 1270 side) of the multilayer wiring layer 1201 is electrically connected to the electrode 1280 for extracting the signal from the logic circuit through the contact via 1260 formed of, for example, tungsten (W) or the like.

[0180] Note that a pad 1290 serving as an external input / output unit (I / O unit) for exchanging various signals with the outside may be formed in the multilayer wiring layer 1201. The pad 1290 may be formed of, for example, aluminum (Al) or the like.

[0181] Here, electrodes are formed in the uppermost layer (the layer farthest from the semiconductor substrate 1170) of the multilayer wiring layer 1101, thereby exposing the metal surface through the interlayer film 1110. Electrodes are also formed in the uppermost layer (the layer farthest from the semiconductor substrate 1270) of the multilayer wiring layer 1201, thereby exposing the metal surface through the interlayer film 1210 in a similar manner. These electrodes constitute an electrode bonding structure 1340 to electrically connect the signal line, the ground line, and the power supply line formed in the respective substrates when the first substrate 1100 and the second substrate 1200 are bonded to each other.

[0182] In this stacked structure of the first substrate 1100 and the second substrate 1200, the color filter layer 1310 and the microlens array 1330 are arranged on the other surface of the semiconductor substrate 1170 on the opposite side to the surface where the multilayer wiring layer 1101 is arranged, via an insulating film or the like.

[0183] The color filter layer 1310 is formed with a plurality of color filters, which are arranged to correspond to pixels. The microlens array 1330 is formed with a plurality of microlenses, which are arranged to correspond to pixels. The color filter layer 1310 and the microlens array 1330 are formed directly above the pixel unit, and one color filter and one microlens are set for the PD of one pixel. It should be noted that the pixels are separated from each other by a pixel definition film 1320 for shading.

[0184] Each color filter of the color filter layer 1310 is, for example, a red, green or blue color filter. The observation light that has passed through the color filter enters the photodiode of the pixel and acquires a pixel signal. Therefore, the pixel signals of the various color components of the observation target are acquired. It should be noted that a pixel corresponding to a color filter can act as a sub-pixel, and a pixel can be formed with a plurality of sub-pixels. For example, a red pixel provided with a red color filter, a green pixel provided with a green color filter, a blue pixel provided with a blue color filter, and a white pixel not provided with any color filter, these four sub-pixels of color can form a pixel.

[0185] The microlens array 1330 is formed so that each microlens is located directly above each color filter. Since the microlens array 1330 is provided, the observation light collected by the microlens enters the photodiode of the pixel via the color filter. Therefore, the microlens array 1330 can improve the light collection efficiency of the observation light and can improve the sensitivity of the solid-state imaging device.

[0186] Now, refer to Figures 11 to 13C A specific position where the void 1153 is formed in the semiconductor device 3 as the solid-state imaging device described above will be described. Fig.11 and Fig.12 Schematic diagram showing a stacked structure formed by wirings of the semiconductor device 3 as a solid-state imaging device. Fig.11 and Fig.12 , the far side of the figure is the semiconductor substrate 1170 side, and Fig.12 The planar structure shown is arranged in Fig.11 On the plane structure shown.

[0187] also, Fig.13A It shows that along Fig.11 A cross-sectional view of a section taken along line A-AA shown in FIG. Fig. 13BIt shows that along Fig.11 A cross-sectional view of a section taken along line B-BB shown in FIG. Fig. 13C It shows that along Fig.12 A cross-sectional view of a section taken along line C-CC shown in FIG.

[0188] like Fig.11 As shown, a photodiode PD is provided for each pixel in the semiconductor substrate 1170. An amplifier transistor AMP, a selection transistor SEL and a reset transistor (not shown) are also provided for each predetermined number of pixels in the semiconductor substrate 1170, and the signal charge photoelectrically converted by the photodiode PD is converted into a pixel signal.

[0189] Specifically, a transfer gate 3080 is arranged on each photodiode PD. The transfer gate 3080 transfers the signal charge photoelectrically converted by the photodiode PD to the floating diffusion (FD) region 3083. The signal charge transferred to the floating diffusion (FD) region 3083 is further transferred to the FD wiring 3033, and controls the gate voltage of the amplifier transistor AMP in a later stage. It should be noted that the transfer gate 3080 acts as a gate electrode of the vertical transistor, and the conduction and cutoff of the transfer gate 3080 are controlled by the TG control line 3032 through the via 3061, the wiring 3031 and the via 3062.

[0190] The amplifier transistor AMP includes a gate electrode 3081, and the on and off states of the gate electrode 3081 are controlled by the signal charge accumulated in the FD wiring 3033. The amplifier transistor AMP converts the signal charge stored in the FD wiring 3033 into a current flowing between the source and the drain. The converted current is transmitted to the FD wiring 3034, the via 3064, the wiring 3035, and the via 3065, for example. Fig.12 The vertical signal line or power line 3036 shown in FIG.

[0191] The selection transistor SEL includes a gate electrode 3082, and the on and off states of the gate electrode 3082 are controlled by a signal from a signal line for controlling the selection of each pixel. The selection transistor SEL is arranged in series with the amplifier transistor AMP, and the selection transistor SEL controls the current flowing between the source and drain of the amplifier transistor AMP. For example, a signal for the gate electrode 3082 of the selection transistor SEL is transmitted through the wiring 3038, the via 3067, the wiring 3037, and the via 3066.

[0192] Here, if Fig.13AAs shown, a gap 1153 may be formed around the FD wiring 3033, and the signal charge photoelectrically converted by the photodiode PD is transferred to the FD wiring 3033. In this case, the gap 1153 may also be formed around the via hole 3061 for controlling the on and off state of the transfer gate 3080. Since the gap 1153 is formed in such a region, the inter-wiring capacitance of the FD wiring 3033 is reduced, whereby the semiconductor device 3 can improve the conversion efficiency when converting the signal charge into the pixel signal.

[0193] In addition, if Fig. 13B As shown, each gap 1153 can be formed around the TG control line 3032 for controlling the on and off state of the transfer gate 3080. Since each gap 1153 is formed in such a region, the inter-wiring capacitance of the TG control line 3032 is reduced, whereby the semiconductor device 3 can increase the transmission rate of the analog signal.

[0194] In addition, if Fig. 13C As shown, a gap 1153 may be formed around a vertical signal line or power line 3036 connected to each pixel. Since the gap 1153 is formed in such a region, the inter-wiring capacitance of the vertical signal line or power line 3036 is reduced, whereby the semiconductor device 3 can increase the transmission rate of analog signals.

[0195] It should be noted that the void 1153 is formed at least in the area where the contact vias electrically connected to the semiconductor substrate 1170 or the electrodes arranged on the semiconductor substrate 1170 are exposed. At this stage, the contact vias exposed to the void 1153 may be multiple contact vias for transmitting the same signal. That is, the contact vias may include dummy contact vias provided to maintain redundancy. Since the mechanical strength of the area where the void 1153 is formed is lower than that of other areas, a larger number of contact vias may be arranged in such an area compared to other areas, so that the contact vias act as a support member for the space between the supporting layers. Examples of such areas include, for example, areas around the FD wiring 3033 and areas connected to the transmission gate 3080.

[0196] <4. Sample Application>

[0197] (4.1. First Application)

[0198] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be applied to an endoscopic surgery system.

[0199] Fig.14 is a diagram schematically showing an example configuration of an endoscopic surgery system to which the technology according to the present invention (the present technology) can be applied.

[0200] Fig.14 The figure shows a situation where a surgeon (physician) 11131 is using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy treatment tool 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are installed.

[0201] The endoscope 11100 includes: a barrel 11101 having a region of a predetermined length from the top end to be inserted into a body cavity of a patient 11132; and a camera 11102 connected to the base end of the barrel 11101. In the example shown in the figure, the endoscope 11100 is designed as a so-called rigid scope having a rigid barrel 11101. However, the endoscope 11100 may be designed as a so-called flexible scope having a flexible barrel.

[0202] An opening is provided at the top end of the lens barrel 11101, and an objective lens is inserted into the opening. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the top end of the lens barrel through a light guide extending inside the lens barrel 11101, and the light is emitted toward a current observation target in the body cavity of the patient 11132 via the objective lens. It should be noted that the endoscope 11100 may be a forward-looking endoscope, an oblique-looking endoscope, or a side-looking endoscope.

[0203] The optical system and the imaging element are arranged inside the camera head 11102, and the reflected light (observation light) from the current observation target is focused on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image, is generated. The image signal is transmitted to the camera control unit (CCU: Camera Control Unit) 11201 as RAW data.

[0204] The CCU 11201 is formed of a central processing unit (CPU) or a graphics processing unit (GPU) or the like, and centrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and, for example, performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0205] Under the control of the CCU 11201 , the display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 .

[0206] For example, the light source device 11203 is formed of a light source such as a light emitting diode (LED), and the light source device 11203 supplies irradiation light to the endoscope 11100 to capture images of a surgical site or the like.

[0207] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information and instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user can input instructions to change the imaging conditions of the endoscope 11100 (such as the type of irradiation light, magnification, and focal length).

[0208] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for tissue cauterization, tissue cutting or blood vessel sealing, etc. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity so as to ensure the field of view of the endoscope 11100 and the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various formats such as text, images and graphics.

[0209] It should be noted that the light source device 11203 that supplies irradiation light to the endoscope 11100 to photograph the surgical site can be formed by, for example, an LED, a laser light source, or a white light source that is a combination of an LED and a laser light source. In the case where the white light source is formed by a combination of RGB laser light sources, the output intensity and output timing of various colors (various wavelengths) can be controlled with high precision. Therefore, the white balance of the image captured by the light source device 11203 can be adjusted. Alternatively, in this case, the laser from each of the RGB laser light sources can be emitted to the current observation target in a time-division manner, and the drive of the imaging element of the camera 11102 can be controlled in a manner synchronized with the illumination timing. Therefore, images corresponding to each RGB color can be captured in a time-division manner. According to this method, a color image can be obtained without providing any color filter in the imaging element.

[0210] In addition, the drive of the light source device 11203 can also be controlled to change the intensity of the output light at a predetermined time interval. The drive of the imaging element of the camera 11102 is controlled in synchronization with the timing of the change in light intensity, and images are acquired in a time-division manner and then synthesized. Therefore, a high dynamic range image without black parts and white spots can be generated.

[0211] In addition, the light source device 11203 can also be designed to supply light of a predetermined band compatible with special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue, light of a narrower band than the irradiation light (or white light) during ordinary observation is emitted. As a result, so-called narrow-band imaging can be performed to perform high-contrast imaging of predetermined tissues such as blood vessels in the surface layer of mucosa. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image using fluorescence generated by irradiation of excitation light. In fluorescence observation, excitation light is emitted onto body tissue, so that fluorescence from body tissue can be observed (autofluorescence observation). Alternatively, for example, a reagent such as indocyanine green (ICG) is locally injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is emitted onto the body tissue, so that a fluorescent image can be obtained. The light source device 11203 can be designed to supply narrow-band light and / or excitation light compatible with such special light observation.

[0212] Fig.15 It shows Fig.14 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown in FIG.

[0213] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400.

[0214] The lens unit 11401 is an optical system, which is provided at a connection portion with the lens barrel 11101. Observation light acquired from the top end of the lens barrel 11101 is guided to the camera 11102 and enters the lens unit 11401. The lens unit 11401 is formed by a combination of a plurality of lenses including a zoom lens and a focus lens.

[0215] The imaging unit 11402 may be formed of one imaging element (so-called single-board type), or may be formed of a plurality of imaging elements (so-called multi-board type). In the case where the imaging unit 11402 is of a multi-board type, for example, each imaging element generates an image signal corresponding to each RGB color, and then the image signals are combined to obtain a color image. Alternatively, the imaging unit 11402 may be designed to include a pair of imaging elements to obtain an image signal for the left eye and an image signal for the right eye that are compatible with a three-dimensional (3D) display. Due to the 3D display, the surgeon 11131 is able to more accurately grasp the depth of the body tissue at the surgical site. It should be noted that in the case where the imaging unit 11402 is of a multi-board type, a plurality of lens units 11401 are provided for each imaging element.

[0216] In addition, the imaging unit 11402 does not have to be disposed in the camera head 11102. For example, the imaging unit 11402 may be disposed in the lens barrel 11101 immediately behind the objective lens.

[0217] The drive unit 11403 is formed of an actuator, and under the control of the camera control unit 11405, the drive unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis. With this arrangement, the magnification and focus of the image captured by the camera unit 11402 can be appropriately adjusted.

[0218] The communication unit 11404 is formed of a communication device to transmit and receive various information to and from the CCU 11201. The communication unit 11404 transmits an image signal obtained from the imaging unit 11402 to the CCU 11201 as RAW data through the transmission cable 11400.

[0219] In addition, the communication unit 11404 also receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, such as information specifying a frame rate for capturing an image, information specifying an exposure value when capturing an image, and / or information specifying a magnification and a focus of a captured image.

[0220] It should be noted that the above imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the endoscope 11100 has a so-called automatic exposure (AE: Auto Exposure) function, an automatic focus (AF: AutoFocus) function, and an automatic white balance (AWB: Auto White Balance) function.

[0221] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404 .

[0222] The communication unit 11411 is formed of a communication device to transmit and receive various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 through the transmission cable 11400.

[0223] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0224] The image processing unit 11412 performs various image processing on the image signal transmitted from the camera 11102 as RAW data.

[0225] The control unit 11413 performs various controls related to the display of the image of the surgical site etc. captured by the endoscope 11100 and the captured image obtained by capturing the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0226] In addition, the control unit 11413 causes the display device 11202 to display a captured image showing a surgical site, etc., based on the image signal subjected to image processing by the image processing unit 11412. With this, the control unit 11413 can use various image recognition technologies to recognize various objects shown in the captured image. For example, the control unit 11413 can detect the shape and color of the edge of the object shown in the captured image, etc., to recognize surgical tools such as forceps, specific body parts, bleeding, and mist when using the energy treatment tool 11112, etc. When causing the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to cause the display device 11202 to superimpose various surgical support information on the image of the surgical site on the display. Since the surgical support information is superimposed and displayed, the surgical support information is presented to the surgeon 11131, thereby reducing the burden on the surgeon 11131 and enabling the surgeon 11131 to perform surgery in a reliable manner.

[0227] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 together is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable of the two.

[0228] Here, in the example shown in the figure, communication is performed in a wired manner using a transmission cable 11400. However, communication between the camera 11102 and the CCU 11201 may be performed in a wireless manner.

[0229] An example of an endoscopic surgical system to which the technology according to the present invention can be applied has been described above. For example, the technology according to the present invention can be applied to the imaging unit 11402 of the camera 11102 in the above-mentioned structure, etc. Specifically, the semiconductor device (solid-state imaging device) according to the third embodiment of the present invention can be applied to the imaging unit 11402 of the camera 11102, etc. Since the technology according to the present invention is applied to the imaging unit 11402 of the camera 11102, a clearer image of the surgical site with less noise can be obtained. Therefore, the surgeon can check the surgical site without error. In addition, since the surgical site image can be obtained with a lower delay, the surgeon can perform treatment with a feeling similar to that in the case where the surgeon touches and observes the surgical site.

[0230] It should be noted that although the endoscopic surgery system has been described herein as an example, the technology according to the present invention can also be applied to, for example, a microsurgery system or the like.

[0231] (4.2. Second Application)

[0232] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be applied to an in vivo information acquisition system.

[0233] Fig.16 is a block diagram schematically showing an example configuration of a patient in vivo information acquisition system using a capsule endoscope to which the technology according to the present invention (the present technology) can be applied.

[0234] The in vivo information acquisition system 10001 includes a capsule endoscope 10100 and an external control device 10200 .

[0235] During the examination, the patient swallows the capsule endoscope 10100. The capsule endoscope 10100 has an imaging function and a wireless communication function. Before being naturally excreted by the patient, the capsule endoscope 10100 moves inside internal organs such as the stomach and intestines by peristaltic motion, etc., sequentially captures internal images of the internal organs at predetermined intervals (hereinafter, these images are referred to as in-vivo images), and sequentially transmits information related to the in-vivo images to an external control device 10200 outside the body in a wireless manner.

[0236] The external control device 10200 controls the overall operation of the in-vivo information acquisition system 10001. The external control device 10200 also receives information related to in-vivo images transmitted from the capsule endoscope 10100, and generates image data for displaying in-vivo images on a display device (not shown) based on the received in-vivo image information.

[0237] In this manner, the in-vivo information acquiring system 10001 is able to acquire in-vivo images showing the state inside the body of the patient at any appropriate time before the swallowed capsule endoscope 10100 is excreted.

[0238] Now, the configuration and function of the capsule endoscope 10100 and the external control device 10200 will be described in more detail.

[0239] The capsule endoscope 10100 has a capsule-shaped casing 10101 , and the casing 10101 accommodates a light source unit 10111 , a camera unit 10112 , an image processing unit 10113 , a wireless communication unit 10114 , a feeding unit 10115 , a power supply unit 10116 , and a control unit 10117 .

[0240] For example, the light source unit 10111 is formed of a light source such as a light emitting diode (LED), and emits light onto the imaging field of the imaging unit 10112 .

[0241] The imaging unit 10112 is formed by an imaging element and an optical system including a plurality of lenses arranged in front of the imaging element. Reflected light of light emitted onto body tissue as a current observation target (hereinafter, the reflected light is referred to as observation light) is collected by the optical system and enters the imaging element. In the imaging unit 10112, the observation light incident on the imaging element is photoelectrically converted, and an image signal corresponding to the observation light is generated. The image signal generated by the imaging unit 10112 is supplied to the image processing unit 10113.

[0242] The image processing unit 10113 is formed of a processor such as a central processing unit (CPU) or a graphics processing unit (GPU), and performs various signal processing on the image signal generated by the imaging unit 10112. The image processing unit 10113 supplies the signal-processed image signal to the wireless communication unit 10114 as RAW data.

[0243] In addition, the wireless communication unit 10114 performs predetermined processing such as modulation processing on the image signal subjected to signal processing by the image processing unit 10113, and transmits the image signal to the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 also receives a control signal related to the drive control of the capsule endoscope 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 supplies the control signal received from the external control device 10200 to the control unit 10117.

[0244] The feed unit 10115 includes an antenna coil for power reception, a power regeneration circuit for regenerating power according to a current generated in the antenna coil, a booster circuit, etc. In the feed unit 10115, power is generated according to the so-called non-contact charging principle.

[0245] The power supply unit 10116 is formed of a secondary battery, and the power supply unit 10116 stores the power generated by the feed unit 10115. Fig.16 In order to avoid complicating the drawings, arrows indicating the destination of the power supply of the power supply unit 10116 are not shown. However, the power stored in the power supply unit 10116 is supplied to the light source unit 10111, the camera unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117, and can be used to drive these components.

[0246] The control unit 10117 is formed by a processor such as a CPU, and the control unit 10117 appropriately drives the light source unit 10111, the camera unit 10112, the image processing unit 10113, the wireless communication unit 10114 and the feeding unit 10115 according to a control signal transmitted from the external control device 10200.

[0247] The external control device 10200 is formed of a processor such as a CPU or a GPU, or a microcomputer or a control board in which a processor and a storage element such as a memory are installed together. The external control device 10200 controls the operation of the capsule endoscope 10100 by sending a control signal to the control unit 10117 of the capsule endoscope 10100 via the antenna 10200A. In the capsule endoscope 10100, for example, the condition under which the light source unit 10111 emits light to the current observation target can be changed according to the control signal from the external control device 10200. In addition, the imaging condition (for example, such as the frame rate and exposure value of the imaging unit 10112) can also be changed according to the control signal from the external control device 10200. In addition, the content of the processing in the image processing unit 10113 and the condition under which the wireless communication unit 10114 transmits the image signal (for example, such as the transmission interval and the number of images to be transmitted) can also be changed according to the control signal from the external control device 10200.

[0248] In addition, the external control device 10200 also performs various image processing on the image signal sent from the capsule endoscope 10100, and generates image data for displaying the captured in-vivo image on the display device. For example, examples of image processing include various signal processing, such as development processing (demosaic processing), image quality enhancement processing (band emphasizing process, super-resolution processing, noise reduction (NR: Noise reduction) processing and / or camera shake correction processing, etc.) and / or magnification processing (electronic zoom processing), etc. The external control device 10200 controls the driving of the display device so that the display device displays the captured in-vivo image based on the generated image data. Alternatively, the external control device 10200 can cause a recording device (not shown) to record the generated image data, or cause a printing device (not shown) to print out the generated image data.

[0249] An example of an in vivo information acquisition system to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be applied to the imaging unit 10112 in the above-mentioned structure. Specifically, the semiconductor device (solid-state imaging device) according to the third embodiment of the present invention can be applied to the imaging unit 10112, etc. Since the technology according to the present invention is applied to the imaging unit 10112, a clearer surgical site image can be obtained, and therefore, the accuracy of the inspection is increased.

[0250] (4.3. Third Application)

[0251] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile body, such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, or a robot.

[0252] Fig.17 : is a block diagram schematically showing an example configuration of a vehicle control system as an example of a moving body control system to which the technology according to the present invention can be applied.

[0253] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Fig.17 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an overall control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional components of the overall control unit 12050.

[0254] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device for generating a vehicle drive force, such as an internal combustion engine or a drive motor, etc.; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a vehicle braking force.

[0255] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, taillights, brake lights, turn signal lights, or fog lights. In this case, the body system control unit 12020 is capable of receiving radio waves transmitted from a portable device that replaces the key or signals of various switches. The body system control unit 12020 receives input of these radio waves or signals and controls the door lock device, power window device, and lights of the vehicle.

[0256] The vehicle exterior information detection unit 12030 detects external information of the vehicle equipped with the vehicle control system 12000. For example, the camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform object detection processing for detecting a person, a vehicle, an obstacle, a sign, or text on the road surface, or may perform distance measurement processing.

[0257] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as ranging information. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared rays.

[0258] The in-vehicle information detection unit 12040 detects the interior information of the vehicle. For example, a driver state detector 12041 for detecting the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detector 12041 includes, for example, a camera for capturing an image of the driver, and based on the detection information input from the driver state detector 12041, the in-vehicle information detection unit 12040 can calculate the degree of fatigue or concentration of the driver, or can determine whether the driver is dozing off.

[0259] Based on the external / internal information acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device, and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to realize the functions of the Advanced Driver Assistance System (ADAS), which includes vehicle collision avoidance or impact mitigation, following vehicle driving based on vehicle-to-vehicle distance, vehicle speed maintenance driving, vehicle collision warning or lane departure warning, etc.

[0260] In addition, based on the information about the vehicle surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform collaborative control by controlling the driving force generating device, steering mechanism or braking device, etc., so as to perform automatic driving that does not rely on the driver's operation.

[0261] In addition, based on the external information acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 controls the headlights according to the position of the front vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control to achieve an anti-glare effect by switching the high beam to the low beam, etc.

[0262] The sound / image output unit 12052 transmits an audio output signal and / or an image output signal to an output device, which can visually or auditorily notify the occupants of the vehicle or the exterior of the vehicle of the information. Fig.17 In the example shown, audio speakers 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include an in-vehicle display and / or a head-up display.

[0263] Fig.18 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0264] exist Fig.18 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0265] The camera units 12101, 12102, 12103, 12104 and 12105 are provided at the following positions, for example: the front edge of the vehicle 12100, the side mirrors, the rear bumper, the rear door, and the upper portion of the front windshield in the vehicle. The camera unit 12101 provided at the front edge and the camera unit 12105 provided at the upper portion of the front windshield in the vehicle mainly capture images in front of the vehicle 12100. The camera units 12102 and 12103 provided at the side mirrors mainly capture images from the side of the vehicle 12100. The camera unit 12104 provided at the rear bumper or the rear door mainly captures images behind the vehicle 12100. The camera unit 12105 provided at the upper portion of the front windshield in the vehicle is mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs or lanes, etc. traveling in front of the vehicle.

[0266] Please note that Fig.18An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front end edge, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the respective side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or the rear door. For example, the image data captured by the imaging units 12101 to 12104 are superimposed on each other, thereby obtaining a bird's-eye view image of the vehicle 12100 viewed from above.

[0267] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0268] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the camera ranges 12111 to 12114 and the time change of the distance (relative to the speed of the vehicle 12100). In this way, it is possible to extract a three-dimensional object that is the closest three-dimensional object on the driving path of the vehicle 12100 and that is driving in the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more) as a vehicle traveling in front of the vehicle 12100. In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be maintained in front of the vehicle traveling in front of the vehicle 12100, and can perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control) and the like. In this way, cooperative control can be performed to perform automatic driving that travels autonomously without relying on the driver's operation.

[0269] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 is capable of extracting three-dimensional object data related to the three-dimensional object according to the classification of two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and utility poles, and is capable of using the three-dimensional object data when automatically avoiding obstacles. For example, the microcomputer 12051 classifies obstacles near the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles that are difficult to visually identify. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is a possibility of collision, the microcomputer 12051 can output a warning to the driver via the audio speaker 12061 and the display unit 12062, or can perform driving support for avoiding collision by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0270] At least one of the camera units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 is capable of identifying pedestrians by determining whether there are pedestrians in the captured images of the camera units 12101 to 12104. For example, such pedestrian recognition is performed by the following processing: a process of extracting feature points from images captured by the camera units 12101 to 12104 used as infrared cameras; and a process of pattern matching a series of feature points representing the contour of an object and determining whether there are pedestrians. If the microcomputer 12051 determines that there are pedestrians in the images captured by the camera units 12101 to 12104 and recognizes the pedestrians, the sound / image output unit 12052 controls the display unit 12062 so as to display a rectangular contour line for emphasizing the recognized pedestrians in a superimposed manner. In addition, the sound / image output unit 12052 may also control the display unit 12062 to display an icon representing a pedestrian at a desired position, etc.

[0271] An example of a vehicle control system to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be applied to the camera unit 12031 in the above-mentioned structure, etc. Specifically, the semiconductor device (solid-state camera device) according to the third embodiment of the present invention can be applied to the camera unit 12031. Since the technology according to the present invention is applied to the camera unit 12031, an easy-to-view captured image can be obtained, and therefore, the driver's fatigue can be reduced. In addition, since the captured image can be obtained with a lower delay, the vehicle can be driven with a feeling similar to that in the case where the driver directly observes the surrounding environment.

[0272] Although the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, the technical scope of the present invention is not limited to these examples. A technician with ordinary skills in the technical field of the present invention can obviously make various changes or modifications within the scope of the technical spirit claimed herein, and it should be understood that these changes or modifications are within the technical scope of the present invention.

[0273] In addition, the effects disclosed in this specification are merely illustrative or exemplary, and not restrictive. That is, in addition to or in place of the above effects, the technology according to the present invention may also exhibit other effects that are obvious to those skilled in the art based on the description in this specification.

[0274] It is to be noted that the configuration described below is also within the technical scope of the present invention.

[0275] (1) A semiconductor device comprising:

[0276] a multilayer wiring layer in which a plurality of interlayer films and a plurality of diffusion prevention films are alternately stacked and wiring is formed inside the interlayer film;

[0277] a contact via formed to penetrate a via insulating layer and electrically connected to the wiring of the multilayer wiring layer, the via insulating layer being formed on one surface of the multilayer wiring layer;

[0278] a through hole formed so as to penetrate at least one of the interlayer film and the diffusion prevention film from another surface of the multilayer wiring layer on the side opposite to the one surface of the multilayer wiring layer; and

[0279] A void is connected to the through hole and is formed in at least one of the interlayer films to expose the contact via.

[0280] (2) The semiconductor device according to (1), wherein a semiconductor substrate is further arranged on the other surface of the via insulating layer on the opposite side to the surface on which the multilayer wiring layer is formed.

[0281] (3) The semiconductor device according to (2), wherein a photodiode is arranged in the semiconductor substrate.

[0282] (4) The semiconductor device according to (3), wherein the void is formed in a region in contact with an FD wiring that stores signal charges read from the photodiode.

[0283] (5) The semiconductor device according to (3) or (4), wherein the gap is also formed in a region in contact with a TG control line, the TG control line being electrically connected to a gate of a transfer transistor that controls reading of signal charge from the photodiode.

[0284] (6) The semiconductor device according to (5), wherein the contact via is electrically connected to the gate of the transfer transistor.

[0285] (7) A semiconductor device according to any one of (3) to (6), wherein the gap is also formed in a region in contact with a vertical signal line or a power line, and the vertical signal line or the power line is electrically connected to a pixel circuit that converts a signal charge read from the photodiode into a pixel signal.

[0286] (8) The semiconductor device according to any one of (2) to (7), wherein a substrate opposing the semiconductor substrate is further arranged on the other surface side of the multilayer wiring layer.

[0287] (9) The semiconductor device according to any one of (1) to (8), wherein the contact via is formed to protrude toward the inside of the interlayer film arranged on the via insulating layer side of the multilayer wiring layer.

[0288] (10) The semiconductor device according to any one of (1) to (9), wherein the void is also formed in at least one of the interlayer films.

[0289] (11) The semiconductor device according to (10), wherein

[0290] The void is also formed in the plurality of interlayer films, and

[0291] An opening is formed in a portion of the diffusion prevention film between the interlayer films in which the gap is formed.

[0292] (12) The semiconductor device according to (11), wherein

[0293] Each of the interlayer films is formed of a first material or a second material, the second material having a lower relative dielectric constant than the first material, and

[0294] The void is formed in the interlayer film formed of the first material.

[0295] (13) The semiconductor device according to any one of (1) to (12), wherein the wiring is formed of a first metal, and the contact via is formed of a second metal different from the first metal.

[0296] (14) The semiconductor device according to (13), wherein a wiring connected to the contact via and formed of the second metal is further formed inside the interlayer film.

[0297] (15) The semiconductor device according to (13) or (14), wherein the first metal is copper, and the second metal is tungsten.

[0298] (16) The semiconductor device according to (14) or (15), wherein surfaces of the contact via and the wiring formed of the second metal are covered with a protective layer.

[0299] (17) The semiconductor device according to any one of (1) to (16), wherein a protective side wall is further formed inside the through hole.

[0300] (18) The semiconductor device according to (17), wherein the diffusion prevention film and the protective sidewall are each formed of a material having higher corrosion resistance to a fluorine compound than the interlayer film.

[0301] Reference numerals list

[0302] 1, 2, 3, 11, 12, 13A, 13B, 13C, 14, 21 Semiconductor devices

[0303] 100 interlayer film

[0304] 101 Multi-layer wiring layer

[0305] 200 Diffusion prevention film

[0306] 300 Wiring

[0307] 400 Through hole

[0308] 510 Through hole

[0309] 520 Protective sidewall

[0310] 530 Gap

[0311] 600 Via insulation layer

[0312] 610 Contact vias

[0313] 620 Zero Wiring

[0314] 710, 720 base plate

Claims

1. A semiconductor device comprising: a multilayer wiring layer in which a plurality of interlayer films and a plurality of diffusion prevention films are alternately stacked, and wirings and through vias are formed inside the interlayer films; a contact via formed to penetrate a via insulating layer and electrically connected to the wiring of the multilayer wiring layer, the via insulating layer being formed on one surface of the multilayer wiring layer; a through hole formed so as to penetrate at least one of the interlayer film and the diffusion prevention film from another surface of the multilayer wiring layer on the side opposite to the one surface of the multilayer wiring layer; as well as a void connected to the through hole and formed in the plurality of the interlayer films to expose the contact via, A semiconductor substrate is further arranged on the other surface of the via insulating layer on the side opposite to the surface on which the multilayer wiring layer is formed. A photodiode is arranged in the semiconductor substrate, The void is also formed in a region in contact with a TG control line electrically connected to a gate of a transfer transistor that controls reading of signal charges from the photodiode, and The contact via is electrically connected to the gate of the pass transistor, wherein the contact via is formed to protrude toward the inside of the interlayer film arranged on the via insulating layer side of the multilayer wiring layer and to contact the wiring in the interlayer film, wherein the through via in the interlayer film in which the void is formed is exposed in the void, and The contact via, the wiring, and the through via are connected to form a wall surrounding a predetermined region, so that a region where the void is formed is limited to the predetermined region in an in-plane direction of the semiconductor device.

2. The semiconductor device according to claim 1, wherein The void is also formed in a region in contact with an FD wiring that stores signal charges read from the photodiode.

3. The semiconductor device according to claim 1, wherein The gap is also formed in a region in contact with a vertical signal line or a power supply line electrically connected to a pixel circuit that converts a signal charge read from the photodiode into a pixel signal.

4. The semiconductor device according to any one of claims 1 to 3, wherein: On the other surface side of the multilayer wiring layer, a substrate opposing the semiconductor substrate is also arranged.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The void is also formed in the plurality of interlayer films, and An opening is formed in a portion of the diffusion prevention film between the interlayer films in which the gap is formed.

6. The semiconductor device according to claim 5, wherein: Each of the interlayer films is formed of a first material or a second material, the second material having a lower relative dielectric constant than the first material, and The void is formed in the interlayer film formed of the first material.

7. The semiconductor device according to any one of claims 1 to 3, wherein: The wiring is formed of a first metal, and the contact via is formed of a second metal different from the first metal.

8. The semiconductor device according to claim 7, wherein: A wiring connected to the contact via and formed of the second metal is also formed inside the interlayer film.

9. The semiconductor device according to claim 7, wherein: The first metal is copper and the second metal is tungsten.

10. The semiconductor device according to claim 8, wherein Surfaces of the contact vias and the wirings formed of the second metal are covered with a protective layer.

11. The semiconductor device according to any one of claims 1 to 3, wherein: A protective side wall is also formed inside the through hole.

12. The semiconductor device according to claim 11, wherein The diffusion prevention film and the protective sidewall are each formed of a material having higher corrosion resistance to fluorine compounds than the interlayer film.

Images