Display device

Abstract

The present application provides a display device, which includes a display substrate, a main circuit board, and a first connection circuit board and a second connection circuit board. The display substrate includes a base layer, an insulating layer, a first signal line, a second signal line, a first pad, and a second pad, wherein the insulating layer is on the base layer, the first signal line is on the base layer, the second signal line is on the base layer, the first pad is exposed from the insulating layer and connected to the first signal line, and the second pad is connected to the side surface of the second signal line and is arranged on the side surface and bottom surface of the base layer. The first connection circuit board electrically connects the first pad and the main circuit board, and the second connection circuit board electrically connects the second pad and the main circuit board.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0014687, filed on February 8, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention relate generally to display devices, and more particularly, to a display device including a slim bezel area. Background Art

[0004] Typically, a display panel may be manufactured, and then, a circuit board may be connected to the display panel. For example, in a tape automated bonding mounting method, the circuit board may be bonded to the display panel by using an anisotropic conductive film.

[0005] Recently, display panel design techniques for reducing a bezel area (or a non-display area) have been variously studied.

[0006] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] The device constructed according to the exemplary embodiment of the present invention can reduce the defect rate of the bonding area.

[0008] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0009] In an exemplary embodiment of the present invention, a display device includes a display substrate, a main circuit board, and a first connection circuit board and a second connection circuit board. The display substrate includes a base layer, an insulating layer, a first signal line, a second signal line, a first pad, and a second pad, wherein the insulating layer is on the base layer, the first signal line is on the base layer, the second signal line is on the base layer, the first pad is exposed from the insulating layer and connected to the first signal line, and the second pad is connected to the side surface of the second signal line and is arranged on the side surface and bottom surface of the base layer. The first connection circuit board electrically connects the first pad and the main circuit board, and the second connection circuit board electrically connects the second pad and the main circuit board.

[0010] In example embodiments, a side surface of the second signal line may be substantially aligned with a side surface of the base layer.

[0011] In example embodiments, a side surface of the second signal line may be substantially aligned with a side surface of the insulating layer.

[0012] In exemplary embodiments, the first pad may be connected to the first signal line through a contact hole penetrating the insulating layer.

[0013] In exemplary embodiments, the first pad may be spaced apart from an edge of the insulating layer in a plan view.

[0014] In exemplary embodiments, the first signal line and the second signal line may be disposed on the same layer.

[0015] In exemplary embodiments, the second pad may include a metal paste.

[0016] In exemplary embodiments, the first pad may include silver (Ag), copper (Cu), gold (Au), or aluminum (Al).

[0017] In an exemplary embodiment, the first connection circuit board and the second connection circuit board may be coupled to the same surface of the main circuit board.

[0018] In an exemplary embodiment, the display device may further include a driving chip mounted on each of the first connection circuit board and the second connection circuit board.

[0019] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0021] Figure 1A is a perspective view showing a display device according to an exemplary embodiment of the present inventive concept;

[0022] Figure 1B and Figure 1C is a cross-sectional view illustrating a display device according to an exemplary embodiment of the present inventive concept;

[0023] Figure 2 is a plan view showing a display device according to an exemplary embodiment of the present inventive concept;

[0024] Figure 3A and Figure 3B is a cross-sectional view illustrating a display area of ​​a display panel according to some exemplary embodiments of the inventive concept;

[0025] Figure 4Ais an enlarged plan view showing a display device according to an exemplary embodiment of the inventive concept;

[0026] Figure 4B is a rear view illustrating a connection circuit board according to an exemplary embodiment of the present inventive concept;

[0027] Figure 4C is a cross-sectional view illustrating a display device according to an exemplary embodiment of the present inventive concept;

[0028] Figure 4D and Figure 4E yes Figure 4C an enlarged cross-sectional view of a region;

[0029] Figure 4F is an enlarged perspective view showing a display device according to an exemplary embodiment of the present inventive concept;

[0030] Figure 5 is a cross-sectional view illustrating a method of manufacturing a display device according to an exemplary embodiment of the present inventive concept;

[0031] Fig. 6A is an enlarged plan view illustrating a display device according to an exemplary embodiment of the inventive concept; and

[0032] Figure 6B FIG. 2 is a diagram showing a display device according to an exemplary embodiment of the present inventive concept. Fig. 6A A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0033] In the following description, for the purpose of explanation, many specific details are elaborated to provide a thorough understanding of various exemplary embodiments or embodiments of the present invention. As used herein, "embodiment" and "embodiment" are interchangeable words, which are non-limiting examples of one or more devices or methods using the inventive concept disclosed herein. However, it is obvious that various exemplary embodiments can be put into practice without these specific details or with one or more equivalent arrangements. In other examples, in order to avoid unnecessarily blurring various exemplary embodiments, known structures and devices are shown in block diagram form. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0034] Unless otherwise specified, the exemplary embodiments shown are to be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0035] The use of cross hatching and / or shading in the drawings is generally used to make the boundaries between adjacent elements clear. Therefore, unless specified, the presence or absence of cross hatching or shading does not represent or indicate any preference or requirement for a specific material, material property, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0036] When an element such as a layer is referred to as being located on another element or layer, being connected to or being coupled to another element or layer, it can be directly located on this other element or layer, being directly connected to or being coupled to this other element or layer, or there can be an element or layer in between. However, when an element or layer is referred to as being directly located on another element or layer, being directly connected to or being directly coupled to another element or layer, there is no element or layer in between. For this reason, the word "connection" can represent physical connection, electrical connection and / or fluid connection in the case of the element in between that exists or does not exist. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes (such as, x-axis, y-axis and z-axis) of the rectangular coordinate system, and can be explained with a broader meaning. For example, the D1 axis, the D2 axis and the D3 axis can be perpendicular to each other, or different directions that are not perpendicular to each other can be represented. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] Although the words "first", "second", etc. can be used in this article to describe various types of elements, these elements should not be limited by these words. These words are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element.

[0038] Spatially relative terms such as "below," "beneath," "under," "down," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein for descriptive purposes and, thereby, to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Thus, the exemplary term "below" may include both above and below orientations. In addition, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0039] The terms used herein are for the purpose of describing specific embodiments, rather than being intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an" and "the" are intended to also include plural forms. In addition, when used in this specification, the words "comprise", "comprises", "includes" and / or "includes" represent the existence of stated features, integral bodies, steps, operations, elements, parts and / or combinations thereof, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or combinations thereof. It should also be noted that, as used herein, the words "substantially", "about" and other similar words are used as approximate words and not as degree words, and are therefore used to allow for the inherent deviations in the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0040] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Therefore, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the regions, but should include deviations in shape due to, for example, manufacturing. In this manner, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore are not necessarily intended to be limiting.

[0041] Unless otherwise defined, all words (including technical and scientific words) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Unless explicitly defined as such herein, words, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formalized meaning.

[0042] Figure 1A is a perspective view illustrating a display device DD according to an exemplary embodiment of the inventive concept. Figure 1B and Figure 1C is a cross-sectional view illustrating a display device DD according to an exemplary embodiment of the inventive concept. Figure 2 is a plan view illustrating a display device DD according to an exemplary embodiment of the inventive concept.

[0043] Reference Figure 1A , Figure 1B , Figure 1C and Figure 2 , the display device DD may include a display panel DP, a first connection circuit board FPCB1 and a second connection circuit board FPCB2, and a main circuit board MPCB. In the present exemplary embodiment, the driving chip DC may be mounted on the first connection circuit board FPCB1 and the second connection circuit board FPCB2. However, the exemplary embodiments of the inventive concept are not limited thereto. In some exemplary embodiments, the driving chip DC may not be mounted on the first connection circuit board FPCB1 and the second connection circuit board FPCB2, but may be mounted on the display panel DP or the main circuit board MPCB.

[0044] The display device DD may further include a chassis member or a molding member, and may further include a backlight unit according to the kind of the display panel DP.

[0045] The display panel DP may be, but is not limited to, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, a micro-electromechanical system (MEMS) display panel, an electrowetting display panel, or a light-emitting display panel.

[0046] The display panel DP may include a first display substrate 100 and a second display substrate 200, wherein the second display substrate 200 faces the first display substrate 100 and is spaced apart therefrom. A cell gap may be formed between the first display substrate 100 and the second display substrate 200. The cell gap may be maintained by a sealant SLM coupling the first display substrate 100 and the second display substrate 200. A grayscale display layer for generating an image may be provided between the first display substrate 100 and the second display substrate 200. Depending on the type of the display panel DP, the grayscale display layer may include a liquid crystal layer, a light emitting layer, or an electrophoretic layer.

[0047] like Figure 1A As shown in , the display panel DP may display an image through the display surface DP-IS. The display surface DP-IS may be parallel to a plane defined by the first direction axis DR1 and the second direction axis DR2. The display surface DP-IS may include a display area DA and a non-display area NDA. The non-display area NDA may be defined along a boundary of the display surface DP-IS. The display area DA may be surrounded by the non-display area NDA. In some exemplary embodiments, the non-display area NDA may be provided only at one side of the display area DA. In corresponding areas, the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may be bonded to the first display substrate 100.

[0048] The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) can be represented by a third directional axis DR3. Hereinafter, the front surface (or top surface) and the rear surface (or bottom surface) of each of the plurality of layers or units can be defined by the third directional axis DR3. However, the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3 of the present exemplary embodiment are shown as examples. Hereinafter, the first direction to the third direction are defined as directions represented by the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3, respectively, and are represented by the same reference numerals as the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3, respectively.

[0049] In the present exemplary embodiment, a display panel DP having a flat display surface DP-IS is shown. However, exemplary embodiments of the inventive concept are not limited thereto. In other exemplary embodiments, the display device DD may include a curved display surface or a three-dimensional (3D) display surface. The 3D display surface may include a plurality of display areas indicated by different directions.

[0050] A signal controller SC may be mounted on the main circuit board MPCB. The signal controller SC may receive image data and control signals from an external graphic controller. The signal controller SC may provide the control signals to the display panel DP.

[0051] The first connection circuit board FPCB1 and the second connection circuit board FPCB2 may electrically connect the display panel DP and the main circuit board MPCB. The first connection circuit board FPCB1 and the second connection circuit board FPCB2 may transmit signals from the main circuit board MPCB to the driving chip DC, and may transmit signals from the driving chip DC to the display panel DP. In this exemplary embodiment, the driving chip DC may be a data driving circuit. In an exemplary embodiment, the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may transmit signals from the signal controller SC to the display panel DP.

[0052] Each of the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may be bonded to each of the display panel DP and the main circuit board MPCB by a conductive adhesive member. The conductive adhesive member may include a solder ball, a solder paste, or an anisotropic conductive film. Hereinafter, an anisotropic conductive film will be described as an example of a conductive adhesive member.

[0053] like Figure 1A As shown in FIG. 1 , the first display substrate 100 may include a plurality of bonding areas BDA. The first connection circuit board FPCB1 and the second connection circuit board FPCB2 may be bonded to each of the plurality of bonding areas BDA.

[0054] like Figure 1B As shown in , the first connection circuit board FPCB1 may be bonded to the top surface of the first display substrate 100. Figure 1C As shown in , the second connection circuit board FPCB2 may be bonded to the bottom surface of the first display substrate 100. Figure 1B and Figure 1C , an anisotropic conductive film ACF is shown as the conductive adhesive member.

[0055] In the present exemplary embodiment, the bonding area BDA is disposed in the lower display substrate. However, the exemplary embodiments of the inventive concept are not limited thereto. The bonding area BDA is disposed in the display substrate on which the signal line and the pad are disposed. In an exemplary embodiment, the first display substrate 100 and the second display substrate 200 may be flipped, and in this case, the bonding area BDA may be disposed in the upper display substrate.

[0056] Figure 2 FIG. 2 shows a planar arrangement of signal lines GL1 to GLn, DL1 to DLm, PL-D1 and PL-D2 and pixels PX11 to PXnm. The signal lines GL1 to GLn, DL1 to DLm, PL-D1 and PL-D2 may include a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm (which may also be as shown in FIG. 2 ), and a plurality of data lines DL1 to DLm (which may also be as shown in FIG. 2 ). Figure 4A and Fig. 6A The signal lines PL-D1 and PL-D2 are collectively referred to as DL as in FIG.

[0057] Each of the pixels PX11 to PXnm may be connected to a corresponding one of a plurality of gate lines GL1 to GLn and a corresponding one of a plurality of data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a display element.

[0058] exist Figure 2, the pixels PX11 to PXnm are arranged in a matrix form as an example. However, the exemplary embodiments of the inventive concept are not limited thereto. In another exemplary embodiment, the pixels PX11 to PXnm may be arranged in a PenTile form. In yet another exemplary embodiment, the pixels PX11 to PXnm may be arranged in a rhombus form.

[0059] The gate lines GL1 to GLn may extend in the first direction DR1 and may be arranged in the second direction DR2, and the data lines DL1 to DLm may be insulated from the gate lines GL1 to GLn and may intersect with the gate lines GL1 to GLn. The gate lines GL1 to GLn and the data lines DL1 to DLm may overlap the display area DA. The auxiliary signal lines PL-D1 and PL-D2 may overlap the non-display area NDA and may be connected to the data lines DL1 to DLm.

[0060] The plurality of gate lines GL1 to GLn may be connected to a gate driving circuit GDC. The gate driving circuit GDC may be integrated in the display panel DP through an oxide silicon gate driving circuit (OSG) process or an amorphous silicon gate driving circuit (ASG) process.

[0061] The auxiliary signal lines PL-D1 and PL-D2 may include a first auxiliary signal line PL-D1 connected to a first pad PD1 and a second auxiliary signal line PL-D2 connected to a second pad PD2. As the resolution of the display panel DP increases, the area of ​​the pixels PX11 to PXnm may be reduced, and the number of pixels PX11 to PXnm in a unit area may increase. If the pads are arranged in a row, a large area of ​​the bonding area may be required, and defects (e.g., short circuits between pads) may occur. It may be necessary to design pads with fine spacing to prevent these limitations. However, pads with fine spacing may cause bonding defects. According to this exemplary embodiment, the pads may be arranged in two groups (e.g., two rows), such as a first pad PD1 and a second pad PD2, to address the above limitations.

[0062] The first pads PD1 may be arranged in the first direction DR1, and the second pads PD2 may be arranged in the first direction DR1 to form a row different from that of the first pads PD1. The first auxiliary signal lines PL-D1 and the second auxiliary signal lines PL-D2 may be alternately arranged.

[0063] The first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2 connected to the data lines DL1 to DLm may be disposed on a layer different from the layer on which the data lines DL1 to DLm are disposed. The first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2 may be disposed on the same layer. For example, the first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2 may be disposed on the same layer as the gate lines GL1 to GLn. Each of the first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2 may be electrically connected to a corresponding one of the data lines DL1 to DLm through a contact hole CH. The contact hole CH may penetrate at least one insulating layer disposed between the data lines DL1 to DLm and the first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2. Figure 2 , two contact holes CH are shown as an example.

[0064] In an exemplary embodiment, the contact hole CH may be omitted. The data lines DL1 to DLm and the first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2 may be disposed on the same layer. In this case, each of the data lines DL1 to DLm connected to each other and each of the first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2 may not be distinguished from each other, but may be defined as one signal line. Here, the data lines and the auxiliary signal lines connected to each other may correspond to different parts of one signal line. In other words, in the present exemplary embodiment, the first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2 are separately disposed. Alternatively, the first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2 may be omitted, and parts of the signal lines may replace the first auxiliary signal line PL-D1 and the second auxiliary signal line PL-D2.

[0065] Figure 3A and Figure 3B 2 is a cross-sectional view illustrating a display area DA of a display panel DP according to some exemplary embodiments of the inventive concept. Figure 3A A cross-sectional view corresponding to a pixel of a liquid crystal display panel is shown, and Figure 3B A cross-sectional view corresponding to a pixel of an organic light emitting display panel is shown.

[0066] A pixel of the liquid crystal display panel may include a transistor TR, a liquid crystal capacitor Clc, and a storage capacitor Cst.

[0067] The transistor TR may include a control electrode GE connected to a gate line, an active portion AL overlapping the control electrode GE, an input electrode DE connected to a data line, and an output electrode SE spaced apart from the input electrode DE. The liquid crystal capacitor Clc may include a pixel electrode PE and a common electrode CE. The storage capacitor Cst may include the pixel electrode PE and a portion of the storage line STL overlapping the pixel electrode PE.

[0068] The control electrode GE and the storage line STL may be disposed on one surface of the first base layer BS1. The first base layer BS1 may be a glass substrate or a plastic substrate. At least one insulating layer and at least one conductive pattern may be disposed on the one surface of the first base layer BS1.

[0069] The first insulating layer 10 may be disposed on one surface of the first base layer BS1 and may cover the control electrode GE and the storage line STL. The first insulating layer 10 may include at least one of an inorganic material and an organic material. An active portion AL overlapping the control electrode GE may be disposed on the first insulating layer 10. The active portion AL may include a semiconductor layer SCL and an ohmic contact layer OCL. The semiconductor layer SCL may be disposed on the first insulating layer 10, and the ohmic contact layer OCL may be disposed on the semiconductor layer SCL.

[0070] The semiconductor layer SCL may include amorphous silicon or polycrystalline silicon. Alternatively, the semiconductor layer SCL may include a metal oxide semiconductor. The ohmic contact layer OCL may be doped with a dopant. The concentration of the dopant in the ohmic contact layer OCL may be higher than the concentration of the dopant in the semiconductor layer SCL. The ohmic contact layer OCL may include two parts spaced apart from each other. In an exemplary embodiment of the inventive concept, the ohmic contact layer OCL may have a single integral shape.

[0071] The input electrode DE and the output electrode SE may be disposed on the active portion AL. The input electrode DE and the output electrode SE may be spaced apart from each other. A second insulating layer 20 may be disposed on the first insulating layer 10, and the second insulating layer 20 may cover the active portion AL, the input electrode DE, and the output electrode SE. A third insulating layer 30 may be disposed on the second insulating layer 20. Each of the second insulating layer 20 and the third insulating layer 30 may include at least one of an inorganic material and an organic material. The third insulating layer 30 may be a single-layer organic layer providing a flat surface. In the present exemplary embodiment, the third insulating layer 30 may include a plurality of color filters. A fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be an inorganic layer covering the color filter.

[0072] like Figure 3AAs shown in FIG. 1 , the pixel electrode PE may be disposed on the fourth insulating layer 40. The pixel electrode PE may be connected to the output electrode SE through a contact hole CH10 penetrating the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. An alignment layer covering the pixel electrode PE may be disposed on the fourth insulating layer 40.

[0073] The second base layer BS2 may be a glass substrate or a plastic substrate. The black matrix layer BM may be disposed on the bottom surface of the second base layer BS2. The black matrix layer BM may define openings corresponding to the pixel regions. The spacer CS may overlap the black matrix layer BM.

[0074] At least one insulating layer covering the black matrix layer BM may be disposed on the bottom surface of the second base layer BS2. Figure 3A 2 and 3. The fifth insulating layer 50 providing a flat surface is shown as an example. The fifth insulating layer 50 may include an organic material.

[0075] like Figure 3A As shown in FIG. 5 , the common electrode CE may be disposed on the bottom surface of the fifth insulating layer 50. A common voltage may be applied to the common electrode CE. The level of the common voltage may be different from that of the pixel voltage.

[0076] exist Figure 3A , a liquid crystal display panel of a vertical alignment (VA) mode is shown as an example. However, exemplary embodiments of the inventive concept are not limited thereto. In other exemplary embodiments, the display panel DP may be a liquid crystal display panel having an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, a surface-to-line switching (PLS) mode, a super vertical alignment (SVA) mode, or a surface-stabilized vertical alignment (SS-VA) mode.

[0077] like Figure 3B As shown in , a pixel of the organic light emitting display panel may include a switching transistor T1, a driving transistor T2 and a light emitting element OLED.

[0078] The organic light emitting display panel may include a first display substrate 100 and a second display substrate 200. The first display substrate 100 may include a first base layer BS1, a circuit element layer DP-CL disposed on the first base layer BS1, and a display element layer DP-OLED disposed on the circuit element layer DP-CL. The second display substrate 200 may include a second base layer BS2, and a black matrix layer BM and a color control layer CCL disposed on the bottom surface of the second base layer BS2.

[0079] The first base layer BS1 may include a synthetic resin substrate or a glass substrate. The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The circuit element may include a signal line and a driving circuit of a pixel. The circuit element layer DP-CL may be formed by forming an insulating layer, a semiconductor layer, and a conductive layer using a coating and / or deposition process and patterning the insulating layer, the semiconductor layer, and the conductive layer using a photolithography process.

[0080] In the present exemplary embodiment, the circuit element layer DP-CL may include a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30. The first insulating layer 10 and the second insulating layer 20 may be inorganic layers, and the third insulating layer 30 may be an organic layer.

[0081] Figure 3B The arrangement relationship of the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, the first control electrode GE1, the second control electrode GE2, the first input electrode SE1, the first output electrode DE1, the second input electrode SE2, and the second output electrode DE2 constituting the switching transistor T1 and the driving transistor T2 is shown. Figure 3B A first through hole CH1, a second through hole CH2, a third through hole CH3, and a fourth through hole CH4 are also shown as examples.

[0082] The display element layer DP-OLED may include a light emitting element OLED. The light emitting element OLED may include a light emitting diode. The light emitting element OLED may include an organic light emitting layer or a quantum dot light emitting layer. The display element layer DP-OLED may include a pixel defining layer PDL. For example, the pixel defining layer PDL may be an organic layer. The display element layer DP-OLED may further include a cover layer CL disposed on the light emitting element OLED.

[0083] The third insulating layer 30 may be provided with a first electrode AE. The first electrode AE ​​may be connected to the second output electrode DE2 through a fifth through hole CH5 penetrating the third insulating layer 30. The pixel defining layer PDL may define an opening OP therein. The opening OP of the pixel defining layer PDL may expose at least a portion of the first electrode AE.

[0084] like Figure 3B As shown in , the display panel DP may include a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA. In the present exemplary embodiment, the light emitting region PXA is defined to correspond to a partial region of the first electrode AE ​​exposed by the opening OP.

[0085] A hole control layer HCL may be provided in common in the light emitting region PXA and the non-light emitting region NPXA. The hole control layer HCL may include a hole transport layer and may further include a hole injection layer. A light emitting layer EML may be provided on the hole control layer HCL. The light emitting layer EML may be provided in common in the light emitting region PXA and the non-light emitting region NPXA. Alternatively, the light emitting layer EML may be provided in the light emitting region PXA but may not be provided in the non-light emitting region NPXA. The light emitting layer EML may include an organic material and / or an inorganic material. The light emitting layer EML may generate a first color light, for example, blue light.

[0086] An electron control layer ECL may be provided on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be formed together in a plurality of pixels by using an open mask. A second electrode CCE may be provided on the electron control layer ECL. The second electrode CCE may be provided together in a plurality of pixels. A covering layer CL may be provided on the second electrode CCE to protect the second electrode CCE. The covering layer CL may include an organic material or an inorganic material.

[0087] The second base layer BS2 may be spaced apart from the cover layer CL. The second base layer BS2 may include a synthetic resin substrate or a glass substrate. The color control layer CCL may transmit the first color light or may convert the first color light into the second color light or the third color light according to the pixel. The color control layer CCL may include quantum dots. The pixels PX11 to PXnm (see Figure 2 ) can be divided into a plurality of pixel groups. Different types of color control layers CCL can be respectively arranged in the pixel groups.

[0088] In an exemplary embodiment of the present inventive concept, the second display substrate 200 may be replaced by a thin film encapsulation layer. In this case, the black matrix layer BM and the color control layer CCL may be disposed on the thin film encapsulation layer.

[0089] Figure 4A is an enlarged plan view illustrating a display device DD according to an exemplary embodiment of the inventive concept. Figure 4B is a rear view illustrating a first connection circuit board FPCB1 according to an exemplary embodiment of the present inventive concept. Figure 4C is a cross-sectional view illustrating a display device DD according to an exemplary embodiment of the inventive concept. Figure 4D and Figure 4E yes Figure 4C An enlarged cross-sectional view of the area. Figure 4F is an enlarged perspective view illustrating a display device DD according to an exemplary embodiment of the inventive concept.

[0090] like Figure 4AAs shown in FIG. 1 , the first connection circuit board FPCB1 may be connected to the first pad PD1, and the second connection circuit board FPCB2 may be connected to the second pad PD2. In a plan view, the first pad PD1 may be spaced apart from an edge E-DP of the first display substrate 100 in the second direction DR2. In a plan view, the edge E-DP of the first display substrate 100 may be substantially the same as an edge of an insulating layer of the first display substrate 100.

[0091] The first connection circuit board FPCB1 may overlap the first and second pads PD1 and PD2 in a plan view. The second pads PD2 may be closer to the edge E-DP of the first display substrate 100 than the first pads PD1.

[0092] In a plan view, the edge of the second pad PD2 may be aligned with the edge E-DP of the first display substrate 100. This may be because during the manufacturing of the display panel DP, the side surface of the first display substrate 100 is polished or ground to expose the side surface of the second pad PD2.

[0093] The size and shape of the first connection circuit board FPCB1 may be partially different from the size and shape of the second connection circuit board FPCB2. However, the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may have structures very similar to each other. Figure 4B 2A and 2B illustrate the first connection circuit board FPCB1 as an example. Hereinafter, the first connection circuit board FPCB1 will be mainly described.

[0094] The first connection circuit board FPCB1 may include an insulating layer, a plurality of pads CPD, PO and PI, and a plurality of signal lines SL-F. The plurality of pads CPD, PO and PI and the plurality of signal lines SL-F may be disposed on the insulating layer. The insulating layer may include a polyimide layer.

[0095] The plurality of pads CPD, PO and PI may include a connection pad CPD connected to a connection terminal of a driving chip DC, a first pad (hereinafter referred to as an output pad) PO connected to a display panel DP, and a second pad (hereinafter referred to as an input pad) PI connected to a main circuit board MPCB. The plurality of signal lines SL-F may connect the connection pad CPD and the output pad PO, and may connect the connection pad CPD and the input pad PI. When the driving chip DC is omitted, the signal line SL-F may connect the output pad PO and the input pad PI.

[0096] The plurality of pads CPD, PO, and PI of the first connection circuit board FPCB1 may be exposed to the outside, and each of the plurality of pads CPD, PO, and PI may be connected to a corresponding signal line SL-F through a contact hole penetrating the insulating layer.

[0097] The first connection circuit board FPCB1 may include three parts divided according to the width in the first direction DR1. In detail, the first connection circuit board FPCB1 may include: a first part P1 on which the output pad PO is provided, a second part P2 on which the input pad PI is provided, and a third part P3 connecting the first part P1 and the second part P2. The width of the first part P1 may be greater than the width of the second part P2. The width of the third part P3 may gradually decrease from the first part P1 toward the second part P2. The driving chip DC may be mounted on the second part P2.

[0098] All of the output pads PO, the input pads PI, and the connection pads CPD of the first connection circuit board FPCB1 may be exposed to the outside at the rear surface of the first connection circuit board FPCB1. Figure 4A The output pads PO of the second connection circuit board FPCB2 can be exposed to the outside at the front surface of the second connection circuit board FPCB2, and the input pads PI and the connection pads CPD of the second connection circuit board FPCB2 can be exposed to the outside at the rear surface of the second connection circuit board FPCB2. Figure 4A As shown in FIG. 1 , the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may be coupled to the same surface of the main circuit board MPCB. However, the coupling structure of the first connection circuit board FPCB1 and the second connection circuit board FPCB2 and the main circuit board MPCB is not limited thereto.

[0099] like Figure 4A and Figure 4C As shown in FIG. 1 , the first connection circuit board FPCB1 and the second connection circuit board FPCB2 disposed in one bonding area BDA may partially overlap each other in a plan view. However, the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may be bonded to different surfaces of the first display substrate 100, and thus physical interference of the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may be minimized.

[0100] Since each of the first connection circuit board FPCB1 and the second connection circuit board FPCB2 has a shape including regions (or portions) having different widths, regions (eg, Figure 4B The second portions P2 of the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may not overlap each other in a plan view. Therefore, physical interference of the first connection circuit board FPCB1 and the second connection circuit board FPCB2 may be minimized.

[0101] Figure 4D yes Figure 4CA magnified view of area "AA". Figure 4D FIG. 4 shows a first connection circuit board FPCB1 including a first insulating layer IL-F1, a signal line SL-F, a second insulating layer IL-F2 and an output pad PO as an example. Figure 4D As shown in FIG. 1 , the first pad PD1 may be exposed from the first insulating layer 10 to the fourth insulating layer 40 and may be connected to the signal line. The first pad PD1 connected to the first auxiliary signal line PL-D1 through the contact hole CH-P penetrating the first insulating layer 10 to the fourth insulating layer 40 is shown as an example. The first pad PD1 may include silver (Ag), copper (Cu), gold (Au), or aluminum (Al).

[0102] The first pad PD1 may be electrically connected to the output pad PO through the anisotropic conductive film ACF. In another exemplary embodiment, the first pad PD1 may be omitted. In this case, the anisotropic conductive film ACF may be directly connected to the first auxiliary signal line PL-D1.

[0103] Figure 4E yes Figure 4C A magnified view of the area "BB". Figure 4E FIG. 4 shows, as an example, a second connection circuit board FPCB2 including a first insulating layer IL-F1, a signal line SL-F, a second insulating layer IL-F2 and an output pad PO. Figure 4E As shown in , the second pad PD2 may be connected to the side surface of the signal line and may be disposed on the side surface BS1-SS and the bottom surface BS1-LS of the first base layer BS1. Figure 4E 2. In other words, the second pad PD2 may be connected to the side surface PL-SS of the second auxiliary signal line PL-D2.

[0104] The anisotropic conductive film ACF may be bonded to a portion of the second pad PD2 disposed on the bottom surface BS1 -LS of the first base layer BS1 .

[0105] The side surface PL-SS of the second auxiliary signal line PL-D2 may be substantially aligned with the side surface BS1-SS of the first base layer BS1. The side surface PL-SS of the second auxiliary signal line PL-D2 may be substantially aligned with the side surfaces of the first to fourth insulating layers 10 to 40. As a representative of the side surfaces of the insulating layers 10 to 40, the reference numeral 20-SS of the side surface of the second insulating layer 20 is shown.

[0106] In another exemplary embodiment, a side surface of at least one of the first to fourth insulating layers 10 to 40 (e.g., an organic insulating layer) may not be aligned with side surfaces of other insulating layers of the first to fourth insulating layers 10 to 40. In other words, side surfaces of all insulating layers may not necessarily be aligned with each other.

[0107] like Figure 4F As shown in , a plurality of second pads PD2 may be spaced apart from each other by a predetermined distance on the side surface 100-SS of the first display substrate 100. A metal paste may be printed on the side surface 100-SS and the bottom surface of the first display substrate 100, and then patterned to form a plurality of second pads PD2. The printing and patterning process of the metal paste is not limited to a specific process. The metal paste may be a silver paste.

[0108] Reference Figure 4D and Figure 4E , in a region where the insulating layer (e.g., the fourth insulating layer 40) overlaps the first connection circuit board FPCB1, the first auxiliary signal line PL-D1 may be partially exposed from the fourth insulating layer 40 through the contact hole CH-P, but the second auxiliary signal line PL-D2 may not be exposed from the fourth insulating layer 40. In the bonding area BDA, one pad area may be defined in the top surface of the first display substrate 100, and another pad area may be defined in the bottom surface of the first display substrate 100.

[0109] Figure 5 is a cross-sectional view illustrating a method of manufacturing a display device DD according to an exemplary embodiment of the inventive concept.

[0110] A display panel DP including a first pad PD1 and a second pad PD2 may be provided. In addition, an anisotropic conductive film ACF and a first connection circuit board FPCB1 and a second connection circuit board FPCB2 may be provided. One of the anisotropic conductive films ACF may be disposed between the first connection circuit board FPCB1 and the first pad PD1, and the other of the anisotropic conductive films ACF may be disposed between the second connection circuit board FPCB2 and the second pad PD2.

[0111] One anisotropic conductive film ACF may be preliminarily bonded to the first pad PD1 or the first connection circuit board FPCB1. Another anisotropic conductive film ACF may be preliminarily bonded to the second pad PD2 or the second connection circuit board FPCB2.

[0112] The first connection circuit board FPCB1 and / or the second connection circuit board FPCB2 may be pressed by the heating block HB. Figure 52 shows two heating blocks HB disposed above and below the display panel DP as an example. The heating block HB may be an extrusion member capable of generating heat, and is not limited to a specific kind. One anisotropic conductive film ACF subjected to thermal extrusion may electrically connect the first pad PD1 to the output pad PO. Another anisotropic conductive film ACF subjected to thermal extrusion may electrically connect the second pad PD2 to the output pad PO.

[0113] Fig. 6A is an enlarged plan view illustrating a display device DD according to an exemplary embodiment of the inventive concept. Figure 6B FIG. 2 is a diagram showing a display device DD according to an exemplary embodiment of the present inventive concept. Fig. 6A A cross-sectional view taken along line II'.

[0114] like Fig. 6A and Figure 6B As shown in FIG. 1 , the display device DD may further include a sealing member SM that seals the first connection circuit board FPCB1 and the insulating layer (eg, Figure 6B The sealing member SM may overlap a portion of an edge of the first connection circuit board FPCB1 that overlaps with the first display substrate 100.

[0115] The sealing member SM may include a synthetic resin. For example, the sealing member SM may include a silicone resin having high resistance to water or moisture. The liquid synthetic resin may be provided to the portion of the edge of the first connection circuit board FPCB1, and thus the liquid synthetic resin may move to the first connection circuit board FPCB1 and the insulating layer (e.g., Figure 6B The liquid synthetic resin may be hardened to form a sealing member SM.

[0116] The display device DD may further include a sealing member sealing a gap between the second connection circuit board FPCB2 and the bottom surface of the first base layer BS1.

[0117] According to an exemplary embodiment of the inventive concept, the first pad and the second pad may be disposed on different surfaces, and thus the plane area or size of the bonding region may be reduced. Thus, a slim bezel region may be provided.

[0118] Since the first pad and the second pad are respectively bonded to the first connection circuit board and the second connection circuit board on different surfaces of the display substrate, interference between the first connection circuit board and the second connection circuit board can be reduced or minimized. Since the first connection circuit board and the second connection circuit board are not directly stacked, physical interference between the first connection circuit board and the second connection circuit board can be reduced or minimized. Therefore, the bonding strength between the connection circuit board and the pad can be increased, and the gap between the connection circuit board and the pad can be reduced.

[0119] Although specific exemplary embodiments and examples have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: A display substrate, comprising a base layer, an insulating layer, a first signal line and a second signal line, wherein the insulating layer is disposed on the base layer, the first signal line is disposed on the base layer, and the second signal line is disposed on the base layer; a first pad and a second pad, the first pad being exposed from the insulating layer and connected to the first signal line, the second pad being connected to a side surface of the second signal line, wherein the first pad is disposed on a top surface of a first side portion of the display substrate, and the second pad is disposed on a side surface and a bottom surface of the first side portion of the display substrate; Main circuit board; a first connecting circuit board, electrically connecting the first pad and the main circuit board; and a second connecting circuit board, electrically connecting the second solder pad and the main circuit board; Wherein, the first connection circuit board is bonded to the first pad on the top surface of the display substrate, and the second connection circuit board is bonded to the second pad on the bottom surface of the display substrate.

2. The display device according to claim 1, wherein: The side surface of the second signal line is aligned with the side surface of the base layer.

3. The display device according to claim 1, wherein: The side surface of the second signal line is aligned with a side surface of the insulating layer.

4. The display device according to claim 1, wherein: The first pad is connected to the first signal line through a contact hole penetrating the insulating layer.

5. The display device according to claim 1, wherein: The first pad is spaced apart from an edge of the insulating layer.

6. The display device according to claim 1, wherein: The first signal line and the second signal line are provided on the same layer.

7. The display device according to claim 1, wherein: The second pad includes metal paste.

8. The display device according to claim 7, wherein: The first pad includes silver, copper, gold or aluminum.

9. The display device according to claim 1, wherein: The first connection circuit board and the second connection circuit board are bonded to the same surface of the main circuit board.

10. The display device according to claim 1, further comprising: A driving chip is mounted on each of the first connection circuit board and the second connection circuit board.

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