Display panel

Abstract

The present application provides a display panel, which includes a first transistor, a capacitor, a light-emitting element, and an additional control electrode. Among them, the first transistor contains an oxide, the capacitor includes a first electrode and a second electrode, the light-emitting element is connected to the capacitor and the first transistor, and the additional control electrode is connected to the second electrode. The first electrode and the second electrode are disposed on different layers from each other and are respectively coupled to the first control electrode and the first output electrode of the first transistor, and the light-emitting element includes a light-emitting layer. When observed in a plan view, the additional control electrode overlaps with the first control electrode and the first semiconductor pattern. The additional control electrode and the second electrode are disposed on the same layer and are formed integrally.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0016279, filed with the Korean Intellectual Property Office on February 12, 2019, the content of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure relate to a display panel, and more particularly, to a display panel having improved electrical properties. Background art

[0004] A display panel includes a plurality of pixels that display an image. Each of the pixels includes a pixel driving circuit and a display element connected to the pixel driving circuit. The pixel driving circuit includes at least one thin - film transistor and a capacitor. The thin - film transistor and the capacitor control the display element in response to an electrical signal received from the pixel driving circuit, wherein the thin - film transistor and the capacitor constitute the pixel driving circuit. Summary of the invention

[0005] Embodiments of the inventive concept provide a display panel having improved electrical properties and display characteristics.

[0006] Embodiments of the inventive concept provide a display panel manufactured through a simplified process.

[0007] According to an embodiment of the inventive concept, a display panel includes a first transistor, a capacitor, a light - emitting element, and an additional control electrode. The first transistor includes a first semiconductor pattern including an oxide, a first control electrode overlapping the first semiconductor pattern, and a first input electrode and a first output electrode disposed on different layers from the first control electrode and respectively connected to two different portions of the first semiconductor pattern. The capacitor includes a first electrode connected to the first control electrode and a second electrode disposed on a different layer from the first electrode and connected to the first output electrode. The light - emitting element is connected to the capacitor and the first transistor and includes a light - emitting layer. The additional control electrode is connected to the second electrode and overlaps the first control electrode and the first semiconductor pattern in a plan view. The additional control electrode and the second electrode are disposed on the same layer to form an integral body.

[0008] In an embodiment, when observed in a cross - sectional view, the first semiconductor pattern is disposed between the additional control electrode and the first control electrode, and the additional control electrode is disposed below the first semiconductor pattern.

[0009] In an embodiment, when observed in a plan view, the additional control electrode overlaps the channel region of the first semiconductor pattern.

[0010] In an embodiment, the display panel further includes a first metal pattern spaced apart from the first semiconductor pattern and forming a first capacitor together with the first input electrode. The first metal pattern and the second electrode are disposed on the same layer.

[0011] In an embodiment, the first metal pattern and the second electrode are connected to each other and form an integral body.

[0012] In an embodiment, the first metal pattern and the additional control electrode are connected to each other and form an integral body.

[0013] In an embodiment, the first input electrode receives a power supply voltage higher than the cathode voltage of the light-emitting element.

[0014] In an embodiment, the first capacitor has a capacitance determined by a potential difference between the anode voltage of the light-emitting element and the power supply voltage.

[0015] In an embodiment, the display panel further includes a second metal pattern spaced apart from the first semiconductor pattern and forming a second capacitor together with the first control electrode. The second metal pattern and the second electrode are disposed on the same layer.

[0016] In an embodiment, the second metal pattern and the second electrode are connected to each other and form an integral body.

[0017] In an embodiment, the display panel further includes a second transistor and a third transistor. The second transistor includes a second semiconductor pattern containing silicon, a second control electrode overlapping the second semiconductor pattern, and a second input electrode and a second output electrode respectively connected to two different portions of the second semiconductor pattern. The third transistor includes a third semiconductor pattern containing silicon and spaced apart from the second semiconductor pattern, a third control electrode overlapping the third semiconductor pattern, and a third input electrode and a third output electrode respectively connected to two different portions of the third semiconductor pattern. The second output electrode is connected to the first electrode, and the third output electrode is connected to the second electrode.

[0018] In an embodiment, the display panel further includes an upper electrode disposed on the second control electrode and overlapping the second control electrode in a plan view. The second control electrode and the first electrode are disposed on the same layer, and the upper electrode and the second electrode are disposed on the same layer.

[0019] According to an embodiment of the inventive concept, a display panel includes a first transistor, a first capacitor, and a light-emitting element. The first transistor includes a first semiconductor pattern including an oxide, a first control electrode overlapping a channel region of the first semiconductor pattern, a first input electrode connected to an input region of the first semiconductor pattern, and a first output electrode connected to an output region of the first semiconductor pattern. The first capacitor is connected to the first transistor. The first capacitor includes a first electrode and a second electrode facing each other. The light-emitting element is connected to the second electrode. The light-emitting element includes a light-emitting layer. When observed in a plan view, the second electrode includes a first portion overlapping the first electrode and a second portion overlapping the channel region of the first semiconductor pattern.

[0020] In an embodiment, the first output electrode is connected to the second electrode.

[0021] In an embodiment, the second electrode further includes a third portion connected to the second portion. When observed in a plan view, the third portion is spaced apart from the first semiconductor pattern and overlaps the first input electrode.

[0022] In an embodiment, the second electrode further includes a fourth portion connected to the second portion. When observed in a plan view, the fourth portion is spaced apart from the first semiconductor pattern and overlaps the first control electrode.

[0023] In an embodiment, the display panel further includes a second transistor. The second transistor includes a second semiconductor pattern including silicon, a second control electrode overlapping the second semiconductor pattern, and a second input electrode and a second output electrode respectively connected to two different portions of the second semiconductor pattern. The second output electrode is connected to the first electrode.

[0024] In an embodiment, the second control electrode and the first electrode are disposed on the same layer.

[0025] In an embodiment, the display panel further includes a third transistor. The third transistor includes a third semiconductor pattern including silicon and spaced apart from the second semiconductor pattern, a third control electrode overlapping the third semiconductor pattern, and a third input electrode and a third output electrode respectively connected to two different portions of the third semiconductor pattern. The third output electrode is connected to the second electrode.

[0026] According to an embodiment of the inventive concept, a display panel includes a first transistor, a capacitor, and an additional control electrode. The first transistor includes a first semiconductor pattern including an oxide, a first control electrode overlapping the first semiconductor pattern, and a first input electrode and a first output electrode disposed on a layer different from the first control electrode and respectively connected to two different portions of the first semiconductor pattern. The capacitor includes a first electrode connected to the first control electrode and a second electrode disposed on a layer different from the first electrode and connected to the first output electrode. The additional control electrode is connected to the second electrode and overlaps the first control electrode and the first semiconductor pattern in a plan view. The additional control electrode and the second electrode are disposed on the same layer and formed integrally. When observed in a cross-sectional view, the first semiconductor pattern is disposed between the additional control electrode and the first control electrode, and the additional control electrode is disposed below the first semiconductor pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram of a display device according to an embodiment of the inventive concept.

[0028] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept.

[0029] Figure 3A is a plan view of some elements of a pixel according to an embodiment of the inventive concept.

[0030] Figure 3B is Figure 3A a cross-sectional view of some elements shown in

[0031] Figure 4A is a plan view of some elements of a pixel according to an embodiment of the inventive concept.

[0032] Figure 4B is Figure 4A a cross-sectional view of some elements shown in

[0033] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept.

[0034] Figure 6A is a plan view of some elements of a pixel according to an embodiment of the inventive concept.

[0035] Figure 6B is Figure 6A a cross-sectional view of some elements shown in

[0036] Figure 7 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept.

[0037] Figure 8AIt is a plan view of some elements of a pixel according to an embodiment of the inventive concept.

[0038] Figure 8B is Figure 8A a cross-sectional view of some elements shown in

[0039] Figure 9 It is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept.

[0040] Figure 10A It is a plan view of some elements of a pixel according to an embodiment of the inventive concept.

[0041] Figure 10B is Figure 10A a cross-sectional view of some elements shown in

[0042] However, it should be noted that these drawings are not to scale and may not accurately reflect the exact structure or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by the exemplary embodiments. The use of like or identical reference numerals in the various drawings may indicate the presence of like or identical elements or features. Detailed Description

[0043] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which the exemplary embodiments are shown. However, the exemplary embodiments of the inventive concept may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the thickness of layers and regions may be exaggerated for clarity. In the drawings, like reference numerals may represent like elements and thus their description will be omitted.

[0044] It should be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. The same numerals always refer to the same elements.

[0045] It should also be understood that the terms "comprises", "comprising", "includes" and / or "including", if used herein, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0046] Exemplary embodiments of the inventive concept are described with reference to cross-sectional views, which are schematic views of intermediate structures between idealized and exemplary embodiments. Thus, variations from the illustrated shape due to, for example, manufacturing methods and / or tolerances are to be envisioned. Accordingly, exemplary embodiments of the inventive concept should not be construed as limited to the specific region shapes illustrated herein, but include, for example, shape deviations due to manufacturing.

[0047] Figure 1 is a block diagram of a display device SD according to an embodiment of the inventive concept.

[0048] As Figure 1 shown, according to an embodiment, the display device SD includes a signal controller 100, a scan driver 200, a data driver 300, and a display panel DP. The display panel DP displays an image based on the electrical signals provided thereto.

[0049] According to an embodiment, the signal controller 100 receives an input image signal and converts the input image signal into image data RGB having a data format suitable for the scan driver 200. The signal controller 100 outputs the image data RGB and various control signals DCS and SCS.

[0050] According to an embodiment, the scan driver 200 receives a scan control signal SCS from the signal controller 100. The scan control signal SCS includes a vertical start signal, a clock signal, etc., where the vertical start signal is used for the initialization operation of the scan driver 200, and the clock signal is used to determine when the signal is output.

[0051] According to an embodiment, the scan driver 200 generates a plurality of scan signals and sequentially outputs the scan signals to a plurality of scan lines SL1 - SLn. In addition, the scan driver 200 generates a plurality of emission control signals in response to the scan control signal SCS and outputs the emission control signals to a plurality of emission lines SSL1 - SSLn.

[0052] Figure 1 An embodiment is shown in which the scan signal and the emission control signal are output from one scan driver 200, but embodiments of the inventive concept are not limited thereto. In an embodiment, a plurality of scan driving circuits are provided to output separate scan signals and separate emission control signals. In addition, in an embodiment, the driving circuit that generates and outputs the scan signal is independent of the driving circuit that generates and outputs the emission control signal.

[0053] According to an embodiment, the data driver 300 receives a data control signal DCS and image data RGB from the signal controller 100. The data driver 300 converts the image data RGB into a data signal and outputs the data signal to data lines DL1-DLm. The data signal is an analog voltage whose level corresponds to the gray level of the image data RGB.

[0054] According to an embodiment, the display panel DP includes scan lines SL1-SLn, emission lines SSL1-SSLn, data lines DL1-DLm, and a plurality of pixels PX. The scan lines SL1-SLn extend in a first direction DR1 and are spaced apart in a second direction DR2 perpendicular to the first direction DR1.

[0055] According to an embodiment, each of the emission lines SSL1-SSLn is parallel to a corresponding one of the scan lines SL1-SLn. The data lines DL1-DLm cross the scan lines SL1-SLn and are electrically insulated from the scan lines SL1-SLn.

[0056] According to an embodiment, each of the pixels PX is connected to a corresponding one of the scan lines SL1-SLn, a corresponding one of the emission lines SSL1-SSLn, and a corresponding one of the data lines DL1-DLm.

[0057] According to an embodiment, each of the pixels PX receives a first power supply voltage VDD and a second power supply voltage VSS lower than the first power supply voltage VDD. Each of the pixels PX is connected to a power line PL on which the first power supply voltage VDD is transmitted. Each of the pixels PX is connected to an initialization line RL that transmits an initialization voltage Vint.

[0058] According to an embodiment, each of the pixels PX is electrically connected to one scan line and two emission lines. For example, as Figure 1 shown, each of the pixels PX in the second pixel row is connected to the second scan line SL2 and the first emission line SSL1 and the second emission line SSL2.

[0059] According to an embodiment, the display panel DP further includes a plurality of dummy scan lines. The display panel DP further includes dummy scan lines connected to the pixels PX of the first pixel row and dummy scan lines connected to the pixels PX of the nth pixel row. In addition, some of the pixels PX in a pixel column connected to one of the data lines DL1-DLm are connected to each other through the power line PL. Two adjacent pixels PX in a pixel column are electrically connected to each other through one emission line.

[0060] According to an embodiment, each of the pixels PX includes an organic light-emitting element and a pixel driving circuit that controls a light-emitting operation of the organic light-emitting element. The pixel driving circuit includes a plurality of thin-film transistors and at least one capacitor. At least one of the scan driver 200 and the data driver 300 includes a thin-film transistor formed by the same process as the pixel driving circuit.

[0061] In the present embodiment, the scan lines SL1-SLn, the emission lines SSL1-SSLn, the data lines DL1-DLm, the power line PL, the initialization line RL, the pixels PX, the scan driver 200, and the data driver 300 are formed on a single base substrate through a plurality of photolithography processes. However, the embodiment of the inventive concept is not limited to this example, and in the embodiment, the scan driver 200 or the data driver 300 may be mounted on an additional circuit substrate or the like, and then electrically connected to the display panel DP through an adhesion process.

[0062] Figure 2 is an equivalent circuit diagram of the pixel PX according to an embodiment of the inventive concept. Figure 3A is a plan view of some elements of the pixel PX according to an embodiment of the inventive concept. Figure 3B is Figure 3A a cross-sectional view of some elements shown in Figure 2 illustrates an example of a driving circuit of each pixel PX that is connected to one of the data lines DL1-DLm (hereinafter, the data line DL), connected to a corresponding one of the scan lines SL1-SLn (hereinafter, the scan line SL), and connected to a corresponding one of the emission lines SSL1-SSLn (hereinafter, the emission line SSL).

[0063] In the present embodiment, the power line PL includes a horizontal power line PL_H and a vertical power line PL_V. The horizontal power line PL_H extends parallel to the scan line SL, and the vertical power line PL_V extends parallel to the data line DL. The horizontal power line PL_H and the vertical power line PL_V are coupled to each other to transmit substantially the same power supply voltage.

[0064] For ease of explanation, the light-emitting element ELD shown in Figure 3A is omitted from Figure 2 and the first transistor T1 and the second transistor T2 are shown briefly or partially in Figure 3B Hereinafter, embodiments of the inventive concept will be described with reference to Figure 2 、 Figure 3A and Figure 3B

[0065] Refer to Figure 2, a pixel driving circuit according to an embodiment of the inventive concept includes three thin film transistors T1, T2, and T3 and a capacitor C ST . Hereinafter, it will be assumed that each of the three thin film transistors T1, T2, and T3 is an n-type thin film transistor. However, Figure 2 the embodiment of the pixel driving circuit is not limited thereto, and the structure of the pixel driving circuit may be differently modified in other embodiments.

[0066] According to an embodiment, the first transistor T1 is connected to a power line PL and a light emitting element ELD. The first transistor T1 is a driving transistor that provides a driving current to the light emitting element ELD.

[0067] According to an embodiment, the second transistor T2 is connected to a scan line SL, a data line DL, the first transistor T1, and the capacitor C ST . The second transistor T2 is turned on by a scan signal received through the scan line SL and then transfers the voltage of the data line DL to the capacitor C ST and the first transistor T1. The voltage output from the second transistor T2 controls the amount of charge stored in the capacitor C ST and controls the on / off state of the first transistor T1. In the present embodiment, the second transistor T2 is a switching transistor that controls the on / off state of the pixel PX.

[0068] According to an embodiment, the third transistor T3 is connected to an initialization line RL and an emission line SSL. The third transistor T3 is turned on by an emission control signal received through the emission line SSL and then transfers the initialization voltage Vint received through the initialization line RL to the capacitor C ST . The third transistor T3 controls the non-emission period of the pixel PX, for example, the sensing period.

[0069] According to an embodiment, the capacitor C ST includes a first electrode E1 connected to the third transistor T3 and a second electrode E2 connected to the first transistor T1 and the second transistor T2. The capacitor C ST is charged to store an amount of charge corresponding to the potential difference between the voltage output from the second transistor T2 and the voltage output from the third transistor T3 or the potential difference between the voltage output from the second transistor T2 and the voltage output from the first transistor T1. The on-period of the first transistor T1 is controlled by the capacitor C ST and affects the length of the light emitting period or the sensing period of the light emitting element ELD.

[0070] According to an embodiment, the light emitting element ELD is connected to the third transistor T3, the first transistor T1, and the capacitor C ST . The light emitting element ELD includes a connection to the capacitor CST one electrode, another electrode receiving a second power supply voltage VSS, and a light-emitting layer between the two electrodes. In the light-emitting device ELD, a potential difference between the two electrodes excites the light-emitting layer and generates light.

[0071] According to an embodiment, the light-emitting layer includes an organic material or an inorganic material. For example, the light-emitting layer includes a fluorescent organic layer or a phosphorescent organic layer. In an embodiment, the light-emitting layer includes a dye or a pigment. In an embodiment, the light-emitting layer includes an inorganic light-emitting layer including quantum dots.

[0072] According to an embodiment of the inventive concept, the first transistor T1 further includes an additional control electrode SC. The additional control electrode SC is electrically connected to an output node ND, to which an output terminal of the first transistor T1 and an output terminal of the third transistor T3 are connected. Accordingly, an on / off state of the first transistor T1 is controlled by a voltage output from the second transistor T2 and a voltage output from the third transistor T3.

[0073] Reference Figure 3A and Figure 3B , according to an embodiment, in addition to the pixel PX, the display panel DP further includes a base substrate BS and a plurality of insulating layers 10, 20, 30, 40, and 50. For simplicity of explanation, the light-emitting device ELD and the insulating layers 10, 20, 30, 40, and 50 are omitted from Figure 3A and the first transistor T1 and the second transistor T2 are briefly or partially shown in Figure 3B . Hereinafter, embodiments of the inventive concept will be described in more detail with reference to Figure 3A and Figure 3B .

[0074] According to an embodiment, the second transistor T2 includes second semiconductor patterns SP21 and SP22, a second control electrode CE2, a second input electrode IE2, and a second output electrode OE2. In the present embodiment, the second semiconductor patterns SP21 and SP22 are shown as two patterns spaced apart from each other.

[0075] However, embodiments of the inventive concept are not limited to this example, and in other embodiments, the second semiconductor patterns SP21 and SP22 may be provided as a single pattern or three or more patterns. For simplicity of explanation, one of the plurality of semiconductor patterns SP21 and SP22 (hereinafter, the second semiconductor pattern SP2) is exemplarily shown in Figure 3B .

[0076] According to an embodiment, the second semiconductor pattern SP2 is disposed above the base substrate BS. The base substrate BS may be one of a silicon substrate, a plastic substrate, a glass substrate, and an insulating film, but embodiments of the inventive concept are not limited to these examples.

[0077] In the present embodiment, a second semiconductor pattern SP2 is disposed on a first insulating layer 10, and the first insulating layer 10 is disposed on a base substrate BS. The first insulating layer 10 may include an organic material or an inorganic material. The first insulating layer 10 may include a buffer layer or a barrier layer and may have a single-layer or multi-layer structure.

[0078] According to an embodiment, the second semiconductor pattern SP2 includes a crystalline semiconductor material. For example, the second semiconductor pattern SP2 includes a polycrystalline semiconductor material, such as polysilicon.

[0079] According to an embodiment, the second semiconductor pattern SP2 includes a channel region A21, an input region A22, and an output region A23. The channel region A21 of the second semiconductor pattern SP2 overlaps with a second control electrode CE2.

[0080] According to an embodiment, the second control electrode CE2 is disposed on a second insulating layer 20. The second insulating layer 20 is disposed on the first insulating layer 10 and covers the second semiconductor pattern SP2. The second insulating layer 20 may include an organic layer or an inorganic layer. In the present embodiment, the second insulating layer 20 is formed of or includes at least one of silicon oxide, silicon nitride, or any combination thereof, but embodiments of the inventive concept are not limited to these examples.

[0081] According to an embodiment, the second control electrode CE2 receives a gate signal through a scan line SL. In the present embodiment, the second control electrode CE2 is disposed on a layer different from the scan line SL. Accordingly, the second control electrode CE2 is connected to the scan line SL through a connection pattern PP.

[0082] According to an embodiment, the scan line SL is disposed between a third insulating layer 30 and a fourth insulating layer 40, and the connection pattern PP is disposed on a fifth insulating layer 50. As Figure 3A shown, the connection pattern PP extending in a second direction DR2 penetrates at least a portion of the insulating layers 30, 40, and 50 and is coupled to the second control electrode CE2 and the scan line SL.

[0083] According to an embodiment, a second input electrode IE2 is disposed on the fifth insulating layer 50. The second input electrode IE2 penetrates the fifth insulating layer 50, the fourth insulating layer 40, the third insulating layer 30, and the second insulating layer 20 and is coupled to the input region A22 of the second semiconductor pattern SP2. In the present embodiment, the second input electrode IE2 corresponds to a portion of a data line DL, and the portion of the data line DL is coupled to the second semiconductor patterns SP21 and SP22. Accordingly, the second input electrode IE2 receives a data voltage through the data line DL.

[0084] According to an embodiment, the second output electrode OE2 is disposed on the fifth insulating layer 50. The second output electrode OE2 is spaced apart from the second input electrode IE2, penetrates through the fifth insulating layer 50, the fourth insulating layer 40, the third insulating layer 30, and the second insulating layer 20, and is coupled to the output region A23 of the second semiconductor pattern SP2. In the present embodiment, the second output electrode OE2 is connected to the capacitor C ST . The second output electrode OE2 is coupled to the capacitor C ST 's first electrode E1.

[0085] According to an embodiment, the first transistor T1 includes first semiconductor patterns SP11 and SP12, a first control electrode CE1, a first input electrode IE1, and a first output electrode OE1. In the present embodiment, the first semiconductor patterns SP11 and SP12 are shown as two patterns spaced apart from each other.

[0086] However, embodiments of the inventive concept are not limited to this example, and in other embodiments, the first semiconductor patterns SP11 and SP12 may be provided as a single pattern or three or more patterns. For simplicity of explanation, in Figure 3B one of the plurality of semiconductor patterns SP11 and SP12 is exemplarily shown (hereinafter, the first semiconductor pattern SP1).

[0087] According to an embodiment, the first semiconductor pattern SP1 is disposed on a layer different from the second semiconductor pattern SP2. In the present embodiment, as shown, the first semiconductor pattern SP1 is disposed between the fourth insulating layer 40 and the fifth insulating layer 50.

[0088] According to an embodiment, the first semiconductor pattern SP1 includes a semiconductor material. In the present embodiment, the first semiconductor pattern SP1 includes an oxide semiconductor. For example, the oxide semiconductor may include a metal oxide whose metal element is at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or may include a mixture of zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides.

[0089] According to an embodiment, the first semiconductor pattern SP1 includes a channel region A11, an input region A12, and an output region A13. The channel region A11 of the first semiconductor pattern SP1 overlaps with the first control electrode CE1.

[0090] According to an embodiment, the first control electrode CE1 is disposed over the first semiconductor pattern SP1. In the present embodiment, the first control electrode CE1 is disposed on the insulating pattern IP. The insulating pattern IP is disposed on the first semiconductor pattern SP1 and under the first control electrode CE1, covering the channel region A11 and exposing the input region A12 and the output region A13. However, embodiments of the inventive concept are not limited to this example, and in other embodiments, the insulating pattern IP is provided as an insulating layer formed on substantially the entire top surface of the fourth insulating layer 40.

[0091] According to an embodiment, when observed in a plan view, the first control electrode CE1 extends in a direction intersecting and overlapping the first semiconductor patterns SP11 and SP12. The first control electrode CE1 is connected to the capacitor C ST . In the present embodiment, the first control electrode CE1 is coupled to the capacitor C ST 's first electrode E1. The first control electrode CE1 is controlled by a signal received from the second transistor T2 through the first electrode E1.

[0092] According to an embodiment, the first input electrode IE1 and the first output electrode OE1 are disposed on the fifth insulating layer 50. The first input electrode IE1 and the first output electrode OE1 penetrate the fifth insulating layer 50 and are respectively connected to the input region A12 and the output region A13 of the first semiconductor pattern SP1.

[0093] In the present embodiment, the first input electrode IE1 corresponds to a part of the vertical power line PL_V, and the part of the vertical power line PL_V is coupled to parts of the first semiconductor patterns SP11 and SP12. The vertical power line PL_V is disposed on the same layer as the data line DL and is disposed on the fifth insulating layer 50.

[0094] According to an embodiment, the first input electrode IE1 receives the first power supply voltage VDD through the vertical power line PL_V. However, embodiments of the inventive concept are not limited to this example, and in other embodiments, the first input electrode IE1 is a separate pattern disposed on a layer different from the vertical power line PL_V, penetrates the insulating layer, and is coupled to the vertical power line PL_V.

[0095] According to an embodiment, the first output electrode OE1 is connected to the capacitor C ST . In the present embodiment, the first output electrode OE1 is coupled to the capacitor C ST 's second electrode E2. The first output electrode OE1 is disposed on a layer different from the second electrode E2 and is coupled to the second electrode E2 through a contact hole.

[0096] According to an embodiment, the third transistor T3 includes third semiconductor patterns SP31 and SP32, a third control electrode CE3, a third input electrode IE3, and a third output electrode OE3. In the present embodiment, the third semiconductor patterns SP31 and SP32 are shown as two patterns spaced apart from each other. However, embodiments of the inventive concept are not limited to this example, and in other embodiments, the third semiconductor patterns SP31 and SP32 may be provided as a single pattern or three or more patterns.

[0097] According to an embodiment, the third semiconductor patterns SP31 and SP32 include a crystalline semiconductor material. For example, the third semiconductor patterns SP31 and SP32 include a polycrystalline semiconductor material, such as polysilicon. The third semiconductor patterns SP31 and SP32 are disposed on the same layer as the second semiconductor pattern SP2 and are formed of the same material as the second semiconductor pattern SP2. Accordingly, the third semiconductor patterns SP31 and SP32 and the second semiconductor pattern SP2 can be formed simultaneously using a single mask. However, embodiments of the inventive concept are not limited to this example, and in other embodiments, the third semiconductor patterns SP31 and SP32 may be disposed on a different layer from the second semiconductor pattern SP2 or may be formed of a material different from that of the second semiconductor pattern SP2.

[0098] According to an embodiment, when observed in a plan view, the third control electrode CE3 extends in a direction intersecting and overlapping the third semiconductor patterns SP31 and SP32. A channel region overlapping the third control electrode CE3 is formed in each of the third semiconductor patterns SP31 and SP32.

[0099] According to an embodiment, the third control electrode CE3 is connected to the emission line SSL. Accordingly, the on / off state of the third transistor T3 is controlled by a signal received from the emission line SSL.

[0100] In the present embodiment, the third control electrode CE3 is disposed on a different layer from the emission line SSL. For example, the third control electrode CE3 is disposed on the same layer as the first electrode E1 and the emission line SSL is disposed on the same layer as the second electrode E2. Accordingly, the third control electrode CE3 is coupled to the emission line SSL through a contact hole.

[0101] According to an embodiment, the third input electrode IE3 is coupled to portions of the third semiconductor patterns SP31 and SP32. The third input electrode IE3 is coupled to the initialization line RL. Accordingly, the third input electrode IE3 receives an initialization voltage through the initialization line RL.

[0102] In the present embodiment, the third input electrode IE3 is provided on a layer different from the initialization line RL. For example, the third input electrode IE3 is provided on the same layer as the data line DL, and the initialization line RL is provided on the same layer as the second electrode E2. Therefore, the third input electrode IE3 is coupled to the initialization line RL through a contact hole.

[0103] According to an embodiment, the third output electrode OE3 is spaced apart from the third input electrode IE3 and coupled to other portions of the third semiconductor patterns SP31 and SP32. The third output electrode OE3 and the third input electrode IE3 are provided on the same layer.

[0104] In the present embodiment, the third output electrode OE3 and the first output electrode OE1 are provided as a single or the same pattern. However, embodiments of the inventive concept are not limited to this example, and in other embodiments, the third output electrode OE3 is formed as a separate pattern different from or independent of the first output electrode OE1, but receives the same electrical signal as the first output electrode OE1.

[0105] According to an embodiment, the third output electrode OE3 is coupled to the capacitor C ST through a contact hole to the second electrode E2 of. Therefore, the potential of the second electrode E2 of the capacitor C ST is controlled by each of the first transistor T1 and the third transistor T3.

[0106] According to an embodiment, the capacitor C ST includes a first electrode E1 and a second electrode E2 provided on different layers. As described above, the first electrode E1 is provided on the same layer as the second control electrode CE2. In other words, the first electrode E1 is provided between the second insulating layer 20 and the third insulating layer 30. In addition, the second electrode E2 is provided between the third insulating layer 30 and the fourth insulating layer 40.

[0107] According to an embodiment, the first electrode E1 is coupled to each of the first control electrode CE1 and the second output electrode OE2, and the second electrode E2 is coupled to each of the third output electrode OE3 and the first output electrode OE1. In addition, the light emitting element ELD is coupled to the capacitor C ST through a connection electrode CNE. For ease of illustration, a dashed line is used to show the position or shape of the contact hole CNT coupled to the light emitting element ELD.

[0108] In the present embodiment, when viewed in a plan view, the second electrode E2 overlaps with the first electrode E1 and the first semiconductor patterns SP11 and SP12. For simplicity of illustration, the second electrode E2 is shown as a shaded pattern. The second electrode E2 includes a first portion and a second portion, wherein the first portion overlaps with the first electrode E1 to form the capacitor CST , the second part overlaps with the first semiconductor patterns SP11 and SP12 to form an additional control electrode SC.

[0109] According to an embodiment, the second part extends in a direction parallel to a part of the first control electrode CE1 and intersects the first semiconductor patterns SP11 and SP12, and thus, the second part can serve as the additional control electrode SC. The additional control electrode SC and the second electrode E2 are disposed on the same layer. For example, the additional control electrode SC is disposed between the third insulating layer 30 and the fourth insulating layer 40.

[0110] According to an embodiment, when observed in a plan view, the additional control electrode SC overlaps at least a part of the first semiconductor pattern SP1 and overlaps the first control electrode CE1. The additional control electrode SC overlaps the channel region A11 of the first semiconductor pattern SP1. In other words, when observed in a plan view, the channel region A11 is disposed between the first control electrode CE1 and the additional control electrode SC and overlaps each of the first control electrode CE1 and the additional control electrode SC.

[0111] According to an embodiment, the additional control electrode SC is connected to the first output electrode OE1. In this embodiment, the first output electrode OE1 penetrates through the fourth insulating layer 40 and the fifth insulating layer 50 and is coupled to the additional control electrode SC. Thus, the additional control electrode SC has the same potential as the first output electrode OE1.

[0112] In this embodiment, the first part and the second part of the second electrode E2 are connected to each other and have substantially the same potential. The first part and the second part have a potential corresponding to the potential of the output node ND.

[0113] According to an embodiment of the inventive concept, since the additional control electrode SC is further disposed in the first transistor T1, the on / off state of the first transistor T1 is controlled by a voltage corresponding to the potential of the output node ND, and thus, the output synchronization of the first transistor T1 can be achieved rapidly. Accordingly, the electrical characteristics of the pixel PX can be improved.

[0114] In an embodiment, the first part and the second part of the second electrode E2 are connected to each other to form an integral body. In other words, the capacitor C ST and the additional control electrode SC are formed by the second electrode E2 substantially as a single pattern. Thus, the integration density of the pixel PX can be improved.

[0115] According to an embodiment of the inventive concept, by changing the shape of the second electrode E2, the second electrode E2 and the additional control electrode SC can be formed simultaneously using a single mask. Accordingly, an additional process of forming the additional control electrode SC can be omitted, and thus, the entire process can be simplified and the process cost can be reduced.

[0116] Figure 4A is a plan view of some elements of a pixel according to an embodiment of the inventive concept. Figure 4B is Figure 4A a cross-sectional view of some elements shown in Figure 4A shows a region corresponding to Figure 3A and Figure 4B shows a region corresponding to Figure 3B In the following, embodiments of the inventive concept will be described with reference to Figure 4A and Figure 4B For the sake of concise description, elements previously described with reference to Figure 1 , Figure 2 , Figure 3A and Figure 3B may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0117] As Figure 4A and Figure 4B shown, according to an embodiment, the display panel further includes an upper electrode AE overlapping with the second transistor T2. The upper electrode AE is disposed between the third insulating layer 30 and the fourth insulating layer 40. The upper electrode AE and the second electrode E2-A are disposed on the same layer.

[0118] In the present embodiment, the upper electrode AE and the second electrode E2-A are formed as an integral pattern. The second electrode E2-A is a part of the integral pattern, and the part overlaps with the first electrode E1 to constitute a capacitor C ST . The upper electrode AE is another part of the integral pattern, and the other part extends to a region overlapping with the second semiconductor patterns SP21 and SP22 and overlapping with the second control electrode CE2. The upper electrode AE is disposed on the same layer as the additional control electrode SC.

[0119] According to an embodiment, the upper electrode AE and the second control electrode CE2 form a capacitor. However, the embodiment of the inventive concept is not limited to this example, and in other embodiments, the upper electrode AE and the second electrode E2-A are formed as separate patterns but are electrically connected to each other through an additional connection electrode.

[0120] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept. Figure 6A is a plan view of some elements of a pixel according to an embodiment of the inventive concept. Figure 6B isFigure 6A Cross-sectional views of some of the components shown in. For ease of description, Figure 6A shows the area corresponding to Figure 3A and Figure 6B shows the area corresponding to Figure 3B .

[0121] Hereinafter, embodiments of the inventive concept will be described with reference to Figure 5 , Figure 6A and Figure 6B . For the sake of concise description, the components previously described with reference to Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4A and Figure 4B may be identified by the same reference numerals without repeating the overlapping description thereof.

[0122] According to an embodiment, except for adding the first capacitor C H , Figure 5 the pixels of Figure 2 correspond to the pixels PX of Figure 2 . The first capacitor C H is formed between the input terminal and the output terminal of the first transistor T1. For example, the capacitance of the first capacitor C H is determined by the difference between the first power supply voltage VDD and the potential of the output node ND.

[0123] Referring to Figure 6A and Figure 6B , according to an embodiment, when viewed in a plan view, the second electrode E21 overlaps with the first electrode E1, the first semiconductor patterns SP11 and SP12, and the vertical power line PL_V. For ease of description, the second electrode E21 is shown as a shaded pattern.

[0124] According to an embodiment, the second electrode E21 includes a first portion, a second portion, and a third portion, wherein the first portion overlaps with the first electrode E1 to form a capacitor C ST , the second portion overlaps with the first semiconductor patterns SP11 and SP12 and forms an additional control electrode SC, and the third portion overlaps with the vertical power line PL_V to form the first capacitor C H .

[0125] In the present embodiment, the first portion to the third portion are connected to each other and have substantially the same potential. The first portion to the third portion have a potential corresponding to the potential of the output node ND. For ease of explanation, in Figure 6B , the first capacitor C H is shown between the additional control electrode SC and the first input electrode IE1., wherein the additional control electrode SC has the same potential as the third part, and the first input electrode IE1 has the same potential as the vertical power line PL_V.

[0126] According to an embodiment, the first capacitor C H allows a light-emitting current to be stably supplied to the light-emitting element ELD through the first transistor T1. The first capacitor C H is formed between the first power supply voltage VDD and the electrode of the light-emitting element ELD connected to the output node ND.

[0127] According to an embodiment, when the capacitance of the first capacitor C H increases, the voltage change of the first control electrode CE1 of the first transistor T1 is affected by the voltage change of the output node ND. Therefore, the potential difference between the output electrode and the control electrode of the first transistor T1 can be more stably maintained, and thus, the light-emitting operation of the light-emitting element ELD can be more stably performed.

[0128] According to an embodiment of the inventive concept, the area of the additional control electrode SC overlapping with the first transistor T1 can be increased such that the additional control electrode SC overlaps with the first input electrode IE1, and thus the first capacitor C H is formed, and the fourth insulating layer 40 and the fifth insulating layer 50 are interposed between the additional control electrode SC and the first input electrode IE1. In other words, according to an embodiment of the inventive concept, two capacitors C H and C ST and the first transistor T1 commonly use a single metal pattern with multiple control electrodes.

[0129] According to an embodiment, the first part to the third part of the second electrode E21 are connected to each other to form an integral body. In other words, the capacitor C ST , the additional control electrode SC, and the first capacitor C H can be formed by the second electrode E21 which is basically a single electrode.

[0130] According to an embodiment of the inventive concept, by changing the shape of the second electrode E21, one electrode of the capacitor C ST , the additional control electrode SC, and one electrode of the first capacitor C H can be formed simultaneously using a single mask. Therefore, an additional process of forming the additional control electrode SC or the first capacitor C H can be omitted, and thus the entire process can be simplified and the process cost can be reduced.

[0131] Figure 7 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept. Figure 8A is a plan view of some elements of a pixel according to an embodiment of the inventive concept.Figure 8B is Figure 8A a cross-sectional view of some of the elements shown in. For convenience of description, Figure 8A shows the region corresponding to Figure 3A , and Figure 8B shows the region corresponding to Figure 3B . Hereinafter, embodiments of the inventive concept will be described with reference to Figure 7 , Figure 8A and Figure 8B . For the sake of concise description, the elements previously described with reference to Figures 1 to 6B may be identified by the same reference numerals without repeating the overlapping description thereof.

[0132] Referring to Figures 7 to 8B , according to an embodiment, except for the capacitor C STP , the pixel corresponds to the pixel PX of Figure 2 . The capacitor C STP includes a second capacitor C ST2 and a third capacitor C ST . The capacitance of the capacitor C STP is the sum of the capacitance of the second capacitor C ST2 and the capacitance of the third capacitor C ST . The third capacitor C ST corresponds to the capacitor C Figure 2 shown in ST . In other words, the third capacitor C ST is formed by a first electrode E1 and a second electrode E22.

[0133] In the present embodiment, except for the first electrode E1, the second electrode E22 overlaps with the entire first control electrode CE1. The second electrode E22 includes a first portion, a second portion, and a third portion, wherein the first portion overlaps with the first electrode E1 to form the third capacitor C ST , the second portion overlaps with the first semiconductor patterns SP11 and SP12 and the first control electrode CE1 and forms an additional control electrode SC, and the third portion is spaced apart from the first semiconductor patterns SP11 and SP12 in a plan view and overlaps with the first control electrode CE1 to form the second capacitor C ST2 .

[0134] In the present embodiment, the first portion to the third portion are connected to each other and have substantially the same potential. The first portion to the third portion have a potential corresponding to the potential of the output node ND.

[0135] In Figure 8B , according to an embodiment, to reduce the complexity of the description, the second capacitor C is shown between the first control electrode CE1 and the first output electrode OE1 having substantially the same potential as the second electrode E22.ST2 The first output electrode OE1 is connected to the additional control electrode SC, and the additional control electrode SC has the same potential as the second electrode E22.

[0136] According to an embodiment, the capacitor C STP is composed of the second electrode E22 and a metal pattern overlapping with the second electrode E22. The capacitor C STP includes not only a third capacitor C ST between the second electrode E22 and the first electrode E1 ST2 , but also a second capacitor C STP between the second electrode E22 and the first control electrode CE1. Figure 2 Therefore, the capacitor C ST has a capacitance larger than that of the capacitor C

[0137] shown in ST2 , and this can improve the display characteristics of the pixel. ST In this embodiment, the first part to the third part are connected to each other to form an integral body. In other words, the second capacitor C STP , the third capacitor C

[0138] Figure 9 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept. Figure 10A is a plan view of some elements of a pixel according to an embodiment of the inventive concept. Figure 10B is a cross-sectional view of some elements shown in FIG. 10A. For convenience of description, Figure 10A shows a region corresponding to Figure 3A , and Figure 10B shows a region corresponding to Figure 3B .

[0139] Hereinafter, embodiments of the inventive concept will be described with reference to Figure 9 , Figure 10A and Figure 10B . For the sake of concise description, the elements previously described with reference to Figures 1 to 8B may be identified by the same reference numerals without repeating the overlapping description thereof.

[0140] As Figure 9 shown, according to an embodiment, in addition to the capacitor C STP , the first capacitor C H and the additional control electrode SC, the pixel is the same asFigure 2 corresponds to the pixel PX. The capacitor C STP is associated with Figure 7 the capacitor C shown in STP corresponds. The first capacitor C H is associated with Figure 5 the first capacitor C shown in H corresponds, and the additional control electrode SC is associated with Figure 2 the additional control electrode SC shown in

[0141] Reference Figure 10A and Figure 10B , according to an embodiment, when observed in a plan view, the second electrode E23 overlaps with the first electrode E1, the first semiconductor patterns SP11 and SP12, the vertical power line PL_V, and the first control electrode CE1. For convenience of description, the second electrode E23 is shown as a shaded pattern.

[0142] According to an embodiment, the second electrode E23 includes a first portion, a second portion, a third portion, and a fourth portion, wherein the first portion overlaps with the first electrode E1 to form a capacitor C ST , the second portion overlaps with the first semiconductor patterns SP11 and SP12 and forms an additional control electrode SC, the third portion overlaps with the vertical power line PL_V to form a first capacitor C H , and the fourth portion is spaced apart from the first semiconductor patterns SP11 and SP12 in a plan view and overlaps with the first control electrode CE1 to form a second capacitor C ST2 .

[0143] In the present embodiment, the first through fourth portions are connected to each other to have substantially the same potential. The first through fourth portions have a potential corresponding to the potential of the output node ND.

[0144] In Figure 10B , to reduce the complexity of the description, a first capacitor C is shown between the first input electrode IE1 and the additional control electrode SC H , wherein the first input electrode IE1 has substantially the same potential as the vertical power line PL_V, and a second capacitor C is shown between the first output electrode OE1 and the first control electrode CE1 ST2 , wherein the first output electrode OE1 has substantially the same potential as the second electrode E23. According to an embodiment of the inventive concept, the capacitor C STP , the additional control electrode SC, and the first capacitor C H are each provided in each pixel, and thus can improve the display characteristics of the pixel.

[0145] In the present embodiment, the first through fourth portions are connected to each other to form a single body. In other words, the first capacitor C H , the second capacitor C ST2 , the third capacitor C ST , and the additional control electrode SC are formed of a second electrode E23 that is substantially a single pattern. According to an embodiment of the inventive concept, by changing the shape of the second electrode E23, the capacitance of the capacitor C STP can be controlled, the first capacitor C H can be additionally formed, and a double-gate structure of the first transistor T1 can be implemented. Accordingly, the entire manufacturing process can be simplified and the process cost can be reduced.

[0146] According to an embodiment of the inventive concept, synchronization of an output signal of a driving device can be easily performed, and the capacitor is provided with an increased capacitance, thereby increasing the operation speed of a pixel and improving display characteristics. According to an embodiment of the inventive concept, the shape of the electrode can be changed, and thus a plurality of elements can be further provided to increase the integration density of the pixel. According to an embodiment of the inventive concept, a plurality of elements can be formed through a single process, which can simplify the process of manufacturing a display panel and reduce the process cost.

[0147] Although exemplary embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art should understand that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. Display panel, comprising: A first transistor, comprising a first semiconductor pattern, a first control electrode, and a first input electrode and a first output electrode, wherein the first semiconductor pattern comprises an oxide, the first control electrode overlaps with the first semiconductor pattern, and wherein the first input electrode and the first output electrode are disposed on a layer different from the first control electrode and are respectively coupled to two different portions of the first semiconductor pattern; A capacitor, comprising a first electrode and a second electrode, wherein the first electrode is coupled to the first control electrode, and the second electrode is disposed on a layer different from the first electrode and is coupled to the first output electrode; A light-emitting element, connected to the capacitor and the first transistor and comprising a light-emitting layer; and An additional control electrode, connected to the second electrode and overlapping with the first control electrode and the first semiconductor pattern in a plan view, wherein the additional control electrode and the second electrode are disposed on the same layer and are formed integrally, and the additional control electrode and the second electrode are disposed on a layer different from the first input electrode and the first output electrode.

2. The display panel according to claim 1, wherein, When observed in a cross-sectional view, the first semiconductor pattern is disposed between the additional control electrode and the first control electrode, and the additional control electrode is disposed below the first semiconductor pattern.

3. The display panel according to claim 1, wherein, When observed in a plan view, the additional control electrode overlaps with the channel region of the first semiconductor pattern.

4. The display panel according to claim 1, further comprising: A first metal pattern, the first metal pattern being spaced apart from the first semiconductor pattern and forming a first capacitor together with the first input electrode, wherein the first metal pattern and the second electrode are disposed on the same layer.

5. The display panel according to claim 4, wherein, The first metal pattern and the second electrode are connected to each other and are formed integrally.

6. The display panel according to claim 5, wherein, The first metal pattern and the additional control electrode are connected to each other and are formed integrally.

7. The display panel according to claim 4, wherein, The first input electrode receives a power supply voltage higher than the cathode voltage of the light-emitting element.

8. The display panel according to claim 7, wherein, The first capacitor has a capacitance determined by a potential difference between the anode voltage of the light-emitting element and the power supply voltage.

9. The display panel according to claim 1, further comprising: A second metal pattern, the second metal pattern being spaced apart from the first semiconductor pattern and forming a second capacitor together with the first control electrode, wherein the second metal pattern and the second electrode are disposed on the same layer.

10. The display panel according to claim 9, wherein, The second metal pattern and the second electrode are connected to each other and are formed integrally.

11. The display panel according to claim 1, further comprising: A second transistor, comprising a second semiconductor pattern, a second control electrode, and a second input electrode and a second output electrode, wherein the second semiconductor pattern comprises silicon, the second control electrode overlaps with the second semiconductor pattern, and wherein the second input electrode and the second output electrode are respectively coupled to two different portions of the second semiconductor pattern; and A third transistor, comprising a third semiconductor pattern, a third control electrode, and a third input electrode and a third output electrode, wherein the third semiconductor pattern includes silicon and is spaced apart from the second semiconductor pattern, the third control electrode overlaps with the third semiconductor pattern, and the third input electrode and the third output electrode are respectively connected to two different portions of the third semiconductor pattern, wherein the second output electrode is connected to the first electrode, and the third output electrode is connected to the second electrode.

12. The display panel according to claim 11 further comprises: An upper electrode, which is disposed on the second control electrode and overlaps with the second control electrode in a plan view, wherein the second control electrode and the first electrode are disposed on the same layer, and the upper electrode and the second electrode are disposed on the same layer.

13. A display panel, comprising: A first transistor, comprising a first semiconductor pattern, a first control electrode, a first input electrode, and a first output electrode, wherein the first semiconductor pattern includes an oxide, the first control electrode overlaps with a channel region of the first semiconductor pattern, the first input electrode is connected to an input region of the first semiconductor pattern, and the first output electrode is connected to an output region of the first semiconductor pattern; A first capacitor, connected to the first transistor, wherein the first capacitor includes a first electrode and a second electrode facing each other; and A light-emitting element, connected to the second electrode, wherein the light-emitting element includes a light-emitting layer, wherein, when observed in a plan view, the second electrode includes a first portion overlapping with the first electrode and a second portion overlapping with both the channel region and the first control electrode of the first semiconductor pattern, and wherein the second electrode and the first input electrode and the first output electrode are disposed on different layers.

14. The display panel according to claim 13, wherein, The first output electrode is connected to the second electrode.

15. The display panel according to claim 13, wherein the second electrode further includes a third portion connected to the second portion, and when observed in a plan view, the third portion is spaced apart from the first semiconductor pattern and overlaps with the first input electrode.

16. The display panel according to claim 13, wherein the second electrode further includes a fourth portion connected to the second portion, and when observed in a plan view, the fourth portion is spaced apart from the first semiconductor pattern and overlaps with the first control electrode.

17. The display panel according to claim 13 further comprises: A second transistor, comprising a second semiconductor pattern, a second control electrode, and a second input electrode and a second output electrode, wherein the second semiconductor pattern includes silicon, the second control electrode overlaps with the second semiconductor pattern, and the second input electrode and the second output electrode are respectively connected to two different portions of the second semiconductor pattern, wherein the second output electrode is connected to the first electrode.

18. The display panel according to claim 17, wherein, The second control electrode and the first electrode are disposed on the same layer.

19. The display panel according to claim 17, further comprising: A third transistor, the third transistor including a third semiconductor pattern, a third control electrode, and a third input electrode and a third output electrode, wherein the third semiconductor pattern includes silicon and is spaced apart from the second semiconductor pattern, the third control electrode overlapping the third semiconductor pattern, and wherein the third input electrode and the third output electrode are respectively coupled to two different portions of the third semiconductor pattern, wherein the third output electrode is coupled to the second electrode.

20. A display panel, comprising: A first transistor, including a first semiconductor pattern, a first control electrode, and a first input electrode and a first output electrode, wherein the first semiconductor pattern includes an oxide, the first control electrode overlapping the first semiconductor pattern, and wherein the first input electrode and the first output electrode are disposed on a layer different from the first control electrode and are respectively coupled to two different portions of the first semiconductor pattern; A capacitor, including a first electrode and a second electrode, wherein the first electrode is coupled to the first control electrode, the second electrode is disposed on a layer different from the first electrode and is coupled to the first output electrode; and An additional control electrode, connected to the second electrode and overlapping the first control electrode and the first semiconductor pattern in a plan view, wherein the additional control electrode and the second electrode are disposed on the same layer and are formed integrally, and are disposed on a layer different from the first input electrode and the first output electrode, and wherein the first semiconductor pattern is disposed between the additional control electrode and the first control electrode.

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