Photodiode

Abstract

Embodiments of the present disclosure relate to a photodiode. The photodiode includes a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. A semiconductor wall is provided in the semiconductor substrate including the first substrate layer and the second substrate layer. The semiconductor wall includes: two outer semiconductor walls and at least one inner semiconductor wall positioned between the two outer semiconductor walls. Each inner semiconductor wall is located between two semiconductor walls having a longer length.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority of French Patent Application No. 1901504, filed on February 14, 2019, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure generally relates to electronic components, and more particularly to photodiodes. Background Art

[0004] A photodiode is a semiconductor component that has the ability to detect radiation from the optical domain and convert it into an electrical signal. More specifically, light forms electrons in the active region of the photodiode. These electrons must then be retrieved through a circuit.

[0005] In a 2D imaging sensor or 3D imaging sensor including a photodiode, the electrons formed at a given moment during the capture of a scene are stored in a memory, and then the amount of electrons is read through a circuit to obtain data about the scene.

[0006] In order to make the data about the scene accurate and corresponding to a given moment, it is preferable to move the electrons quickly towards the memory. Summary of the Invention

[0007] In one embodiment, the photodiode includes two outer semiconductor walls and at least one inner semiconductor wall, each inner semiconductor wall being located between two longer walls.

[0008] According to one embodiment, the outer wall and at least one inner wall extend along the entire height of the photodiode.

[0009] According to one embodiment, the outer wall and at least one inner wall extend through the entire substrate in which the photodiode is formed.

[0010] According to one embodiment, the photodiode includes n rows of inner walls, where n is an integer greater than or equal to 1.

[0011] According to one embodiment, when viewed from above, the inner walls of the same row have substantially the same length.

[0012] According to one embodiment, the photodiode includes 2^(i - 1) inner walls of row i, where i is an integer from 1 to n.

[0013] According to one embodiment, the inner walls of row i have a length substantially equal to 3 / 4 of the length of the inner walls of row i - 1, where i is an integer included in the range from 2 to n.

[0014] According to one embodiment, a negative voltage is applied to the inner walls and the outer walls.

[0015] According to one embodiment, an outer semiconductor wall including an outer wall at least partially surrounds an active region of a photodiode.

[0016] According to one embodiment, an inner wall is interconnected by one of the outer walls.

[0017] According to one embodiment, the outer wall completely surrounds the active region of the photodiode.

[0018] According to one embodiment, when viewed from above, the inner wall and the outer wall have widths included in a range of approximately 100 nm and approximately 300 nm.

[0019] According to one embodiment, when viewed from above, the inner wall is spaced from the closest inner wall or outer wall by a distance substantially equal to five times its width. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the following description of specific embodiments given by way of example and not limitation, the above and other features and advantages, as well as other features and advantages, will be described in detail with reference to the accompanying drawings, in which:

[0021] Figure 1A and 1B Embodiments of a photodiode are shown by a top view and a cross-sectional view.

[0022] Figure 2 Shows Figure 1A and 1B the potential V in a photodiode as a Figure 1A and 1B function of position in an embodiment of a photodiode.

[0023] Figure 3 Another embodiment of a photodiode is shown by a top view.

[0024] Figure 4 Shows another embodiment of a photodiode; and

[0025] Figure 5 Shows Figure 4 the potential V in a photodiode as a Figure 4 function of position in an embodiment of a photodiode. DETAILED DESCRIPTION

[0026] In the various figures, like features have been denoted by like reference numerals. In particular, structural and / or functional features common between the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0027] For clarity, only the operations and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, the application of the photodiode will not be described in detail.

[0028] Unless otherwise specified, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements linked or coupled together, this means that the two elements can be connected or linked or coupled through one or more other elements.

[0029] In the following disclosure, unless otherwise specified, when referring to absolute position determiners such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative position determiners such as the terms "above", "below", "higher", "lower", etc., or direction determiners such as "horizontal", "vertical", etc., the directions shown in the figures are referred to.

[0030] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "on the order of" mean within 10%, preferably within 5%.

[0031] One solution for increasing the speed of electrons moving in the memory direction is to form an electric field in the photodiode, for example, by applying a progressive voltage to the photodiode, where the voltage is lower away from the contact point and higher closer to the contact point.

[0032] Figure 1A A top view is shown, and Figure 1B A cross-sectional view taken along Figure 1A plane B-B shown is a cross-sectional view of an embodiment of the photodiode 100.

[0033] The photodiode 100 is located in a semiconductor substrate made of, for example, silicon and includes a PN junction. The PN junction includes a p-type semiconductor layer 102 covered by an n-type semiconductor layer 103. The layer 103 is covered, for example, by a heavily p-doped (P++) semiconductor layer 104. The semiconductor layers 102, 103, and 104 are made of, for example, silicon.

[0034] The photodiode 100 includes a connection pad 105. The pad 105 enables a connection, for example, between the photodiode 100 and another electronic component, which may be a sampling system that may include a transmission gate, a memory, or an n-type semiconductor region forming a node.

[0035] Figure 1A Only a single pad 105 is shown. In fact, the photodiode 100 may include multiple pads 105. For example, two pads 105 may be located on the layer 104.

[0036] The photodiode 100 includes a wall 110 or a trench that extends along the entire height of the photodiode. Hereinafter, the wall or the trench shall be understood as a structure made of semiconductor material, for example made of silicon. For example, the wall 110 extends at least from the upper surface of the layer 103 to the lower surface of the layer 102. Preferably, the wall 110 extends through the entire semiconductor substrate in which the photodiode 110 is formed. In Figure 1B the example, the wall also crosses the layer 104.

[0037] The wall 110 includes an outer wall, in Figure 1A the example, the outer wall completely surrounds the photodiode. More specifically, the photodiode 100 is surrounded by outer walls 110a, 110b, 110c, and 110d. The outer walls 110a and 110c are, for example, substantially parallel. Similarly, the outer walls 110b and 110d are, for example, substantially parallel. The outer walls 110a and 110c are, for example, substantially perpendicular to the outer walls 110b and 110d.

[0038] The wall 110a is, for example, the wall closest to one or more connection pads 105 among the walls 110a, 110b, 110c, and 110d. Figure 1A The connection pads 105 shown are, for example, located at substantially equal distances from the walls 110b and 110d.

[0039] When the photodiode 100 includes a plurality of pads 105, the pads 105 can, for example, form a line parallel to the walls 110a and 110c.

[0040] In addition to the outer walls 110a, 110b, 110c, and 110d, the wall 110 also includes an inner wall or a central wall that extends from the wall 110c and is substantially parallel to the walls 110b and 110d. The inner wall and the walls 110b and 110d form the branches of a comb-like structure. In Figure 1A the example, the branches are interconnected by the wall 110c.

[0041] In Figure 1A the example shown, the comb includes nine walls, including the walls 110b and 110d. Preferably, the comb includes an odd number of walls.

[0042] Figure 1A The comb shown includes:

[0043] - a first inner wall M1 (of row 1), which is the longest among the inner walls, where the length is measured in the Figure 1A plane shown;

[0044] - two second inner walls M2 (of row 2), each second wall having a length preferably substantially equal to 3 / 4 of the length of the first wall M1;

[0045] - Four third inner walls M3 (of row 3), each third inner wall having a length y which is preferably substantially equal to 3 / 4 of the length of the second wall M2.

[0046] For example, the pad 105 is located in the portion of the photodiode between the wall 110a and the end of the inner wall M1.

[0047] Each inner wall 110 is included between two walls of greater length. In Figure 1A the example shown, the wall M1 is included between the walls 110b and 110d. In this example, each wall M2 is included between the wall M1 and one of the outer walls 110b, 110d. In this example, each wall M3 is included between one of the walls M2 and the wall M1 or between one of the walls M2 and one of the outer walls 110b, 110d.

[0048] More generally, the comb includes at least the outer walls 110b and 110d (or the wall M0) and at least the inner wall M1. The comb includes n rows of walls M1 to Mn, where n is an integer greater than or equal to 1 and preferably less than or equal to 3. The comb preferably includes 2^(i - 1) walls Mi of row i (^ represents the power function), where i is an integer included in the range from 1 to n. For i included in the range from 2 to n, the length of each wall Mi of row i is preferably substantially equal to 3 / 4 of the length of the wall Mi - 1. Each wall Mi - 1 of row i - 1 is located between the walls Mj and Mk, where i is an integer in the range from 2 to n, and j and k are integers less than i, and j and k may be equal to the same integer.

[0049] The walls 110 all have, for example, the same width x, which is the minimum dimension of the wall when viewed from above (in Figure 1A the view shown in the plane of), for example, being included in the range of approximately 100 nm to approximately 300 nm, and the distance x1 between each wall and the next nearest wall is substantially equal to 5 * x (* represents multiplication).

[0050] In Figure 1A the example shown, the wall M2 is separated from the wall 110b or 110d and from the wall M1 by a distance x2 which is substantially equal to 11 * x. The wall M1 is spaced from the outer walls 110b and 110d by a distance x3, which distance x3 is substantially equal to 23 * x. The outer walls 110b and 110d are spaced by a distance x4 which is substantially equal to 47 * x.

[0051] When viewed from above, the shortest wall, i.e., the wall Mn ( Figure 1A M3 in) has a length, for example, in the range from 200 nm to 1500 nm. Preferably, when viewed from above, the walls of the same row have substantially the same length.

[0052] The inner wall (central wall) 110 and the outer wall 110 are connected to a negative voltage source, for example, substantially less than -1V. For example, the same negative voltage is applied to all the walls 110, and the walls 110 are interconnected.

[0053] The negative voltage applied to the walls causes a gradual formation of an electrostatic potential in the photodiode. More specifically, the electrostatic potential in the part of the photodiode where the wall is closest (at wall Mn) is lower than the electrostatic potential at the pad 105 (where there is no inner wall Mi around it). The electric field generated by this potential gradient, preferably substantially constant, enables the electrons formed by the photodiode to move faster.

[0054] As a variant, a wall substantially perpendicular to the inner wall Mi may not be formed. Thus, the outer wall may only partially surround the active region of the photodiode. For example, the wall 110a and / or the wall 110c may be absent. If the wall 110c is absent, the inner wall is thus coupled to the application node for applying the negative voltage in another way, preferably coupled to the same application node for applying the negative voltage.

[0055] Figure 2 An example of the potential V in the photodiode as a function of the position (Z) on the path 150 ( Figure 1A ) is shown. The path 150 starts at the point 152 ( Figure 1A ) in the wall 110c and terminates in the wall 150c. The memory (not shown) is electrically connected through the connection pad 105 ( Figure 1A ).

[0056] The origin of the horizontal axis corresponds to the point 152 located in the wall 110c.

[0057] Figure 2 Includes arrows 200, 202, 204, and 206. Each arrow corresponds to a channel entering a different region of the photodiode 100.

[0058] Arrow 200 corresponds to the channel entering the first region, which is bounded on one side by the wall 110c and on the other side by the point 156 ( Figure 1A ) on the path 150. More specifically, the first region extends from the wall 110c to the end of the wall M3. This is the region where the electrons are always located at a distance less than x1 from the wall. The potential V in the first region is greater than the potential in the wall 110c and increases as it approaches the point 156.

[0059] Arrow 202 corresponds to the channel entering the second region, which is bounded on one side by the point 156 and on the other side by the point 158 ( Figure 1A)。More specifically, the second region extends from the end of wall M3 to the end of wall M2. This is the region where the electrons are always located at a distance less than x2 from the wall. The electric potential V in the second region is greater than the electric potential in the first region and increases as it approaches point 158.

[0060] Arrow 204 corresponds to the channel for entering the third region, which is bounded on path 150 by point 158 on one side and point 160 on the other side ( Figure 1A )。More specifically, the third region extends from the end of wall M2 to the end of wall M1. This is the region where the electrons are always located at a distance less than x3 from the wall. The electric potential V in the third region is greater than the electric potential in the second region and increases as it approaches point 160.

[0061] Arrow 206 corresponds to the channel for entering the fourth region, which is bounded on path 150 by point 160 on one side and point 154 on the other side ( Figure 1A )。More specifically, the fourth region extends from the end of wall M1 to pad 105. This is the region where the electrons are always located at a distance below the distance x4 from the wall. The electric potential V in the fourth region is greater than the electric potential in the third region and increases as it approaches point 154.

[0062] Therefore, the electric potential V in the photodiode, which represents the electric field present in the photodiode, gradually increases between point 152 and point 154 as it approaches wall 110a and pad 105.

[0063] The drop in the potential V after point 154 corresponds to the channel for entering the sampling system.

[0064] Figure 3 Another embodiment of the photodiode 300 is shown in a top view.

[0065] Like Figure 1A and 1B the photodiode 100, the photodiode 300 includes an n-type doped layer 103 ( Figure 1B shown), a p-type doped layer 102 ( Figure 1B shown) and a heavily p++-type doped layer 104. Additionally, the photodiode includes walls 110b, 110c and 110d. In Figure 3 the example shown, wall 110a is absent.

[0066] Except for walls M0 110b and 110d, the photodiode 300 only includes wall M1. As described for Figure 1B the wall 110 shown, walls 110 (M0 and M1) extend along the entire height of the photodiode 300.

[0067] The photodiode 300 further includes one or more connection pads 105, as described above. In Figure 3 a single pad 105 is shown. In fact, multiple pads 105 may be located on the photodiode 300.

[0068] In Figure 3 the case of the embodiment shown, the change in electric potential between the wall 110c and one or more connection pads 105 is Figure 1A and 1B more irregular than in the embodiments shown. Therefore, the acceleration caused by the electric field is lower. However, compared to Figure 1A and 1B the walls M1, M2, and M3 of the embodiments shown, the surface area occupied by the single wall M1 in the active region of the photodiode is smaller.

[0069] More generally, an increase in the integer n corresponding to the number of rows of walls results in a continuity of the change in electric potential V, i.e., a more regular change in electric potential V. This continuity also results in a loss of surface area in the active material in the active region of the photodiode. However, this loss of surface area is at least partially compensated for by the walls 110. Indeed, the walls 110 cross the photodiode and thus accelerate the movement of electrons positioned along the height of the photodiode, including those electrons that would not be attracted to the connection pads 105 in the absence of the electric field caused by the walls 110. Therefore, the yield of the photodiode is increased.

[0070] Figure 4 Another embodiment of a photodiode 400 is depicted.

[0071] The photodiode includes two parts 400a and 400b. Except for the wall 100c, each of these parts 400a and 400b is similar to the photodiode 100 shown in FIG. 1. The parts 400a and 400b are symmetric about the axis X located at the position of each part where the wall 110c is located with respect to the axis between the components 400a and 400b.

[0072] Like Figure 1A and 1B the photodiode 100 and Figure 3 the photodiode 300, the photodiode 400 thus includes an n-type doped layer 103 ( Figure 1B shown), a p-type doped layer 102 ( Figure 1B shown), and a heavily p++-type doped layer 104.

[0073] The photodiode includes outer walls 410a, 410b, 412a, and 412b. The walls 412a and 412b correspond to the walls 110a of each part 400a and 400b. The axis X is, for example, at substantially equal distances from the walls 412a and 412b.

[0074] The photodiode 400 further includes outer walls 410a and 410b. Walls 410a and 410b correspond to walls 110b and 110d of portions 400a and 400b.

[0075] The outer walls 410a and 410b are, for example, substantially parallel to each other. Similarly, the outer walls 412a and 412b are, for example, substantially parallel to each other. The outer walls 410a and 410b are, for example, substantially perpendicular to the outer walls 412a and 412b.

[0076] Like the outer walls 110a and 110c of the foregoing embodiment, the outer walls 412a and 412b may be absent.

[0077] In this example, the photodiode 400 includes two connection pads 105. A connection pad 105 is located at the wall 412a, and another connection pad 105 is located at the wall 412b in the same manner as the connection pad located at the wall 110a in the Figure 1A and 1B embodiment. Each connection pad is, for example, at a substantially equal distance from the walls 410a and 410b. For example, each pad 105 is located in a portion of the photodiode between one of the ends of the wall 412a or 412b and the wall M1.

[0078] As a variant, as regarding Figure 1A and 1B described, the photodiode may include a greater number of connection pads 105.

[0079] The photodiode 400 further includes inner (central) walls M1 to Mn. The inner walls M1 to Mn extend, for example, from the axis X towards the walls 412a and 412b. Preferably, in each of the portions 400a and 400b, the length of each inner wall is substantially equal.

[0080] In this example, the inner walls are not interconnected by the wall 110c, as Figure 1A and 1B shown. However, the walls 410a, 410b and the inner walls form the branches of a comb.

[0081] Thus, similar to the photodiode 100 of Figure 1A and 1B , the photodiode 400 includes:

[0082] - A first wall M1, the longest of the inner walls;

[0083] - Two second walls M2, each second wall having a length preferably substantially equal to 3 / 4 of the length of the first wall M1;

[0084] - Four third walls M3, each third wall having a length preferably substantially equal to 3 / 4 of the length of the second wall.

[0085] Each inner (central) wall is included between two walls of greater length. In Figure 4 the example shown, wall M1 is included between walls 410a and 410b, each wall M2 is included between wall M1 and one of the outer walls 410a, 410b, and each wall M3 is included between one of walls M2 and wall M1 or between one of walls M2 and one of the outer walls 410a, 410b.

[0086] More generally, the photodiode 400 includes at least the outer walls 410a and 410b (or wall M0) and at least the inner wall M1. The photodiode 400 includes n rows of walls M1 to Mn, where n is an integer greater than or equal to 1 and preferably less than 3. The photodiode 400 preferably includes 2^(i - 1) walls Mi (^ represents the power function), where i is an integer in the range from 1 to n. For i included in the range from 2 to n, the length of each wall Mi in row i is preferably substantially equal to 3 / 4 of the length of the wall Mi in row i - 1. Each wall Mi - 1 is located between wall Mj and wall Mk, where i is an integer from 1 to n and j and k are integers less than i.

[0087] The walls 110, i.e., the inner walls Mi, all have, for example, the same width x, which is the minimum dimension when viewed from above, e.g., in the range of approximately 100 nm to approximately 300 nm. The walls are, for example, spaced apart from adjacent walls by a distance x1 that is substantially equal to 5 * x (* represents multiplication).

[0088] In Figure 4 the example, wall M2 is separated from wall 410a or 410b and from wall M1 by a distance x2 that is substantially equal to 11 * x. Wall M1 is spaced apart from the outer wall 410b or 410b by a distance x3 that is substantially equal to 23 * x. The outer walls 410a and 410b are separated by a distance x4 that is substantially equal to 47 * x.

[0089] The shortest wall, i.e., wall Mn ( Figure 1A M3 in

[0090] has, for example, a length included in the range from 400 to 3000 nm.

[0091] The negative voltage applied to the wall 110 causes the gradual formation of an electrostatic potential in the photodiode. More specifically, the electrostatic potential in the portion of the wall of the photodiode 400 closest (at the wall Mn) is lower than the electrostatic potential near the pad 105, where there is no inner wall Mi around the pad 105. The electric field generated by this electrostatic potential can cause the electrons formed on both sides of the photodiode to move faster.

[0092] As a variant, a wall that is substantially perpendicular to the inner wall Mi may not be formed. For example, the wall 412a and / or the wall 412b may not exist.

[0093] Figure 5 An example of the variation of the electric potential V is shown, which is a function of the position on the path 450 ( Figure 4 ), which starts from a first electron collection point (such as a first memory) and ends at a second electron collection point (such as a second memory), for example, by connecting the pad 105, and is shown by the points 452 and 454 of the path 450 ( Figure 4 ). Therefore, the origin of the horizontal axis corresponds to the first memory.

[0094] This variation is similar to the variation described for each of the sections 400a and 400b with respect to Figure 2 .

[0095] Figure 5 Includes arrows 504, 506, 508, 510, 512, 514, and 516. Each arrow corresponds to a channel entering a different region of the photodiode 400.

[0096] Arrow 510 shows the point 462 located at the intersection between the path 450 and the axis of symmetry X of the photodiode 400. The electrons located between the point 462 and the wall 412a will move towards the point 454.

[0097] The region 550 between arrows 508 and 512 corresponds to the variation of the electric potential between the points 460 ( Figure 4 ) and 464 ( Figure 4 ), that is, in the first region, where the electrons are always located at a distance less than the distance x1 from the wall. The electric potential V in the first region is greater and increases as it approaches the points 460 and 464.

[0098] Arrows 508 and 512 correspond to the channels on the path 150 that enter the second region, one located between the points 460 and 458, and the other located between the points 464 and 466 ( Figure 4 ). These are the regions of the photodiode 400 shown by the region 552, where the electrons are always located at a distance less than the distance x2 from the wall. The electric potential V in the second region is greater than that in the first region and increases as it approaches the points 458 and 466.

[0099] Arrows 506 and 514 correspond to the channels on path 150 that enter the third region, one between points 458 and 456, and the other between points 466 and 468( Figure 4 ). These are regions of the photodiode 400, shown by region 554, in which electrons are always at a distance less than distance x3 from the wall. The electric potential V in the third region is greater than the electric potential in the second region and increases as it approaches points 456 and 468.

[0100] Arrows 504 and 516 correspond to the channels on path 150 that enter the fourth region, one between points 456 and 452, and the other between points 468 and 454( Figure 4 ). These are regions of the photodiode 400, shown by region 556, in which electrons are always at a distance less than distance x4 from the wall. The electric potential V in the fourth region is greater than the electric potential in the third region and increases as it approaches points 452 and 454.

[0101] Thus, the electric potential V in the photodiode 400 representing the electric field is asymptotic between point 462 and points 452 and 454 and increases as it approaches walls 412a and 412b. This makes it possible to increase the speed of electrons towards one or the other connection pad.

[0102] The significant rise 500 and significant fall 502 in potential represent the channels into the memory through connection pad 105.

[0103] It is possible to deposit a plurality of electrodes on the surface of the photodiode, each at a different potential, to form the desired electric field. However, this structure requires obtaining different voltages and thus requires a complex power management circuit. Moreover, this structure is energy - expensive.

[0104] The advantage of the embodiment described here is that a single voltage is provided to wall 110. Thus, power management for implementing the described embodiment is simple.

[0105] It is also possible to select the shape of the photodiode such that, when viewed from above, the width of the photodiode decreases along a rounded - corner curve as it moves away from connection pad 105. In this way, it is possible to form a gradual electrostatic potential in the photodiode. However, this would involve forming a photodiode with a complex shape, which is not easy to manufacture. Moreover, this would lead to considerable limitations regarding the shape and size of the photodiode.

[0106] The advantage of the described embodiments is that the walls contact the semiconductor layers 102 and 103 along their entire height. Thus, the electric field is also positioned along the entire volume of the photodiode. As a result, the velocity of the electrons is accelerated, regardless of their position in the photodiode. This is not the case in the example where only a negative voltage is applied to the upper surface of the photodiode.

[0107] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily occur to those skilled in the art. In particular, the n and p doping types can be reversed.

[0108] Finally, based on the functional description provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. A photodiode, comprising: A semiconductor substrate, the semiconductor substrate including a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer; A plurality of semiconductor walls in the semiconductor substrate; Wherein the plurality of semiconductor walls includes: A first outer semiconductor wall and a second outer semiconductor wall, extending parallel to each other in a first direction, each of the first outer semiconductor wall and the second outer semiconductor wall having a first length; and A plurality of inner semiconductor walls, extending parallel to each other in the first direction and positioned between the first outer semiconductor wall and the second outer semiconductor wall, the plurality of inner semiconductor walls including: A first inner semiconductor wall having a second length less than the first length; and A second inner semiconductor wall and a third inner semiconductor wall, each having a third length less than the second length, wherein the second inner semiconductor wall is positioned between the first outer semiconductor wall and the first inner semiconductor wall, and wherein the third inner semiconductor wall is positioned between the second outer semiconductor wall and the first inner semiconductor wall.

2. The photodiode according to claim 1, wherein the plurality of inner semiconductor walls are centered along their length at a common axis, the common axis extending between the first outer semiconductor wall and the second outer semiconductor wall and perpendicular to the first outer semiconductor wall and the second outer semiconductor wall.

3. The photodiode according to claim 2, wherein the plurality of semiconductor walls further includes a third outer semiconductor wall and a fourth outer semiconductor wall extending parallel to each other in a second direction perpendicular to the first direction, and wherein the plurality of inner semiconductor walls are positioned between the third outer semiconductor wall and the fourth outer semiconductor wall.

4. The photodiode according to claim 3, wherein the ends of the third outer semiconductor wall and the fourth outer semiconductor wall are coupled to the ends of the first outer semiconductor wall and the second outer semiconductor wall.

5. The photodiode according to claim 3, wherein the third outer semiconductor wall and the fourth outer semiconductor wall, and the first outer semiconductor wall and the second outer semiconductor wall at least partially surround the active region of the photodiode.

6. The photodiode according to claim 3, wherein the third outer semiconductor wall and the fourth outer semiconductor wall, and the first outer semiconductor wall and the second outer semiconductor wall surround the active region of the photodiode.

7. The photodiode according to claim 2, wherein the plurality of inner semiconductor walls further includes: A fourth inner semiconductor wall and a fifth inner semiconductor wall, each having a fourth length greater than the third length, wherein the fourth inner semiconductor wall is positioned between the first outer semiconductor wall and the second inner semiconductor wall, and wherein the fifth inner semiconductor wall is positioned between the second outer semiconductor wall and the third inner semiconductor wall.

8. The photodiode according to claim 7, wherein the fourth length is less than the second length.

9. The photodiode according to claim 7, wherein the plurality of inner semiconductor walls further comprise: a sixth inner semiconductor wall and a seventh inner semiconductor wall, each having a fifth length less than the fourth length, wherein the sixth inner semiconductor wall is positioned between the first outer semiconductor wall and the fourth inner semiconductor wall, and wherein the seventh inner semiconductor wall is positioned between the second outer semiconductor wall and the fifth inner semiconductor wall.

10. The photodiode according to claim 9, wherein the fifth length is equal to the third length.

11. The photodiode according to claim 1, wherein the plurality of semiconductor walls further comprise a third outer semiconductor wall extending in a second direction perpendicular to the first direction, and wherein ends of the plurality of inner semiconductor walls are coupled to the third outer semiconductor wall.

12. The photodiode according to claim 11, wherein the third outer semiconductor wall, and the first outer semiconductor wall and the second outer semiconductor wall at least partially surround an active region of the photodiode.

13. The photodiode according to claim 11, wherein the plurality of semiconductor walls further comprise a fourth outer semiconductor wall extending in the second direction parallel to the third outer semiconductor wall, and wherein the plurality of inner semiconductor walls are positioned between the third outer semiconductor wall and the fourth outer semiconductor wall.

14. The photodiode according to claim 13, wherein ends of the third outer semiconductor wall and the fourth outer semiconductor wall are coupled to ends of the first outer semiconductor wall and the second outer semiconductor wall.

15. The photodiode according to claim 13, wherein the third outer semiconductor wall and the fourth outer semiconductor wall, and the first outer semiconductor wall and the second outer semiconductor wall surround an active region of the photodiode.

16. The photodiode according to claim 11, wherein the plurality of inner semiconductor walls further comprise: a fourth inner semiconductor wall and a fifth inner semiconductor wall, each having a fourth length greater than the third length, wherein the fourth inner semiconductor wall is positioned between the first outer semiconductor wall and the second inner semiconductor wall, and wherein the fifth inner semiconductor wall is positioned between the second outer semiconductor wall and the third inner semiconductor wall.

17. The photodiode according to claim 16, wherein the fourth length is less than the second length.

18. The photodiode according to claim 16, wherein the plurality of inner semiconductor walls further comprise: a sixth inner semiconductor wall and a seventh inner semiconductor wall, each having a fifth length less than the fourth length, wherein the sixth inner semiconductor wall is positioned between the first outer semiconductor wall and the fourth inner semiconductor wall, and wherein the seventh inner semiconductor wall is positioned between the second outer semiconductor wall and the fifth inner semiconductor wall.

19. The photodiode according to claim 18, wherein the fifth length is equal to the third length.

20. The photodiode according to claim 1, wherein the first outer semiconductor wall, the second outer semiconductor wall, and the plurality of inner semiconductor walls extend completely through the first substrate layer and the second substrate layer.

21. The photodiode according to claim 1, further comprising an upper semiconductor substrate layer of the first dopant type on top of the second substrate layer, and wherein the first outer semiconductor wall, the second outer semiconductor wall, and the plurality of inner semiconductor walls extend through the first substrate layer, the second substrate layer, and the upper semiconductor substrate layer.

22. The photodiode according to claim 1, wherein a negative voltage is applied to the first outer semiconductor wall, the second outer semiconductor wall, and the plurality of inner semiconductor walls.

23. The photodiode according to claim 1, wherein each semiconductor wall of the first outer semiconductor wall, the second outer semiconductor wall, and the plurality of inner semiconductor walls has a width perpendicular to its length, and the width is in the range of 100 nm to 300 nm.

24. The photodiode according to claim 1, wherein each semiconductor wall of the plurality of inner semiconductor walls has a width perpendicular to its length, and wherein adjacent inner semiconductor walls are spaced apart by a distance substantially equal to five times the width.

25. The photodiode according to claim 1, wherein each semiconductor wall of the plurality of inner semiconductor walls has a width perpendicular to its length, and wherein the inner semiconductor wall closest to the outer semiconductor wall is spaced apart from the outer semiconductor wall by a distance substantially equal to five times the width.

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