Two-choice data selector

Abstract

The present invention provides a two-to-one data selector, which includes: an NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOR logic circuit configured to receive a selection signal, a second input and an intermediate result of the NOR logic circuit and generate an inverted output.

Description

Technical Field

[0001] The invention relates to a two-or-one data selector. Background Art

[0002] The area occupied by the data selector is proportional to the number of transistors used to implement the data selector. Therefore, as the total number of transistors decreases, the area occupied by the data selector will also decrease. The reduction in the area of ​​the data selector will directly translate into a reduction in chip area and cost savings. Summary of the invention

[0003] The present invention provides a novel circuit implementation of a two-to-one data selector, which can reduce the number of transistors of the two-to-one data selector and thus reduce the chip area.

[0004] According to one aspect of the present invention, a two-to-one data selector is provided, comprising: an NOR logic circuit, configured to receive a selection signal and an inverted first input, and generate an intermediate result; and an AND-OR-NOR logic circuit, configured to receive a selection signal, a second input and the intermediate result of the NOR logic circuit, and generate an inverted output.

[0005] Preferably, when the selection signal is a logic 0, the inverted output is the inverted first input, and when the selection signal is a logic 1, the inverted output is the inverted second input.

[0006] Preferably, the NOR logic circuit includes: a first PMOS transistor, whose gate terminal is configured to receive a selection signal, wherein a source terminal of the first PMOS transistor is coupled to a power supply terminal; a second PMOS transistor, whose gate terminal is configured to receive an inverted first input, whose source terminal is coupled to a drain terminal of the first PMOS transistor, and whose drain terminal is coupled to a first node; a first NMOS transistor, whose gate terminal is configured to receive a selection signal and whose drain terminal is coupled to the first node; and a second NMOS transistor, whose gate terminal is configured to receive an inverted first input and whose drain terminal is coupled to the first node, wherein a source terminal of each of the first NMOS transistor and the second NMOS transistor is coupled to a ground terminal, wherein the NOR logic circuit is configured to generate an intermediate result at the first node.

[0007] Preferably, the AND-OR-N logic circuit comprises: a third PMOS transistor, whose gate terminal is configured to receive an intermediate result of the OR-N logic circuit, wherein a source terminal of the third PMOS transistor is coupled to the power supply terminal; a fourth PMOS transistor, whose gate terminal is configured to receive a selection signal, whose source terminal is coupled to the drain terminal of the third PMOS transistor, and whose drain terminal is coupled to the second node; a fifth PMOS transistor, whose gate terminal is configured to receive a second input, whose source terminal is coupled to the drain terminal of the third PMOS transistor, and whose drain terminal is coupled to the second node; and a third PMOS transistor. an NMOS transistor, whose gate terminal is configured to receive an intermediate result of the NOR logic circuit and whose drain terminal is coupled to the second node; a fourth NMOS transistor, whose gate terminal is configured to receive a selection signal and whose drain terminal is coupled to the second node; and a fifth NMOS transistor, whose gate terminal is configured to receive a second input and whose drain terminal is coupled to the source terminal of the fourth NMOS transistor, wherein a source terminal of each of the third NMOS transistor and the fifth NMOS transistor is coupled to the ground terminal, wherein the NOR logic circuit is configured to produce an inverted output at the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A better understanding of the present invention can be obtained when considering the following detailed description of the embodiments in conjunction with the accompanying drawings. The same or similar reference numerals are used in the various drawings to represent the same or similar parts. The accompanying drawings, together with the following detailed description, are included in this specification and form a part of the specification to illustrate the embodiments of the present invention and to explain the principles and advantages of the present invention.

[0009] Figure 1 The truth table of a two-to-one data selector is shown.

[0010] Figure 2 The logic diagram of a two-to-one data selector is shown.

[0011] Figure 3 The structural block diagram of the MUX2 two-to-one data selector is shown.

[0012] Figure 4 Shows the structural block diagram of the MUXI2 two-to-one data selector.

[0013] Figure 5 A block diagram of a two-to-one data selector in which one of the inputs is inverted is shown.

[0014] Figure 6 A structural block diagram of a two-choice data selector according to an embodiment of the present invention is shown.

[0015] Figure 7A CMOS circuit diagram of a two-to-one data selector according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0016] The following detailed description of the embodiments presents various details of specific embodiments of the present invention. However, the present invention can be implemented in many different ways as defined and covered by the claims. In this specification, the same reference numerals may represent the same or functionally similar elements.

[0017] A data selector is a device that selects and transmits data from multiple channels to a single common data channel to implement data selection. The logical expression of a two-to-one data selector is: sel is the selection signal, a0 is the first input, and a1 is the second input. Figure 1 The truth table of a two-to-one data selector is shown in Figure 2 The logic diagram of the two-to-one data selector is shown. When the selection signal sel is logic 0, the output X is the first input a0. When the selection signal sel is logic 1, the output X is the second input a1.

[0018] Figure 3 The structure block diagram of MUX2 two-choice data selector is shown. Figure 3 As shown, the MUX2 two-to-one data selector includes an AOI22 logic circuit and two inverter INV logic circuits. The input terminal A0 receives the first input a0, and the input terminal A1 receives the second input a1. The output of the AOI22 logic circuit is Therefore, the output of the MUX2 two-to-one data selector is The MUX2 two-to-one data selector occupies a large chip area, has a large delay, and is slow.

[0019] Figure 4 The block diagram of the MUXI2 two-to-one data selector is shown. Figure 4 As shown, the MUXI2 two-to-one data selector includes an AOI22 logic circuit and an inverter INV logic circuit. The input terminal A0 receives the first input a0, the input terminal A1 receives the second input a1, and the output for Figure 3 The output X inverts. The MUXI2 two-to-one data selector has a small delay, but in some cases the chip area occupied is still large.

[0020] Figure 5 The block diagram of a two-to-one data selector in which one input is inverted is shown. Figure 5As shown, the two-to-one data selector includes an AOI22 logic circuit and two inverter INV logic circuits. The input terminal A0 receives the inverted first input a0_n (i.e., the inverted a0), the input terminal A1 receives the second input a1, and the output for Figure 3 The output X in the two-to-one data selector also has the disadvantages of large chip area, large delay and slow speed.

[0021] For CMOS circuits, their natural output is inverted. If a positive output is to be achieved, an inverter needs to be added after the natural output. The present invention utilizes this characteristic of CMOS circuits to provide a novel circuit implementation of a two-to-one data selector, which does not require an inverter, thereby reducing the number of transistors of the two-to-one data selector and thus reducing the chip area.

[0022] Figure 6 A structural block diagram of a two-choice data selector according to an embodiment of the present invention is shown. Figure 6 The two-to-one data selector includes an NOR logic circuit NR2 and an AND-NOR logic circuit AOI21.

[0023] The NOR logic circuit NR2 is configured to receive the selection signal sel and the inverted first input a0_n and generate an intermediate result The AND-OR logic circuit AOI21 is configured to receive the selection signal sel, the second input a1 and the intermediate result gn1 of the OR-OR logic circuit, and generate an inverted output

[0024] The inverted first input a0_n is the inverted version of the first input a0, that is, Further we can get That is to say That is, XN is the inversion of output X.

[0025] Therefore, when the selection signal sel is logic 0, the inverted output XN is the inverted first input When the selection signal sel is logic 1, the inverted output XN is the inverted second input

[0026] Figure 7 A CMOS circuit diagram of a two-to-one data selector according to an embodiment of the present invention is shown.

[0027] like Figure 7As shown, the NOR logic circuit NR2 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The gate terminal of the first PMOS transistor P1 is configured to receive a selection signal sel. The source terminal of the first PMOS transistor P1 is coupled to the power supply terminal VDD. The gate terminal of the second PMOS transistor P2 is configured to receive an inverted first input a0_n, its source terminal is coupled to the drain terminal of the first PMOS transistor, and its drain terminal is coupled to the first node J1. The gate terminal of the first NMOS transistor N1 is configured to receive a selection signal sel and its drain terminal is coupled to the first node J1. The gate terminal of the second NMOS transistor N2 is configured to receive an inverted first input a0_n and its drain terminal is coupled to the first node J1. The source terminal of each of the first NMOS transistor N1 and the second NMOS transistor N2 is coupled to the ground terminal VSS. The NOR logic circuit NR2 is configured to generate an intermediate result gn1 at the first node J1.

[0028] The AND-NOR logic circuit AOI21 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. The gate terminal of the third PMOS transistor P3 is configured to receive the intermediate result gn1 of the OR-NOR logic circuit. The source terminal of the third PMOS transistor P3 is coupled to the power supply terminal VDD. The gate terminal of the fourth PMOS transistor P4 is configured to receive the selection signal sel, the source terminal thereof is coupled to the drain terminal of the third PMOS transistor, and the drain terminal thereof is coupled to the second node J2. The gate terminal of the fifth PMOS transistor P5 is configured to receive the second input a1, the source terminal thereof is coupled to the drain terminal of the third PMOS transistor P3, and the drain terminal thereof is coupled to the second node J2. The gate terminal of the third NMOS transistor N3 is configured to receive the intermediate result gn1 of the OR-NOR logic circuit and the drain terminal thereof is coupled to the second node J2. The gate terminal of the fourth NMOS transistor N4 is configured to receive the selection signal sel and its drain terminal is coupled to the second node J2. The gate terminal of the fifth NMOS transistor N5 is configured to receive the second input a1 and its drain terminal is coupled to the source terminal of the fourth NMOS transistor N4. The source terminal of each of the third NMOS transistor N3 and the fifth NMOS transistor N5 is coupled to the ground terminal VSS. The AND-OR-NOR logic circuit AOI21 is configured to generate an inverted output XN at the second node J2.

[0029] The one-out-of-two data selector of the embodiment of the present invention is composed of a combination of an NOR logic circuit NR2 and an AND NOR logic circuit AOI21. No inverter is required in the entire circuit, thus reducing the use of transistors and saving chip area.

[0030] The two-or-one data selector of the present invention is described above in conjunction with specific embodiments. However, it should be understood that any feature of any embodiment may be combined with and / or replaced with any other feature of any other embodiment.

[0031] Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, etc. Examples of electronic devices may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washing machines / dryers, peripheral devices, clocks, etc. In addition, electronic devices may include incomplete products.

[0032] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprises", "contains", "has", etc. should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense. That is, the meaning is "including but not limited to". As generally used herein, the term "coupled" refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, as generally used herein, the term "connected" refers to two or more elements that can be directly connected or connected through one or more intermediate elements. In addition, when used in this application, the words "herein", "above", "below", "hereafter", "supra" and words of similar meaning shall refer to the entirety of this application rather than any particular part of this application.

[0033] Furthermore, unless expressly stated otherwise or otherwise understood in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments in any way require features, elements, and / or states, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0034] Although certain embodiments have been described, these embodiments are presented as examples only, and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein can be embodied in various other forms. In addition, without departing from the spirit of the present disclosure, various omissions, replacements, and changes can be made to the form of the methods and systems described herein. For example, although blocks are presented in a given arrangement, alternative embodiments can perform similar functions with different components and / or circuit topologies, and some blocks can be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks can be implemented in various different ways. Any suitable combination of the elements and actions of the various embodiments described above can be combined to provide further embodiments. The various features and processes described above can be implemented independently of each other, or can be combined in various ways. All suitable combinations and subcombinations of the features of the present disclosure are intended to fall within the scope of the present disclosure.

Claims

1. A two-choice data selector, comprising: a NOR logic circuit (NR2) configured to receive a selection signal (sel) and an inverted first input (a0_n) and generate an intermediate result (gn1); and The AND-NOR logic circuit (AOI21) is configured to receive the selection signal (sel), the second input (a1) and the intermediate result (gn1) of the NOR logic circuit, and generate an inverted output (XN).

2. The one-out-of-two data selector as claimed in claim 1, wherein: When the select signal (sel) is logic 0, the inverted output (XN) is the inverted first input, In the case where the select signal (sel) is a logic 1, the inverted output (XN) is the inverted second input.

3. The one-out-of-two data selector as claimed in claim 1, wherein: The NOR logic circuit (NR2) includes: a first PMOS transistor having a gate terminal configured to receive a selection signal (sel), wherein a source terminal of the first PMOS transistor is coupled to a power supply terminal; a second PMOS transistor having a gate terminal configured to receive the inverted first input (a0_n), a source terminal coupled to the drain terminal of the first PMOS transistor, and a drain terminal coupled to the first node; a first NMOS transistor having a gate terminal configured to receive a selection signal (sel) and a drain terminal coupled to the first node; and a second NMOS transistor having a gate terminal configured to receive the inverted first input (a0_n) and a drain terminal coupled to the first node, wherein a source terminal of each of the first NMOS transistor and the second NMOS transistor is coupled to a ground terminal, The NOR logic circuit (NR2) is configured to generate an intermediate result (gn1) at the first node.

4. The one-out-of-two data selector as claimed in claim 1, wherein: The AND-OR-NON logic circuit (AOI21) includes: a third PMOS transistor having a gate terminal configured to receive an intermediate result (gn1) of the NOR logic circuit, wherein a source terminal of the third PMOS transistor is coupled to the power supply terminal; a fourth PMOS transistor having a gate terminal configured to receive a selection signal (sel), a source terminal coupled to the drain terminal of the third PMOS transistor, and a drain terminal coupled to the second node; a fifth PMOS transistor having a gate terminal configured to receive the second input (a1), a source terminal coupled to the drain terminal of the third PMOS transistor, and a drain terminal coupled to the second node; a third NMOS transistor having a gate terminal configured to receive the intermediate result (gn1) of the NOR logic circuit and a drain terminal coupled to the second node; a fourth NMOS transistor having a gate terminal configured to receive a selection signal (sel) and a drain terminal coupled to the second node; and a fifth NMOS transistor having a gate terminal configured to receive the second input (a1) and a drain terminal coupled to the source terminal of the fourth NMOS transistor, wherein a source terminal of each of the third NMOS transistor and the fifth NMOS transistor is coupled to the ground terminal, The AND-OR-N logic circuit (AOI21) is configured to generate an inverted output (XN) at the second node.

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