Semiconductor device manufacturing method and semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device and a semiconductor device. The method for manufacturing a semiconductor device includes the following steps: forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate; forming a gate electrode having a stacked structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer, forming a first metal film having the same stacked structure as the gate electrode in a region adjacent to the source electrode at a distance; forming a second metal film in contact with the source electrode and the first metal film; forming a hole that reaches the first metal film from the back side of the SiC substrate; and forming a metal through hole in the hole that reaches the first metal film from the back side.

Description

[0001] Cross-reference

[0002] This application claims the benefit of priority based on Japanese Application No. 2019-027429, filed on February 19, 2019, and all the contents described in this Japanese Application are incorporated by reference. Technical Field

[0003] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0004] Japanese Patent Publication No. 2013-191763 (JP2013-191763A) discloses a method for manufacturing a semiconductor device. The method described in the document includes the following steps: forming a through hole having a first hole and a second hole having a smaller diameter than the first hole from the back side of a semiconductor substrate having a compound semiconductor stacking structure on the surface side. The through hole forming step includes the following steps: forming the first hole in a semiconductor substrate in which the etching bottom surface is formed into a curved surface and the central part of the etching bottom surface is formed into a compound semiconductor stacking structure, and the outer peripheral part of the etching bottom surface is used as the semiconductor substrate by dry etching; and forming the second hole in the compound semiconductor stacking structure by wet etching using the semiconductor substrate at the outer peripheral part of the etching bottom surface as a mask.

[0005] Japanese Patent Publication No. 2008-085020 (JP2008-085020A) discloses the structure of a semiconductor device. The semiconductor device described in the document includes a semiconductor element, a blocking film, a first through-hole wiring and a second through-hole wiring. The semiconductor element is formed on the first surface of a semiconductor substrate. The blocking film is provided in a first through-hole formed in a concave shape on the first surface of the semiconductor substrate. The blocking film includes at least one or more Group VIII elements. The first through-hole wiring contacts the blocking film and is connected to the electrode of the semiconductor element. The second through-hole wiring is formed in the second through-hole, and the second through-hole reaches the blocking film on the second surface facing the first surface of the semiconductor substrate and is formed in a concave shape. The second through-hole wiring is electrically connected to the first through-hole wiring via the blocking film and is formed as a part of the wiring formed on the second surface. Japanese Patent Publication No. 2012-033690 (JP2012-033690A) discloses a semiconductor device and a semiconductor method. Summary of the invention

[0006] The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device comprises the following steps: forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate; forming a gate electrode having a stacked structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer; forming a first metal film having the same stacked structure as the gate electrode in a region adjacent to the source electrode at a distance; forming a second metal film in contact with the source electrode and the first metal film; forming a hole that reaches the first metal film from the back side of the SiC substrate; and forming a metal through hole in the hole that reaches the first metal film from the back side.

[0007] The present invention provides a semiconductor device. The semiconductor device comprises: a SiC substrate; a nitride semiconductor layer provided on the main surface of the SiC substrate; a source electrode and a drain electrode provided on the nitride semiconductor layer; a gate electrode provided between the source electrode and the drain electrode on the nitride semiconductor layer, and having a stacked structure including a Ni layer and an Au layer on the Ni layer; a first metal film provided in a region adjacent to the source electrode at a distance on the nitride semiconductor layer, and having the same stacked structure as the gate electrode; a second metal film in contact with the source electrode and the first metal film; and a metal through hole provided in a hole of the SiC substrate, and reaching the first metal film from the back side of the SiC substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects, aspects and advantages will be more clearly understood from the following detailed description of the embodiments according to the present invention with reference to the following drawings.

[0009] Figure 1 FIG. 1 is a plan view showing the structure of a transistor as a semiconductor device according to one embodiment.

[0010] Figure 2 Yes Figure 1 A portion of the transistor is shown in an enlarged top view.

[0011] Figure 3 is along Figure 2 A cross-sectional view of a portion of a III-III line transistor.

[0012] Figure 4 1A is a cross-sectional view showing each step included in a method for manufacturing the transistor 1A.

[0013] Figure 5 1A is a cross-sectional view showing each step included in a method for manufacturing the transistor 1A.

[0014] Figure 6 1A is a cross-sectional view showing each step included in a method for manufacturing the transistor 1A.

[0015] Figure 7 1A is a cross-sectional view showing each step included in a method for manufacturing the transistor 1A.

[0016] Figure 8 1A is a cross-sectional view showing each step included in a method for manufacturing the transistor 1A.

[0017] Fig. 9 1A is a cross-sectional view showing each step included in a method for manufacturing the transistor 1A.

[0018] Fig.10 This is an enlarged top view of a transistor according to a modification example. DETAILED DESCRIPTION

[0019] [Problems to be Solved by the Invention]

[0020] In recent years, with the development of semiconductor technology, the size of semiconductor elements has been reduced and the internal components have been miniaturized. In addition, in transistors, in order to improve high-frequency characteristics (specifically, improvement and stabilization of gain based on reduction of source inductance), a so-called island source via (ISV) is effective in forming a through hole directly below the source finger. However, in the case of nitride-based semiconductor devices, chlorine-based gases are usually used in the formation of holes for through holes, but Al, which is the main material of the source electrode, is easily etched by chlorine-based gases. Therefore, it is difficult to form a through hole directly below the source electrode.

[0021] [Effects of the invention]

[0022] According to the present invention, a through hole can be easily formed just below a source finger in a semiconductor device.

[0023] [Description of Embodiments of the Invention]

[0024] First, the contents of the embodiments of the present invention are listed and described. A method for manufacturing a semiconductor device according to one embodiment includes the following steps: forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate; forming a gate electrode having a stacked structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer, forming a first metal film having the same stacked structure as the gate electrode in a region adjacent to the source electrode separated by a gap; forming a second metal film in contact with the source electrode and the first metal film; forming a hole that reaches the first metal film from the back side of the SiC substrate; and forming a metal through hole in the hole that reaches the first metal film from the back side.

[0025] As an embodiment, in the process of forming the hole, after etching the SiC substrate by reactive ion etching using a fluorine-based gas, the nitride semiconductor layer may be etched by reactive ion etching using a chlorine-based gas. In this case, in the process of forming the hole, fluorine ions derived from the fluorine-based gas may be intermittently irradiated toward the SiC substrate. In addition, in the process of forming the hole, chlorine ions derived from the chlorine-based gas may be intermittently irradiated toward the nitride semiconductor layer.

[0026] As one embodiment, the source electrode may have an opening, and the first metal film may be formed in the opening.

[0027] As one embodiment, the planar shape of the source electrode may be U-shaped, and the first metal film may be formed inside the U-shape.

[0028] As one embodiment, the stacked structure may include a Pd layer between the Ni layer and the Au layer.

[0029] As one embodiment, the step of forming the source electrode and the drain electrode may include a step of alloying a multilayer metal mainly containing Al at a temperature in a range of 500° C. to 600° C.

[0030] A semiconductor device according to one embodiment comprises: a SiC substrate; a nitride semiconductor layer, provided on a main surface of the SiC substrate; a source electrode and a drain electrode, provided on the nitride semiconductor layer; a gate electrode, provided between the source electrode and the drain electrode on the nitride semiconductor layer, and having a stacked structure including a Ni layer and an Au layer on the Ni layer; a first metal film, provided in a region adjacent to the source electrode at a distance from the nitride semiconductor layer, and having the same stacked structure as the gate electrode; a second metal film, in contact with the source electrode and the first metal film; and a metal through hole, provided in a hole of the SiC substrate, and reaching the first metal film from the back side of the SiC substrate.

[0031] As one embodiment, the source electrode and the drain electrode may mainly contain Al.

[0032] As one embodiment, the source electrode may have an opening, and the first metal film may be provided in the opening.

[0033] As one embodiment, the planar shape of the source electrode may be a U-shape, and the first metal film may be provided inside the U-shape.

[0034] As an embodiment, the source electrode may have a width of at least 30 μm.

[0035] [Details of the embodiments of the present invention]

[0036] Hereinafter, a method for manufacturing a semiconductor device and a specific example of a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the present invention is not limited to these examples, but is represented by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims. In the following description, the same reference numerals are marked on the same elements in the description of the drawings, and repeated descriptions are omitted.

[0037] Figure 1 FIG. 1 is a plan view showing the structure of a transistor 1A as a semiconductor device according to one embodiment. Figure 2 Yes Figure 1 A top view showing an enlarged portion of transistor 1A is shown. Figure 3 is along Figure 2 FIG. 1 is a cross-sectional view of a portion of the transistor 1A along line III-III. Figure 1 to Figure 3 As shown, the transistor 1A includes a SiC substrate 3, a nitride semiconductor layer 4, insulating films 5 to 8, a gate electrode (gate finger) 21, a source electrode 22, a drain electrode 23, a gate wiring 31, a source wiring 32, a drain wiring 33, a field plate 35, a metal film 42 and a metal via 44.

[0038] The SiC substrate 3 is a substrate made of SiC having a flat main surface 3a and a flat back surface 3b located on the opposite side of the main surface 3a. The SiC substrate 3 is used for epitaxial growth of the nitride semiconductor layer 4. The thickness of the SiC substrate 3 is, for example, in the range of 50 μm to 120 μm, and is 100 μm in one example.

[0039] The nitride semiconductor layer 4 is an epitaxial layer formed on the main surface 3a of the SiC substrate 3. In the case where the transistor 1A is a high electron mobility transistor (HEMT), the nitride semiconductor layer 4 has, for example, an AlN buffer layer in contact with the main surface 3a, a GaN channel layer provided on the AlN buffer layer, an AlGaN (or InAlN) barrier layer provided on the GaN channel layer, and a GaN capping layer provided on the barrier layer. The GaN capping layer may also be omitted depending on the circumstances. The AlN buffer layer is undoped, and its thickness is, for example, in the range of 10nm to 30nm. The GaN channel layer is undoped, and its thickness is, for example, in the range of 0.3μm to 2.0μm. The thickness of the barrier layer is, for example, in the range of 10nm to 30nm. However, in the case of the InAlN barrier layer, its thickness is set to be less than 20nm. The GaN capping layer is n-type, and its thickness is, for example, 1.5nm to 5nm.

[0040] The insulating films 5 to 8 constitute an insulating stacked structure located on the nitride semiconductor layer 4. For example, the insulating films 5 to 8 are composed of a silicon compound such as SiN, SiO2, or SiON. In the present embodiment, the insulating films 5 to 8 are in contact with each other, but this does not prevent other layers from being provided between at least one layer. When the insulating films 5 to 8 are SiN layers, the thickness of the insulating film 5 is, for example, in the range of 10 nm to 30 nm, the thickness of the insulating film 6 is, for example, in the range of 30 nm to 90 nm, the thickness of the insulating film 7 is, for example, in the range of 150 nm to 500 nm, and the thickness of the insulating film 8 is, for example, in the range of 100 nm to 1000 nm.

[0041] A plurality of source electrodes 22 are provided on the active region of the nitride semiconductor layer 4 to form an ohmic contact with the nitride semiconductor layer 4. Figure 2 As shown, a plurality of source electrodes 22 are arranged in a direction D1 along the main surface 3a, and the planar shape of each source electrode 22 is a rectangular shape with a direction D2 intersecting the direction D1 as the long side direction. The source electrode 22 has one or more (two in the figure) openings 22a. The two openings 22a are, for example, rectangular or oval in shape with the direction D2 as the long side direction, and are arranged along the direction D2. The source electrode 22 is formed, for example, by alloying a stacked structure consisting of a Ti layer, an Al layer and a Ti layer (or a Ta layer, an Al layer and a Ta layer), and mainly contains Al. The source electrode 22 has a width of at least 30 μm in the direction D1 as the short side direction.

[0042] A plurality of drain electrodes 23 are provided on the active region of the nitride semiconductor layer 4 to form an ohmic contact with the nitride semiconductor layer 4. Figure 2 As shown, a plurality of drain electrodes 23 are arranged alternately with the source electrodes 22 along the direction D1, and the planar shape of each drain electrode 23 is a rectangular shape with the direction D2 as the long side direction. The drain electrode 23 is also formed by alloying a stacked structure consisting of a Ti layer, an Al layer, and a Ti layer (or a Ta layer, an Al layer, and a Ta layer), and mainly contains Al.

[0043] A plurality of gate electrodes (gate fingers) 21 are provided on the active region of the nitride semiconductor layer 4. Each gate electrode 21 extends in the direction D2 and is located between the source electrode 22 and the drain electrode 23. These gate electrodes 21 form a Schottky contact with the nitride semiconductor layer 4. The contact width (gate length) between the gate electrode 21 and the nitride semiconductor layer 4 in the direction D1 is, for example, 0.5 μm. The gate electrode 21 has a stacked structure including a Ni layer and an Au layer on the Ni layer. In one example, the Ni layer contacts the nitride semiconductor layer 4, and the Au layer contacts the Ni layer. Alternatively, a Pd layer may be sandwiched between the Ni layer and the Au layer. In this case, the thickness of the Ni layer is, for example, 50 nm to 100 nm, the thickness of the Pd layer is, for example, 20 nm to 70 nm, and the thickness of the Au layer is, for example, 100 nm to 500 nm.

[0044] The field plate 35 is a metal film provided along the gate electrode 21. An insulating film 7 is interposed between the field plate 35 and the gate electrode 21. The field plate 35 has, for example, a stacked structure of a Ti layer (or a Ta layer) and an Au layer. The thickness of the Ti layer is, for example, in the range of 3 nm to 10 nm, and the thickness of the Au layer is, for example, in the range of 100 nm to 500 nm.

[0045] The metal film 42 is the first metal film in the present embodiment. The metal film 42 is provided in a region adjacent to the source electrode 22 at a distance on the nitride semiconductor layer 4, and has the same stacked structure as the gate electrode 21. That is, when the gate electrode 21 has a stacked structure of Ni / Au, the metal film 42 also has a stacked structure of Ni / Au. Alternatively, when the gate electrode 21 has a stacked structure of Ni / Pd / Au, the metal film 42 also has a stacked structure of Ni / Pd / Au. The thickness of each Ni layer, Pd layer, and Au layer is also the same as that of the gate electrode 21.

[0046] In the present embodiment, the metal film 42 is provided in the opening 22a. The planar shape of the metal film 42 is a shape similar to the opening 22a, for example, a rectangular shape or an oval shape with the direction D2 as the long side direction. The size of the metal film 42 in the direction D2 is, for example, in the range of 20 μm to 100 μm, and the size in the direction D1 is, for example, in the range of 10 μm to 50 μm. The distance between the outer edge of the metal film 42 and the inner edge of the opening 22a of the source electrode 22 is, for example, in the range of 1 μm to 5 μm.

[0047] The gate wiring 31 is a metal film that covers a portion of the gate electrode 21 and extends on the inactive region of the nitride semiconductor layer 4. In the present embodiment, a plurality of gate wirings 31 are arranged on one side of the active region of the nitride semiconductor layer 4 in the direction D2. Each gate wiring 31 is connected to two or more gate electrodes 21 to form a gate pad, and is electrically connected to the external wiring of the transistor 1A via a bonding wire. Therefore, the surface of each gate wiring 31 is exposed from the opening of the outermost protective film (not shown). Each gate wiring 31 has, for example, a stacked structure including a TiW layer and an Au layer on the TiW layer.

[0048] The source wiring 32 is a second metal film in this embodiment, covers the corresponding source electrode 22 and the metal film 42, and contacts the upper surface of the source electrode 22 and the upper surface of the metal film 42. Each source wiring 32 has a stacked structure similar to the gate wiring 31, for example, a stacked structure including a TiW layer and an Au layer on the TiW layer. Each source wiring 32 has, for example, a rectangular shape with the direction D2 as the long side direction.

[0049] The drain wiring 33 is a metal film, overlaps with the drain electrode on the active region of the nitride semiconductor layer 4, and is arranged to extend from the drain electrode to the inactive region. That is, the drain wiring 33 has a plurality of interdigital portions 33a provided on the active region and a plurality of pad portions 33b provided on the inactive region. The drain wiring 33 has a laminated structure similar to the gate wiring 31 and the source wiring 32, for example, a laminated structure including a TiW layer and an Au layer on the TiW layer. Each interdigital portion 33a covers the corresponding drain electrode 23 and contacts the upper surface of the drain electrode 23. Each interdigital portion 33a is, for example, in a rectangular shape with the direction D2 as the long side direction. The plurality of pad portions 33b are arranged on the other side of the active region of the nitride semiconductor layer 4 in the direction D2 (the side opposite to the gate wiring 31). Each pad portion 33b is connected to two or more interdigital portions 33a, respectively, and is electrically connected to the external wiring of the transistor 1A via a bonding wire. Therefore, the surface of each pad portion 33b is exposed from the opening of the outermost protective film (not shown).

[0050] The metal through hole 44 is a metal film provided in the hole 11 penetrating the SiC substrate 3 and the nitride semiconductor layer 4, and reaches the metal film 42 from the back surface 3b of the SiC substrate 3, and contacts the metal film 42. The metal through hole 44 is provided to electrically connect the back metal film 45 provided on the back surface 3b and the source electrode 22 to each other via the source wiring 32 and the metal film 42. When the transistor 1A is mounted on a mounting component connected to the ground potential (reference potential), the mounting component and the back metal film 45 on the back surface 3b are electrically connected via a conductive adhesive such as solder. Thus, the ground potential is given to the source electrode 22.

[0051] A method for manufacturing the transistor 1A of this embodiment having the above-described structure will be described. Figures 4 to 9 1A is a cross-sectional view showing each step included in a method for manufacturing the transistor 1A.

[0052] First, if Figure 4 As shown in part (a) of , a SiC substrate 3 is prepared. The thickness of the SiC substrate 3 is, for example, 500 μm. A nitride semiconductor layer 4 is epitaxially grown on the main surface 3a of the SiC substrate 3. The details of the nitride semiconductor layer 4 are as described above. Next, an insulating film 5 is deposited on the nitride semiconductor layer 4. For example, in the case where the insulating film 5 is composed of a silicon compound such as SiN, the insulating film 5 is deposited by a plasma CVD method or a reduced pressure CVD (LPCVD) method. As described above, the thickness of the insulating film 5 is, for example, in the range of 10 nm to 30 nm.

[0053] Then, if Figure 4 As shown in part (b) of , openings corresponding to the source electrode 22 and the drain electrode 23 are formed in the insulating film 5. Specifically, a resist mask having an opening pattern corresponding to the opening is formed on the insulating film 5, and the insulating film 5 is etched through the opening pattern to form an opening. Thereafter, the source electrode 22 and the drain electrode 23 are formed in the opening using a lift-off method. That is, with the resist mask remaining, each metal layer (for example, Ti / Al / Ti or Ta / Al / Ta) for the source electrode 22 and the drain electrode 23 is sequentially deposited using a method such as evaporation. The thickness of each Ti layer (or Ta layer) is, for example, in the range of 10nm to 30nm, and the thickness of the Al layer is, for example, in the range of 200nm to 400nm. That is, the source electrode 22 and the drain electrode 23 at this point in time are multilayer metals mainly containing Al.

[0054] After the metal material deposited on the resist mask is removed together with the resist mask, heat treatment (annealing) is performed at 500° C. to 600° C. to alloy the multiple layers of metal deposited in the previous step. The temperature within the range of 500° C. to 600° C. is maintained for, for example, 1 minute.

[0055] Then, if Figure 4 As shown in part (c) of FIG. 1 , an insulating film 6 is deposited to cover the insulating film 5, the source electrode 22, and the drain electrode 23. For example, when the insulating film 6 is made of a silicon compound such as SiN, the insulating film 6 is deposited by a plasma CVD method.

[0056] Then, if Figure 5As shown in part (a) of FIG. 6 , the gate electrode 21 and the metal film 42 are formed. First, a photoresist having openings for the gate electrode 21 and the metal film 42 is formed on the insulating film 6. An opening pattern for the gate electrode 21 is formed between the source electrode 22 and the drain electrode 23. An opening pattern for the metal film 42 is formed in a region adjacent to the source electrode 22 with a gap therebetween (for example, formed in the opening of the source electrode 22).

[0057] Next, the insulating film 6 and the insulating film 5 are continuously etched through the opening pattern of the photoresist, thereby forming openings that penetrate the insulating films 5 and 6 and exposing the nitride semiconductor layer 4. Thereafter, the gate electrode 21 and the metal film 42 are formed in the corresponding openings of the insulating films 5 and 6 using a lift-off method. That is, in a state where the photoresist remains, the metal layers (for example, Ni / Au or Ni / Pd / Au) for the gate electrode 21 and the metal film 42 are sequentially deposited by evaporation or the like. As described above, the thickness of the Ni layer is, for example, in the range of 50nm to 100nm, the thickness of the Pd layer is, for example, in the range of 20nm to 70nm, and the thickness of the Au layer is, for example, in the range of 100nm to 500nm. Then, the metal material deposited on the photoresist is removed together with the photoresist.

[0058] Then, if Figure 5 As shown in part (b) of FIG. 4 , an insulating film 7 is deposited to cover the insulating film 6, the gate electrode 21, and the metal film 42. For example, when the insulating film 7 is made of a silicon compound such as SiN, the insulating film 7 is deposited by a plasma CVD method.

[0059] Then, if Figure 5 As shown in part (c) of FIG. 2 , a field plate 35 is formed along the gate electrode 21. In this process, for example, a lift-off method is used to form the field plate 35. That is, a resist mask having an opening pattern corresponding to the planar shape of the field plate 35 is formed, and each metal layer (for example, Ti / Au) for the field plate 35 is sequentially deposited using a method such as evaporation. Then, the metal material deposited on the resist mask is removed together with the resist mask.

[0060] Then, if Figure 6 As shown in part (a) of FIG. 3 , an insulating film 8 is deposited to cover the insulating film 7 and the field plate 35. For example, when the insulating film 8 is made of a silicon compound such as SiN, the insulating film 8 is deposited by a plasma CVD method.

[0061] Then, if Figure 6As shown in part (b) of FIG. 1 , the insulating films 7 and 8 on the metal film 42 are etched away to form an opening, exposing the metal film 42. At the same time, the insulating films 6, 7, and 8 on the source electrode 22 and the drain electrode 23 are etched away to form an opening, exposing the source electrode 22 and the drain electrode 23, respectively. At the same time, the insulating films 5 to 8 in the regions corresponding to the pad portions 33b of the gate wiring 31 and the drain wiring 33 are etched away to form an opening, exposing the nitride semiconductor layer 4.

[0062] Then, if Figure 6 As shown in part (c) of , a gate wiring 31, a source wiring 32, and a drain wiring 33 are formed simultaneously. Specifically, a seed metal layer (TiW / Au) covering the insulating film 8 and the metal film 42 exposed from the opening formed in the insulating films 5 to 8, the source electrode 22, the drain electrode 23, and the nitride semiconductor layer 4 is formed by sputtering. Furthermore, a resist mask having openings in the region where the gate wiring 31, the source wiring 32, and the drain wiring 33 are formed is formed on the seed metal layer. Thereafter, a plating process is performed to form an Au layer in the opening of the resist mask. At this time, the thickness of the Au layer is, for example, 5 μm. After the plating process, the resist mask is removed.

[0063] Next, a protective film (passivation film) is formed on the entire surface of the main surface 3a, and openings are formed on the gate wiring 31 and the pad portion 33b of the drain wiring 33 to expose the gate wiring 31 and the pad portion 33b. Thus, the process on the main surface 3a side is completed.

[0064] Then, if Figure 7 As shown in part (a) of FIG. 1 , a protective resist 51 is formed on the main surface 3a by spin coating, and all components on the main surface 3a are covered by the resist 51. Figure 7 As shown in part (b) of FIG. 5 , a support substrate 52 is attached to the resist 51. The support substrate 52 is, for example, a glass plate. Next, the back surface 3b of the SiC substrate 3 is polished to thin the SiC substrate 3. At this time, for example, the SiC substrate 3 having a thickness of 500 μm is thinned to 100 μm.

[0065] Then, if Figure 7 As shown in part (c) of FIG. 3 , a seed metal film 53 (eg, TiW / Au) is formed on the back surface 3b and the side surface of the SiC substrate 3 by, for example, sputtering. Figure 8 As shown in part (a) of FIG. 4 , after forming a resist pattern 55 at a position facing the metal film 42, Ni plating is performed to form a Ni mask 54. Figure 8As shown in part (b) of FIG. 4 , the resist pattern 55 is removed, and the exposed seed metal film 53 is etched and removed. As a result, the area of ​​the back surface 3b facing the metal film 42 is exposed through the opening of the Ni mask 54. In addition, when the seed metal film 53 is composed of TiW / Au, the seed metal film 53 can be easily removed by reactive ion etching (RIE) based on fluorine-based gas.

[0066] Then, if Figure 8 As shown in part (c) of FIG. 5 , the SiC substrate 3 and the nitride semiconductor layer 4 are etched through the opening of the Ni mask 54, thereby forming a hole 11 that penetrates the SiC substrate 3 and the nitride semiconductor layer 4. The hole 11 reaches the metal film 42 from the back surface 3b of the SiC substrate 3. As a result, the metal film 42 is exposed on the back surface 3b side through the hole 11.

[0067] In this process, the hole 11 is formed by so-called pulse etching, which is performed intermittently. The etching method is, for example, RIE (Reactive Ion Etching). Specifically, after the SiC substrate 3 is first etched by RIE using a fluorine-based gas, the reactive gas is changed, and the nitride semiconductor layer 4 is etched by RIE using a chlorine-based gas. And, when etching the SiC substrate 3, fluorine ions derived from the fluorine-based gas are intermittently irradiated toward the SiC substrate 3. In addition, when etching the nitride semiconductor layer 4, chlorine ions derived from the chlorine-based gas are intermittently irradiated toward the nitride semiconductor layer 4. In addition, when etching the nitride semiconductor layer 4, etching can also be performed continuously from the SiC substrate 3 through the fluorine-based gas, and the nitride semiconductor layer 4 can be etched by utilizing its sputtering effect. In this case, fluorine ions derived from the fluorine-based gas can also be intermittently irradiated toward the nitride semiconductor layer 4.

[0068] The metal film 42 includes a Ni layer and an Au layer on the Ni layer. When etching the nitride semiconductor layer 4, the Ni layer is exposed first. At this time, the Ni layer is slightly etched by the chlorine-based gas, but the etching rate of Ni by the chlorine-based gas is much lower than the etching rate of the nitride semiconductor by the chlorine-based gas. Therefore, the etching can be stopped in the metal film 42. Even if the Ni layer is removed due to the sputtering effect, there is an Au layer on the Ni layer that is much thicker than the Ni layer, so the etching by the chlorine-based gas can be reliably stopped in the Au layer.

[0069] Here, in the above-mentioned etching process, the Ni mask 54 may be removed at the stage where the SiC substrate 3 is completely etched, and then the nitride semiconductor layer 4 may be etched using a chlorine-based gas. The Ni mask 54 needs to be removed before the next process, but the Ni layer of the metal film 42 is exposed in the hole 11 just after the hole 11 is formed. When the Ni mask 54 removal process is performed in this state, the Ni layer of the metal film 42 is also removed at the same time. Therefore, the Ni mask 54 is removed before the Ni layer of the metal film 42 is exposed, that is, after the etching of the SiC substrate 3 is completed and before the etching of the nitride semiconductor layer 4 is started. In addition, the Ni mask 54 is removed using, for example, dilute nitric acid.

[0070] Then, if Fig. 9 As shown in part (a) of FIG. 1 , a seed metal film 56 (eg, TiW / Au) is formed on the back surface 3b of the SiC substrate 3 and the inner surface of the hole 11 (including the exposed metal film 42) by, for example, sputtering. Fig. 9 As shown in part (b) of FIG. 1 , a resist pattern 57 is formed in the area overlapping with the scribe line. Then, the seed metal film 56 exposed from the resist pattern 57 is plated to form a back metal film 45 on the back surface 3b, and a metal through hole 44 is formed in the hole 11 from the back surface 3b to the metal film 42. Then, as shown in FIG. Fig. 9 As shown in part (c) of FIG. 5 , the resist pattern 57 is removed, and the exposed seed metal film 56 is etched and removed.

[0071] Finally, the protective resist 51 is removed, and the components on the main surface 3a side of the SiC substrate 3 are separated from the support substrate 52. After the substrate product including the SiC substrate 3 and the nitride semiconductor layer 4 is cleaned, it is cut along the scribe line to separate the individual chips from each other. Through the above steps, the transistor 1A of this embodiment is completed.

[0072] The effects obtained by the transistor 1A and the manufacturing method thereof of the present embodiment described above are described. In the present embodiment, a metal film 42 is formed in a region adjacent to the source electrode 22 at a distance therefrom. The metal film 42 has a stacked structure including a Ni layer and an Au layer on the Ni layer. Furthermore, the metal film 42 is connected to the source electrode 22 via the source wiring 32, and a metal via 44 extending from the back side 3b of the SiC substrate 3 is in contact with the metal film 42. Thus, the metal via 44 can be realized directly below the source interdigital finger (source wiring 32), and the high-frequency characteristics can be improved (specifically, the improvement and stabilization of the gain based on the reduction of the source inductance).

[0073] Since the Ni layer of the metal film 42 has high etching resistance to the chlorine-based gas when the hole 11 for the metal via 44 is formed in the nitride semiconductor layer 4 using the chlorine-based gas, the metal film 42 can be used as an etching stopper film. Therefore, the hole 11 can be easily formed just below the source finger (source wiring 32). That is, the metal via 44 can be easily formed.

[0074] In this embodiment, the metal film 42 has the same stacked structure as the gate electrode 21, and the gate electrode 21 and the metal film 42 are formed simultaneously. In this case, there is no need to add a step for forming the metal film 42, and the number of steps can be reduced.

[0075] As in the present embodiment, in the process of forming the hole 11, after etching the SiC substrate 3 by RIE using a fluorine-based gas, the nitride semiconductor layer 4 may be etched by RIE using a chlorine-based gas. In this case, the SiC substrate 3 and the nitride semiconductor layer 4 can be easily etched separately. In addition, in this case, the fluorine ions derived from the fluorine-based gas may be intermittently irradiated toward the SiC substrate 3. Similarly, the chlorine ions derived from the chlorine-based gas may be intermittently irradiated toward the nitride semiconductor layer 4.

[0076] In recent years, with the miniaturization of transistor 1A, the metal through hole 44 is also required to be miniaturized. In order to miniaturize the metal through hole 44, the hole 11 needs to be miniaturized, but the smaller the inner diameter of the hole 11, the larger the aspect ratio. When the aspect ratio of the hole 11 becomes larger, it is difficult for the molecules and ions that are decomposed and regenerated during etching to be discharged from the hole 11. Therefore, it is difficult for the etching species to enter the hole 11, and the etching rate is greatly reduced. In addition, when etching a semiconductor with a wide band gap such as a nitride semiconductor, not only chemical etching elements but also physical etching elements are required. Therefore, a higher power is required during etching, and the bottom periphery of the hole 11 is charged due to the influence of the incident ions. When the bottom periphery of the hole 11 is charged, the effect of physical etching is weakened and the etching rate is greatly reduced. The larger the aspect ratio of the hole 11, the more significant this tendency is.

[0077] As described in the present embodiment, by using a so-called pulse etching method in which fluorine ions derived from a fluorine-based gas and chloride ions derived from a chlorine-based gas are intermittently irradiated toward the SiC substrate 3 and the nitride semiconductor layer 4, respectively, molecules and ions decomposed and regenerated during etching are easily discharged from the hole 11, and the charging around the bottom of the hole 11 can be alleviated. Therefore, the reduction in the etching rate can be suppressed, and the hole 11 with a large aspect ratio can be easily formed.

[0078] As in this embodiment, the metal film 42 may be formed in the opening 22a of the source electrode 22. In this case, the pair of side surfaces of the source electrode 22 can be respectively opposed to the gate electrode 21, and each electrode can be efficiently arranged to reduce the size of the transistor 1A.

[0079] As in the present embodiment, the stacked structure of the gate electrode 21 and the metal film 42 may include a Pd layer between the Ni layer and the Au layer. In this case, the adhesion between the Ni layer and the Au layer is enhanced, and the gate electrode 21 and the metal film 42 can be formed more firmly.

[0080] As in the present embodiment, the process of forming the source electrode 22 and the drain electrode 23 may also include the following process: alloying a multilayer metal mainly containing Al at a temperature in the range of 500°C to 600°C. Assuming that the hole 11 is formed toward the source electrode 22 mainly containing Al, it is easy to cause the source electrode 22 to be etched by the chlorine-based gas. The reason is that the etching rates of Al and nitride semiconductors relative to the chlorine-based gas are roughly the same. Therefore, it is difficult to form the hole 11 directly below the source electrode 22 mainly containing Al. In the present embodiment, since the hole 11 is formed toward the metal film 42, such a problem can be avoided and the hole 11 can be easily formed.

[0081] (Variation Example)

[0082] The source electrode 22 may have any planar shape as long as it is adjacent to the metal film 42 with a gap therebetween. Fig.10 This is an enlarged top view of a transistor 1B involved in a variation of the above-mentioned embodiment. The difference between this variation and the above-mentioned embodiment lies in the shape of the source electrode. The source electrode 22 of the above-mentioned embodiment has one or more openings 22a, but the source electrode 24 of this variation has a planar shape such as a U-shape with one end side in the direction D2 opened. In addition, one or more metal films 42 are provided on the inner side of the U-shape. When manufacturing the transistor 1B, after the source electrode 24 is formed into a U-shape, one or more metal films 42 are formed on the inner side of the U-shape. Even in this way, the effect of the above-mentioned embodiment can be obtained in the same way.

[0083] The method for manufacturing a semiconductor device and a semiconductor device according to the present invention are not limited to the above-mentioned embodiment, and various modifications are possible. For example, in the above-mentioned embodiment, the hole 11 is formed by pulse etching, but when the aspect ratio of the hole 11 is small, fluorine ions derived from a fluorine-based gas and chlorine ions derived from a chlorine-based gas may be continuously irradiated toward the SiC substrate and the nitride semiconductor layer, respectively.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: depositing an insulating film on the nitride semiconductor layer formed on the main surface of the SiC substrate; forming a source electrode and a drain electrode arranged along a first direction in each opening of the insulating film corresponding to the source electrode and the drain electrode; forming a gate electrode between the source electrode and the drain electrode on the nitride semiconductor layer in an opening of the insulating film corresponding to the gate electrode; forming a first metal film including a Ni layer located in a region adjacent to the source electrode with a gap therebetween in an opening of the insulating film corresponding to the first metal film; forming a second metal film located on the insulating film, contacting the source electrode and the first metal film, and electrically connecting the source electrode and the first metal film; forming a hole reaching the first metal film from the back side of the SiC substrate; and forming a metal through hole in the hole that reaches the first metal film from the back surface, The source electrode includes a first portion and a second portion arranged along the first direction, The first metal film is formed between the first portion and the second portion, The insulating film exists between the first metal film and the first portion and the second portion.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The source electrode has an opening, and the first metal film is formed in the opening.

3. A method for manufacturing a semiconductor device, comprising the following steps: forming a source electrode and a drain electrode on the nitride semiconductor layer formed on the main surface of the SiC substrate; A gate electrode having a stacked structure including a Ni layer and an Au layer on the Ni layer is formed between the source electrode and the drain electrode on the nitride semiconductor layer, and a first metal film having the same stacked structure as the gate electrode is formed in a region adjacent to the source electrode and spaced apart from the source electrode; forming a second metal film in contact with the source electrode and the first metal film; forming a hole reaching the first metal film from the back side of the SiC substrate; and forming a metal through hole in the hole that reaches the first metal film from the back surface, The planar shape of the source electrode is a U-shape, and the first metal film is formed inside the U-shape.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: In the step of forming the hole, after the SiC substrate is etched by reactive ion etching using a fluorine-based gas, the nitride semiconductor layer is etched by reactive ion etching using a chlorine-based gas.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: In the step of forming the holes, fluorine ions derived from the fluorine-based gas are intermittently irradiated toward the SiC substrate.

6. The method for manufacturing a semiconductor device according to claim 4, wherein: In the step of forming the holes, the nitride semiconductor layer is intermittently irradiated with chlorine ions derived from the chlorine-based gas.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: In the step of forming the holes, the nitride semiconductor layer is intermittently irradiated with chlorine ions derived from the chlorine-based gas.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The gate electrode has a stacked structure, and the first metal film has the same stacked structure as the gate electrode. The stacked structure is a structure including the Ni layer and the Au layer on the Ni layer, or a structure including the Ni layer, the Au layer on the Ni layer, and a Pd layer between the Ni layer and the Au layer.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The step of forming the source electrode and the drain electrode includes a step of alloying a multilayer metal including Al at a temperature in a range of 500° C. to 600° C.

10. A semiconductor device comprising: SiC substrate; A nitride semiconductor layer is provided on the main surface of the SiC substrate; A source electrode and a drain electrode arranged along a first direction, and disposed on the nitride semiconductor layer; a gate electrode disposed between the source electrode and the drain electrode on the nitride semiconductor layer, and having a stacked structure including a Ni layer and an Au layer on the Ni layer; A first metal film is provided on the nitride semiconductor layer in a region adjacent to the source electrode at a distance therefrom, and includes a Ni layer; an insulating film, disposed on the nitride semiconductor layer; a second metal film, located on the insulating film, in contact with the source electrode and the first metal film, and electrically connecting the source electrode and the first metal film; and a metal through hole provided in the hole of the SiC substrate and reaching the first metal film from the back side of the SiC substrate, The source electrode includes a first portion and a second portion arranged along the first direction, The first metal film is formed between the first portion and the second portion, The insulating film exists between the first metal film and the first portion and the second portion.

11. The semiconductor device according to claim 10, wherein The source electrode and the drain electrode include Al.

12. The semiconductor device according to claim 10, wherein: The source electrode has an opening, and the first metal film is disposed in the opening.

13. The semiconductor device according to claim 11, wherein The source electrode has an opening, and the first metal film is disposed in the opening.

14. The semiconductor device according to any one of claims 10 to 13, wherein The source electrode has a width of at least 30 μm.

15. A semiconductor device comprising: SiC substrate; A nitride semiconductor layer is provided on the main surface of the SiC substrate; A source electrode and a drain electrode are disposed on the nitride semiconductor layer; a gate electrode disposed between the source electrode and the drain electrode on the nitride semiconductor layer, and having a stacked structure including a Ni layer and an Au layer on the Ni layer; A first metal film is provided in a region adjacent to the source electrode at a distance on the nitride semiconductor layer and has the same stacked structure as the gate electrode; a second metal film in contact with the source electrode and the first metal film; and a metal through hole provided in the hole of the SiC substrate and reaching the first metal film from the back side of the SiC substrate, The planar shape of the source electrode is U-shaped, and the first metal film is provided inside the U-shape.

16. The semiconductor device according to claim 15, wherein: The source electrode has a width of at least 30 μm.

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