semiconductor packages

Abstract

The present disclosure provides a semiconductor package, which includes: a connection structure having a first surface and a second surface opposite to each other and including a first redistribution layer; a semiconductor chip arranged on the first surface of the connection structure and including a connection pad connected to the first redistribution layer; an encapsulant arranged on the first surface of the connection structure and encapsulating the semiconductor chip; a second redistribution layer arranged on the encapsulant; a wiring structure connecting the first redistribution layer and the second redistribution layer to each other and extending in a stacking direction; and a heat dissipation element arranged on at least a portion of the second surface of the connection structure.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0022542 filed on February 26, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package. Background Art

[0003] A significant recent trend in the development of semiconductor chip technology has been to reduce the size of components used in semiconductor chips. Consequently, in the field of packaging technology, in response to the rapid growth in demand for small-sized semiconductor chips, there has been a growing demand for semiconductor packages that are compact in size while enabling a large number of pins.

[0004] One type of packaging technology proposed to meet the aforementioned technical requirements is a fan-out semiconductor package. Such a fan-out semiconductor package is compact and can accommodate a large number of pins by redistributing connection terminals to areas outside the area overlapping the semiconductor chip. Furthermore, semiconductor packages have recently been required to improve heat dissipation characteristics. Summary of the Invention

[0005] An aspect of the present disclosure may provide a semiconductor package having improved heat dissipation characteristics.

[0006] According to one aspect of the present disclosure, a semiconductor package may include: a connection structure having a first surface and a second surface opposite to each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including a connection pad connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and covering the semiconductor chip; a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first redistribution layer and the second redistribution layer to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

[0007] According to another aspect of the present disclosure, a semiconductor package may include: a frame having a first surface and a second surface opposite to each other and including a through-hole and a wiring structure, the through-hole passing through the first surface and the second surface, the wiring structure connecting the first surface and the second surface to each other; a connection structure arranged on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip arranged in the through-hole and located on the connection structure, and including a connection pad connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip arranged in the through-hole; a second redistribution layer arranged on the second surface of the frame and connected to the wiring structure; and a heat dissipation element arranged on at least a portion of the connection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0010] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0011] Figure 3A and Figure 3B is a schematic cross-sectional view showing a fan-in type semiconductor package before and after being packaged;

[0012] Figure 4 shows a series of schematic cross-sectional views illustrating a packaging process for a fan-in semiconductor package;

[0013] Figure 5 is a schematic cross-sectional view showing a fan-in type semiconductor package mounted on an interposer substrate and ultimately mounted on a mainboard of an electronic device;

[0014] Figure 6 is a schematic cross-sectional view showing a fan-in type semiconductor package embedded in an interposer substrate and ultimately mounted on a mainboard of an electronic device;

[0015] Figure 7 is a schematic cross-sectional view showing a fan-out type semiconductor package;

[0016] Figure 8 is a schematic cross-sectional view showing a fan-out type semiconductor package mounted on a main board of an electronic device;

[0017] Figure 9 is a schematic cross-sectional view illustrating a semiconductor package according to an example embodiment of the present disclosure;

[0018] Figure 10 It is along Figure 9 A plan view of the semiconductor package taken along line II′;

[0019] 11A to 11D are cross-sectional views illustrating processes of a method of manufacturing a semiconductor package according to example embodiments;

[0020] Figure 12 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments;

[0021] Figure 13 It shows Figure 12 a plan view of a semiconductor package;

[0022] Figure 14 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments;

[0023] Figure 15 It shows Figure 14 a plan view of a semiconductor package; and

[0024] Figure 16 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes, sizes, etc. of components may be exaggerated or simplified for clarity.

[0026] electronic devices

[0027] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0028] Reference Figure 1 , the electronic device 1000 may house a motherboard 1010 therein. The motherboard 1010 may include chip-related components 1020, network-related components 1030, and other components 1040, etc., which are physically or electrically connected thereto. These components may be connected to other components described below via various signal lines 1090.

[0029] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, chip-related components 1020 may be combined with each other.

[0030] The network-related components 1030 may include components that implement protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (EV-DO), High-Speed Packet Access Plus (HSPA+), High-Speed Downlink Packet Access Plus (HSDPA+), High-Speed Uplink Packet Access Plus (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may include components that operate according to various other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the aforementioned chip-related component 1020 .

[0031] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, other components 1040 may be combined with the chip-related components 1020 or the network-related components 1030 described above.

[0032] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disc (CD) drive (not shown), a digital versatile disc (DVD) drive (not shown), etc. However, these other components are not limited thereto, and other components for various purposes may be included depending on the type of the electronic device 1000, etc.

[0033] The electronic device 1000 may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0034] Figure 2 is a schematic perspective view illustrating an example of an electronic device.

[0035] Reference Figure 2 , the semiconductor package can be used for various purposes in various electronic devices 1000 as described above. For example, a motherboard 1110 can be housed in a body 1101 of a smartphone 1100, and various electronic components 1120 can be physically or electrically connected to the motherboard 1110. In addition, other components (such as a camera module 1130) that may or may not be physically or electrically connected to the motherboard 1110 can be housed in the body 1101. Some of the electronic components 1120 may be chip-related components, and the semiconductor package 100 may be, for example, an application processor among the chip-related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0036] semiconductor packages

[0037] Typically, semiconductor chips integrate a large number of microelectronic circuits. However, the semiconductor chips themselves may not be usable as finished semiconductor products and may be damaged by external physical or chemical impacts. Therefore, semiconductor chips may not be used on their own and are instead packaged and used in electronic devices, etc.

[0038] The reason for the widespread use of semiconductor packaging is that, in terms of electrical connection, there is usually a difference in circuit width between the semiconductor chip and the mainboard of the electronic device. Specifically, the size of the connection pad (pad, or also called "pad" or "pad") of the semiconductor chip and the spacing between the connection pads of the semiconductor chip are very small, while the size of the component mounting pad of the mainboard used in the electronic device and the spacing between the component mounting pad of the mainboard are significantly larger than the size of the connection pad of the semiconductor chip and the spacing between the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and therefore, it is advantageous to use packaging technology to alleviate the difference in circuit width between the semiconductor chip and the mainboard.

[0039] Semiconductor packages manufactured by packaging technology may be classified into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and purposes.

[0040] Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.

[0041] Fan-in semiconductor packages

[0042] Figure 3A and Figure 3B is a schematic cross-sectional view showing a fan-in type semiconductor package before and after being packaged, Figure 4 A series of schematic cross-sectional views illustrating a packaging process for a fan-in semiconductor package are shown.

[0043] Reference Figures 3A to 4 Semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state, including: a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; connection pads 2222 formed on one surface of body 2221 and including a conductive material such as aluminum (Al); and a passivation layer 2223 (such as an oxide film or a nitride film) formed on one surface of body 2221 and covering at least a portion of connection pads 2222. In this case, since connection pads 2222 are very small, it may be difficult to mount the integrated circuit (IC) on a medium-sized printed circuit board (PCB) or a main board of an electronic device.

[0044] Therefore, depending on the size of the semiconductor chip 2220, a connecting member 2240 may be formed on the semiconductor chip 2220 to redistribute the connection pads 2222. The connecting member 2240 may be formed by forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin, forming a via hole 2243h that exposes the connection pads 2222, and then forming a wiring pattern 2242 and a via 2243. A passivation layer 2250 may then be formed to protect the connecting member 2240, and an opening 2251 may be formed to have an underbump metallurgy layer 2260 extending through the opening 2251. In other words, a fan-in semiconductor package 2200 including, for example, the semiconductor chip 2220, the connecting member 2240, the passivation layer 2250, and the underbump metallurgy layer 2260 may be manufactured through a series of processes.

[0045] As described above, a fan-in semiconductor package may have a package form in which all connection pads (e.g., input / output (I / O) terminals) of a semiconductor chip are arranged inside the semiconductor chip, may have excellent electrical characteristics, and may be produced at low cost. Therefore, many components installed in smartphones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smartphones have been developed to achieve fast signal transmission while having a compact size.

[0046] However, in a fan-in semiconductor package, since all the I / O terminals generally need to be provided inside the semiconductor chip, the fan-in semiconductor package has a large space limitation. Therefore, it may be difficult to apply this structure to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a small size. In addition, due to the above-mentioned disadvantages, it may not be possible to directly mount and use the fan-in semiconductor package on a mainboard of an electronic device. The reason is that even in the case where the size of the I / O terminals of the semiconductor chip and the spacing between the I / O terminals of the semiconductor chip are increased by a redistribution process, the size of the I / O terminals of the semiconductor chip and the spacing between the I / O terminals of the semiconductor chip may still be insufficient to mount the fan-in semiconductor package directly on the mainboard of the electronic device.

[0047] Figure 5 is a schematic cross-sectional view showing a fan-in type semiconductor package mounted on an interposer substrate and ultimately mounted on a mainboard of an electronic device, Figure 6 is a schematic cross-sectional view showing a fan-in type semiconductor package embedded in an interposer and ultimately mounted on a main board of an electronic device.

[0048] Reference Figure 5In the fan-in semiconductor package 2200, the connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 can be redistributed again through the interposer substrate 2301, and in a state where the fan-in semiconductor package 2200 is mounted on the interposer substrate 2301, the fan-in semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device. In this case, the solder balls 2270 and the like can be fixed by the underfill resin 2280 and the like, and the outer surface of the semiconductor chip 2220 can be covered with the encapsulant 2290 and the like. Optionally, referring to Figure 6 The fan-in semiconductor package 2200 can be embedded in a separate intermediate substrate 2302. In a state where the fan-in semiconductor package 2200 is embedded in the intermediate substrate 2302, the connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 can be redistributed again through the intermediate substrate 2302, and the fan-in semiconductor package 2200 can be finally mounted on a mainboard 2500 of an electronic device.

[0049] As described above, it may be difficult to directly mount and use a fan-in semiconductor package on a main board (e.g., 2500) of an electronic device. Therefore, the fan-in semiconductor package may be mounted on a separate interposer substrate (e.g., 2301 or 2302) and then mounted on the main board of the electronic device through a packaging process, or the fan-in semiconductor package may be mounted and used on the main board of the electronic device while being embedded in the interposer substrate.

[0050] Fan-out semiconductor packages

[0051] Figure 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

[0052] Reference Figure 7 In the fan-out semiconductor package 2100, for example, the outer surface of the semiconductor chip 2120 may be protected by an encapsulant 2130, and the connection pads 2122 of the semiconductor chip 2120 may be redistributed to the outside of the semiconductor chip 2120 via a connection member 2140. In this case, a passivation layer 2150 may be further formed on the connection member 2140, and an under-bump metallurgy layer 2160 may be further formed in an opening of the passivation layer 2150. Solder balls 2170 may be further formed on the under-bump metallurgy layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, connection pads 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and vias 2143 electrically connecting the connection pads 2122 and the redistribution layer 2142 to each other.

[0053] In this manufacturing process, the connection member 2140 may be formed after the encapsulant 2130 is formed outside the semiconductor chip 2120. In this case, the process for forming the connection member 2140 is performed to form a redistribution layer 2142 and vias connecting the redistribution layer and the connection pads 2122 of the semiconductor chip 2120 to each other. Therefore, the vias 2143 may have a width that decreases toward the semiconductor chip 2120 (see the enlarged area).

[0054] As described above, a fan-out semiconductor package may have a form in which the I / O terminals of the semiconductor chip are redistributed and arranged outside the semiconductor chip 2120 via a connection member 2140 formed on the semiconductor chip 2120. As described above, in a fan-in semiconductor package, all of the I / O terminals of the semiconductor chip generally need to be arranged inside the semiconductor chip (e.g., within the footprint of the semiconductor chip on the package). Therefore, when the size of the semiconductor chip is reduced, the size and pitch of the balls generally need to be reduced, making it impossible to use a standardized ball layout in a fan-in semiconductor package. On the other hand, a fan-out semiconductor package has a form in which the I / O terminals of the semiconductor chip 2120 are redistributed and arranged outside the semiconductor chip 2120 (e.g., arranged outward from the footprint of the semiconductor chip) via a connection member 2140 formed on the semiconductor chip as described above. Therefore, even when the size of the semiconductor chip 2120 is reduced, the standardized ball layout can still be used as is in the fan-out semiconductor package, allowing the fan-out semiconductor package to be mounted on the mainboard of an electronic device without using a separate interposer substrate, as described below.

[0055] Figure 8 is a schematic cross-sectional view showing a fan-out type semiconductor package mounted on a main board of an electronic device.

[0056] Reference Figure 8 , the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device via solder balls 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the connection member 2140 formed on the semiconductor chip 2120 and capable of redistributing the connection pads 2122 to a fan-out area outside the area / footprint of the semiconductor chip 2120, so that a standardized ball layout can be used as is in the fan-out type semiconductor package 2100. As a result, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate interposer substrate or the like.

[0057] As described above, since the fan-out semiconductor package can be mounted on the mainboard of the electronic device without using a separate interposer substrate, the fan-out semiconductor package can be implemented with a thickness smaller than that of the fan-in semiconductor package using an interposer substrate. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, making it particularly suitable for mobile products. Therefore, the fan-out semiconductor package can be implemented in a more compact form than a conventional package-on-package (POP) type using a printed circuit board (PCB), and can solve the problem caused by the occurrence of warping.

[0058] In addition, the fan-out semiconductor packaging technology refers to a packaging technology for mounting a semiconductor chip on a mainboard of an electronic device and protecting the semiconductor chip from external impact as described above. The fan-out semiconductor package is a concept different from the concept of a printed circuit board (PCB) such as an interposer substrate (which has specifications, uses, etc. different from those of the fan-out semiconductor package and in which the fan-in semiconductor package is embedded).

[0059] Figure 9 is a schematic cross-sectional view of a semiconductor package according to example embodiments, Figure 10 It is along Figure 9 A plan view of a semiconductor package taken along line II′.

[0060] Reference Figure 9 and Figure 10 The semiconductor package 100 according to the present exemplary embodiment includes a connection structure 140 having a first surface 140A and a second surface 140B opposite to each other; a semiconductor chip 120 disposed on the first surface 140A of the connection structure 140; and an encapsulant 130 disposed on the first surface 140A of the connection structure 140 and encapsulating the semiconductor chip 120. The encapsulant 130 includes an encapsulation portion encapsulating the semiconductor chip 120 and an insulating resin layer disposed on the encapsulation portion.

[0061] The connection structure 140 used in the present example embodiment includes a plurality of (eg, at least two) insulating layers 141 and a first redistribution layer 145 including two layers, and the connection pads 120P of the semiconductor chip 120 may be connected to the first redistribution layer 145 .

[0062] like Figure 9 As shown in FIG, the semiconductor package 100 includes a frame 110 having a first surface 110A and a second surface 110B opposite to each other; and a second redistribution layer 155 disposed on the first surface 110A of the frame 110 .

[0063] The frame 110 may be provided on the first surface 140A of the connection structure 140 and include a cavity 110H for accommodating the semiconductor chip 120 therein. The frame 110 includes a wiring structure for connecting the upper and lower surfaces of the frame 110 to each other. The wiring structure used in this exemplary embodiment may include three layers of wiring patterns 112a, 112b, and 112c and first wiring vias 113a and second wiring vias 113b for connecting the wiring patterns 112a, 112b, and 112c to each other, but is not limited thereto. In another embodiment (see Figure 16 ), the wiring structure may include a different number of layers or may be formed in a different structure. The wiring structure of the frame 110 (specifically, the first wiring pattern 112a) may be connected to the first redistribution layer 145 of the connection structure 140.

[0064] In this example embodiment, the encapsulant 130 extends to cover the lower surface of the frame 110. A second redistribution layer 155 may be provided on the encapsulant 130 and electrically connected to the wiring structure (specifically, the third wiring pattern 112c). The second redistribution layer 155 may include a redistribution pattern 152 provided on the encapsulant 130, and include redistribution vias 153 that pass through an extended portion of the encapsulant 130 and are connected to the third wiring pattern 112c.

[0065] The heat dissipation system used in this exemplary embodiment may include a heat dissipation element 195 disposed on the second surface 140B of the connection structure 140. The heat dissipation element 195 may be bonded to the connection structure 140 using an adhesive layer 191. For example, the adhesive layer 191 may include a thermal interface material (TIM). If the adhesive layer 191 is conductive, an additional insulating layer (e.g., a passivation layer) may be present on the connection structure 140.

[0066] Since the active surface of semiconductor chip 120 (the surface of semiconductor chip 120 on which connection pads 120P are provided) serves as a heat source, as shown in this exemplary embodiment, heat dissipation element 195 may be provided on connection structure 140 to reduce the distance from the active surface of semiconductor chip 120, thereby significantly improving heat dissipation. Although connection structure 140 is located between semiconductor chip 120 and heat dissipation element 195, connection structure 140 is less likely to hinder heat dissipation because it includes first redistribution layer 145, which is relatively thin and formed using a highly thermally conductive metal (e.g., Cu).

[0067] like Figure 9 and Figure 10As shown in , the heat dissipation element 195 may have a surface area corresponding to the surface area of the connection structure 140. For example, the heat dissipation element 195 may be provided to substantially cover the entire surface area of the second surface 140B of the connection structure 140, but is not limited thereto. For example, the heat dissipation element 195 may be provided to cover only a portion of the second surface 140B of the connection structure 140, in which case the remaining portion of the second surface 140B may be provided as an area for mounting surface-mounted components (such as passive components) (see FIG. Figure 12 and Figure 14 ).

[0068] Hereinafter, main components of the semiconductor package 100 according to the present example embodiment will be described in more detail.

[0069] Depending on the material used to form the frame 110, the frame 110 can be used to further enhance the rigidity of the semiconductor package 100 and can also serve other functions (such as ensuring a uniform thickness of the encapsulant 130). The semiconductor chip 120 disposed within the cavity 110H of the frame 110 can be spaced apart from the inner sidewall of the frame 110 by a predetermined distance. The frame 110 can be provided to surround the side surface of the semiconductor chip 120. However, the frame 110 is not limited thereto and can be variously modified in other forms to perform other functions.

[0070] The frame 110 includes a first insulating layer 111a adjacent to the connection structure 140; a first wiring pattern 112a adjacent to the connection structure 140 and embedded in the first insulating layer 111a; a second wiring pattern 112b disposed on a surface of the first insulating layer 111a opposite the surface of the first insulating layer 111a in which the first wiring pattern 112a is embedded; a second insulating layer 111b disposed on the first insulating layer 111a and covering the second wiring pattern 112b; and a third wiring pattern 112c disposed on the second insulating layer 111b. The first wiring pattern 112a, the second wiring pattern 112b, and the third wiring pattern 112c are electrically connected to each other via a first wiring via 113a passing through the first insulating layer 111a and a second wiring via 113b passing through the second insulating layer 111b. The first wiring pattern 112a and the third wiring pattern 112c can be electrically connected to the first redistribution layer 145 and the second redistribution layer 155, respectively.

[0071] When the first wiring pattern 112a is embedded in the first insulating layer 111a, as in the present exemplary embodiment, the step formed by the thickness of the first wiring pattern 112a can be significantly reduced, and the insulation distance of the connection structure 140 can thereby be made more uniform. The first wiring pattern 112a can be recessed into the first insulating layer 111a, so that the one surface of the first insulating layer 111a and the upper surface of the first wiring pattern 112a can have a step formed therebetween. In this case, such a step can be used to prevent the material of the encapsulant 130 from seeping out and contaminating the first wiring pattern 112a. Since the connection structure 140 is manufactured to a small thickness using a semiconductor process, etc., while the frame 110 can be manufactured to a sufficient thickness using a substrate process, the thickness of each of the first wiring pattern 112a, the second wiring pattern 112b, and the third wiring pattern 112c of the frame 110 can be greater than the thickness of each of the redistribution patterns 142 of the connection structure 140.

[0072] For example, the first insulating layer 111a and the second insulating layer 111b may use a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler or impregnated with an inorganic filler in a core material such as glass fiber, glass cloth, and glass fabric (for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, and bismaleimide triazine (BT)). Alternatively, in some example embodiments, a photosensitive dielectric (PID) resin may be used for the first insulating layer 111a and the second insulating layer 111b. In terms of maintaining rigidity, a prepreg may be preferably used for the first insulating layer 111a and the second insulating layer 111b.

[0073] The first wiring pattern 112a, the second wiring pattern 112b, and the third wiring pattern 112c can be used to redistribute the connection pads 120P of the semiconductor chip 120. The first wiring pattern 112a, the second wiring pattern 112b, and the third wiring pattern 112c may contain conductive materials (such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti), or alloys thereof). The first wiring pattern 112a, the second wiring pattern 112b, and the third wiring pattern 112c can perform various functions according to the design of the corresponding layer. For example, each of the first wiring pattern 112a, the second wiring pattern 112b, and the third wiring pattern 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Specifically, the S pattern includes various signal patterns (such as data signal patterns) in addition to the GND pattern, the PWR pattern, etc. In addition, the first wiring pattern 112 a , the second wiring pattern 112 b , and the third wiring pattern 112 c may include a via pad, a wiring pad, a ball pad, and the like.

[0074] The first wiring vias 113a and the second wiring vias 113b can electrically connect the first wiring pattern 112a, the second wiring pattern 112b, and the third wiring pattern 112c formed on different insulating layers 111a and 111b to each other, thereby forming a wiring structure having an interlayer connection path within the frame 110. The first wiring vias 113a and the second wiring vias 113b can be formed using at least one of the above-mentioned conductive materials. Each of the first wiring vias 113a and the second wiring vias 113b can be a filled-type via filled with a conductive material, or a conformal via in which the conductive material is formed along the inner wall of each of the vias. In addition, depending on the process, when viewed in cross section, the first wiring vias 113a and the second wiring vias 113b can have a tapered shape with the same tapering direction as each other (i.e., a tapered shape in which the width of the upper portion is smaller than the width of the lower portion). When formed through the same plating process, the first and second wiring vias 113 a and 113 b may be integrated with the second and third wiring patterns 112 b and 112 c , respectively.

[0075] The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. For example, the IC may be a processor chip such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc. More specifically, the semiconductor chip 120 may be an application processor (AP), but is not limited thereto. The semiconductor chip 120 may be a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc., a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), etc., or other types of chips such as a power management IC (PMIC), or a combination thereof may be used for the semiconductor chip 120.

[0076] The semiconductor chip 120 can be formed using an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. can be used as the base material for forming the main body 121. The main body 121 can have various circuits formed therein. The connection pads 120P are used to electrically connect the semiconductor chip 120 to other components and can be formed using conductive materials (such as aluminum (Al) and copper (Cu)) but are not limited thereto. A passivation layer that opens the connection pads 120P can be formed on the active surface of the main body. The passivation layer can be an oxide layer, a nitride layer, etc., or can have a double layer including both an oxide layer and a nitride layer. Due to the thickness of the passivation layer, the upper surface of the connection pad 120P may have a step relative to the upper surface of the encapsulant 130. Therefore, the encapsulant 130 can fill at least a portion of the space between the passivation layer and the connection structure 140. In this case, the encapsulant 130 can be prevented from seeping onto the upper surface of the connection pad 120P to a certain extent. An insulating layer (not shown) may be further provided on other suitable areas. Since the semiconductor chip 120 may be a bare die, the connection pads 120P may be in physical contact with the redistribution vias 143 of the connection structure 140. Depending on the type of the semiconductor chip 120, an additional redistribution layer (not shown) may be present on an active surface of the semiconductor chip 120, and the semiconductor chip 120 may have a structure in which bumps (not shown) or the like are connected to the connection pads 120P.

[0077] The encapsulant 130 may be used to protect the frame 110, the semiconductor chip 120, and the like. The encapsulation form of the encapsulant 130 is not limited to any particular form, as long as it surrounds at least a portion of each of the frame 110 and the semiconductor chip 120. For example, the encapsulant 130 may cover the inactive surfaces of the frame 110 and the semiconductor chip 120 (surfaces on which the connection pads 120P are not formed) and fill at least a portion of the cavity 110H. Since the encapsulant 130 fills the cavity 110H, depending on the type of material forming the encapsulant 130, the encapsulant 130 may function as an adhesive while also reducing buckling of the semiconductor chip 120.

[0078] For example, the material of the encapsulant 130 may be, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler or impregnated with an inorganic filler in a core material (such as glass fiber), but is not limited thereto. In some example embodiments, the material of the encapsulant 130 may be a curable resin (such as prepreg, ABF, FR-4, and BT, or a photosensitive insulating epoxy (PIE) resin).

[0079] The first redistribution layer 145 of the connection structure 140 can redistribute the connection pads 120P of the semiconductor chip 120. Tens to hundreds of connection pads 120P having various functions of the semiconductor chip 120 can be redistributed through the connection structure 140 and can be physically and / or electrically connected to external components through the electrical connection metal 170 according to their functions.

[0080] The connection structure 140 includes: an insulating layer 141 disposed adjacent to the frame 110 and the semiconductor chip 120; a redistribution pattern 142 disposed on the insulating layer 141; and a redistribution via 143 passing through the insulating layer 141 to connect the connection pad 120P and the redistribution pattern 142 to each other. Figure 9 , the connection structure 140 is illustrated as including two insulating layers 141 and the first redistribution layer 145 having two layers, but in other example embodiments, the first redistribution layer 145 may be implemented as a single layer or three or more layers.

[0081] The insulating layer 141 can be formed using a material other than the above-mentioned insulating material, such as a photosensitive insulating material (e.g., PID resin). When the insulating layer 141 has a photosensitive property, the insulating layer 141 can be manufactured thinner, thereby facilitating the realization of a fine pitch of the redistribution via 143. In some example embodiments, each of the insulating layers 141 can be a photosensitive insulating layer including an insulating resin and an inorganic filler. If the insulating layers 141 are provided as multiple layers, they can be the same material or different materials from each other as needed. The insulating layer 141 provided as a multiple layer can be processed so that the boundary between two adjacent insulating layers 141 is not obvious.

[0082] The first redistribution layer 145 can be used to substantially redistribute the connection pads 120P and can be formed using at least one of the aforementioned conductive materials. Depending on the design of the corresponding layer, the first redistribution layer 145 can perform various functions. For example, the first redistribution layer 145 may include a GND pattern, a PWR pattern, an S pattern, etc. The S pattern includes various signal patterns (such as a data signal pattern) in addition to the GND pattern and the PWR pattern, and can include pad patterns of various shapes as needed.

[0083] The redistribution vias 143 can electrically connect the redistribution patterns 142 and the connection pads 120P provided on different layers, and can form an electrical path in the vertical (interlayer) direction within the semiconductor package 100. The redistribution vias 143 can be formed using at least one of the above-mentioned conductive materials. The redistribution vias 143 can be completely filled with a conductive material, or can be formed using a conductive material formed along the wall of each of the via holes. Each of the redistribution vias 143 of the connection structure 140 can have a tapered shape that tapers in a direction opposite to the direction of the first wiring vias 113a and the second wiring vias 113b. More specifically, each of the redistribution vias 143 can have a tapered cross-sectional shape in which the width at the first surface 140A is smaller than the width at the second surface 140B.

[0084] As described above, the second redistribution layer 155 may be disposed on the encapsulant 130 and connected to the wiring structure of the frame 110 (specifically, the third wiring pattern 112c). The redistribution vias 153 pass through at least a portion of the encapsulant 130 to electrically connect the redistribution pattern 152 to the third wiring pattern 112c (the third wiring pattern 112c is the lowest wiring pattern of the frame 110). The materials forming the redistribution pattern 152 and the redistribution vias 153 also include the above-mentioned conductive materials, and in some example embodiments may include metals such as copper (Cu). In addition, the redistribution pattern 152 and the redistribution vias 153 may each be a plurality of conductive layers including a seed layer and a plating layer. Depending on the design of the corresponding layers, the redistribution pattern 152 may perform various functions. For example, the redistribution pattern 152 may include a GND pattern, a PWR pattern, an S pattern, etc. When viewed in cross section, each of the redistribution vias 153 may have a tapered shape that tapers toward the frame 110.

[0085] The passivation layer 180 may be used to protect the second redistribution layer 155 from external physical or chemical damage. The passivation layer 180 may include at least one of the above-mentioned insulating materials. In some example embodiments, the passivation layer 180 may include prepreg, ABF, FR-4, BT, solder resist, or PID resin. The passivation layer 180 may have a plurality of openings that partially expose the second redistribution layer 155.

[0086] The semiconductor package 100 may further include a plurality of under bump metallurgy (UBM) layers 160 connected to a portion of the second redistribution layer 155 through the plurality of openings; and a plurality of electrical connection metals 170 respectively disposed on the plurality of UBM layers 160 .

[0087] The UBM layer 160 may be formed in the opening of the passivation layer 180 by a metallization method known in the art using a conductive material known in the art, such as metal. However, the method of forming the UBM layer 160 is not limited thereto.

[0088] The number, spacing, and arrangement of the electrical connection metals 170 are not particularly limited and can be modified by those skilled in the art according to the design details of the corresponding layer. For example, the number of electrical connection metals 170 can range from tens to thousands, or can be greater or less than the above range, depending on the number of connection pads 120P.

[0089] Electrical connection metal 170 is used to physically and / or electrically connect semiconductor package 100 to an external component (such as a motherboard of an electronic device). Electrical connection metal 170 may include solder of a low-melting-point metal, such as tin (Sn)-aluminum (Al)-copper (Cu) solder. Electrical connection metal 170 may have a single layer or multiple layers. For example, a multi-layer structure may include copper pillars and solder, while a single layer may include tin-silver solder or copper.

[0090] The electrical connection metal 170 is shown as having a ball shape, but may have other structures with a fixed length, such as pads or pins. Therefore, a fixed amount of space can be ensured for mounting components under the insulating layer 141 due to the length of the electrical connection metal 170.

[0091] At least one of the electrical connection metals 170 is disposed in the fan-out region. The fan-out region refers to a region outside the region overlapping the semiconductor chip 120. Compared to fan-in packages, fan-out packages have excellent reliability, can implement multiple I / O terminals, and can easily implement 3D interconnection. In addition, compared to packages such as ball grid array (BGA) packages and land grid array (LGA) packages, fan-out packages can be manufactured with a smaller thickness and can have a competitive cost.

[0092] In some example embodiments, a metal layer may be additionally formed on the wall of the cavity 110H for the purpose of heat dissipation and electromagnetic wave shielding. Figure 910H, other semiconductor chips that perform the same function or functions different from each other may be additionally provided in the cavity 110H. In some example embodiments, there may be a plurality of cavities 110H, and a semiconductor chip 120 and / or a surface mount component may be provided in each of the plurality of cavities 110H. The surface mount components may include passive components such as inductors and capacitors. As described above, the area for placing the heat dissipation element 195 can be adjusted to ensure more space for the surface mount components (see FIG. 10H ). Figure 12 and Figure 14 ).

[0093] 11A to 11D are cross-sectional views illustrating processes of a method of manufacturing a semiconductor package according to example embodiments.

[0094] Reference Figure 11A , the semiconductor chip 120 and the frame 110 having the cavity 110H accommodating the semiconductor chip 120 therein are disposed on the first adhesive film 210 , and then the encapsulant 130 is formed to encapsulate the semiconductor chip 120 .

[0095] As described above, in addition to the first insulating layer 111a and the second insulating layer 111b, the frame 110 used in this exemplary embodiment also includes a wiring structure. The wiring structure includes wiring patterns 112a, 112b, and 112c, and wiring vias 113a and 113b that connect the wiring patterns 112a, 112b, and 112c to each other. A first adhesive film 210 is attached to the lower surface of the first insulating layer 111a. For example, the first adhesive film 210 can be a tape containing epoxy resin or the like. The semiconductor chip 120 is mounted in the cavity 110H of the frame 110, and then an encapsulant 130 can be formed using a suitable encapsulation material to encapsulate the semiconductor chip 120. The encapsulant 130 can extend onto the upper surface of the frame 110 and cover the third wiring pattern 112c.

[0096] Next, refer to Figure 11B , the second adhesive film 220 is attached to the upper surface of the encapsulant 130 , and after removing the first adhesive film 210 , the connection structure 140 is formed on the surface from which the first adhesive film 210 has been removed.

[0097] More specifically, the connection structure 140 may be formed by forming the insulating layer 141 using a lamination method or a coating method, then forming via holes in the insulating layer 141, and then forming the redistribution pattern 142 and the redistribution via holes 143 by electroplating or electroless plating. When PID resin is used for the insulating layer 141, the via holes may be formed by photolithography to achieve a fine pitch.

[0098] Next, refer to Figure 11C, the third adhesive film 230 is attached to the second surface 140B of the connection structure 140. After the second adhesive film 220 is removed, the second redistribution layer 155, the passivation layer 180, and the UBM layer 160 are formed on the surface from which the second adhesive film 220 has been removed.

[0099] More specifically, a second redistribution layer 155 connected to the wiring structure is formed on the encapsulant 130, and the second redistribution layer 155 includes redistribution vias 153 and redistribution patterns 152. A passivation layer 180 is formed on the encapsulant 130 to cover the second redistribution layer 155, and a plurality of openings are formed in the passivation layer 180 to expose portions of the redistribution patterns 152. A UBM layer 160 is formed on the passivation layer 180, such that the UBM layer 160 is connected to the redistribution patterns 152 through the plurality of openings. Next, an electrical connection metal 170 may be formed on the UBM layer 160. Alternatively, the process of forming the electrical connection metal 170 may be performed in a subsequent process after the process of attaching the heat dissipation member 195.

[0100] Next, refer to Figure 11D , the third adhesive film 230 is removed from the connection structure 140 , and the heat dissipation member 195 is formed on the surface from which the third adhesive film 230 has been removed.

[0101] After removing the third adhesive film 230, the heat dissipation element 195 is attached to the upper surface of the encapsulant 130 by using the adhesive layer 191. The adhesive layer 191 may include a thermal interface material (TIM). Therefore, since the effective surface of the semiconductor chip 120 is arranged adjacent to the heat dissipation element 195 and a relatively thin connection structure 140 is provided between them, the heat dissipation effect can be significantly improved. Although in the above description, the adhesive layer 191 is attached to the connection structure 140 after removing the third adhesive film 230, it is not limited thereto. Figure 11B As shown in , the adhesive layer 191 may be attached to the connection structure 140 after forming the connection structure 140 and before forming the third adhesive film 230, and as shown in FIG. Figure 11C As shown in FIG, the third adhesive film 230 may be attached to the adhesive layer 191. In this case, the heat dissipation member 195 may be attached to the adhesive layer 191 after the third adhesive film 230 is removed.

[0102] Furthermore, a series of the above-described processes can be performed at a panel level, and by modifying the cutting process, a plurality of semiconductor packages 100 can be manufactured in a single process.

[0103] The heat dissipation system used in this exemplary embodiment can be modified and implemented in various ways. For example, the region on which the heat dissipation element is formed can be modified in various ways.

[0104] Figure 12is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments, Figure 13 yes Figure 12 A plan view of a semiconductor package.

[0105] Reference Figure 12 and Figure 13 , except that the heat dissipation member 195A is formed only on the inner region of the second surface 140B of the connection structure 140 and the surface mount component 185 is provided on the outer region of the second surface 140B of the connection structure 140, the semiconductor package 100A according to the present example embodiment can be understood as similar to Figure 9 and Figure 10 Unless otherwise indicated, reference is made to Figure 9 and Figure 10 The components in this example embodiment may be better understood by referring to the description of the same or similar components described above with reference to the semiconductor package 100 shown in FIG.

[0106] In this exemplary embodiment, the second surface 140B of the connection structure 140 can be divided into a first region 140B1 and a second region 140B2 surrounding the first region 140B1, and the heat dissipation element 195A can be provided on the first region 140B1 so that the second region 140B2 of the connection structure 140 remains exposed. The first region 140B1 on which the heat dissipation element 195A is provided overlaps the semiconductor chip 120, thereby serving as an effective heat dissipation path. According to this exemplary embodiment, the region (first region 140B1) on which the heat dissipation element 195A is provided can have a sufficient surface area to cover the region overlapping the semiconductor chip 120.

[0107] A plurality of surface mount components 185 may be disposed on the second region 140B2 of the connection structure 140 and electrically connected to the first redistribution layer 145. For example, the surface mount components 185 may include passive components such as inductors and capacitors. As described in this exemplary embodiment, the surface mount components 185 can be positioned using the corner portion (second region 140B2) adjacent to the region of the connection structure 140 on which the heat dissipation element 195A is formed.

[0108] Figure 14 is a schematic cross-sectional view illustrating a semiconductor package according to an example embodiment of the present disclosure, Figure 15 yes Figure 14 A plan view of a semiconductor package.

[0109] Reference Figure 14 and Figure 15, except that the heat dissipation member 195B has the through hole H opening the inner area of the second surface 140B of the connection structure 140 and the surface mount component 185 is provided on the inner area of the second surface 140B of the connection structure 140, the semiconductor package 100B according to the present example embodiment can be understood as Figure 9 and Figure 10 Unless otherwise indicated, reference is made to Figure 9 and Figure 10 The components in this example embodiment may be better understood by referring to the description of the same or similar components described above with reference to the semiconductor package 100 shown in FIG.

[0110] In the present example embodiment, the heat dissipation member 195B may have a structure having a through hole H. The second surface 140B of the connection structure 140 may be divided into a first region 140B1 and a second region 140B2 surrounding the first region 140B1, and the heat dissipation member 195B may be disposed on the second surface 140B of the connection structure 140 such that the first region 140B1 of the connection structure 140 is exposed through the through hole H of the heat dissipation member 195B. To improve heat dissipation efficiency, the second region 140B2 on which the heat dissipation member 195B is disposed may be disposed to overlap at least a portion of the semiconductor chip 120.

[0111] A plurality of surface mount components 185 may be disposed on the first region 140B1 of the connection structure 140 and electrically connected to the first redistribution layer 145. In this example embodiment, the heat dissipation member 195B may have reduced heat dissipation performance due to having a smaller area overlapping the semiconductor chip 120 than in the previous example embodiments; however, since the surface mount components 185 are disposed on the first region 140B1 (a region adjacent to the corner of the connection member 140 where the heat dissipation member 195B is disposed), the surface mount components can be more conveniently accommodated.

[0112] Figure 16 is a schematic cross-sectional view of a semiconductor package according to an example embodiment of the present disclosure.

[0113] Reference Figure 16 , except that the surface mount component 185 is disposed on the second redistribution layer 155 and the frame 110 has a different wiring structure, the semiconductor package 100C according to this example embodiment can be understood as similar to Figure 9 and Figure 10 Unless otherwise indicated, reference is made to Figure 9 and Figure 10 The components in this example embodiment may be better understood by referring to the description of the same or similar components described above with reference to the semiconductor package 100 shown in FIG.

[0114] Reference Figure 16 , a plurality of surface mount components 185 may be provided on an area overlapping the semiconductor chip 120 and connected to the second redistribution layer 155. In the present example embodiment, in addition to the first opening O1 for the UBM layer 160, a second opening O2 for the surface mount components 185 may also be formed in the passivation layer 180, and a plurality of surface mount components 185 may be provided thereon to be connected to the redistribution pattern 152 exposed through the second opening O2. Although a plurality of surface mount components 185 are shown as being provided in the present example embodiment and the other example embodiments described above, a single surface mount component may be provided as needed.

[0115] The frame 110 used in this exemplary embodiment may have a modified structure, and the wiring structure therein may be modified accordingly. More specifically, the frame 110 includes: a first insulating layer 111a; a first wiring pattern 112a, which is provided on one surface of the first insulating layer 111a; a second wiring pattern 112b, which is provided on the other surface of the first insulating layer 111a; a second insulating layer 111b, which is provided on the one surface of the first insulating layer 111a and covers at least a portion of the first wiring pattern 112a; a third wiring pattern 112c, which is provided on the other surface of the second insulating layer 111b opposite to the one surface of the second insulating layer 111b in which the first wiring pattern 112a is embedded; and a third insulating layer 111c, which is provided on the other surface of the first insulating layer 111a and covers the second insulating layer 111b. At least a portion of the wiring pattern 112b; a fourth wiring pattern 112d disposed on a surface of the third insulating layer 111c opposite to a surface of the third insulating layer 111c in which the second wiring pattern 112b is embedded; a first wiring via 113a passing through the first insulating layer 111a to electrically connect the first wiring pattern 112a and the second wiring pattern 112b to each other; a second wiring via 113b passing through the second insulating layer 111b to electrically connect the first wiring pattern 112a and the third wiring pattern 112c to each other; and a third wiring via 113c passing through the third insulating layer 111c to electrically connect the second wiring pattern 112b and the fourth wiring pattern 112d to each other. Therefore, the frame 110 used in this exemplary embodiment accommodates a relatively large number of wiring patterns 112a, 112b, 112c, and 112d, and thus can further simplify the first redistribution layer 145 of the connection structure 140.

[0116] The thickness of the first insulating layer 111a may be greater than the thickness of each of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain basic rigidity, and may include the second insulating layer 111b and the third insulating layer 111c to accommodate a large number of wiring patterns 112c and 112d. The first insulating layer 111a may include an insulating material different from the insulating material of the second insulating layer 111b or the third insulating layer 111c. For example, the first insulating layer 111a may be a prepreg including a core material (such as glass fiber), an inorganic filler, and an insulating resin, while the second insulating layer 111b and the third insulating layer 111c may each be a PID resin or ABF including an inorganic filler and an insulating resin. However, the first insulating layer 111a, the second insulating layer 111b, and the third insulating layer 111c are not limited thereto. Similarly, the diameter of the first wiring via 113a passing through the first insulating layer 111a can be larger than the diameter of each of the second wiring via 113b passing through the second insulating layer 111b and the third wiring via 113c passing through the third insulating layer 111c. Furthermore, the first wiring via 113a can have a shape similar to an hourglass or a cylinder, and the second wiring via 113b and the third wiring via 113c can have shapes that taper in opposite directions. The thickness of the first wiring pattern 112a, the second wiring pattern 112b, the third wiring pattern 112c, and the fourth wiring pattern 112d can each be greater than the thickness of the redistribution pattern 142 of the connection structure 140.

[0117] According to example embodiments disclosed herein, a semiconductor package may be provided that has significantly improved heat dissipation characteristics by having a heat dissipation member disposed adjacent to an active surface of a semiconductor chip.

[0118] For convenience, the terms "lower side," "lower portion," "lower surface," etc. are used herein to refer to a downward direction with respect to a cross section of the drawings, while the terms "upper side," "upper portion," "upper surface," etc. are used herein to refer to a direction opposite to the downward direction. However, these directions are defined for convenience of description, and the claims are not particularly limited to the directions defined above, and the concepts of upper and lower are interchangeable.

[0119] Throughout this specification, statements that an element is “connected to” or “bonded to” another element include situations where the element is indirectly connected or bonded to the other element through an adhesive layer or the like, as well as situations where the element is directly connected or bonded to the other element. In addition, when an element is “electrically connected” to another element, the element may or may not be physically connected to the other element. In addition, the terms “first,” “second,” and any variations thereof as used herein do not indicate any order or importance of the elements, but are instead used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0120] The term "exemplary embodiment" as used herein does not refer to the same exemplary embodiment, but is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another exemplary embodiment. However, the exemplary embodiments described herein can be implemented by combining them in whole or in part. For example, unless otherwise stated, an element described in a particular exemplary embodiment can be understood as being related to another exemplary embodiment even if it is not described in another exemplary embodiment.

[0121] The terms used herein are for illustrating example embodiments only and do not limit the scope of the present disclosure.In addition, the use of the singular includes the plural unless specifically stated otherwise.

[0122] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A semiconductor package, comprising: a connection structure having a first surface and a second surface and comprising a first redistribution layer, wherein the first surface of the connection structure and the second surface of the connection structure are opposite to each other; a semiconductor chip disposed on the first surface of the connection structure and comprising connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first redistribution layer and the second redistribution layer to each other and extending along a stacking direction; and a heat dissipation element, disposed on at least a portion of the second surface of the connection structure, The second surface of the connection structure includes a first area and a second area surrounding the first area, the first area includes an area overlapping the semiconductor chip in the stacking direction, The heat dissipation element is arranged on the first area to expose the second area of the connection structure, and the semiconductor package further includes at least one surface mount component, which is arranged on the second area of the connection structure and connected to the first redistribution layer.

2. The semiconductor package of claim 1 , further comprising at least one surface mount component connected to the second redistribution layer and disposed on a region overlapping the semiconductor chip when viewed parallel to the stacking direction.

3. The semiconductor package according to claim 1 , further comprising a frame provided on the first surface of the connection structure and having a through hole for accommodating the semiconductor chip therein, wherein The wiring structure passes through the frame.

4. The semiconductor package according to claim 3, wherein The encapsulant includes an extension portion that covers another surface of the frame opposite to a surface that contacts the first surface of the connection structure, and the second redistribution layer includes: a redistribution pattern provided on the encapsulant; and a redistribution via that passes through the extension portion and is connected to the redistribution pattern.

5. The semiconductor package according to claim 3, in, The frame includes a first insulating layer and a second insulating layer stacked one on top of the other in sequence, Wherein, the wiring structure includes: a first wiring pattern provided in the first insulating layer and connected to the connection structure; a second wiring pattern provided on one surface of the first insulating layer, the one surface of the first insulating layer being a side opposite to a side on which the first wiring pattern is provided; a third wiring pattern provided on one surface of the second insulating layer, the one surface of the second insulating layer being a side opposite to the side on which the second wiring pattern is provided; a first wiring via that passes through the first insulating layer to connect the first wiring pattern and the second wiring pattern to each other; and A second wiring via passes through the second insulating layer to connect the second wiring pattern and the third wiring pattern to each other.

6. The semiconductor package according to claim 3, in, The frame includes: a first insulating layer; a second insulating layer provided on one surface of the first insulating layer; and a third insulating layer provided on the other surface of the first insulating layer, and Wherein, the wiring structure includes: a first wiring pattern provided on the one surface of the first insulating layer; a second wiring pattern provided on the other surface of the first insulating layer; a third wiring pattern, disposed on the second insulating layer; a fourth wiring pattern, disposed on the third insulating layer; a first wiring via hole passing through the first insulating layer to connect the first wiring pattern and the second wiring pattern to each other; a second wiring via that passes through the second insulating layer to connect the first wiring pattern and the third wiring pattern to each other; and A third wiring via passes through the third insulating layer to connect the second wiring pattern and the fourth wiring pattern to each other.

7. The semiconductor package according to claim 1, wherein The encapsulant includes an encapsulation part encapsulating the semiconductor chip, and includes an insulating resin layer provided on the encapsulation part.

8. The semiconductor package according to claim 1, further comprising: a passivation layer disposed on the encapsulant and covering the second redistribution layer; and a plurality of under bump metallurgy (UBM) layers, wherein the passivation layer includes a plurality of openings exposing portions of the second redistribution layer, and the plurality of UBM layers are connected to the portions of the second redistribution layer through the plurality of openings. 9 . The semiconductor package according to claim 8 , further comprising a plurality of electrical connection metals, wherein the plurality of electrical connection metals are respectively disposed on the plurality of under bump metallurgy layers.

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