A device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a memory and computing integrated chip

Abstract

The present invention provides a device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a compute-in-memory chip, which includes a digital-to-analog conversion circuit (DAC) module, an analog vector-matrix multiplication operation circuit (AMAC) module, an analog-to-digital conversion circuit (ADC) module, a first multi-to-one multiplexer (M1-MUX) module, a second multi-to-one multiplexer module, a first one-to-many multiplexer (1M-MUX) module, a second one-to-many multiplexer module, and a switching transistor module. At the input end of the AMAC, each DAC corresponds to multiple input ports, which are shared in a time-division multiplexing manner through the first M1-MUX module and the first 1M-MUX module; at the output end of the AMAC, each ADC corresponds to multiple output ports, which are shared in a time-division multiplexing manner through the second M1-MUX module and the second 1M-MUX module; the number of DACs and ADCs is reduced, and the chip area is reduced.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic integrated circuits, and particularly to a device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a memory-computing integrated chip. Background Art

[0002] The memory-computing integrated chip architecture is currently considered to be one of the efficient hardware platforms for solving real-time intelligent processing of big data, and analog vector-matrix multiplication is the core circuit of the memory-computing integrated chip, especially for the memory-computing integrated chip based on flash memory. For a typical analog vector-matrix multiplication circuit, since the signals it processes are analog signals, while the input signals and output signals are usually required to be digital signals, therefore, it is usually necessary to convert digital signals into analog signals through a digital-to-analog conversion circuit (DAC) at the input end, and convert the processed analog signals into digital signals through an analog-to-digital conversion circuit (ADC) at the output end, as Figure 1 shown.

[0003] However, the areas of high-precision DAC and ADC are usually very large. In a typical memory-computing integrated chip, it is required that each input end of the analog vector-matrix multiplication circuit is connected to a DAC, and each output end is connected to an ADC, as Figure 2 shown. This way greatly causes area waste and cost overhead. Summary of the Invention

[0004] In view of this, the present invention provides a device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a memory-computing integrated chip, which shares the DAC and ADC through a time-division multiplexing method, thereby effectively reducing the number of components, reducing the circuit area, reducing the cost overhead, and being beneficial to integration.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a memory-computing integrated chip includes a first multi-to-one multiplexer (M1-MUX) module, a digital-to-analog conversion circuit (DAC) module, and a first one-to-multi multiplexer (1M-MUX) module; wherein the input end of the DAC module is connected to the output end of the first M1-MUX module, and the output end of the DAC module is connected to the input end of the first 1M-MUX module;

[0007] The first M1-MUX module includes a plurality of first M1-MUX units for selecting one signal from multiple input ports as the output;

[0008] The first 1M-MUX module includes a plurality of first 1M-MUX units for outputting one input signal to different output ports;

[0009] The described DAC module includes multiple DAC units for converting digital signals into analog signals; the input ends of each DAC unit are connected to the output ends of corresponding first M1-MUX units, and the output ends of the DAC units are connected to the input ends of corresponding first 1M-MUX units;

[0010] Each of the described DAC units corresponds to multiple input ports and is shared with the corresponding first 1M-MUX unit in a time-division multiplexing manner through the corresponding first M1-MUX unit.

[0011] Furthermore, the multiplexing device further includes an analog vector-matrix multiplication operation circuit (AMAC) module and a switching transistor module; wherein, the output end of the first 1M-MUX module is connected to the input end of the AMAC module through the switching transistor module;

[0012] The described AMAC module is composed of programmable semiconductor devices, and the threshold voltage of each programmable semiconductor device can be dynamically programmed;

[0013] The described switching transistor module includes multiple switching transistor units for conducting or disconnecting the signal connection between the first 1M-MUX unit and the input end of the AMAC module;

[0014] Each row of the described AMAC module is respectively connected to its corresponding switching transistor unit.

[0015] Furthermore, the multiplexing device further includes a second M1-MUX module, an analog-to-digital conversion circuit (ADC) module, and a second 1M-MUX module; wherein, the input end of the ADC module is connected to the output end of the second M1-MUX, the output end of the ADC module is connected to the input end of the second 1M-MUX module, and the input end of the second M1-MUX module is connected to the output end of the AMAC module.

[0016] The described second M1-MUX module includes multiple second M1-MUX units for selecting one signal from multiple input ports as the output;

[0017] The described ADC module includes multiple ADC units;

[0018] The described second 1M-MUX module includes multiple second 1M-MUX units for outputting one input signal to different output ports.

[0019] Further, it further includes a controller, which is connected to the first M1-MUX module, the DAC module, the first 1M-MUX module, the AMAC module, the switching transistor module, the second M1-MUX module, the ADC module, and the second 1M-MUX module; it is used to control selecting one signal from multiple input signals as the output through the first and second M1-MUX units at each moment; it is used to control selecting one input signal and outputting it to different output ports through the first and second 1M-MUX units at each moment; it is used to control the opening and closing of the corresponding switching transistor unit at each moment.

[0020] The controller controls the switching transistor module, the first M1-MUX module connected to the DAC module, and the first 1M-MUX module in a time-division multiplexing manner to select the corresponding input signal and introduce it into the AMAC module; the controller controls the second M1-MUX module and the second 1M-MUX module connected to the ADC module in a time-division multiplexing manner to select the corresponding output signal at the output end of the AMAC module for output.

[0021] In the digital-to-analog conversion circuit and analog-to-digital conversion circuit multiplexing device in the memory-computation integrated chip provided by the present invention, by setting the first and second M1-MUX modules, the switching transistor module, and the first and second 1M-MUX modules, and adopting a specific connection relationship and control, it realizes sharing the DAC and ADC units in a time-division multiplexing manner, thereby effectively reducing the number of components, reducing the circuit area, reducing the cost overhead, and being conducive to integration.

[0022] To make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a structural block diagram of an analog vector-matrix multiplication operation circuit, a corresponding digital-to-analog conversion circuit, and an analog-to-digital conversion circuit in a typical memory-computation integrated chip;

[0025] Figure 2 It is an implementation diagram of an analog vector-matrix multiplication operation circuit, a corresponding digital-to-analog conversion circuit, and an analog-to-digital conversion circuit in a typical memory-computation integrated chip;

[0026] Figure 3Block diagram of an embodiment of a device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a memory-computing integrated chip according to the present invention;

[0027] Figure 4 Circuit diagram of an embodiment of a device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a memory-computing integrated chip according to the present invention;

[0028] Figure 5 Flowchart of a method for multiplexing a digital-to-analog conversion circuit in a memory-computing integrated chip according to the present invention;

[0029] Figure 6 Flowchart of a method for multiplexing an analog-to-digital conversion circuit in a memory-computing integrated chip according to the present invention; Detailed implementation manners

[0030] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] The analog vector-matrix multiplication circuit (AMAC) is the core circuit of the memory-computing integrated chip. In a typical AMAC, since the signals it processes are analog signals, while the input and output signals are usually required to be digital signals, generally, a digital-to-analog conversion circuit (DAC) is needed at the input end to convert the digital signal into an analog signal for input, and an analog-to-digital conversion circuit (ADC) is needed at the output end to convert the processed analog signal into a digital signal for output, as Figure 1 shown. In this way, it is required that each input end of the AMAC is connected to a DAC, and each output end is connected to an ADC, as Figure 2 shown. This method greatly causes area waste and cost overhead.

[0032] To solve the above technical problems in the prior art, an embodiment of the present invention provides a device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a memory-computing integrated chip, as Figure 3 shown, including a first M1-MUX module, a DAC module, a first 1M-MUX module, an AMAC module, a switching transistor module, a second M1-MUX module, an ADC module, and a second 1M-MUX module.

[0033] The AMAC includes: a programmable semiconductor device array;

[0034] Among them, the principle of the AMAC to implement analog vector-matrix multiplication is as follows: For an array of programmable semiconductor devices with M rows × N columns, the sources of all programmable semiconductor devices in each column are connected to the same analog voltage input terminal, and the N columns of programmable semiconductor devices are correspondingly connected to N analog voltage input terminals. The gates of all programmable semiconductor devices in each row are connected to the same bias voltage input terminal, and the M rows of programmable semiconductor devices are correspondingly connected to M bias voltage input terminals. The drains of all programmable semiconductor devices in each column are connected to the same analog current output terminal, and the N columns of programmable semiconductor devices are correspondingly connected to N analog current output terminals. Among them, the threshold voltage of each programmable semiconductor device can be adjusted. N is a positive integer greater than or equal to zero, M is a positive integer greater than or equal to zero, and M and N can be equal or unequal, thus forming a source-coupled and drain-summing topology structure.

[0035] Among them, by dynamically adjusting the threshold voltage V of each programmable semiconductor device according to a certain rule in advance TH , each programmable semiconductor device can be regarded as a variable equivalent analog weight (denoted as W k,j , where 0 < k < M and 0 < j < N respectively represent the row number and column number), which is equivalent to storing an analog data, while the programmable semiconductor device array stores an analog data array

[0036] When the circuit works, a row of analog voltage signals V1 to V N are respectively applied to the N columns of programmable semiconductor devices. Among them, the sources of all programmable semiconductor devices in the Kth column all receive an analog voltage signal V k , the gates receive a bias voltage V b , and the drains respectively output current signals I k,1 to I k,N . Among them, according to the characteristics of the programmable semiconductor device, I = V × W. The drain output current of each programmable semiconductor device is equal to the source voltage multiplied by the weight of this programmable semiconductor device, that is, I k,1 = V k W k,1 , I k,N = V k W k,N . Because the drains of all programmable semiconductor devices in each column are connected to the same analog current output terminal, according to Kirchhoff's law, the current I j at this analog current output terminal is the sum of the drain currents of all programmable semiconductor devices in this column, that is Multiple current sums are output from multiple analog current output terminals to achieve the matrix multiplication operation function.

[0037] Of course, the programmable semiconductor device array may also adopt a gate-coupled, source-summing topology or a gate-coupled, drain-summing topology, and the embodiments of the present invention do not limit this.

[0038] Next, the principle of the digital-to-analog conversion circuit and analog-to-digital conversion circuit multiplexing device according to the embodiments of the present invention will be described: As Figure 3 and Figure 4 shown, it includes a first M1-MUX module, a DAC module, a first 1M-MUX module, an AMAC module, a switching transistor module, a second M1-MUX module, an ADC module, and a second 1M-MUX module. Among them, the output end of the first M1-MUX module is connected to the input end of the DAC module, the output end of the DAC module is connected to the input end of the first 1M-MUX module, the output end of the first 1M-MUX module is connected to the input end of the AMAC module through the switching transistor module, the output end of the AMAC module is connected to the input end of the second M1-MUX module, the output end of the second M1-MUX module is connected to the input end of the ADC module, and the output end of the ADC module is connected to the input end of the second 1M-MUX module.

[0039] By sharing each DAC among multiple (e.g., T) input ends of the AMAC in a time-division multiplexing manner; similarly, sharing each ADC among multiple (e.g., P) output ends of the AMAC in a time-division multiplexing manner, so as to reduce the number of ADCs and DACs, thereby reducing the chip area. Here, T is usually a factor of 2 to M. For example, T takes values such as 2, 4, 6, 8, …, etc.; here, P is usually a factor of N. For example, P takes values such as 2, 4, 6, 8, …, etc. The values of T and P are determined according to the actual chip area and delay, etc.

[0040] The multiplexing method for the DAC is as follows: When M digital signals need to be input to the AMAC module, the controller controls the first M1-MUX module and the first 1M-MUX module connected to the DAC module, and at the same time controls the corresponding switching transistors to input the digital signals in a time-sharing manner. Specifically as follows (as Figure 5As shown in the figure: At the first moment, select the 1st, T+1, 2T+1, …, (M / T-1)T+1 digital signals, and at the same time turn on the switching transistor units in the corresponding rows of the AMAC module (the switching transistor units in other rows are turned off). The digital signals are converted into analog signals through the DAC module and input into the 1st, T+1, 2T+1, …, (M / T-1)T+1 rows of the AMAC module; then turn off the switching transistor units in the 1st, T+1, 2T+1, …, (M / T-1)T+1 rows to clamp the input signals of the current rows. At the second moment, select the 2nd, T+2, 2T+2, …, (M / T-1)T+2 digital signals, and at the same time turn on the switching transistor units in the corresponding rows of the AMAC module (the switching transistor units in other rows are turned off). The digital signals are converted into analog signals through the DAC module and input into the 2nd, T+2, 2T+2, …, (M / T-1)T+2 rows of the AMAC module; then turn off the switching transistor units in the 2nd, T+2, 2T+2, …, (M-1) / T+2 rows to clamp the input signals of the current rows; and so on until all digital signals are input into the AMAC module; finally, perform the analog vector-matrix multiplication operation.

[0041] The multiplexing method for the ADC is as follows (as Figure 6 shown in the figure): When the AMAC module needs to output the results of N analog vector-matrix multiplication operations, the controller controls the second M1-MUX module and the second 1M-MUX module connected to the ADC module to output the operation results time-divisionally. At the first moment, select the output ports of the 1st, P+1, 2P+1, …, (N / P-1) / P+1 columns of the AMAC module, and the corresponding analog signals are converted into digital signals through the ADC module for output; at the second moment, select the output ports of the 2nd, P+2, 2P+2, …, (N / P-1) / P+2 columns of the AMAC module, and the corresponding analog signals are converted into digital signals through the ADC module for output; and so on until the analog signals of all columns of the AMAC module are converted into digital signals and output through the ADC module.

[0042] If the existing solution is adopted, we need to connect a DAC unit to each row and an ADC unit to each column, so we need M DAC units and N ADC units. Usually, both M and N are relatively large, for example, 1024. However, by adopting the solution provided by the present invention, we only need M / T DAC units, N / P ADC units, (M / T) first M1-MUX units, (N / P) second M1-MUX units, (M / T) first 1M-MUX units, (N / P) second 1M-MUX units and M switching transistor units. It should be noted that the area of each (first and second) M1-MUX unit and (first and second) 1M-MUX unit is much smaller than the area of the ADC unit and the DAC unit. Those skilled in the art can understand that the larger M and N are, and the larger T and P are at the same time, the more obvious the advantages of the present invention are.

[0043] In an optional embodiment, it further includes: a programming circuit, connected to the source, gate and / or substrate of each programmable semiconductor device, for regulating the threshold voltage of the programmable semiconductor device.

[0044] In an optional embodiment, it further includes: a controller, controlling the multiplexing process of the above-mentioned DAC and DAC.

[0045] In the above embodiment, the programmable semiconductor device can adopt a floating-gate transistor.

[0046] In an optional embodiment, the analog vector-matrix multiplication operation circuit may further include: a conversion device, connected before a plurality of analog voltage input terminals, for respectively converting a plurality of analog current input signals into analog voltage input signals and outputting them to the corresponding analog voltage input terminals.

[0047] The above is only an example to illustrate the specific structures of the modules of the present invention. In specific implementation, the specific structures of the above modules are not limited to the above structures provided by the embodiments of the present invention, and may also be other structures known to those skilled in the art, which are not limited herein.

[0048] On the other hand, an embodiment of the present invention further provides a chip, which includes the above-mentioned analog vector-matrix multiplication operation circuit, a digital-to-analog conversion circuit and an analog-to-digital conversion circuit multiplexing device.

[0049] In addition, an embodiment of the present invention further provides an electronic device, which may include the above-mentioned analog vector-matrix multiplication operation circuit, a digital-to-analog conversion circuit and an analog-to-digital conversion circuit multiplexing device. More specifically, the electronic device may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device or any combination of these devices.

[0050] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, commodity or device comprising the said element.

[0051] In the present invention, specific embodiments are used to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only for helping to understand the method and its core idea of the present invention. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A device for multiplexing a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a compute-in-memory chip, characterized in that It includes an analog vector-matrix multiplication operation circuit module, a first many-to-one multiplexer module, a digital-to-analog conversion circuit module, a first one-to-many multiplexer module, a second many-to-one multiplexer module, an analog-to-digital conversion circuit module, and a second one-to-many multiplexer module. Among them, the first many-to-one multiplexer module is used to couple digital signal inputs. The input end of the digital-to-analog conversion circuit module is connected to the output end of the first many-to-one multiplexer module. The output end of the digital-to-analog conversion circuit module is connected to the input end of the first one-to-many multiplexer module. The output end of the first one-to-many multiplexer module is connected to the input end of the analog vector-matrix multiplication operation circuit module. Among them, the input end of the analog-to-digital conversion circuit module is connected to the output end of the second many-to-one multiplexer module. The output end of the analog-to-digital conversion circuit module is connected to the input end of the second one-to-many multiplexer module. The input end of the second many-to-one multiplexer module is connected to the output end of the analog vector-matrix multiplication operation circuit module. The second one-to-many multiplexer module is used to output digital signals. The first many-to-one multiplexer module described above includes a plurality of first many-to-one multiplexer units. The digital-to-analog conversion circuit module described above includes a plurality of digital-to-analog conversion circuit units. The first one-to-many multiplexer module described above includes a plurality of first one-to-many multiplexer units. The second many-to-one multiplexer module described above includes a plurality of second many-to-one multiplexer units. The analog-to-digital conversion circuit module described above includes a plurality of analog-to-digital conversion circuit units. The second one-to-many multiplexer module described above includes a plurality of second one-to-many multiplexer units. Among them, one digital-to-analog conversion circuit unit corresponds to one first many-to-one multiplexer unit and one first one-to-many multiplexer unit, and is connected between the output end of the corresponding first many-to-one multiplexer unit and the input end of the corresponding first one-to-many multiplexer unit. Among them, one analog-to-digital conversion circuit unit corresponds to one second many-to-one multiplexer unit and one second one-to-many multiplexer unit, and is connected between the output end of the corresponding second many-to-one multiplexer unit and the input end of the corresponding second one-to-many multiplexer unit.

2. The multiplexing device according to claim 1, wherein Each digital-to-analog conversion circuit unit corresponds to multiple input ports, and is shared with the corresponding first one-to-many multiplexer unit in a time-division multiplexing manner through the corresponding first many-to-one multiplexer unit.

3. The multiplexing device according to claim 1, wherein It further includes a switching transistor module. Among them, the output end of the first one-to-many multiplexer module is connected to the input end of the analog vector-matrix multiplication operation circuit module through the switching transistor module. The analog vector-matrix multiplication operation circuit module described above includes programmable semiconductor devices, and the threshold voltage of each programmable semiconductor device can be dynamically programmed. The switching transistor module described above includes a plurality of switching transistor units. Each row of the analog vector-matrix multiplication operation circuit module is respectively connected to its corresponding switching transistor unit.

4. The multiplexing device according to claim 1, characterized in that, Each analog-to-digital conversion circuit unit corresponds to multiple output ports, and is shared with the corresponding second one-to-many multiplexer unit in a time-division multiplexing manner through the corresponding second many-to-one multiplexer unit.

5. The multiplexing device according to claim 1, characterized in that, It further includes a controller, which is connected to the first multi-to-one multiplexer module, the digital-to-analog conversion circuit module, the first one-to-multi multiplexer module, the analog vector-matrix multiplication operation circuit module, the switching transistor module, the second multi-to-one multiplexer module, the analog-to-digital conversion circuit module, and the second one-to-multi multiplexer module; and is used to control selecting one signal from multiple input signals as the output through the first and second multi-to-one multiplexer units at each moment; used to control selecting one input signal and outputting it to different output ports through the first and second one-to-multi multiplexer units at each moment; used to control the opening and closing of the corresponding switching transistor units at each moment.

6. The multiplexing device according to claim 5, characterized in that, The controller controls the switching transistor module, the first multi-to-one multiplexer module connected to the digital-to-analog conversion circuit module, and the first one-to-multi multiplexer module in a time-division multiplexing manner to select corresponding input signals and import them into the analog vector-matrix multiplication operation circuit module; the controller controls the second multi-to-one multiplexer module and the second one-to-multi multiplexer module connected to the analog-to-digital conversion circuit module in a time-division multiplexing manner to select corresponding output signals at the output end of the analog vector-matrix multiplication operation circuit module for output.

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