Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. Based on the use of bit line groups and isolation line groups to define a node contact window array, auxiliary lines are further provided to define auxiliary contact windows at the periphery of the node contact window array. The auxiliary contact windows effectively balance the arrangement density of node contact windows in the edge and middle regions of the node contact window array, thereby improving the morphological accuracy of the node contact windows in the edge regions and further improving the morphological uniformity of the node contact windows in the edge and middle regions.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] A memory, such as a dynamic random access memory (DRAM), typically includes a storage capacitor and a storage transistor electrically connected to the storage capacitor. The storage capacitor is used to store charge representing storage information, and the storage transistor can be electrically connected to the storage capacitor through a node contact.

[0003] Currently, a method for preparing a node contact portion is, for example, to define a node contact window using a bit line and an isolation line, and then fill the node contact window with a conductive material to form a node contact portion.

[0004] However, when preparing the bit lines and isolation lines, the graphic morphology of the bit lines and isolation lines corresponding to the edge positions is very easy to be deformed, which will not only have an adverse effect on the performance of the bit lines and isolation lines, resulting in poor stability of the semiconductor device finally formed, but also cause the morphology of the defined node contact window to be abnormal, thereby affecting the quality of the node contact portion finally formed. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor device to solve the problem that the node contact window formed at the edge of the memory region in the existing semiconductor device has abnormal morphology, thereby affecting the node contact portion filled in the node contact window.

[0006] In order to solve the above technical problems, the present invention provides a semiconductor device, comprising:

[0007] a substrate, wherein a memory area and a peripheral area located outside the memory area are defined on the substrate;

[0008] A bit line group is formed on the substrate and is located at least in the memory area, and the bit line group includes a plurality of bit lines, the bit lines extend along a first direction, and the plurality of bit lines are sequentially spaced apart along a second direction;

[0009] an isolation line group formed on the substrate and located at least in the memory region, wherein the isolation line group includes a plurality of isolation lines, the isolation lines extending along the second direction, the plurality of isolation lines being sequentially spaced apart along the first direction and intersecting the isolation lines with the bit lines to define a node contact window array in the memory region; and

[0010] A plurality of auxiliary lines are formed in the peripheral region of the substrate and are used to define a plurality of auxiliary contact windows in the peripheral region. The plurality of auxiliary contact windows are located outside the node contact window array.

[0011] Optionally, the node contact window is filled with a conductive material to form a node contact portion; and the auxiliary contact window is filled with an insulating material to form an auxiliary filling column.

[0012] Optionally, the bit line also extends from the memory area to the peripheral area in its extension direction; and the multiple auxiliary lines include a plurality of first auxiliary lines, which are arranged along a first direction on the outside of the isolation line group, and the first auxiliary lines extend along a second direction, and the part of the bit line extending to the peripheral area intersects with the first auxiliary line to define the auxiliary contact window in the peripheral area.

[0013] Optionally, the first auxiliary line among the plurality of first auxiliary lines that is arranged farthest from the memory area is a first auxiliary boundary line, and the end of the bit line extending to the peripheral area reaches the first auxiliary boundary line and does not exceed the outer boundary of the first auxiliary boundary line.

[0014] Optionally, the isolation line also extends from the memory area to the peripheral area in its extension direction; and the multiple auxiliary lines include a plurality of second auxiliary lines, which are arranged along the second direction on the outside of the bit line group, and the second auxiliary lines extend along the first direction, and the part of the isolation line extending to the peripheral area intersects with the second auxiliary lines to define the auxiliary contact window in the peripheral area.

[0015] Optionally, the second auxiliary line among the plurality of second auxiliary lines that is arranged farthest from the memory area is a second auxiliary boundary line, and the end of the isolation line extending to the peripheral area reaches the second auxiliary boundary line and does not exceed the outer boundary of the second auxiliary boundary line.

[0016] Optionally, a trench isolation structure is formed in the substrate of the peripheral area, and at least part of the trench isolation structure is located outside the memory area, and at least part of the auxiliary line is formed on the trench isolation structure to define the auxiliary contact window above the trench isolation structure.

[0017] In addition, the present invention also provides a method for forming a semiconductor device, comprising:

[0018] Providing a substrate, wherein a memory area and a peripheral area located outside the memory area are defined on the substrate;

[0019] forming a bit line group on the substrate, the bit line group being located at least in the memory region, and the bit line group comprising a plurality of bit lines extending along a first direction, and the plurality of bit lines being sequentially spaced apart along a second direction;

[0020] forming an isolation line group on the substrate, the isolation line group being located at least in the memory region, and the isolation line group including a plurality of isolation lines, the isolation lines extending along the second direction, the plurality of isolation lines being sequentially spaced apart along the first direction, and the isolation lines intersecting the bit lines to define a node contact window array in the memory region;

[0021] Furthermore, the method for forming the semiconductor device further includes: forming a plurality of auxiliary lines in the peripheral region of the substrate to define a plurality of auxiliary contact windows in the peripheral region using the auxiliary lines, wherein the plurality of auxiliary contact windows are located around the outer periphery of the node contact window array.

[0022] Optionally, the plurality of auxiliary lines include a plurality of first auxiliary lines and a plurality of second auxiliary lines;

[0023] The method for forming the second auxiliary lines and the bit line group includes: forming a second thin film layer on the substrate, the second thin film layer covering the memory area and the peripheral area; and patterning the second thin film layer to form a plurality of second lines extending along a first direction, wherein the second lines at least partially located in the memory area constitute the bit lines, and the second lines entirely located in the peripheral area constitute the second auxiliary lines.

[0024] Furthermore, the method for forming the first auxiliary line and the isolation line group includes: forming a first thin film layer on the substrate, the first thin film layer being formed in the memory area and the peripheral area; and patterning the first thin film layer to form a plurality of first lines extending along a second direction, wherein at least part of the first lines located in the memory area constitute the isolation line, and all of the first lines located in the peripheral area constitute the first auxiliary lines.

[0025] Optionally, after forming the node contact window array and the auxiliary contact window, the method further includes:

[0026] filling the auxiliary contact window with an insulating material to form an auxiliary filling column; and

[0027] A conductive material is filled in the node contact window to form a node contact portion.

[0028] In the semiconductor device provided by the present invention, in addition to using the bit line group and the isolation line group to define the node contact window array, auxiliary lines are further provided, so that the auxiliary lines can be further used to define auxiliary contact windows around the outer periphery of the node contact window array. In this case, based on the auxiliary contact windows, the arrangement density of the node contact windows in the edge region and the middle region of the node contact window array can be effectively balanced, avoiding the arrangement density of the node contact windows in the edge region being much lower than the arrangement density of the node contact windows in the middle region, thereby effectively improving the morphological accuracy of the node contact windows in the edge region and correspondingly improving the morphological uniformity of the node contact windows in the edge region and the node contact windows in the middle region. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1a A top view of the semiconductor device in the first embodiment of the present invention, which defines a node contact window and an auxiliary contact window;

[0030] Figure 1b for Figure 1a The schematic cross-sectional view of the semiconductor device in the aa' direction in the first embodiment of the present invention is shown;

[0031] Figure 2a FIG1 is a top view of the semiconductor device in the first embodiment of the present invention, which is filled with node contacts and auxiliary filling pillars;

[0032] Figure 2b for Figure 2a The schematic cross-sectional view of the semiconductor device in the aa' direction in the first embodiment of the present invention is shown;

[0033] Figure 3 A top view of the semiconductor device in the second embodiment of the present invention, which defines a node contact window and an auxiliary contact window;

[0034] Figure 4 is a schematic flow chart of a method for forming a semiconductor device in one embodiment of the present invention;

[0035] Figure 5a-5b FIG. 1 is a structural diagram of a method for forming a semiconductor device during its preparation process in one embodiment of the present invention.

[0036] The accompanying drawings are numerals as follows:

[0037] 100-substrate;

[0038] 100A-memory area;

[0039] 100B-surrounding area;

[0040] 200A-bit line group;

[0041] 210A-bit line;

[0042] 210B-second auxiliary line;

[0043] 300A-isolated wire set;

[0044] 310A-isolated wire;

[0045] 310B-first auxiliary line;

[0046] 400A-node contact window;

[0047] 400B- auxiliary contact window;

[0048] 500A-node contact;

[0049] 500B-Auxiliary packing column. DETAILED DESCRIPTION

[0050] The semiconductor device and its formation method proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0051] Example 1

[0052] Figure 1a FIG1 is a top view of the semiconductor device in the first embodiment of the present invention, which defines the node contact window and the auxiliary contact window. Figure 1b for Figure 1a The cross-sectional view of the semiconductor device in the first embodiment of the present invention along the aa' direction is shown in FIG. Figure 2a FIG1 is a top view of a semiconductor device in a first embodiment of the present invention filled with node contacts and auxiliary filling columns. Figure 2b for Figure 2a FIG. 1 is a schematic cross-sectional view of a semiconductor device in the first embodiment of the present invention along the aa′ direction.

[0053] Specific reference Figure 1a-1b as well as Figure 2a-2b As shown, the semiconductor device includes a substrate 100 , and a bit line group 200A and an isolation line group 300A formed on the substrate 100 .

[0054] A memory region 100A is defined on the substrate 100. Multiple active areas AA may be further formed in the memory region 100A, for example. The active areas AA may be used to form memory cells. Furthermore, a peripheral region 100B is defined on the substrate 100. The peripheral region 100B is located outside the memory region 100A.

[0055] Furthermore, a trench isolation structure is formed in the substrate 100 in the peripheral region 100 , and at least a portion of the trench isolation structure is located outside the memory region 100A.

[0056] Continue to refer Figure 1a and Figure 1b As shown, the bit line group 200A is formed on the substrate 100 and is located at least in the memory region 100A. Specifically, the bit line group 200A includes a plurality of bit lines 210A, each of which extends along a first direction and is sequentially spaced apart along a second direction. In this manner, each bit line 210A intersects a corresponding active area AA in the memory region 100A.

[0057] Furthermore, the isolation line group 300A is formed on the substrate 100 and is located at least in the memory region 100A. Specifically, the isolation line group 300A includes a plurality of isolation lines 310A, each extending along the second direction. The plurality of isolation lines 310A are sequentially spaced apart along the first direction. In this case, the isolation lines 310A can intersect with the bit lines 210A at least in the memory region 100A to define a node contact window array in the memory region 100A. The node contact window array accordingly includes a plurality of node contact windows 400A, each corresponding to at least a portion of the active area AA.

[0058] In this embodiment, a plurality of auxiliary lines are formed on the substrate 100 . The plurality of auxiliary lines are located in the peripheral region and are used to define a plurality of auxiliary contact windows 400B in the peripheral region 100B. The plurality of auxiliary contact windows 400B are located outside the node contact window array.

[0059] It should be noted that by providing auxiliary lines in the peripheral region 100B to define the auxiliary contact windows 400B around the outer periphery of the node contact window array, the auxiliary contact windows 400B are used to balance the arrangement density of the node contact windows 400A in the edge region and the middle region of the node contact window array, thereby preventing the arrangement density of the node contact windows 400A in the edge region from being much lower than that in the middle region. This effectively improves the morphological accuracy of the node contact windows 400A in the edge region and further improves the uniformity of the morphology of the node contact windows 400A in the edge region and the morphology of the node contact windows 400A in the middle region.

[0060] Based on this, the node contact portion 500A filled in the node contact window 400A can have a higher morphology accuracy, and the morphology uniformity of the node contact portion 500A in different regions can be improved.

[0061] Specifically, focus on Figure 2a and Figure 2b As shown, the node contact window 400A is filled with a conductive material to form a node contact portion 500A, and the plurality of node contacts 500A in the memory region 100A may form a node contact portion array.

[0062] In this embodiment, the node contact portion 500A may include multiple conductive layers, for example, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer fills the bottom of the node contact window 400A to connect to the active area AA; the second conductive layer covers the top surface of the first conductive layer and also covers the sidewalls of the node contact window 400A that are higher than the first conductive layer; and the third conductive layer is formed on the second conductive layer and fills the node contact window 400A. Furthermore, the material of the first conductive layer may include, for example, polysilicon, the material of the second conductive layer may include, for example, titanium or titanium nitride, and the material of the third conductive layer may include, for example, tungsten.

[0063] In an optional solution, the auxiliary contact window 400B may be further filled with an insulating material to form an auxiliary filling column 500B. The plurality of auxiliary filling columns 500B in the peripheral region 100B accordingly surround the outer periphery of the node contact array. The insulating material of the auxiliary filling columns 500B may include, for example, at least one of silicon oxide and silicon nitride.

[0064] Furthermore, the auxiliary lines can be located in the same structural layer as the bit line group 200A and the isolation line group 300A to uniformly distribute the line density between the edge and middle regions of the bit line group 200A, thereby improving the pattern uniformity between the bit lines 210A in the edge and middle regions of the bit line group 200A. Alternatively, the auxiliary lines can also be used to uniformly distribute the line density between the edge and middle regions of the isolation line group 300A, thereby improving the pattern uniformity between the isolation lines 310A in the edge and middle regions of the isolation line group 300A. This accordingly improves the topography accuracy of the node contact windows 400A in the edge regions, resulting in more uniform topography for both the node contact windows 400A in the edge and middle regions.

[0065] It should be noted that the multiple bit lines 210A in the bit line group 200A extend continuously in their extension direction, that is, the bit lines 210A are continuously extended lines. Furthermore, the isolation line group 300A and the bit line group 200A are located in the same structural layer. Based on this, when the top surface of the isolation line 310A is not higher than the top surface of the bit line 210, it can be considered that the isolation line 310A is a discontinuously extended extension line, that is, the isolation line 310A includes multiple isolation segments arranged sequentially along its extension direction. The isolation segments are formed in adjacent bit lines 210A and connect adjacent bit lines 210A to surround the node contact window 400A. Alternatively, when the top surface of the isolation line 310A is higher than the top surface of the bit line 210, the portion of the isolation line 310A that is higher than the bit line 210A may also be continuously extended. Specifically, the portion of the isolation line 310A that is higher than the bit line 210A also covers the top surface of the bit line 210A to continuously extend in its extension direction.

[0066] Continue to refer Figure 1a and Figure 1b As shown, in this embodiment, the bit line 210A in the bit line group 200A further extends from the memory region 100A to the peripheral region 100B in its extending direction.

[0067] Furthermore, the plurality of auxiliary lines include a plurality of first auxiliary lines 310B, which are arranged outside the isolation line group 300A along a first direction and extend along a second direction. Specifically, the first auxiliary lines 310B extend parallel to the isolation lines 310A and are arranged at intervals outside the isolation line group 300A. Portions of the bit lines 210A extending into the peripheral region 100B intersect with the first auxiliary lines 310B to define auxiliary contact windows 400B within the peripheral region 100B. In this case, the auxiliary contact windows 400B defined by the intersection of the first auxiliary lines 310B and the bit lines 210A are arranged outside the isolation line group 300A.

[0068] In a specific embodiment, the first auxiliary line 310B and the isolation line 310A are located in the same structural layer, and the top of the first auxiliary line 310B is located at the same position as the top of the isolation line 310A. In this case, if the isolation line 310A is not higher than the bit line 210A, the top surface of the first auxiliary line 310B is also not higher than the top surface of the bit line 210A, allowing the first auxiliary line 310B to extend discontinuously along its extension direction.

[0069] Furthermore, the first auxiliary line of the plurality of first auxiliary lines 310B, which is arranged farthest from the memory region, serves as a first auxiliary boundary line. The end of the bit line 210A extending into the peripheral region reaches the first auxiliary boundary line and does not extend beyond the outer boundary of the first auxiliary boundary line. That is, the first auxiliary boundary line has an inner boundary close to the memory region 100A and an outer boundary opposite the inner boundary and away from the memory region 100A. The end boundary of the bit line 210A lies between the inner and outer boundaries of the first auxiliary boundary line. This is equivalent to utilizing the first auxiliary boundary line to surround the auxiliary contact window 400B arranged at the outermost edge, thereby ensuring a complete topography of the auxiliary contact window 400B arranged at the outermost edge and smoothing the edges of the auxiliary contact window.

[0070] The spacing between adjacent first auxiliary lines 310B among the plurality of first auxiliary lines 310B may be the same or different. For example, the spacing between adjacent first auxiliary lines 310B may be the same as the spacing between adjacent isolation lines 310A, or may be different from the spacing between adjacent isolation lines 310A. For another example, the spacing between adjacent first auxiliary lines 310B near the memory area 100A among the plurality of first auxiliary lines 310 is the same as the spacing between adjacent isolation lines 310A, and the spacing between adjacent first auxiliary lines 310B away from the memory area 100A among the plurality of first auxiliary lines 310 is different from the spacing between adjacent isolation lines 310A.

[0071] Furthermore, the width of the plurality of first auxiliary lines 310B can be the same as or different from the width of the isolation line 310A. For example, among the plurality of first auxiliary lines 310, the width of the first auxiliary lines 310 close to the memory region can be the same as the width of the isolation line 310A, while the width of the first auxiliary lines 310 far from the memory region can be different from the width of the isolation line 310A. In this embodiment, the width of the first auxiliary boundary line farthest from the memory region can be greater than the width of the isolation line 310A.

[0072] In an optional solution, the isolation line 310A in the isolation line group 300A further extends from the memory area 100A to the peripheral area 100B in its extension direction.

[0073] Furthermore, the plurality of auxiliary lines include a plurality of second auxiliary lines 210B, which are arranged outside the bit line group 200A along the second direction and extend along the first direction. Specifically, the second auxiliary lines 210B extend parallel to the bit lines 210A and are arranged at intervals outside the bit line group 200A. The portion of the isolation line 310A extending into the peripheral region 100B intersects with the second auxiliary lines 210B to define the auxiliary contact windows 400B within the peripheral region 100B. In this case, the auxiliary contact windows 400B defined by the intersection of the second auxiliary lines 210B and the isolation line 310A are arranged outside the bit line group 200A.

[0074] In a specific embodiment, the second auxiliary line 210B and the bit line 210A are located in the same structural layer, and the top of the second auxiliary line 210B is located at the same position as the top of the bit line 210A. In this case, the second auxiliary line 210B can extend continuously in its extension direction. When the isolation line 310A is not higher than the bit line 210A, the portion of the isolation line 310A extending into the peripheral region can also be discontinuous. In the peripheral region, the isolation segment of the isolation line 310A is located between adjacent second auxiliary lines 210B and connects adjacent second auxiliary lines 210B to surround the auxiliary contact window 400B.

[0075] Furthermore, the second auxiliary line of the plurality of second auxiliary lines 210B that is arranged farthest from the memory area is a second auxiliary boundary line. The end of the isolation line 310A extending into the peripheral area reaches the second auxiliary boundary line and does not extend beyond the outer boundary of the second auxiliary boundary line. That is, the second auxiliary boundary line has an inner boundary close to the memory area 100A and an outer boundary opposite the inner boundary and away from the memory area 100A. The end boundary of the isolation line 310A is between the inner and outer boundaries of the second auxiliary boundary line. In this way, it is equivalent to using the second auxiliary boundary line to surround the auxiliary contact window 400B arranged at the outermost edge, thereby ensuring the morphology of the auxiliary contact window 400B arranged at the outermost edge is complete and the edge of the auxiliary contact window is smooth.

[0076] Similarly, the spacing between adjacent second auxiliary lines 210B in the plurality of second auxiliary lines 210B may be the same or different. For example, the spacing between adjacent second auxiliary lines 210B may be the same as or different from the spacing between adjacent bit lines 210A. For another example, the spacing between adjacent second auxiliary lines 210B in the plurality of second auxiliary lines 210 near the memory area 100A may be the same as the spacing between adjacent bit lines 210A, while the spacing between adjacent second auxiliary lines 210B in the plurality of second auxiliary lines 210 away from the memory area 100A may be different from the spacing between adjacent bit lines 210A.

[0077] Furthermore, the width of the plurality of second auxiliary lines 210B may be the same as or different from the width of the bit line 210A. For example, the width of the second auxiliary lines 210 located near the memory region may be the same as the width of the bit line 210A, while the width of the second auxiliary lines 210 located far from the memory region may be different from the width of the bit line 210A. In this embodiment, the width of the second auxiliary boundary line located farthest from the memory region may be greater than the width of the bit line 210A.

[0078] like Figure 1a and Figure 2a As shown, in this embodiment, the memory region 100A is, for example, a rectangular region having a first side and a second side connected to each other. Furthermore, the first auxiliary line 310B and the bit line 210A can form an auxiliary contact window 400B on the outer side of the memory region 100A near the first side, and the second auxiliary line 210B and the isolation line 310B can form an auxiliary contact window 400B on the outer side of the memory region 100A near the second side.

[0079] In this embodiment, the first auxiliary line 310B and the second auxiliary line 210B also intersect in the peripheral area 100B to define the auxiliary contact window 400B. Specifically, the first auxiliary line 310B and the second auxiliary line 210B form the auxiliary contact window 400B outside the diagonal corners of the memory area 100A.

[0080] Furthermore, as described above, a trench isolation structure is formed in the substrate 100 in the peripheral region 100B, and at least a portion of the trench isolation structure is located outside the memory region 100A. Based on this, at least a portion of the auxiliary line can be formed on the trench isolation structure. Furthermore, the portion of the bit line 210A extending into the peripheral region 100B can also be located above the trench isolation structure, and the portion of the isolation line 310A extending into the peripheral region 100B can also be located above the trench isolation structure. Consequently, the auxiliary contact window 400B is defined above the trench isolation structure.

[0081] Continue to refer Figure 1a and Figure 2a As shown, in this embodiment, the number of first auxiliary lines 310B arranged outside the isolation line group 300A is different from the number of second auxiliary lines 210B arranged outside the bit line group 200A. Based on this, the number of rows of auxiliary contact windows defined outside the isolation line group 300A is different from the number of rows of auxiliary contact windows defined outside the bit line group 200A. For example, if four first auxiliary lines 310B are arranged outside the isolation line group 300A and three second auxiliary lines 210B are arranged outside the bit line group 200A, three rows of auxiliary contact windows can be defined outside the isolation line group 300A, and two rows of auxiliary contact windows can be defined outside the bit line group 200A.

[0082] In a more specific embodiment, the bit line 210A extends into the peripheral region for a longer length. This allows, for example, the bit line 210A to be smoothly connected to the semiconductor devices in the peripheral region. Therefore, a larger number of first auxiliary lines 310B can be provided (for example, the number of first auxiliary lines 310B is greater than the number of second auxiliary lines 210B). This allows the bit line 210A extending into the peripheral region to mostly intersect with the first auxiliary lines 310B, thus preventing the sidewalls of the bit line 210A in the peripheral region from being exposed to a large space and thus preventing the bit line 210A in the peripheral region from being susceptible to lateral erosion.

[0083] Alternatively, in other specific solutions, the number of the plurality of second auxiliary lines 210B may be greater than the number of the plurality of first auxiliary lines 310B. In this case, more second auxiliary lines 210B are arranged outside the bit line group 200A, thereby better balancing the line arrangement density in the edge areas of the bit line group 210B and further ensuring the performance of the bit lines 210A located at the edge.

[0084] It will be appreciated that, in this embodiment, the number of auxiliary contact windows arranged outside the memory region along the first direction is different from the number of auxiliary contact windows arranged outside the memory region along the second direction. For example, the memory region 100A may be a rectangular area, and the trench isolation structure may surround the memory region 100A. The total number of auxiliary contact windows formed on two opposite sides of the trench isolation structure along the first direction is different from the total number of auxiliary contact windows formed on two opposite sides of the trench isolation structure along the second direction.

[0085] Of course, it should be appreciated that in other embodiments, the number of the first auxiliary lines 310B arranged outside the isolation line group 300A may be the same as the number of the second auxiliary lines 210B arranged outside the bit line group 200A.

[0086] Implementation List 2

[0087] The difference from the first embodiment is that, in this embodiment, the ends of the bit lines and isolation lines extending from the memory area are all beyond the boundaries of the auxiliary lines arranged at the outermost edge.

[0088] Figure 3 This is a top view of a semiconductor device according to the second embodiment of the present invention, which defines a node contact window and an auxiliary contact window. Figure 3 As shown, the first auxiliary line of the plurality of first auxiliary lines 310B, which is arranged farthest from the memory region, is a first auxiliary boundary line. The end of the bit line 210A extending into the peripheral region extends beyond the first auxiliary boundary line. That is, the end boundary of the bit line 210A is located on the side of the first auxiliary boundary line away from the memory region. This allows the auxiliary contact window 400B arranged at the outermost edge to have a laterally exposed opening.

[0089] Continue to refer Figure 3 As shown, the second auxiliary line of the plurality of second auxiliary lines 210B that is arranged farthest from the memory region serves as a second auxiliary boundary line. The end of the isolation line 310A extending into the peripheral region extends beyond the second auxiliary boundary line. That is, the end boundary of the isolation line 310A is located on the side of the second auxiliary boundary line that is away from the memory region. This also allows the auxiliary contact window 400B arranged at the outermost edge to have a laterally exposed opening.

[0090] Based on the semiconductor device described above, the following Figure 4 as well as Figure 5a-5b The method for forming the semiconductor device is described in detail. Figure 4 FIG. 1 is a flow chart of a method for forming a semiconductor device in one embodiment of the present invention. Figure 5a-5bFIG. 1 is a structural diagram of a method for forming a semiconductor device during its preparation process in one embodiment of the present invention.

[0091] Step S100, see Figure 5a As shown, a substrate 100 is provided. A memory region 100A and a peripheral region 100B located outside the memory region 100A are defined on the substrate 100.

[0092] The memory region 100A may include, for example, a plurality of active regions, which may be further used to form memory cells of a memory.

[0093] Step S200, continue to refer to Figure 5a As shown, a bit line group 200A is formed on the substrate 100 , and the bit line group 200A is at least located in the memory region 100A.

[0094] The bit line group 200A includes a plurality of bit lines 210A, the bit lines 210A extend along a first direction, and the plurality of bit lines 210A are sequentially spaced apart along a second direction.

[0095] Furthermore, while forming the bit line group 200A, the process further includes forming a plurality of second auxiliary lines 210B in the peripheral region 100B of the substrate 100 .

[0096] Specifically, the method for forming the bit line group 200A and the second auxiliary line 210B includes, for example:

[0097] First, a second thin film layer is formed on the substrate 100 , where the second thin film layer covers the memory area 100A and the peripheral area 100B; and

[0098] Next, the second thin film layer is patterned to form a plurality of second lines extending along the first direction. The plurality of second lines are sequentially spaced apart along the second direction. Some of the plurality of second lines are formed in the memory region 100A, while others are formed in the peripheral region 100B. The second lines at least partially located in the memory region 100A constitute the bit lines 210A, and the second lines entirely located in the peripheral region 100B constitute the second auxiliary lines 210B.

[0099] That is, in this embodiment, when performing a graphic process to form the bit line group 200A, a second auxiliary line 210B is also formed on the outside of the bit line group 200A, thereby avoiding the exposure of the bit lines 210A located in the edge area of ​​the bit line group 200A to a larger spatial area, thereby preventing the bit lines 210A in the edge area from being easily corroded, and effectively reducing the density difference between the line arrangement density in the edge area and the line arrangement density in the middle area of ​​the bit line group 200A. This is conducive to improving the morphological uniformity of the bit lines 210A located in the edge area and the bit lines 210A located in the middle area of ​​the bit line group 200A.

[0100] Step S300, see Figure 5b As shown, an isolation line group 300A is formed on the substrate 100 , and the isolation line group 300A is at least located in the memory region 100A.

[0101] The isolation line group 300A includes a plurality of isolation lines 310A extending along the second direction. The isolation lines 310A are sequentially spaced apart along the first direction and intersect the bit lines 210A to define a node contact array within the memory region 100A. Specifically, the node contact array includes a plurality of node contact windows 400A arranged in an array.

[0102] Furthermore, the isolation line 310A in the isolation line group 300A extends from the memory region 100A to the peripheral region 100B. As described above, a second auxiliary line 210B is also formed on the substrate 100. Therefore, the portion of the isolation line 310A extending to the peripheral region intersects with the second auxiliary line 210B to define the auxiliary contact window 400B in the peripheral region 100B.

[0103] In this embodiment, while forming the isolation line group 300A, the method further includes forming a plurality of first auxiliary lines 310B in the peripheral region 100B of the substrate 100 .

[0104] Specifically, the method for forming the isolation line group 300A and the first auxiliary line 310B includes the following steps, for example.

[0105] In the first step, a first thin film layer is formed on the substrate 100 , wherein the first thin film layer is formed in the memory region 100A and the peripheral region 100B.

[0106] In this embodiment, the first thin film layer may be further planarized so that the top surface of the first thin film layer is no higher than the top surface of the bit line 210A, and the first thin film layer is filled between adjacent bit lines 210A.

[0107] The second step involves patterning the second thin film layer to form a plurality of first lines extending along the second direction. The plurality of first lines are sequentially spaced apart along the first direction. Part of the plurality of first lines is formed in the memory area 100A, while the remainder is formed in the peripheral area 100B. The first lines at least partially located in the memory area 100A constitute the isolation lines 310A, while the first lines entirely located in the peripheral area 100B constitute the first auxiliary lines 310B.

[0108] Similarly, in this embodiment, when performing a graphic process to form the isolation line group 300A, a first auxiliary line 310B is also formed on the outside of the isolation line group 300A, thereby avoiding the isolation lines 310A located in the edge area of ​​the isolation line group 300A from being exposed to a larger spatial area, preventing the problem of a large difference in the line arrangement density of the edge area and the line arrangement density of the middle area of ​​the isolation line group 300A, which is beneficial to improving the morphological uniformity of the isolation lines 310A located in the edge area and the isolation lines 310A located in the middle area of ​​the isolation line group 300A.

[0109] It should be recognized that by improving the morphological accuracy and uniformity of the bit line 210A and the isolation line 310A, not only the electrical conductivity performance of the bit line 210A and the isolation performance of the isolation line 310A can be guaranteed; at the same time, the morphological accuracy and uniformity of the defined node contact window 400A are also correspondingly improved, which can further improve the quality of the node contact part subsequently filled in the node contact window 400A.

[0110] Continue to refer Figure 5b As shown, the bit line 210A in the bit line group 200A further extends from the memory area 100A to the peripheral area 100B. Based on this, the portion of the bit line 210A extending to the peripheral area may also intersect with the first auxiliary line 310B to define the auxiliary contact window 400B in the peripheral area 100B.

[0111] In a further embodiment, after forming the node contact window 400A and the auxiliary contact window 400B, it further includes: filling insulating material in the auxiliary contact window 400B to form an auxiliary filling column 500B; and filling conductive material in the node contact window 400A to form a node contact portion 500A.

[0112] For details, please refer to Figure 2b As shown, in this embodiment, the auxiliary contact window 400B may be filled with insulating material first, and then the node contact window 400A may be filled with conductive material, so as to avoid a small amount of conductive material remaining in the auxiliary contact window 400B. Of course, in other embodiments, the node contact window 400A may be filled with conductive material first, and then the auxiliary contact window 400B may be filled with insulating material.

[0113] In summary, in the semiconductor device provided in this embodiment, based on defining the node contact window array by using the bit line group and the isolation line group, auxiliary lines are further provided to define auxiliary contact windows on the periphery of the node contact window array.

[0114] At this point, it can be considered that the auxiliary lines are utilized to balance the line arrangement density in the edge regions and the line arrangement density in the middle regions of the bit line group / isolation line group, thereby resolving the problem of line arrangement density in the edge regions being much lower than that in the middle regions, which results in abnormal morphology of the lines in the edge regions. This improves the morphological uniformity of the lines in the edge regions and the middle regions of the bit line group / isolation line group. This not only improves the morphological uniformity of the node contact windows in the edge regions and the middle regions of the defined node contact window array, but also correspondingly improves the morphological accuracy of the bit lines at the edge locations and the isolation lines at the edge locations, which helps to ensure the electrical transmission performance of the bit lines and the isolation performance of the isolation lines.

[0115] Alternatively, it can also be understood that auxiliary lines are used to define the periphery of the node contact window array by auxiliary lines. At this time, the arrangement density of the node contact windows in the edge area and the middle area of ​​the node contact window array can be balanced, avoiding the arrangement density of the node contact windows in the edge area being much lower than the arrangement density of the node contact windows in the middle area, thereby effectively improving the morphological accuracy of the node contact windows located in the edge area, and further improving the morphological uniformity of the node contact windows located in the edge area and the node contact windows located in the middle area.

[0116] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. Also, although the present invention has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention that do not depart from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0117] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0118] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that: include: a substrate, wherein a memory area and a peripheral area located outside the memory area are defined on the substrate; A bit line group is formed on the substrate and is located at least in the memory area, and the bit line group includes a plurality of bit lines, the bit lines extend along a first direction, and the plurality of bit lines are sequentially spaced apart along a second direction; an isolation line group formed on the substrate and located at least in the memory region, wherein the isolation line group includes a plurality of isolation lines, the isolation lines extending along the second direction, the plurality of isolation lines being sequentially spaced apart along the first direction and intersecting the isolation lines with the bit lines to define a node contact window array in the memory region; A plurality of auxiliary lines are formed in the peripheral region of the substrate, and are used to define a plurality of auxiliary contact windows in the peripheral region, wherein the plurality of auxiliary contact windows are located outside the node contact window array; The bit line further extends from the memory region to the peripheral region in its extending direction; and the plurality of auxiliary lines include a plurality of first auxiliary lines, the plurality of first auxiliary lines being arranged outside the isolation line group along a first direction, and the first auxiliary lines extending along a second direction, such that portions of the bit line extending to the peripheral region intersect with the first auxiliary lines to define the auxiliary contact windows in the peripheral region; wherein the node contact windows are filled with a conductive material to form node contact portions; The auxiliary contact window is filled with insulating material to form an auxiliary filling column.

2. The semiconductor device according to claim 1, wherein The first auxiliary line of the plurality of first auxiliary lines that is arranged farthest from the memory area is a first auxiliary boundary line. The end of the bit line extending to the peripheral area reaches the first auxiliary boundary line and does not exceed the outer boundary of the first auxiliary boundary line.

3. The semiconductor device according to claim 1, wherein The isolation line extends from the memory area to the peripheral area, and the plurality of auxiliary lines further include a plurality of second auxiliary lines; Parts of the bit lines extending to the peripheral region intersect with the first auxiliary lines to define auxiliary contact windows outside the isolation line group; and the plurality of second auxiliary lines are arranged along a second direction outside the bit line group, and the second auxiliary lines extend along the first direction, so that parts of the isolation lines extending to the peripheral region intersect with the second auxiliary lines to define auxiliary contact windows outside the bit line group. Furthermore, the number of the first auxiliary lines is different from the number of the second auxiliary lines, so that the number of rows of auxiliary contact windows outside the isolation line group is different from the number of rows of auxiliary contact windows outside the bit line group.

4. The semiconductor device according to claim 1, wherein A trench isolation structure is formed in the substrate of the peripheral area, and at least part of the trench isolation structure is located outside the memory area, and at least part of the auxiliary line is formed on the trench isolation structure to define the auxiliary contact window above the trench isolation structure.

5. The semiconductor device according to claim 1, wherein The number of the auxiliary contact windows arranged outside the memory area along the first direction is different from the number of the auxiliary contact windows arranged outside the memory area along the second direction.

6. A semiconductor device, characterized in that: include: a substrate, wherein a memory area and a peripheral area located outside the memory area are defined on the substrate; A bit line group is formed on the substrate and is located at least in the memory area, and the bit line group includes a plurality of bit lines, the bit lines extend along a first direction, and the plurality of bit lines are sequentially spaced apart along a second direction; an isolation line group formed on the substrate and located at least in the memory region, wherein the isolation line group includes a plurality of isolation lines, the isolation lines extending along the second direction, the plurality of isolation lines being sequentially spaced apart along the first direction and intersecting the isolation lines with the bit lines to define a node contact window array in the memory region; A plurality of auxiliary lines are formed in the peripheral region of the substrate, and are used to define a plurality of auxiliary contact windows in the peripheral region, wherein the plurality of auxiliary contact windows are located outside the node contact window array; The isolation line further extends from the memory region to the peripheral region in its extending direction; and the plurality of auxiliary lines include a plurality of second auxiliary lines, the plurality of second auxiliary lines being arranged outside the bit line group along a second direction, and the second auxiliary lines extending along a first direction, and portions of the isolation line extending to the peripheral region intersecting with the second auxiliary lines to define the auxiliary contact windows in the peripheral region; wherein the node contact windows are filled with a conductive material to form node contact portions; The auxiliary contact window is filled with insulating material to form an auxiliary filling column.

7. The semiconductor device according to claim 6, wherein The second auxiliary line among the plurality of second auxiliary lines that is arranged farthest from the memory area is a second auxiliary boundary line, and the end of the isolation line extending to the peripheral area reaches the second auxiliary boundary line and does not exceed the outer boundary of the second auxiliary boundary line.

8. The semiconductor device according to claim 6, wherein A trench isolation structure is formed in the substrate of the peripheral area, and at least part of the trench isolation structure is located outside the memory area, and at least part of the auxiliary line is formed on the trench isolation structure to define the auxiliary contact window above the trench isolation structure.

9. The semiconductor device according to claim 6, wherein The number of the auxiliary contact windows arranged outside the memory area along the first direction is different from the number of the auxiliary contact windows arranged outside the memory area along the second direction.

10. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, wherein a memory area and a peripheral area located outside the memory area are defined on the substrate; forming a bit line group on the substrate, the bit line group being located at least in the memory region, and the bit line group comprising a plurality of bit lines extending along a first direction, and the plurality of bit lines being sequentially spaced apart along a second direction; forming an isolation line group on the substrate, the isolation line group being located at least in the memory region, and the isolation line group including a plurality of isolation lines, the isolation lines extending along the second direction, the plurality of isolation lines being sequentially spaced apart along the first direction, and the isolation lines intersecting the bit lines to define a node contact window array in the memory region; Furthermore, the method for forming the semiconductor device further comprises: forming a plurality of auxiliary lines in the peripheral region of the substrate, so as to define a plurality of auxiliary contact windows in the peripheral region using the auxiliary lines, wherein the plurality of auxiliary contact windows are located outside the node contact window array; The bit lines further extend from the memory region to the peripheral region in their extending direction; and the plurality of auxiliary lines include a plurality of first auxiliary lines, the plurality of first auxiliary lines being arranged outside the isolation line group along a first direction, and the first auxiliary lines extending along a second direction such that portions of the bit lines extending to the peripheral region intersect with the first auxiliary lines to define the auxiliary contact windows in the peripheral region; After forming the node contact window array and the auxiliary contact window, the method further includes: filling the auxiliary contact window with an insulating material to form an auxiliary filling column; and A conductive material is filled in the node contact window to form a node contact portion.

11. The method for forming a semiconductor device according to claim 10, wherein: The method for forming the first auxiliary line and the isolation line group includes: forming a first thin film layer on the substrate, the first thin film layer being formed in the memory area and the peripheral area; and patterning the first thin film layer to form a plurality of first lines extending along a second direction, wherein the first lines at least partially located in the memory area constitute the isolation line, and the first lines entirely located in the peripheral area constitute the first auxiliary lines.

12. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, wherein a memory area and a peripheral area located outside the memory area are defined on the substrate; forming a bit line group on the substrate, the bit line group being located at least in the memory region, and the bit line group comprising a plurality of bit lines extending along a first direction, and the plurality of bit lines being sequentially spaced apart along a second direction; forming an isolation line group on the substrate, the isolation line group being located at least in the memory region, and the isolation line group including a plurality of isolation lines, the isolation lines extending along the second direction, the plurality of isolation lines being sequentially spaced apart along the first direction, and the isolation lines intersecting the bit lines to define a node contact window array in the memory region; Furthermore, the method for forming the semiconductor device further comprises: forming a plurality of auxiliary lines in the peripheral region of the substrate, so as to define a plurality of auxiliary contact windows in the peripheral region using the auxiliary lines, wherein the plurality of auxiliary contact windows are located outside the node contact window array; The isolation line further extends from the memory region to the peripheral region in its extending direction; and the plurality of auxiliary lines include a plurality of second auxiliary lines, the plurality of second auxiliary lines being arranged outside the bit line group along a second direction, and the second auxiliary lines extending along a first direction, and portions of the isolation lines extending to the peripheral region intersecting with the second auxiliary lines to define the auxiliary contact windows in the peripheral region; After forming the node contact window array and the auxiliary contact window, the method further includes: filling the auxiliary contact window with an insulating material to form an auxiliary filling column; and A conductive material is filled in the node contact window to form a node contact portion.

13. The method for forming a semiconductor device according to claim 12, wherein: The method for forming the second auxiliary lines and the bit line group includes: forming a second thin film layer on the substrate, the second thin film layer covering the memory area and the peripheral area; and patterning the second thin film layer to form a plurality of second lines extending along a first direction, wherein the second lines at least partially located in the memory area constitute the bit lines, and the second lines entirely located in the peripheral area constitute the second auxiliary lines.

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