Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, comprising: a lower metal layer, the lower metal layer comprising a first region and a second region; an interlayer dielectric layer located on the upper surface of the first region and the second region of the lower metal layer; a through hole extending from the upper surface of the interlayer dielectric layer to the lower metal layer, the through hole exposing the upper surface of the lower metal layer; a first conductive layer covering the bottom, sidewall and upper surface of the through hole; a dielectric layer covering the first conductive layer on the first region of the lower metal layer; a first metal filling the through hole; and an upper metal layer located on the upper surface of the interlayer dielectric layer, wherein the upper metal layer contacts the first metal and the dielectric layer on the first region of the lower metal layer. The semiconductor device provided by the present invention improves the density of capacitance without increasing the complexity.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the integration of semiconductor devices increases, capacitors are increasingly required to have high capacitance density, especially for radio frequency (RF) and analog / mixed signal (AMS) integrated circuit devices, which have higher requirements for capacitance density. In the prior art, high dielectric constant metal-insulator-metal (MIM) capacitors have been widely studied.

[0003] Currently, in the back-end of line (BEOL) process, a MIM capacitor with a top-middle-bottom sandwich structure is usually formed when forming an aluminum interconnect structure, such as Figure 1 As shown, the upper plate 101 and the lower plate 103 of the MIM capacitor are adjacent aluminum metal layers in the aluminum interconnect structure, and the material of the dielectric layer 102 of the MIM capacitor is generally a dielectric with a high dielectric constant such as SiON, SiN, Al2O3 or HfO2. However, under the condition that the dielectric layer remains unchanged, changing the MIM capacitor structure can greatly improve the capacitance density to meet the needs of higher capacitance density. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor device and a manufacturing method thereof, which improves the capacitance density by changing the capacitance structure.

[0005] According to a first aspect of the present invention, a semiconductor device is proposed, comprising: a lower metal layer, the lower metal layer comprising a first region and a second region; an interlayer dielectric layer located on the upper surface of the first region and the second region of the lower metal layer; a through hole extending from the upper surface of the interlayer dielectric layer to the lower metal layer, the through hole exposing the upper surface of the lower metal layer; a first conductive layer covering the bottom, sidewalls and upper surface of the through hole; a dielectric layer covering the first conductive layer on the first region of the lower metal layer; a first metal filling the through hole; and an upper metal layer located on the upper surface of the interlayer dielectric layer, wherein, on the first region of the lower metal layer, the upper metal layer is in contact with the first metal and the dielectric layer.

[0006] Preferably, the semiconductor device includes a capacitor structure, wherein the upper electrode of the capacitor structure is the upper metal layer and the first metal, the medium of the capacitor structure is the dielectric layer, and the lower electrode of the capacitor structure is the lower metal layer and the first conductive layer.

[0007] Preferably, on the second region of the lower metal layer, the upper metal layer is in contact with the first metal and the first conductive layer.

[0008] Preferably, the method further comprises a second conductive layer located between the lower metal layer and the interlayer dielectric layer.

[0009] Preferably, the first region and the second region of the lower metal layer are isolated from each other.

[0010] Preferably, the method further includes an insulating layer located between the first region and the second region of the lower metal layer.

[0011] Preferably, the method further comprises a third conductive layer located on the upper metal layer.

[0012] Preferably, the lower metal layer is located on a semiconductor substrate.

[0013] Preferably, the lower metal layer is located on a metal through hole of a lower metal interconnection structure.

[0014] Preferably, it further comprises a fourth conductive layer located between the lower metal layer and the semiconductor substrate or the metal through hole of the lower metal interconnection structure.

[0015] Preferably, the upper metal layer and the lower metal layer are configured as aluminum.

[0016] Preferably, the dielectric layer is configured as a medium having a high dielectric constant.

[0017] Preferably, the dielectric layer is configured as SiON or SiN or Al2O3 or HfO2.

[0018] Preferably, the first conductive layer and the second conductive layer are formed of Ti or TiN.

[0019] Preferably, the first metal is tungsten.

[0020] Preferably, the interlayer dielectric layer comprises oxide.

[0021] According to a first aspect of the present invention, a method for manufacturing a semiconductor device is proposed, comprising: forming an interlayer dielectric layer on the upper surface of a lower metal layer, the lower metal layer comprising a first region and a second region; forming a through hole in the interlayer dielectric layer extending from its upper surface to the lower metal layer, the through hole exposing the upper surface of the lower metal layer; forming a first conductive layer covering the bottom, sidewalls and upper surface of the through hole; forming a dielectric layer covering the first conductive layer on the first region of the lower metal layer; filling the through hole with a first metal; and forming an upper metal layer on the upper surface of the interlayer dielectric layer, wherein, on the first region of the lower metal layer, the upper metal layer is in contact with the first metal and the dielectric layer.

[0022] Preferably, the semiconductor device includes a capacitor structure, wherein the upper electrode of the capacitor structure is the upper metal layer and the first metal, the medium of the capacitor structure is the dielectric layer, and the lower electrode of the capacitor structure is the lower metal layer and the first conductive layer.

[0023] Preferably, the step of forming the dielectric layer on the first area of ​​the lower metal layer includes: forming a dielectric layer covering the first conductive layer on the first area and the second area of ​​the lower metal layer; and removing the dielectric layer on the second area of ​​the lower metal layer by etching, wherein, on the second area of ​​the lower metal layer, the upper metal layer is in contact with the first metal and the first conductive layer.

[0024] Preferably, before forming the interlayer dielectric layer, the method further includes forming a second conductive layer on the upper surface of the lower metal layer.

[0025] Preferably, the method for forming the through hole comprises etching the interlayer dielectric layer starting from the upper surface of the interlayer dielectric layer and stopping until the upper surface of the lower metal is exposed.

[0026] Preferably, the method further includes forming an insulating layer between the first region and the second region of the lower metal layer.

[0027] Preferably, the method further comprises forming a third conductive layer on the upper surface of the upper metal layer.

[0028] Preferably, the method further comprises forming the lower metal layer on the semiconductor substrate by deposition.

[0029] Preferably, the capacitor structure is located between metal layers of two metal interconnect structures.

[0030] Preferably, the method further comprises forming the lower metal layer on the metal through hole of the lower metal interconnect structure by deposition.

[0031] Preferably, before forming the lower metal layer, the method further comprises forming a fourth conductive layer on the semiconductor substrate or the metal through hole of the lower metal interconnect structure.

[0032] Preferably, the upper metal layer and the lower metal layer are configured as aluminum.

[0033] Preferably, the dielectric layer is configured as a medium having a high dielectric constant.

[0034] Preferably, the dielectric layer is configured as SiON or SiN or Al2O3 or HfO2. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1A cross-sectional view of a semiconductor device in the prior art;

[0036] Figure 2a-2e FIG. 1 is a cross-sectional view of a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same components are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and techniques of each component, so that the present invention is more clearly understood. However, as those skilled in the art will understand, the present invention may not be implemented in accordance with these specific details.

[0038] The present invention provides a method for manufacturing a semiconductor device, comprising: forming an interlayer dielectric layer on the upper surface of a lower metal layer, the lower metal layer comprising a first region and a second region; forming a through hole in the interlayer dielectric layer extending from its upper surface to the lower metal layer, the through hole exposing the upper surface of the lower metal layer; forming a first conductive layer covering the bottom, sidewalls and upper surface of the through hole; forming a dielectric layer covering the first conductive layer on the first region of the lower metal layer; filling the through hole with a first metal; and forming an upper metal layer on the upper surface of the interlayer dielectric layer, wherein, on the first region of the lower metal layer, the upper metal layer is in contact with the first metal and the dielectric layer.

[0039] like Figure 2a-2e 4 is a cross-sectional view of a partial stage of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0040] like Figure 2a As shown, an interlayer dielectric layer 102 is formed on the upper surface of the lower metal layer 101, and a through hole 120 extending from the upper surface of the interlayer dielectric layer 102 to the lower metal layer 101 is formed in the interlayer dielectric layer 102, and the through hole 120 exposes the upper surface of the lower metal layer 101. The through hole 120 can be formed by etching. Specifically, the interlayer dielectric layer 102 is etched from the upper surface of the interlayer dielectric layer 102 until the upper surface of the lower metal layer 101 is exposed. In this embodiment, the through hole 120 can include a plurality of holes, at least two.

[0041] Before forming the interlayer dielectric layer 102, a second conductive layer 112 is formed on the upper surface of the lower metal layer 101. While etching the interlayer dielectric layer 102, a portion of the second conductive layer 112 is also etched until the through hole 120 exposes the upper surface of the lower metal layer 101. The second conductive layer 112 is used as an adhesion layer between the lower metal layer 101 and the interlayer dielectric layer 102.

[0042] The lower metal layer 101 includes a first region and a second region, and the method further includes forming an insulating layer 100 between the first region and the second region of the lower metal layer to isolate the first region from the second region.

[0043] It should be noted that the lower metal layer 101 can be located on a semiconductor substrate, specifically, the lower metal layer 101 is located on the contact area of ​​the semiconductor substrate. The lower metal layer 101 can also be located above the lower metal interconnect structure, specifically, the lower metal layer 101 is located on the metal through hole of the lower metal interconnect structure, or the lower metal layer 101 is located on the lower interlayer dielectric layer. This is not limited here. In the present embodiment, the lower metal layer 101 is formed by deposition. Before forming the lower metal layer 101, it also includes forming a fourth conductive layer 111 on the semiconductor substrate or the metal through hole of the lower metal interconnect structure (or the lower interlayer dielectric layer). The fourth conductive layer 111 serves as an adhesion layer to prevent problems such as cracks between the lower metal layer and the interlayer dielectric layer.

[0044] In this embodiment, the second conductive layer 112 and the fourth conductive layer 111 are made of Ti / TiN. The lower metal layer 101 is made of Al material. The interlayer dielectric layer includes oxide.

[0045] like Figure 2b As shown, a first conductive layer 113 is formed covering the bottom, sidewalls and upper surface of the interlayer dielectric layer 102 of the through hole 120. Optionally, the first conductive layer at the bottom of the through hole 120 may also be etched away. In this embodiment, the first conductive layer 113 is set to Ti / TiN. The first conductive layer 113 not only serves as an electrode of the capacitor structure, but also serves as an adhesion layer for the interlayer dielectric layer 102 and the first metal formed in the subsequent process.

[0046] like Figure 2cAs shown, a dielectric layer 114 of the first conductive layer covering the first region of the lower metal layer is formed. Specifically, a dielectric layer covering the first conductive layer is formed, and then the dielectric layer of the second region of the lower metal layer is removed by etching, so that the first conductive layer of the second region is exposed. The dielectric layer is made of a dielectric with a high dielectric constant, such as SiON, SiN, Al2O3 or HfO2.

[0047] like Figure 2d As shown, the through hole 120 is filled with the first metal 115. Specifically, the first metal is deposited in the through hole 120, and then a planarization process (etching back the first metal) is performed so that the first metal 115 is flush with the dielectric layer 114 on the first area of ​​the lower metal layer; and the first metal 115 is flush with the first conductive layer 113 on the second area of ​​the lower metal layer. The first metal 115 is set to tungsten material.

[0048] like Figure 2e As shown, in Figure 2d An upper metal layer 103 is formed on the upper surface of the structure shown. Specifically, the upper metal layer 103 is formed on the first metal 115, the dielectric layer 114 and the first conductive layer 113. The upper metal layer 103 is set to Al material. On the first area of ​​the lower metal layer, the upper metal layer 103 is in contact with the first metal 115 and the dielectric layer 114. On the second area of ​​the lower metal layer, the upper metal layer 103 is in contact with the first metal 115 and the first conductive layer 113.

[0049] Optionally, the method further includes forming a third conductive layer 116 on the upper metal layer 103. The third conductive layer is configured to be Ti / TiN.

[0050] The semiconductor device formed in this embodiment includes a capacitor structure, and the capacitor structure is located in the first area of ​​the lower metal layer. The upper electrode of the capacitor structure is the upper metal layer 103 and the first metal 115, the medium of the capacitor structure is the dielectric layer 114, and the lower electrode of the capacitor structure is the lower metal layer 101 and the first conductive layer 113. The capacitor structure can be located between the semiconductor substrate and the metal layer of the first metal interconnection structure, and of course, the capacitor structure can also be located between the metal layers of two metal interconnection structures.

[0051] The present invention also provides a semiconductor device, such as Figure 2eAs shown, the semiconductor device includes a lower metal layer 101, an interlayer dielectric 102 with a through hole, a first conductive layer 113, a dielectric layer 114, a first metal 115 and an upper metal layer 103. The lower metal layer 101 includes a first region and a second region, the interlayer dielectric layer 102 is located on the upper surface of the first region and the second region of the lower metal layer 101; the through hole extends from the upper surface of the interlayer dielectric layer 102 to the lower metal layer 101, and the through hole exposes the upper surface of the lower metal layer 101; the first conductive layer 113 covers the bottom, sidewall and upper surface of the through hole; the dielectric layer 114 covers the first conductive layer 113 on the first region of the lower metal layer; the first metal 115 fills the through hole, and the upper metal layer 103 is located on the upper surface of the interlayer dielectric layer 102, wherein the upper metal layer 103 is in contact with the first metal 115 and the dielectric layer 114 on the first region of the lower metal layer. On the second region of the lower metal layer, the upper metal layer 103 is in contact with the first metal 115 and the first conductive layer 113 .

[0052] The semiconductor device further includes a second conductive layer 112 located between the lower metal layer 101 and the interlayer dielectric layer 102, serving as an adhesion layer between the lower metal layer 101 and the interlayer dielectric layer 102. The upper metal layer 103 and the lower metal layer 101 are configured as aluminum materials. The dielectric layer 102 is configured as a medium with a high dielectric constant, specifically, the dielectric layer is configured as SiON, SiN, Al2O3 or HfO2, etc.

[0053] The semiconductor device includes a capacitor structure, wherein the upper electrode of the capacitor structure is the upper metal layer 103 and the first metal 115, the medium of the capacitor structure is the dielectric layer 102, and the lower electrode of the capacitor structure is the lower metal layer 101 and the first conductive layer 113. In this embodiment, the capacitor structure can be located between the semiconductor substrate and the metal layer of the first metal interconnection structure, that is, the lower metal layer 101 is located on the semiconductor substrate, specifically, located on the contact area of ​​the semiconductor substrate. Of course, in other embodiments, the capacitor structure can also be located between the metal layers of two metal interconnection structures, that is, the lower metal layer 101 is located on the metal through hole of the lower metal interconnection structure, or the lower metal layer 101 is located on the lower interlayer dielectric layer. In addition, the semiconductor device also includes a fourth conductive layer 111 located on the lower surface of the lower metal layer 101, specifically, the fourth conductive layer 111 is located between the lower metal layer 101 and the semiconductor substrate or between the lower metal layer and the metal through hole of the lower metal interconnection structure. Furthermore, the semiconductor device further includes a third conductive layer 116 located on the upper surface of the upper metal layer 103 .

[0054] The first conductive layer 113, the second conductive layer 112, the third conductive layer 116 and the fourth conductive layer 111 are set to Ti or TiN, the first metal is set to tungsten, and the interlayer dielectric layer includes oxide.

[0055] In this embodiment, the semiconductor device further comprises an insulating layer 100 located in the first region and the second region of the lower metal layer to isolate the first region from the second region. The semiconductor device further comprises an insulating layer located between the upper metal layers corresponding to the first region and the second region of the lower metal layer.

[0056] The present invention provides a semiconductor device with a new structure, which forms a first conductive layer, a dielectric layer and a first metal in a through hole to form a capacitor structure, and utilizes the vertical structure of the through hole to improve the density of the capacitor while keeping the cost unchanged and not increasing the complexity.

[0057] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, comprising: a lower metal layer, the lower metal layer comprising a first region and a second region; an interlayer dielectric layer located on the upper surfaces of the first region and the second region of the lower metal layer; A plurality of through holes extending from the upper surface of the interlayer dielectric layer to the lower metal layer, the through holes exposing the upper surface of the lower metal layer, and the plurality of through holes are respectively located above the first region and the second region; A first conductive layer covering the bottom, sidewalls of the through hole and the upper surface of the interlayer dielectric layer on the first area and the second area; a dielectric layer on the first conductive layer covering the first region of the lower metal layer; A first metal filling the through-holes on the first region and the second region; as well as an upper metal layer located on the upper surfaces of the dielectric layer, the first metal and the first conductive layer, It is characterized in that, on the first area of ​​the lower metal layer, the upper metal layer is in contact with the first metal and the dielectric layer; on the second area of ​​the lower metal layer, the upper metal layer is in contact with the first metal and the first conductive layer; the first area and the second area are isolated by an insulating layer, wherein the semiconductor device includes a capacitor structure, the upper electrode of the capacitor structure is the upper metal layer and the first metal in the first area, the medium of the capacitor structure is the dielectric layer, and the lower electrode of the capacitor structure is the lower metal layer and the first conductive layer in the first area.

2. The semiconductor device according to claim 1, wherein Also included is a second conductive layer located between the lower metal layer and the interlayer dielectric layer.

3. The semiconductor device according to claim 1, wherein Also included is a third conductive layer located on the upper metal layer.

4. The semiconductor device according to claim 1, wherein: The lower metal layer is located on the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein The lower metal layer is located on the metal through hole of the lower metal interconnection structure.

6. The semiconductor device according to claim 4, wherein: A fourth conductive layer is also included, and the fourth conductive layer is located between the lower metal layer and the semiconductor substrate.

7. The semiconductor device according to claim 5, wherein: A fourth conductive layer is also included, and the fourth conductive layer is located between the lower metal layer and the metal through hole of the lower metal interconnection structure.

8. The semiconductor device according to claim 1, wherein The upper metal layer and the lower metal layer are provided as aluminum.

9. The semiconductor device according to claim 1, wherein: The dielectric layer is provided as a medium having a high dielectric constant.

10. The semiconductor device according to claim 1, wherein The dielectric layer is configured as SiON or SiN or Al2O3 or HfO2.

11. The semiconductor device according to claim 2, wherein: The first conductive layer and the second conductive layer are provided with Ti or TiN.

12. The semiconductor device according to claim 1, wherein The first metal is set to be tungsten.

13. The semiconductor device according to claim 1, wherein The interlayer dielectric layer includes oxide.

14. A method for manufacturing a semiconductor device, comprising: forming an interlayer dielectric layer on an upper surface of a lower metal layer, wherein the lower metal layer includes a first region and a second region; forming a plurality of through holes extending from the upper surface of the interlayer dielectric layer to the lower metal layer in the interlayer dielectric layer, wherein the through holes expose the upper surface of the lower metal layer, and the plurality of through holes are respectively located above the first region and the second region; Forming a first conductive layer covering the bottom, sidewalls of the through hole on the first area and the second area and the upper surface of the interlayer dielectric layer; forming a dielectric layer on the first conductive layer covering the first region of the lower metal layer; filling the through hole with a first metal; and forming an upper metal layer on the upper surfaces of the dielectric layer, the first metal and the first conductive layer, Wherein, on a first region of the lower metal layer, the upper metal layer is in contact with the first metal and the dielectric layer, and the first region is isolated from the second region by an insulating layer; On the second region of the lower metal layer, the upper metal layer is in contact with the first metal and the first conductive layer; Before forming the interlayer dielectric layer, the method further includes forming a second conductive layer on the upper surface of the lower metal layer.

15. The method according to claim 14, wherein: The semiconductor device includes a capacitor structure, wherein the upper electrode of the capacitor structure is the upper metal layer and the first metal, the medium of the capacitor structure is the dielectric layer, and the lower electrode of the capacitor structure is the lower metal layer and the first conductive layer.

16. The method according to claim 14, wherein: The step of forming the dielectric layer on the first region of the lower metal layer comprises: forming a dielectric layer covering the first conductive layer on the first region and the second region of the lower metal layer; The dielectric layer located on the second area of ​​the lower metal layer is removed by etching.

17. The method according to claim 14, wherein: The method for forming the plurality of through holes comprises etching the interlayer dielectric layer from the upper surface of the interlayer dielectric layer until the upper surface of the lower metal is exposed.

18. The method according to claim 14, wherein: The method also includes forming a third conductive layer on the upper surface of the upper metal layer.

19. The method according to claim 14, wherein: The method also includes forming the lower metal layer on the semiconductor substrate by deposition.

20. The method according to claim 15, wherein: The capacitor structure is located between two metal layers of the metal interconnect structure.

21. The method according to claim 20, wherein: The method also includes forming the lower metal layer on the metal through hole of the lower metal interconnect structure by deposition.

22. The method according to claim 19, wherein: Before forming the lower metal layer, the method further includes forming a fourth conductive layer on the semiconductor substrate.

23. The method according to claim 21, wherein: Before forming the lower metal layer, the method further includes forming a fourth conductive layer on the metal through holes of the lower metal interconnect structure.

24. The method according to claim 14, wherein: The upper metal layer and the lower metal layer are provided as aluminum.

25. The method of claim 14, wherein: The dielectric layer is provided as a medium having a high dielectric constant.

26. The method of claim 14, wherein: The dielectric layer is configured as SiON or SiN or Al2O3 or HfO2.

Images