Semiconductor device including trench structure and manufacturing method

Abstract

The present invention relates to a SiC semiconductor device and a method for manufacturing the same. The semiconductor device includes a silicon carbide semiconductor body, which includes a source region of a first conductivity type and a body region of a second conductivity type. The semiconductor device also includes a trench structure extending from a first surface into the silicon carbide semiconductor body in a vertical direction, wherein the trench structure includes a gate electrode and a gate dielectric. The semiconductor device also includes a contact electrically connected to the source region at the first surface. The source region includes a first source sub-region, a second source sub-region, and a third source sub-region directly adjacent to the contact at a source contact region of the first surface.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to silicon carbide (SiC) semiconductor devices and methods for manufacturing the same. Background Art

[0002] Technological development of SiC semiconductor devices including field effect transistor units aims to reduce the area-specific on-state resistance R DS（on） Without affecting the blocking voltage capability V between the source and the drain DS Although one device characteristic can be improved by changing a certain device parameter, this may cause degradation of another device characteristic. As an example, the area-specific on-resistance R can be improved by, for example, increasing the drift region doping concentration. DS（on） , however, this may result in a blocking voltage capability V between the source and drain DS Therefore, device parameters are designed during technology development based on some trade-offs to be satisfied, given the target device specifications.

[0003] There is a need for improved silicon carbide based semiconductor devices. Summary of the invention

[0004] Embodiments of the present disclosure relate to a semiconductor device, which includes a silicon carbide semiconductor body, which includes a source region of a first conductivity type and a body region of a second conductivity type. The semiconductor device further includes: a trench structure extending from a first surface to the silicon carbide semiconductor body in a vertical direction, wherein the trench structure includes a gate electrode and a gate dielectric. The semiconductor device further includes: a contact electrically connected to the source region at the first surface. The source region includes: a first source sub-region, a second source sub-region, and a third source sub-region directly adjacent to the contact at the source contact region of the first surface. The second source sub-region is arranged between the first source sub-region and the third source sub-region in the vertical direction. The doping concentration distribution of the source region in the vertical direction includes: a minimum doping concentration in the second source sub-region and a maximum doping concentration in the third source sub-region. Each of the second source sub-region and the third source sub-region overlaps with the source contact region.

[0005] Another embodiment of the present disclosure relates to another semiconductor device, which includes a silicon carbide semiconductor body, which includes a source region of a first conductivity type and a body region of a second conductivity type. The semiconductor device further includes: a trench structure extending from the first surface into the silicon carbide semiconductor body along a vertical direction, wherein the trench structure includes a gate electrode and a gate dielectric. The trench structure is strip-shaped and extends along a longitudinal direction perpendicular to the vertical direction. The source region includes: a first source sub-region and a second source sub-region arranged alternately along the longitudinal direction. The doping concentration distribution of the first source sub-region along the vertical direction is different from the doping concentration distribution of the second source sub-region along the vertical direction.

[0006] Embodiments of the present disclosure relate to a method for manufacturing a semiconductor device. The method includes: forming a source region of a first conductivity type and a body region of a second conductivity type in a silicon carbide semiconductor body. The method further includes: forming a trench structure extending from a first surface into the silicon carbide semiconductor body in a vertical direction, wherein the trench structure includes a gate electrode and a gate dielectric. The method further includes: forming a contact electrically connected to the source region at the first surface. The source region includes: a first source sub-region, a second source sub-region, and a third source sub-region directly adjacent to the contact at a source contact region of the first surface. The second source sub-region is arranged between the first source sub-region and the third source sub-region in a vertical direction. The doping concentration distribution of the source region in the vertical direction includes: a minimum doping concentration in the second source sub-region and a maximum doping concentration in the third source sub-region. Each of the second source sub-region and the third source sub-region overlaps with the source contact region.

[0007] Embodiments of the present disclosure relate to another method for manufacturing a semiconductor device. The method includes: forming a source region of a first conductivity type and a body region of a second conductivity type in a silicon carbide semiconductor body. The method further includes: forming a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, wherein the trench structure includes a gate electrode and a gate dielectric. The trench structure is strip-shaped and extends along a longitudinal direction perpendicular to the vertical direction. The source region includes: a first source sub-region and a second source sub-region arranged alternately along the longitudinal direction. The doping concentration distribution of the first source sub-region along the vertical direction is different from the doping concentration distribution of the second source sub-region along the vertical direction.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the present embodiments of the semiconductor device and the method of manufacturing the semiconductor device and together with the present description are used to explain the principles of the embodiments. Additional embodiments and intended advantages will be readily appreciated as they become better understood by reference to the detailed description below. Additional embodiments are described in the following detailed description and claims.

[0010] Figure 1 An embodiment cross-sectional view of an embodiment of a silicon carbide semiconductor device including a source sub-region is illustrated.

[0011] Figure 2A and 2B It is used to illustrate the Figure 1 0047 is an exemplary graph of a vertical doping profile of line AA′ of the semiconductor device illustrated in FIG.

[0012] Figure 3 It is used to illustrate the Figure 1 FIG. 4 is an exemplary graph of a lateral doping concentration profile along line BB′ of the semiconductor device illustrated in FIG.

[0013] Figure 4 and Figure 5 A cross-sectional view of an embodiment of a silicon carbide semiconductor device including a source sub-region is illustrated.

[0014] Figure 6 A schematic plan view of an embodiment of a silicon carbide semiconductor device including a source sub-region is illustrated.

[0015] Figure 7 Is used for illustration Figure 6 An exemplary graph of different vertical doping concentration distributions of adjacent source sub-regions of a semiconductor device illustrated in FIG. DETAILED DESCRIPTION

[0016] In the detailed description below, reference is made to the accompanying drawings that form a part of this document and in which specific embodiments are shown by way of illustration, in which semiconductor devices can be practiced. It is to be understood that other embodiments can be utilized, and structural changes or logical changes can be made without departing from the scope of the present disclosure. For example, the features illustrated or described for one embodiment can be used on other embodiments or used in combination with other embodiments to produce another embodiment. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the attached claims. The drawings are not to scale and are for illustrative purposes only. If not otherwise stated, corresponding elements are designated by the same figure numbers in different drawings.

[0017] The terms "having", "containing", "comprising", "including", etc. are open, and these terms indicate the presence of stated structures, elements or features, but do not exclude additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. If two components are "adjacent" to each other, they can be in direct contact with each other (i.e., directly adjacent to each other) or at least in appropriate places, or can be separated from each other by a small distance. The small distance can be at most 100 nm, typically at most 20 nm or at most 10 nm.

[0018] The term "electrically connected" describes a permanent low resistance connection between electrically connected elements, such as direct contact between the elements under consideration or a low resistance connection via metal and / or heavily doped semiconductor material. The term "electrically coupled" includes that one or more intermediate elements adapted for signal and / or power transmission may be between electrically coupled elements (e.g., electrically decoupled elements controllable to temporarily provide a low resistance connection in a first state and a high resistance in a second state).

[0019] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions can have the same or different absolute doping concentrations.

[0020] Two directly adjacent doped regions of the same conductivity type and having different dopant concentrations form a unipolar junction, such as an n / n+ or p / p+ junction, along the boundary surface between the two doped regions. At the unipolar junction, the dopant concentration profile orthogonal to the unipolar junction may show a step or turning point, where the dopant concentration profile changes from concave to convex, or vice versa.

[0021] Ranges given for physical dimensions include the boundary values. For example, a parameter y ranging from a to b is read as a≤y≤b. A parameter y having a value of at least c is read as c≤y, and a parameter y having a value of at most d is read as y≤d.

[0022] An IGFET (insulated gate field effect transistor) is a voltage controlled device that includes MOSFETs (metal oxide semiconductor FETs) and other FETs having a gate electrode based on a doped semiconductor material and / or having a gate dielectric that is not or is not exclusively based on oxide.

[0023] According to an embodiment, a semiconductor device may include a silicon carbide semiconductor body including a source region of a first conductivity type and a body region of a second conductivity type. The semiconductor device may further include: a trench structure extending from a first surface to the silicon carbide semiconductor body in a vertical direction, wherein the trench structure may include a gate electrode and a gate dielectric. The semiconductor device may further include: a contact electrically connected to the source region at the first surface. The source region may include: a first source sub-region, a second source sub-region, and a third source sub-region directly adjacent to the contact at the source contact region of the first surface. The second source sub-region may be arranged between the first source sub-region and the third source sub-region in a vertical direction. The doping concentration distribution of the source region in the vertical direction may include: a minimum doping concentration in the second source sub-region and a maximum doping concentration in the third source sub-region. Each of the second source sub-region and the third source sub-region may overlap with the source contact region.

[0024] The doping concentration maximum in the third source sub-region may be a local maximum. The doping concentration minimum in the second source sub-region may be a local, in particular a global minimum. For example, the doping concentration distribution of the source region may include a global maximum in the first source sub-region. In some embodiments, the maximum in the third source sub-region may be the second highest maximum of the doping concentration distribution of the source region.

[0025] It is possible that the maximum in the third source sub-region and / or the minimum in the second source sub-region are not very distinct. This may be the case if the doping concentration in the third source sub-region is relatively low (e.g. at most 60%) compared to the doping concentration in the first source sub-region, or if the maximum in the third source sub-region is close to the minimum in the second source sub-region due to, for example, an overlap of doping profiles of different ion implantations. In this case, due to the overlap of the doping concentrations in the first source sub-region and the second source sub-region, and the overlap of the doping concentrations in the second source sub-region and the third source sub-region, the doping concentration profile may show a shoulder-shaped and / or flat curve in the region of the maximum in the third source sub-region and the minimum in the second source sub-region.

[0026] The first conductivity type may be an n-type, and the second conductivity type may be a p-type. Alternatively, the first conductivity type may be a p-type, and the second conductivity type may be an n-type.

[0027] The silicon carbide (SiC) semiconductor body may be from a hexagonal phase of silicon carbide, for example, 4H-SiC. The silicon carbide semiconductor body may have an off-direction, for example in a <11-20> or <1-100> direction. The off-axis angle of the silicon carbide semiconductor body may be in the range of 2° to 8°, typically 4°. The first surface of the silicon carbide semiconductor body may be the main extension plane of the silicon carbide semiconductor body and is spanned by a lateral direction. The vertical direction may extend perpendicular to the first surface and / or the lateral direction.

[0028] The trench structure may be vertical relative to the first surface, or may taper as the distance from the first surface increases. For example, the taper angle of the trench gate structure 150 relative to the vertical direction may be equal to the off-axis angle α, or may deviate from the off-axis angle α by no more than ±2 degrees (e.g., no more than ±1 degree), so that at least the first of the two opposite longitudinal mesa sidewalls of the SiC mesa is formed in a crystal plane with high charge carrier mobility (e.g., a {11-20} crystal plane).

[0029] The gate dielectric may separate the gate electrode from the silicon carbide semiconductor body along at least one side of the trench structure. The gate dielectric may include thermally grown or deposited silicon oxide, silicon nitride, silicon oxynitride, another deposited dielectric material, or any combination thereof or consist thereof. For example, the thickness of the gate dielectric may be selected to obtain a transistor cell having a threshold voltage in the range of from 1.0 V to 8 V (e.g., in the range of from 3.0 V to 7.0 V). The trench structure may exclusively include a gate electrode and a gate dielectric, or may include additional conductive and / or dielectric structures in addition to the gate electrode and the gate dielectric. The gate electrode and any optional additional auxiliary electrodes may include or consist of an electrode material or a combination of electrode materials, which material is, for example, a doped semiconductor material (e.g., a degenerately doped semiconductor material), such as, for example, doped polysilicon, a metal, or a metal compound.

[0030] The first source sub-region may directly adjoin the second sub-region, and the second source sub-region may directly adjoin the third source sub-region. In other words, the first source sub-region may not be separated from the second source sub-region by a certain vertical distance, and the second source sub-region may not be separated from the third source sub-region by a certain vertical distance. In addition to the first to third sub-regions, the source region may also include another source sub-region, for example, a fourth source sub-region directly adjoining the bottom side of the third source sub-region. In some embodiments, the doping concentration minimum in the second source sub-region may be formed by merging a first doping concentration tail that decreases from the first source sub-region toward the third source sub-region and a second doping concentration tail that decreases from the third source sub-region toward the first source sub-region. Therefore, the first to third source regions may be defined by a section of the vertical doping concentration distribution of the source region in the vertical direction, wherein these sections are directly adjacent to each other in the vertical direction. In some embodiments, the second source sub-region may include two or more doping concentration minimums, and one or more doping concentration maximums. Any doping concentration maximum in the second source sub-region may be less than the doping concentration maximum in the first and / or third source sub-region. The doping concentration distribution along the vertical direction may allow the body resistance of the source region to be adjusted. The body resistance may be adjusted to provide a voltage drop during a short-circuit current load that enables the line current (current filament) to be offset and the effective gate overvoltage to be reduced. When adjusting the body resistance of the source region, for example, the trade-off between i) offsetting the line current and / or reducing the effective gate overvoltage by increasing the body resistance of the source region during a short-circuit current load and ii) reducing the on-resistance of the device by reducing the body resistance of the source region may also be considered.

[0031] In some embodiments, the maximum doping concentration in the third source sub-region may be less than the maximum doping concentration in the first source sub-region. The maximum doping concentration in the first sub-region may be located at the first surface or at a small vertical distance from the first surface. The small vertical distance may be, for example, a vertical distance less than 50 nm, for example, less than 30 nm or less than 10 nm. Thus, the electrical contact resistance between the first source sub-region and the contact may be reduced or minimized. For example, the contact may include or consist of a conductive material or a combination of conductive materials, the conductive material being, for example, a doped semiconductor material (e.g., a degenerately doped semiconductor material) (such as, for example, doped polysilicon), a metal or a metal compound.

[0032] When the second (third) source sub-region overlaps the source contact region, the vertical projection of the second (third) source sub-region to the first surface at least partially coincides with the source contact region. In other words, in a plan view of the semiconductor device, the region of the second (third) source sub-region and the source contact region at least partially coincide. For example, in the vertical direction, the source contact region can be directly above the second and / or third source sub-region. This allows a compact transistor cell design. For example, outside the source contact region, the dielectric can directly adjoin the first source sub-region. For example, the dielectric can also cover the top of the trench structure.

[0033] According to an embodiment of the semiconductor device, the gate electrode may be directly opposite to each of the first source sub-region, the second source sub-region and the third source sub-region. In other words, the gate electrode faces each of the first source sub-region, the second sub-region and the third source sub-region along a lateral direction parallel to the first main surface. Therefore, a portion of the gate electrode is arranged at the same vertical distance from each of the first to third source sub-regions to the first main surface. For example, this can allow the gate resistance to the gate pad to be reduced or minimized.

[0034] According to an embodiment of the semiconductor device, a doping concentration distribution of the source region along the vertical direction may include: a doping concentration valley in the second source sub-region and a doping concentration peak in the third source sub-region. The doping concentration peak may be caused, for example, by an ion implantation process of a dopant through the first surface. For example, a doping valley in the second source sub-region may be caused by merging a first doping concentration tail that decreases from the first source sub-region toward the third source sub-region and a second doping concentration tail that decreases from the third source sub-region toward the first source sub-region. For example, the body resistance of the source region may be optimized by adjusting the doping tail.

[0035] According to an embodiment of the semiconductor device, the lateral extent of the second source sub-region may be defined between i) an interface to the sidewall of the trench structure and ii) a pn junction to the body region. The doping concentration profile of the second source sub-region may be constant along at least 80% of the lateral extent. In other words, the second source sub-region may not be divided into a plurality of sub-regions having different doping concentrations. Thus, the second source region may be formed by a single lithography process (e.g., including one or more ion implantation processes involving a mask on the first surface). For example, this may allow a simple and cost-effective adjustment of the body resistance of the source.

[0036] According to an embodiment of the semiconductor device, the doping concentration minimum in the second source sub-region may be in the range of at least 0.01% to at most 50% of the doping concentration maximum in the third source sub-region, or from 0.1% to at most 50% or from 1% to at most 30% of the doping concentration maximum in the third source sub-region. Thus, for example, the bulk resistance of the source region may be optimized.

[0037] According to an embodiment of the semiconductor device, the vertical extent of the second source sub-region may be in a range from at least 30 nm to at most 500 nm, or from at least 50 nm to at most 200 nm, or from at least 80 nm to at most 150 nm. For example, the vertical extent may be adjusted depending on the doping concentration for setting the desired bulk resistance of the source region.

[0038] According to an embodiment of the semiconductor device, at least a portion of the second source sub-region may include a dopant of the second conductivity type, wherein the dopant of the second conductivity type may partially compensate the dopant of the first conductivity type, the compensation ranging from at least 10% to at most 99.9%, or ranging from at least 10% to at most 90%, or ranging from 20% to 80%, or ranging from 30% to 70%. Partial compensation of dopants means that the donor exceeds the acceptor, or vice versa. Partial compensation provides a further degree of freedom for adjusting the desired body resistance of the source region. Partial compensation can not only be used to increase or decrease the number of donors or acceptors, but also the mobility of electrons and holes can be reduced by compensation, because the mobility is affected by the sum of donor and acceptor ions. As an example, p-type dopants in SiC (e.g., aluminum (Al) and / or Ga (Ga) and / or boron (B)) can be used to partially compensate for n-type doping caused by n-type dopants in SiC (e.g., phosphorus (P) and / or nitrogen (N)), and vice versa.

[0039] According to an embodiment, the semiconductor device may include lattice defects in the second source sub-region, wherein the lattice defects reduce the mobility of free charge carriers and may also reduce the effective doping concentration in the second source sub-region by partially compensating the donors in the second source sub-region. Exemplary implanted particles for such mobility reduction and partial anti-doping are argon (Ar), protons, helium (He), resulting in, for example, Z involving carbon vacancies. 1 / 2 Defects. The provision of lattice defects may provide a further degree of freedom for tuning the desired bulk resistance of the source region.

[0040] According to an embodiment, a semiconductor device may include a silicon carbide semiconductor body including a source region of a first conductivity type and a body region of a second conductivity type. The semiconductor device may further include a trench structure extending from a first surface into the silicon carbide semiconductor body in a vertical direction, wherein the trench structure may include a gate electrode and a gate dielectric. The trench structure may be strip-shaped and extend in a longitudinal direction perpendicular to the vertical direction. The source region may include a first source sub-region and a second source sub-region arranged alternately in the longitudinal direction. The doping concentration distribution of the first source sub-region along the vertical direction may be different from the doping concentration distribution of the second source sub-region along the vertical direction. The embodiment may allow the body resistance of the source region to be adjusted, depending on one or more of the lateral extent of the first and second source sub-regions along the longitudinal direction, the doping concentration distribution of the first and second source sub-regions along the vertical direction, and the contact scheme for electrically connecting the first and / or second source sub-regions at the first surface. This embodiment may be combined with any of the above embodiments. In other words, each of the first sub-region and the second sub-region may be divided into at least three sub-regions along the vertical direction as described in the above embodiments.

[0041] According to an embodiment of the semiconductor device, the doping amount of the first conductivity type in the first source sub-region may be greater than the doping amount of the first conductivity type in the second source sub-region. For example, the doping amount of the source sub-region may correspond to the vertical integration of the dopant of the first conductivity type between the top and the bottom of the source sub-region. In some examples, the amount may correspond to the total ion implantation dose used to manufacture the source sub-region. The doping amount is per unit area (e.g., cm -2 ) of the dopant amount. The dopant of the first conductivity type may include one or more dopant species of the first conductivity type, for example, one or more dopant elements, such as phosphorus (P) and nitrogen (N), and other suitable elements or compounds for n-type doping, or one or more dopant elements, such as boron (B), gallium (Ga) and aluminum (Al), and other suitable elements or compounds for p-type doping. The term "dopant species" refers to a specific dopant element, for example, P for n-type doping or B for p-type doping in silicon carbide. For example, the dopant may be introduced into the silicon carbide semiconductor body by means of ion implantation and / or during epitaxial growth.

[0042] According to an embodiment, the semiconductor device may further include a contact and a dielectric, wherein the contact may be electrically connected to the source region at the first surface. The dielectric may be at least partially replaced by a cavity (i.e., a hollow space). The contact may directly adjoin at least a portion of the first source sub-region at the first surface, and the dielectric may adjoin at least a portion of the second source sub-region at the first surface. In some embodiments, the contact may directly contact only the first source sub-region, and the second source sub-region may not be in direct contact with the contact.

[0043] According to an embodiment, the semiconductor device may further include a doping region of the second conductivity type arranged between the second source sub-region and the first surface.

[0044] According to an embodiment, the semiconductor device may further include a current extension region of the first conductivity type. The semiconductor device may further include a drift region of the first conductivity type, wherein the drift region may be arranged between the current extension region and the semiconductor substrate of the first conductivity type, and / or between the current extension region and the contact region of the first conductivity type, and / or between the current extension region and the buffer or drain region. The doping concentration of the current extension region may be greater than the doping concentration of the drift region. Exemplary values ​​of the average net dopant concentration in the drift region may be in the range from 10 15 cm-3 to 5x10 16 cm -3 For example, the average net dopant concentration in the current extension region may be greater than the average net dopant concentration in the drift region, for example, 5 to 1000 times, or 10 to 500 times, or 50 to 200 times. For example, the arrangement of the current extension region may allow for a further reduction in the area-specific on-resistance RDS(on).

[0045] According to an embodiment, the semiconductor device may further include a shielding region of a second conductivity type directly adjacent to at least the bottom portion of the trench structure. For example, the shielding region can protect the gate dielectric from the influence of the high electric field strength occurring during the reverse voltage mode of the semiconductor device. The shielding region may also be adjacent to the sidewall of the trench structure. The shielding region and the body region may, for example, be adjacent to the trench structure from the opposite sidewalls. For example, the body region may also be adjacent to the trench structure from the opposite sidewalls of the trench structure, and the shielding region may be adjacent to the trench structure at the bottom of the trench structure. The maximum dopant concentration in the shielding region may be higher than the maximum dopant concentration in the body region. However, in other embodiments, the maximum dopant concentration in the shielding region may be lower than the maximum dopant concentration in the body region. The vertical dopant concentration distribution in the shielding region may have a local maximum at a certain position below the trench gate structure. In addition to the protection function of the shielding region, the shielding region may also provide an integrated fly-back diode (also called a "body diode") function for the silicon carbide device.

[0046] According to an embodiment of the semiconductor device, the contact may include a positive temperature coefficient (PTC) material directly adjacent to the source region. PTC materials are conductive materials whose resistivity increases at least gradually (particularly sharply) when the switching temperature is reached. If the jump in resistivity is high enough, the resistivity can effectively block the current and prevent or offset further local heating of the semiconductor device. Exemplary PTC materials are conductive polymer composites and / or barium titanate.

[0047] According to an embodiment, a method for manufacturing a semiconductor device may include forming a source region of a first conductivity type and a body region of a second conductivity type in a silicon carbide semiconductor body. The method may further include forming a trench structure extending from a first surface to the silicon carbide semiconductor body in a vertical direction, wherein the trench structure may include a gate electrode and a gate dielectric. The method may further include: forming a contact electrically connected to the source region at the first surface, wherein the source region may include: a first source sub-region, a second source sub-region, and a third source sub-region directly adjacent to the contact at the source contact region of the first surface. The second source sub-region may be arranged between the first source sub-region and the third source sub-region in a vertical direction. The doping concentration distribution along the vertical direction of the source region may include: a doping concentration minimum in the second source sub-region and a doping concentration maximum in the third source sub-region. Each of the second source sub-region and the third source sub-region may overlap with the source contact region.

[0048] According to an embodiment of the method for manufacturing a semiconductor device, the first source sub-region, the second source sub-region, and the third source sub-region can be formed by an ion implantation process using the same ion implantation mask. In some embodiments, the first to third source sub-regions can be formed by two ion implantations with different ion implantation energies. For example, the doping peak of one of the two ion implantations can define a doping concentration maximum in the third source sub-region, and the doping concentration peak of the other of the two ion implantations can define a doping concentration maximum in the first source sub-region. For example, the doping concentration minimum in the second source sub-region can be defined by the overlap of the doping concentration tails of the two ion implantation distributions. More than two ion implantations can also be used to form the first to third source sub-regions.

[0049] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a source region of a first conductivity type and a body region of a second conductivity type in a silicon carbide semiconductor body. The method may further include: forming a trench structure extending from a first surface into the silicon carbide semiconductor body in a vertical direction, wherein the trench structure may include a gate electrode and a gate dielectric. The trench structure may be strip-shaped and extend in a longitudinal direction perpendicular to the vertical direction. The source region may include a first source sub-region and a second source sub-region alternately arranged in the longitudinal direction. The doping concentration distribution of the first source sub-region in the vertical direction may be different from the doping concentration distribution of the second source sub-region in the vertical direction.

[0050] The method can be applied to manufacture a semiconductor device as described in relation to any of the above embodiments or any of the embodiments described below in conjunction with the accompanying drawings. In at least some embodiments of the method, the following features are applied alone or in combination (if applicable):

[0051] (i) forming at least one of the source region, the body region, the current spreading region and the shielding region may include at least one masked or unmasked ion implantation process;

[0052] (ii) forming the source region may include two or more ion implantation processes with different ion implantation energies / ion implantation doses, wherein the ion implantation processes may be performed based on different ion implantation masks or may be performed based on a common ion implantation mask;

[0053] (iii) forming the source region may include: introducing lattice defects in the second source sub-region by one or more ion implantation processes.

[0054] It will be appreciated that although the method is described above and below as a series of steps or events, the order of such steps or events described is not to be interpreted in a limiting sense. Rather, some steps may occur in a different order and / or simultaneously with other steps or events other than those described above and below.

[0055] The functional and structural details described with respect to the above embodiments shall likewise apply to the exemplary embodiments illustrated in the drawings and further described below.

[0056] refer to Figure 1 1 is a schematic cross-sectional view of a semiconductor device 100 illustrating an embodiment of the semiconductor device 100 .

[0057] The semiconductor device 100 includes a silicon carbide semiconductor body 102. The silicon carbide semiconductor body 102 includes n + The first surface 110 includes a p-doped source region 104 and a p-doped body region 106. A trench structure 108 extends from the first surface 110 into the silicon carbide semiconductor body 102 along a vertical direction y. The trench structure 108 includes a gate electrode 1081 and a gate dielectric 1082. The contact 112 is electrically connected to the source region 104 at the first surface 110. The source region 104 includes: a first source sub-region 1041 directly adjacent to the contact 112 at a source contact area 113 of the first surface 110. The source region 104 further includes: a second source sub-region 1042 and a third source sub-region 1043. The second source sub-region 1042 is arranged between the first source sub-region 1041 and the third source sub-region 1043 along the vertical direction y. Each of the second source sub-region 1042 and the third source sub-region 1043 overlaps with the source contact region 113. For example, the trench structure 108 may be strip-shaped and extend along the longitudinal direction x1.

[0058] exist FIG. 2A to FIG. 2B The schematic diagram shows that the doping concentrations c1, c2, c3 of the source region 104 are along Figure 1 Example distribution of line AA'.

[0059] refer to Figure 2A , the doping concentrations c1, c2 along the vertical direction y of the source region 104 include: a doping concentration minimum or valley 150 in the second source sub-region 1042, and a doping concentration maximum or peak 151 in the third source sub-region 1043. For example, the doping concentration value at the minimum 150 can be adjusted relative to the desired bulk resistance of the source region 104.

[0060] Reference Figure 2B According to the distribution of the doping concentration c3 shown in FIG. 1 , the second source sub-region 1042 has more than one doping concentration minimum value 150. Figure 2BIn the example shown in FIG. 1 , there are two doping concentration minimum values ​​and one doping concentration maximum value in the second source sub-region 1042. The number of doping minimum values ​​and doping maximum values ​​may also be greater than Figure 2B The number shown in the figure.

[0061] In the embodiments described and illustrated herein, the plurality of groove structures 108 may be equally spaced, may have equal widths, and may form a regular stripe pattern, wherein the center-to-center distance between the groove structures 108 may be in the range of from 1 μm to 10 μm (e.g., from 2 μm to 5 μm). The length of the groove structure 108 along the longitudinal direction x1 may be up to several millimeters (e.g., at least 300 μm and at most 2 mm). The vertical extent of the groove structure 108 may be in the range of from 0.3 μm to 5 μm, for example, in the range of from 0.5 μm to 2 μm. At the bottom, the groove structure 108 may be circular.

[0062] In other embodiments (not shown in the figures), the trench structure 108 may be circular, hexagonal or square. The lateral width may then correspond approximately to the length of the trench structure 108. The channel region and / or the body region may adjoin more than one sidewall or even more than two sidewalls of the trench structure.

[0063] Figure 3 The schematic diagram illustrates the distribution of the doping concentration c4 along the lateral direction x2 defining the lateral extent of the second source sub-region 1042 (see Figure 1 The lateral extent of the second source sub-region 1042 is defined between i) the interface of the sidewalls of the trench structure 108 and ii) the pn junction 154 to the body region 106. The doping concentration c4 of the second source sub-region 104 is constant along at least 80% of the lateral extent.

[0064] exist Figure 4 Another embodiment of a semiconductor device 100 is illustrated in the schematic cross-sectional view of FIG.

[0065] The semiconductor device 100 comprises a dielectric 156 . The contact 112 directly adjoins a first portion of the first source sub-region 1041 at the first surface 110 , and the dielectric 156 adjoins a second portion of the first source sub-region 1041 at the first surface 110 .

[0066] The semiconductor device 100 further includes an n-doped current spreading region 158. The semiconductor device 100 further includes an n-doped current spreading region 158. -A doped drift region 160, wherein the drift region 160 is arranged between the current spreading region 158 and the semiconductor substrate, and / or between the current spreading region 158 and the contact region 164, and / or between the current spreading region and a buffer or highly doped drain contact region. The doping concentration of the current spreading region 158 is greater than the doping concentration of the drift region 160.

[0067] The semiconductor device 100 further includes a p-type semiconductor layer directly adjacent to at least a bottom portion of the trench structure 108. + Doped shielding region 162. The shielding region 162 also adjoins the sidewalls of the trench structure 108 opposite to the sidewalls where the source region 104 is arranged.

[0068] refer to Figure 5 , the contact 112 of the embodiment of the semiconductor device 100 further includes a positive temperature coefficient (PTC) material 1121 directly adjoining the source region 104 .

[0069] refer to Figure 6 , illustrating a top view of an embodiment of a semiconductor device 200 .

[0070] The semiconductor device 200 includes a silicon carbide semiconductor body 202. The silicon carbide semiconductor body 202 includes n + The semiconductor device 200 includes a p-doped source region 204 and a p-doped body region 206. The semiconductor device 200 includes a trench structure 208. The trench structure 208 includes a gate electrode 2081 and a gate dielectric 2082. The trench structure 208 is strip-shaped and extends along a longitudinal direction x1 perpendicular to the vertical direction y. For example, the vertical direction y is perpendicular to Figure 6 The source region 204 includes first source sub-regions 2041 and second source sub-regions 2042 alternately arranged along the longitudinal direction x1. The doping concentration distribution of the first source sub-regions 2041 along the vertical direction y is different from the doping concentration distribution of the second source sub-regions 2042 along the vertical direction y.

[0071] refer to Figure 7 Schematic diagram illustrating an exemplary distribution of doping concentration distribution along the vertical direction y. The distribution of doping concentration c5 is obtained along the vertical direction y through one of the first and second source sub-regions 2041, 2042, and the distribution of doping concentration c6 is obtained along the vertical direction through the other of the first and second source sub-regions 2041, 2042. Figure 7In the exemplary distribution of doping concentrations c5 and c6 illustrated in FIG, in the region close to the first surface 210, the concentration c5 is greater than the concentration c6. For example, according to the above-described embodiment, one or two distributions of the doping concentrations of the first sub-region 2041 and the second sub-region 2042 may be formed along the vertical direction y. According to other embodiments, one or two distributions of the doping concentrations of the first sub-region 2041 and the second sub-region 2042 may also be different from the distributions described in the above embodiments, as long as the distributions of the doping concentrations of the first sub-region 2041 and the second sub-region 2042 are different from each other.

[0072] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the invention. The present application is intended to cover any adaptation or variation of the specific embodiments discussed herein. It is therefore intended that the present invention is limited only by the claims and their equivalents.

Claims

1. A semiconductor device (100), comprising: A silicon carbide semiconductor body (102) comprising a source region (104) of a first conductivity type and a body region (106) of a second conductivity type; A trench structure (108) extending from a first surface (110) of the silicon carbide semiconductor body (102) into the silicon carbide semiconductor body (102) along a vertical direction (y), wherein the trench structure (108) comprises a gate electrode (1081) and a gate dielectric (1082); A contact (112) electrically connected to the source region (104) at the first surface (110), wherein The source region (104) comprises a first source sub-region (1041) directly adjacent to the contact (112) at the source contact region (113) of the first surface (110), a second source sub-region (1042) and a third source sub-region (1043), wherein the second source sub-region (1042) is arranged between the first source sub-region (1041) and the third source sub-region (1043) along a vertical direction (y); The doping concentration distribution (c) along the vertical direction (y) of the source region (104) includes a doping concentration minimum in the second source sub-region (1042) and a doping concentration maximum in the third source sub-region (1043), and Each of the second source sub-region (1042) and the third source sub-region (1043) overlaps with the source contact region (113).

2. The semiconductor device (100) according to claim 1, wherein: The gate electrode (1081) is directly opposite to each of the first source sub-region (1041), the second source sub-region (1042), and the third source sub-region (1043).

3. The semiconductor device (100) according to any one of the preceding claims 1 to 2, wherein: The doping concentration profile (c) along the vertical direction (y) of the source region (104) includes a doping concentration valley in the second source sub-region (1042) and a doping concentration peak in the third source sub-region (1043).

4. The semiconductor device (100) according to any one of the preceding claims 1 to 2, wherein: The lateral extent (lx) of the second source sub-region (1042) is defined between i) the interface with the sidewall of the trench structure and ii) the pn junction to the body region, and The doping concentration distribution (c) of the second source sub-region (1042) is constant along at least 80% of the lateral extent (lx).

5. The semiconductor device (100) according to any one of the preceding claims 1 to 2, wherein: The minimum doping concentration in the second source sub-region (1042) is in the range of at least 0.01% to a maximum of 50% of the maximum doping concentration in the third source sub-region (1043).

6. The semiconductor device (100) according to any one of the preceding claims 1 to 2, wherein: The vertical extent (d) of the second source sub-region (1042) is in the range from at least 30 nm to at most 300 nm.

7. The semiconductor device (100) according to any one of the preceding claims 1 to 2, wherein: At least a portion of the second source sub-region (1042) includes a dopant of the second conductivity type, wherein the dopant of the second conductivity type partially compensates for the dopant of the first conductivity type in a range from at least 10% to at most 99.9%.

8. The semiconductor device (100) according to any one of the preceding claims 1 to 2, further comprising: A lattice defect in the second source sub-region (1042), wherein the lattice defect reduces the mobility of free charge carriers in the second source sub-region.

9. The semiconductor device (100) according to any one of the preceding claims 1 to 2, further comprising: A lattice defect in the second source sub-region (1042), wherein the lattice defect reduces an effective n-type doping level in the second source sub-region.

10. A semiconductor device (200), comprising: A silicon carbide semiconductor body (202) comprising a source region (204) of a first conductivity type and a body region (206) of a second conductivity type; A trench structure (208) extending from a first surface (210) into a silicon carbide semiconductor body (202) along a vertical direction (y), wherein the trench structure (208) comprises a gate electrode (2081) and a gate dielectric (2082), and wherein the trench structure (208) is strip-shaped and extends along a longitudinal direction (x1) perpendicular to the vertical direction (y), The source region (204) includes first source sub-regions (2041) and second source sub-regions (2042) alternately arranged along a longitudinal direction (x1), and The doping concentration distribution of the first source sub-region (2041) along the vertical direction (y) is different from the doping concentration distribution of the second source sub-region (2042) along the vertical direction (y), wherein the thickness of the first source sub-region (2041) along the vertical direction (y) is equal to the thickness of the second source sub-region (2042) along the vertical direction (y).

11. The semiconductor device (200) according to claim 10, wherein: The doping amount of the first conductivity type in the first source sub-region (2041) is greater than the doping amount of the first conductivity type in the second source sub-region (2042).

12. The semiconductor device (200) according to any one of claims 10 to 11, further comprising: A contact and a dielectric, wherein the contact is electrically connected to a source region (204) at a first surface (210), wherein the contact directly adjoins at least a portion of a first source sub-region (2041) at the first surface (210), and wherein the dielectric adjoins at least a portion of a second source sub-region (2042) at the first surface (210).

13. The semiconductor device (200) according to any one of claims 10 to 11, further comprising: A doped region of the second conductivity type is arranged between the second source sub-region (2042) and the first surface (210).

14. The semiconductor device (100, 200) according to any one of the preceding claims 10 to 11, further comprising: A current spreading region (158) of a first conductivity type; a drift region (160) of a first conductivity type, wherein The drift region (160) is arranged between the current spreading region (158) and the semiconductor substrate of the first conductivity type and / or between the current spreading region (158) and the contact region (164) of the first conductivity type and / or between the current spreading region and the buffer or drain region, and The doping concentration of the current spreading region (158) is greater than the doping concentration of the drift region (160).

15. The semiconductor device (100, 200) according to any one of the preceding claims 10 to 11, further comprising: A shielding region (162) of the second conductivity type directly adjoins at least a bottom portion of the trench structure (108, 208).

16. The semiconductor device (100, 200) according to any one of the preceding claims 10 to 11, wherein: The contact (112) includes a positive temperature coefficient material (1121) directly adjacent to the source region (104, 204).

17. A method for manufacturing a semiconductor device, the method comprising: forming a source region (104) of a first conductivity type and a body region (106) of a second conductivity type in a silicon carbide semiconductor body (102); forming a trench structure (108) extending from the first surface (110) into the silicon carbide semiconductor body (102) along a vertical direction (y), wherein the trench structure (108) comprises a gate electrode (1081) and a gate dielectric (1082); A contact (112) is formed at the first surface (110) electrically connected to the source region (104), wherein The source region (104) comprises a first source sub-region (1041), a second source sub-region (1042) and a third source sub-region (1043) directly adjacent to the contact (112) at the source contact region (113) of the first surface (110), wherein the second source sub-region (1042) is arranged between the first source sub-region (1041) and the third source sub-region (1043) along a vertical direction (y); The doping concentration distribution (c) along the vertical direction (y) of the source region (104) includes a doping concentration minimum in the second source sub-region (1042) and a doping concentration maximum in the third source sub-region (1043), and Each of the second source sub-region (1042) and the third source sub-region (1043) overlaps with the source contact region (113).

18. The method according to claim 17, wherein: The first source sub-region (1041), the second source sub-region (1042), and the third source sub-region (1043) are formed by an ion implantation process using the same ion implantation mask.

19. A method for manufacturing a semiconductor device (200), the method comprising: forming a source region (204) of a first conductivity type and a body region (206) of a second conductivity type in a silicon carbide semiconductor body (202); A trench structure (208) is formed extending from a first surface (210) into a silicon carbide semiconductor body (202) along a vertical direction (y), wherein the trench structure (208) comprises a gate electrode (2081) and a gate dielectric (2082), wherein the trench structure (280) is strip-shaped and extends along a longitudinal direction (xlo) perpendicular to the vertical direction (y), and the source region (204) comprises a first source sub-region (2041) and a second source sub-region (2042) alternately arranged along the longitudinal direction (xlo); and The doping concentration distribution of the first source sub-region (2041) along the vertical direction (y) is different from the doping concentration distribution of the second source sub-region (2042) along the vertical direction (y), wherein the thickness of the first source sub-region (2041) along the vertical direction (y) is equal to the thickness of the second source sub-region (2042) along the vertical direction (y).

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