Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a substrate having a first active region and a second active region; a first active pattern and a second active pattern respectively on the first active region and the second active region; a first gate electrode and a second gate electrode respectively extending across the first active pattern and the second active pattern; and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains impurities the same as those of the high-k dielectric layer. The impurity concentration of the first work function metal pattern of the second gate electrode is greater than the impurity concentration of the work function metal pattern of the first gate electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0027042, filed with the Korean Intellectual Property Office on March 8, 2019, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including field - effect transistors and methods of manufacturing the same. Background art

[0004] Semiconductor devices include integrated circuits composed of metal - oxide - semiconductor field - effect transistors (MOSFETs). As the size and design rules of semiconductor devices gradually decrease, the size of MOSFETs also gradually shrinks. The shrinkage of MOSFETs may deteriorate the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to manufacture semiconductor devices with excellent performance while overcoming the limitations caused by the high integration of semiconductor devices. Summary of the invention

[0005] Some example embodiments of the present disclosure provide a semiconductor device having improved electrical characteristics.

[0006] According to some example embodiments of the present disclosure, a semiconductor device may include: a substrate having a first active region and a second active region; a first active pattern and a second active pattern on the first active region and the second active region, respectively; a first gate electrode and a second gate electrode extending across the first active pattern and the second active pattern, respectively; and a high - k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode may include: a work - function metal pattern on the high - k dielectric layer; and an electrode pattern on the work - function metal pattern. The second gate electrode may include: a first work - function metal pattern on the high - k dielectric layer; a second work - function metal pattern on the first work - function metal pattern; and an electrode pattern on the second work - function metal pattern. The first work - function metal pattern may contain impurities identical to those of the high - k dielectric layer. The impurity concentration of the first work - function metal pattern of the second gate electrode may be greater than the impurity concentration of the work - function metal pattern of the first gate electrode.

[0007] According to some example embodiments of the present disclosure, a semiconductor device may include: a substrate; a device isolation layer defining an active pattern on the substrate, a channel region of the active pattern protruding vertically from the device isolation layer; a gate electrode extending across the channel region; and a high-k dielectric layer between the channel region and the gate electrode. The gate electrode may include: a work function metal pattern on the high-k dielectric layer; and an electrode pattern on the work function metal pattern. The high-k dielectric layer may include: a first portion on sidewalls of the channel region; and a second portion on a top surface of the channel region. The work function metal pattern and the high-k dielectric layer may contain the same impurities. An impurity concentration of the first portion of the high-k dielectric layer may be less than an impurity concentration of the work function metal pattern.

[0008] According to some example embodiments of the present disclosure, a semiconductor device may include: a substrate; a first semiconductor pattern and a second semiconductor pattern vertically stacked on the substrate, the first semiconductor pattern and the second semiconductor pattern being spaced apart from each other in a vertical direction; a gate electrode on the first semiconductor pattern and the second semiconductor pattern; and a high-k dielectric layer between the gate electrode and the first semiconductor pattern and the second semiconductor pattern. The gate electrode may include: a first work function metal pattern on the high-k dielectric layer; and an electrode pattern on the first work function metal pattern. The high-k dielectric layer and the gate electrode may fill a first space between the first semiconductor pattern and the second semiconductor pattern. The first work function metal pattern and the high-k dielectric layer may contain the same impurities. An impurity concentration of the high-k dielectric layer may be less than an impurity concentration of the first work function metal pattern.

[0009] According to some example embodiments of the present disclosure, a method of manufacturing a semiconductor device may include: forming a device isolation layer defining an active pattern on a substrate; forming a high-k dielectric layer on an upper portion of the active pattern, the upper portion protruding from the device isolation layer; forming an impurity doping layer containing impurities on the high-k dielectric layer; and performing an annealing process on the impurity doping layer to inject the impurities into the high-k dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A plan view showing a semiconductor device according to some example embodiments of the present disclosure is shown.

[0011] Figure 2A 、 Figure 2B and Figure 2C Cross-sectional views taken along lines A-A', B-B', and C-C' of Figure 1 are shown, respectively.

[0012] Figure 3 shows Figure 2B an enlarged cross-sectional view of a portion M shown.

[0013] Figure 4 、 Figure 6 、 Figure 8 , Fig.10 and Fig.12 show a plan view of a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0014] Figure 5 , Fig. 7A , Fig. 9A , Fig.11A and Fig.13A respectively show cross-sectional views taken along line A-A' of Figure 4 , Figure 6 , Figure 8 , Fig.10 and Fig.12 .

[0015] Figure 7B , Fig. 9B , Fig. 11B and Fig. 13B respectively show cross-sectional views taken along line B-B' of Figure 6 , Figure 8 , Fig.10 and Fig.12 .

[0016] Figure 7C , Fig. 9C , Fig. 11C and Fig. 13C respectively show cross-sectional views taken along line C-C' of Figure 6 , Figure 8 , Fig.10 and Fig.12 .

[0017] Fig.14A and Fig. 14B show an enlarged cross-sectional view of portion M shown in Fig. 11B , showing a doping method according to some example embodiments of the present disclosure.

[0018] Fig.15 show a plan view of a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0019] Fig.16A , Fig. 16B and Fig. 16C respectively show cross-sectional views taken along lines A-A', B-B' and C-C' of Fig.15 .

[0020] Fig.17 show a plan view of a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0021] Fig.18A , Fig.18B and Fig.18C respectively show along Fig.17 Cross-sectional views taken along lines A-A', B-B' and C-C'.

[0022] Fig.19 A plan view showing a semiconductor device according to some example embodiments of the present disclosure is shown.

[0023] Fig. 20A Shows along Fig.19 Cross-sectional views taken along lines A-A' and B-B'.

[0024] Fig. 20B Shows along Fig.19 Cross-sectional views taken along lines C-C' and D-D'.

[0025] Fig.21A Shows Fig. 20B An enlarged cross-sectional view of the portion M shown.

[0026] Fig. 21B Shows Fig. 20B An enlarged cross-sectional view of the portion N shown.

[0027] Fig. 22 , Fig.23 And Fig.24 Shows along Fig.19 Cross-sectional views taken along lines C-C' and D-D', showing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0028] Fig.25 A plan view showing a semiconductor device according to some example embodiments of the present disclosure is shown.

[0029] Fig.26A , Fig.26B And Fig.26C Respectively show cross-sectional views taken along lines A-A', B-B' and C-C' along Fig.25 .

[0030] Fig. 27 , Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 And Fig.39 A plan view showing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure is shown.

[0031] Fig.28 , Fig. 30A , Fig.32A , Fig.34A , Fig.36A , Fig.38A And Fig.40A Respectively show along Fig. 27 , Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 and Fig.39 The cross-sectional view taken along line A-A’ of

[0032] Fig. 30B , Fig.32B , Fig.34B , Fig.36B , Fig.38B and Fig.40B respectively show the cross-sectional views taken along line B-B’ of Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 and Fig.39

[0033] Fig.32C , Fig.34C , Fig.36C , Fig.38C and Fig.40C respectively show the cross-sectional views taken along line C-C’ of Fig.31 , Fig.33 , Fig.35 , Fig.37 and Fig.39

[0034] Fig.41 shows a plan view of a semiconductor device according to some example embodiments of the present disclosure.

[0035] Fig.42A shows the cross-sectional views taken along line A-A’ and B-B’ of Fig.41

[0036] Fig.42B shows the cross-sectional views taken along line C-C’ and D-D’ of Fig.41 Detailed Description

[0037] Figure 1 shows a plan view of a semiconductor device according to some example embodiments of the present disclosure. Figure 2A , Figure 2B and Figure 2C respectively show the cross-sectional views taken along line A-A’, B-B’ and C-C’ of Figure 1 Figure 3 shows the Figure 2B magnified cross-sectional view of the portion M shown in

[0038] Reference is made to Figure 1 , FIG. 2A to FIG. 2C and Figure 3 ​​​​​, the substrate 100 can be configured to include an active region AR. The substrate 100 can be a compound semiconductor substrate or a semiconductor substrate, including silicon, germanium, silicon germanium, etc. For example, the substrate 100 can be a silicon substrate.

[0039] In some embodiments, the active region AR can be a logic unit region, which includes logic transistors that constitute the logic circuit of the semiconductor device. For example, the logic transistors that constitute the logic circuit can be disposed on the logic unit region of the substrate 100. The active region AR can include one of the logic transistors.

[0040] The active region AR can be defined by a second trench TR2 formed on the upper portion of the substrate 100. An active pattern AP can be disposed on the active region AR. The active pattern AP can extend in the second direction D2. The active pattern AP can be a vertically protruding portion of the substrate 100. A first trench TR1 can be defined between adjacent active patterns AP. The first trench TR1 can be shallower than the second trench TR2.

[0041] The device isolation layer ST can fill the first trench TR1 and the second trench TR2. The device isolation layer ST can include a silicon oxide layer. The upper portion of the active pattern AP can protrude vertically from the device isolation layer ST (see Figure 2B ). The upper portion of each active pattern AP can have a fin shape. The device isolation layer ST can not cover the upper portion of the active pattern AP. The device isolation layer ST can cover the lower sidewalls of the active pattern AP.

[0042] Source / drain patterns SD can be disposed on the upper portion of the active pattern AP. The source / drain patterns SD can be regions doped with p-type or n-type impurities. A channel region CH can be interposed between a pair of source / drain patterns SD. The source / drain patterns SD can be epitaxial patterns formed by a selective epitaxial growth process. The top surface of the source / drain patterns SD can be at a height higher than the top surface of the channel region CH.

[0043] For example, when the source / drain pattern SD is a region doped with p-type impurities, the source / drain pattern SD can include a semiconductor element (e.g., SiGe) having a lattice constant larger than the lattice constant of the semiconductor element of the substrate 100. As a result, the source / drain pattern SD can provide compressive stress to the channel region CH.

[0044] Again, for example, when the source / drain pattern SD is a region doped with n-type impurities, the source / drain pattern SD can include the same semiconductor element as the substrate 100 (e.g., Si).

[0045] The gate electrode GE can be arranged to extend in a first direction D1 while spanning the active pattern AP. The gate electrode GE can span the active region AR. The gate electrode GE can overlap with the channel region CH in the vertical direction. The gate electrode GE can surround the top surface TS and the opposing sidewalls SW of each channel region CH (see Figure 2B ).

[0046] A pair of gate spacers GS can be arranged on the opposing sidewalls of the gate electrode GE. The gate spacers GS can extend along the gate electrode GE in the first direction D1. The top surface of the gate spacers GS can be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS can be coplanar with the top surface of the first interlayer dielectric layer 110 to be described below. The gate spacers GS can include one or more of SiCN, SiCON, and SiN. Alternatively, the gate spacers GS can include a multi-layer composed of two or more of SiCN, SiCON, and SiN.

[0047] The gate capping pattern GP can be arranged on the gate electrode GE. The gate capping pattern GP can extend along the gate electrode GE in the first direction D1. The gate capping pattern GP can include a material having an etching selectivity with respect to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to be described below. For example, the gate capping pattern GP can include one or more of SiON, SiCN, SiCON, and SiN.

[0048] The gate dielectric pattern GI can be interposed between the gate electrode GE and the active pattern AP. The gate dielectric pattern GI can extend along the bottom surface of the gate electrode GE. The gate dielectric pattern GI can include an interface layer IL and a high-k dielectric layer HK between the interface layer IL and the gate electrode GE.

[0049] The interface layer IL can cover the top surface TS and the opposing sidewalls SW of the channel region CH. The high-k dielectric layer HK can also be interposed between the gate electrode GE and the gate spacers GS. The high-k dielectric layer HK can extend from the active pattern AP to the next adjacent active pattern AP. Thus, the high-k dielectric layer HK can cover the top surface of the device isolation layer ST under the gate electrode GE (see Figure 2B ).

[0050] For example, the interface layer IL can include a silicon oxide layer. The high-k dielectric layer HK can include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0051] The gate electrode GE may include a work function metal pattern WF and an electrode pattern EL on the work function metal pattern WF. The work function metal pattern WF may be disposed on the high-k dielectric layer HK. For example, the high-k dielectric layer HK may be interposed between the work function metal pattern WF and the channel region CH.

[0052] The work function metal pattern WF may include a metal nitride layer (e.g., TiN, TaN, AlN, WN, MoN, WCN, or LaN), a metal nitride layer doped with aluminum or silicon (e.g., TiAlN or TiSiN), and a metal oxide layer (e.g., Al 2 O 3 or LaO), or one or more of them. The resistance of the electrode pattern EL may be less than the resistance of the work function metal pattern WF. For example, the electrode pattern EL may include at least one low-resistance metal, such as aluminum (Al), tungsten (W), titanium (Ti), or tantalum (Ta).

[0053] The high-k dielectric layer HK on the channel region CH may include a first portion P1 on the sidewall SW of the channel region CH and a second portion P2 on the top surface TS of the channel region CH. The second portion P2 may be parallel to the top surface of the substrate 100. The first portion P1 may extend from the second portion P2 along the sidewall SW of the channel region CH to the top surface of the device isolation layer ST.

[0054] The high-k dielectric layer HK may include impurities DPT. The impurities DPT may be uniformly doped within the high-k dielectric layer HK. For example, the impurity concentration of the first portion P1 of the high-k dielectric layer HK may be substantially the same as the impurity concentration of the second portion P2 of the high-k dielectric layer HK.

[0055] Return Figure 3 Furthermore, the work function metal pattern WF may also include impurities DPT. The impurity concentration of the work function metal pattern WF may be greater than the impurity concentration of the high-k dielectric layer HK. For example, the impurity concentration of the high-k dielectric layer HK may be in the range of 0.1 atomic percentage (at%) to 5 atomic percentage (at%), and the impurity concentration of the work function metal pattern WF may be in the range of 1 at% to 10 at%.

[0056] The impurities DPT may be selected from the group consisting of nitrogen (N), fluorine (F), phosphorus (P), boron (B), and combinations thereof. For example, the impurities DPT may include nitrogen (N) and fluorine (F). In certain embodiments, the impurities DPT may include fluorine (F). In this case, the fluorine (F) concentration of the high-k dielectric layer HK on the top surface TS of the channel region CH may be substantially the same as the fluorine (F) concentration of the high-k dielectric layer HK on the sidewall SW of the channel region CH. The fluorine (F) concentration of the work function metal pattern WF may be greater than the fluorine (F) concentration of the high-k dielectric layer HK.

[0057] A first interlayer dielectric layer 110 may be disposed on the substrate 100. The first interlayer dielectric layer 110 may cover the gate spacer GS and the source / drain pattern SD. A top surface of the first interlayer dielectric layer 110 may be substantially coplanar with a top surface of the gate capping pattern GP and a top surface of the gate spacer GS. A second interlayer dielectric layer 120 covering the gate capping pattern GP may be disposed on the first interlayer dielectric layer 110. For example, the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 may include a silicon oxide layer.

[0058] An active contact AC may be disposed adjacent to opposite sides of the gate electrode GE. The active contact AC may penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 and be electrically connected to the source / drain pattern SD. The active contact AC may include at least one metal material, such as aluminum, copper, tungsten, molybdenum, or cobalt.

[0059] A silicide layer (not shown) may be interposed between the source / drain pattern SD and the active contact AC. The active contact AC may be electrically connected to the source / drain pattern SD through the silicide layer. The silicide layer may include metal silicide, such as one or more of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0060] Although not shown, a gate contact may be provided to penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP and be electrically connected to the gate electrode GE. The gate contact may include the same metal material as the active contact AC.

[0061] According to some example embodiments of the present disclosure, the high-k dielectric layer HK may include an impurity DPT. Although the high-k dielectric layer HK has a three-dimensional structure covering the top surface TS and the sidewall SW of the channel region CH, the high-k dielectric layer HK may have a uniform impurity concentration. Because the high-k dielectric layer HK includes the impurity DPT uniformly distributed therein, current leakage through the high-k dielectric layer HK may be suppressed or even prevented and the characteristics of the high-k dielectric layer HK may be improved. In addition, changes in the type and concentration of the impurity DPT may adjust the characteristics of the high-k dielectric layer HK to meet the design goals.

[0062] Figure 4 , Figure 6 , Figure 8 , Fig.10 and Fig.12 A plan view illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure is shown. Figure 5 , Fig. 7A , Fig. 9A , Fig.11A and Fig.13A The Figure 4 , Figure 6 , Figure 8 , Fig.10 and Fig.12 A sectional view taken along line A-A’ of Figure 7B , Fig. 9B , Fig. 11B and Fig. 13B respectively show sectional views taken along line B-B’ of Figure 6 , Figure 8 , Fig.10 and Fig.12 Figure 7C , Fig. 9C , Fig. 11C and Fig. 13C respectively show sectional views taken along line C-C’ of Figure 6 , Figure 8 , Fig.10 and Fig.12 Fig.14A and Fig. 14B show an enlarged sectional view of part M shown in Fig. 11B , showing a doping method according to some example embodiments of the present disclosure.

[0063] Referring to Figure 4 and Figure 5 , a substrate 100 can be provided. The upper portion of the substrate 100 can be patterned to form an active pattern AP. A first trench TR1 can be formed between the active patterns AP. The substrate 100 can be patterned to form a second trench TR2 defining an active region AR. The second trench TR2 can be formed deeper than the first trench TR1.

[0064] A device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. The device isolation layer ST can include a dielectric material, such as a silicon oxide layer. The device isolation layer ST can be recessed until the upper portion of the active pattern AP is exposed. Thus, the upper portion of the active pattern AP can protrude vertically from the device isolation layer ST.

[0065] Referring to Figure 6 and FIG. 7A to FIG. 7C , a sacrificial pattern PP can be formed to extend across the active pattern AP. The sacrificial pattern PP can be formed to have a linear or strip shape extending along a first direction D1.

[0066] For example, the formation of the sacrificial pattern PP can include: forming a sacrificial layer on the entire surface of the substrate 100, forming a hard mask pattern MA on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer can include a polysilicon layer.

[0067] ​​A pair of gate spacer walls GS can be formed on the opposing sidewalls of the sacrificial pattern PP. The gate spacer walls GS can also be formed on the opposing sidewalls of each active pattern AP. The said opposing sidewalls of each active pattern AP can be the exposed portions not covered by the device isolation layer ST and the sacrificial pattern PP.

[0068] The formation of the gate spacer walls GS can include: conformally forming a gate spacer layer on the entire surface of the substrate 100, and anisotropically etching the gate spacer layer. The gate spacer layer can include one or more of SiCN, SiCON, and SiN. Alternatively, the gate spacer layer can be a multi-layer including two or more of SiCN, SiCON, and SiN.

[0069] Reference Figure 8 And 9A to 9C , a pair of source / drain patterns SD can be formed on the upper portion of each active pattern AP. The pair of source / drain patterns SD can be formed on the opposing sides of the sacrificial pattern PP.

[0070] For example, the hard mask pattern MA and the gate spacer walls GS can be used as etching masks to etch the upper portion of the active pattern AP, which can result in the formation of a recess. While etching the upper portion of the active pattern AP, the gate spacer walls GS can also be removed from the opposing sidewalls of each active pattern AP. During the etching of the upper portion of the active pattern AP, the device isolation layer ST can be recessed at its upper portion between the active patterns AP.

[0071] The inner sidewalls of the recesses of the active pattern AP can be used as a seed layer for performing a selective epitaxial growth process to form the source / drain patterns SD. The formation of the source / drain patterns SD can define a channel region CH between the pair of source / drain patterns SD. For example, the selective epitaxial growth process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0072] The source / drain patterns SD can be doped as one of p-type and n-type. For example, impurities can be in-situ implanted during the selective epitaxial growth process for forming the source / drain patterns SD. Another example is that impurities can be implanted into the source / drain patterns SD after the formation of the source / drain patterns SD.

[0073] Reference Fig.10 And FIG. 11A to FIG. 11C , a first interlayer dielectric layer 110 can be formed to cover the source / drain patterns SD, the hard mask pattern MA, and the gate spacer walls GS. The first interlayer dielectric layer 110 can include, for example, a silicon oxide layer.

[0074] The first interlayer dielectric layer 110 can be planarized until the top surface of the sacrificial pattern PP is exposed. A etch-back or chemical mechanical polishing (CMP) process can be used to planarize the first interlayer dielectric layer 110. The hard mask pattern MA can be removed during the planarization process. As a result, the top surface of the first interlayer dielectric layer 110 can be substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0075] The exposed sacrificial pattern PP can be selectively removed to form an empty space EP. The empty space EP can be defined between a pair of gate spacers GS. A gate dielectric pattern GI can be formed in the empty space EP. The gate dielectric pattern GI can include an interface layer IL and a high-k dielectric layer HK.

[0076] For example, the interface layer IL can be formed on the top surface TS and sidewalls SW of the channel region CH exposed in the empty space EP. The formation of the interface layer IL can include oxidizing the upper portion of the exposed active pattern AP. The interface layer IL can include a silicon oxide layer.

[0077] The high-k dielectric layer HK can be conformally formed on the interface layer IL. The high-k dielectric layer HK can partially fill the empty space EP. The high-k dielectric layer HK can cover the inner sidewalls of the gate spacers GS. The high-k dielectric layer HK can be formed using a high-k dielectric material.

[0078] A capping layer CAP can be formed on the gate dielectric pattern GI. The capping layer CAP can partially fill the empty space EP. The capping layer CAP can include one or more of a metal nitride layer, a metal nitride layer doped with aluminum or silicon, and a metal oxide layer.

[0079] An impurity doped layer DDL can be formed on the capping layer CAP. The impurity doped layer DDL can partially or completely fill the empty space EP. The impurity doped layer DDL can be conformally formed on the top surface TS and sidewalls SW of the channel region CH.

[0080] According to some example embodiments of the present disclosure, the high-k dielectric layer HK can be doped through the impurity doped layer DDL. A method of doping the high-k dielectric layer HK will be discussed in detail below with reference to Fig.14A and Fig. 14B The method of doping the high-k dielectric layer HK will be discussed in detail below with reference to

[0081] Referring to Fig.14A , the impurity doped layer DDL can be doped with an impurity DPT. In certain embodiments, injecting the impurity DPT into the impurity doped layer DDL can include in-situ injecting the impurity DPT during the deposition of the impurity doped layer DDL. For example, during the deposition of the impurity doped layer DDL, an impurity gas can be introduced into the chamber to uniformly dope the impurity into the impurity doped layer DDL.

[0082] The impurity doping layer DDL may include, for example, a silicon layer or a polysilicon layer. The impurity DPT may be selected from the group consisting of nitrogen (N), fluorine (F), phosphorus (P), boron (B), and combinations thereof. The impurity concentration of the impurity doping layer DDL may be adjusted to be in the range of 0.1 at% to 20 at%.

[0083] Reference Fig. 14B , an annealing process may be performed on the impurity doping layer DDL. The annealing process may cause the impurity DPT to diffuse from the impurity doping layer DDL into the high-k dielectric layer HK. A part of the impurity DPT in the impurity doping layer DDL may migrate from the impurity doping layer DDL to the high-k dielectric layer HK through the capping layer CAP. Another part of the impurity DPT in the impurity doping layer DDL may migrate from the impurity doping layer DDL to the capping layer CAP. For example, due to the difference in the diffusion distance of the impurity DPT, a part of the impurity DPT may be implanted into the high-k dielectric layer HK, while another part of the impurity DPT may be implanted into the capping layer CAP.

[0084] The capping layer CAP may be in direct contact with the impurity doping layer DDL, and the high-k dielectric layer HK may be spaced apart from the impurity doping layer DDL with the capping layer CAP therebetween. Therefore, the impurity concentration of the capping layer CAP may be greater than the impurity concentration of the high-k dielectric layer HK.

[0085] Since the impurity doping layer DDL is conformally formed on the top surface TS and the sidewall SW of the channel region CH, the impurity concentration of the high-k dielectric layer HK on the top surface TS of the channel region CH may be substantially the same as the impurity concentration of the high-k dielectric layer HK on the sidewall SW of the channel region CH. For example, the impurity doping layer DDL may dope the high-k dielectric layer HK to have a uniform impurity concentration.

[0086] Reference Fig.12 And FIG. 13A to FIG. 13C , the impurity doping layer DDL may be selectively removed. A gate electrode GE may be formed to fill the empty space EP. A gate capping pattern GP may be formed on the gate electrode GE.

[0087] The formation of the gate electrode GE may include: forming a work function metal pattern WF on the gate dielectric pattern GI, and forming an electrode pattern EL on the work function metal pattern WF.

[0088] In some embodiments, the capping layer CAP may not be removed but may be retained. The remaining capping layer CAP may form the work function metal pattern WF. In other embodiments, after removing the impurity doping layer DDL, the capping layer CAP may be selectively removed. The work function metal pattern WF and the electrode pattern EL may be sequentially formed on the exposed gate dielectric pattern GI.

[0089] Return reference Figure 1and FIG. 2A to FIG. 2C A second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 may include a silicon oxide layer or a low-k oxide layer. For example, the low-k oxide layer may include a carbon-doped silicon oxide layer, such as SiCOH. The second interlayer dielectric layer 120 may be formed by chemical vapor deposition (CVD).

[0090] An active contact AC may be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110 and be electrically connected to the source / drain pattern SD. Although not shown, a gate contact may be formed to penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP and be electrically connected to the gate electrode GE.

[0091] Fig.15 A plan view showing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure is shown. Fig.16A 、 Fig. 16B and Fig. 16C respectively show cross-sectional views taken along lines A-A', B-B', and C-C' of Fig.15 . In the following embodiments, detailed descriptions of technical features repeated from the manufacturing method discussed above with reference to Figures 1 to 14B will be omitted, and their differences will be discussed in detail.

[0092] Reference Fig.15 and FIG. 16A to FIG. 16C , different from that discussed above with reference to Fig.10 and FIG. 11A to FIG. 11C is that the capping layer CAP may be omitted. For example, an impurity-doped layer DDL may be directly formed on the high-k dielectric layer HK. The impurity-doped layer DDL may undergo an annealing process to directly diffuse impurities from the impurity-doped layer DDL into the high-k dielectric layer HK. After that, the impurity-doped layer DDL may be removed, and then a work function metal pattern WF and an electrode pattern EL may be sequentially formed on the high-k dielectric layer HK (see Fig.12 and FIG. 13A to FIG. 13C ).

[0093] Fig.17 A plan view showing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure is shown. Fig.18A 、 Fig.18B and Fig.18C respectively show cross-sectional views taken along lines A-A', B-B', and C-C' of Fig.17 . In the following embodiments, detailed descriptions of technical features repeated from the manufacturing method discussed above with reference to Figures 1 to 14B will be omitted, and their differences will be discussed in detail.

[0094] Reference Fig.17 and 18A to 18C , different from the above reference Fig.10 and FIG. 11A to FIG. 11C is that the capping layer CAP can include multiple layers. For example, the capping layer CAP can include a first capping layer CAP1 and a second capping layer CAP2. The first capping layer CAP1 and the second capping layer CAP2 can be formed of materials different from each other. For example, the first capping layer CAP1 can be formed of a metal nitride layer (e.g., TiN), and the second capping layer CAP2 can be formed of a silicon-doped metal nitride layer (e.g., TiSiN). According to this embodiment, since the capping layer CAP is designed to have a multi-layer structure, the doping concentration and profile of the high-k dielectric layer HK can be adjusted.

[0095] Fig.19 FIG. shows a plan view of a semiconductor device according to some example embodiments of the present disclosure. Fig. 20A FIG. shows a cross-sectional view taken along Fig.19 lines A-A' and B-B'. Fig. 20B FIG. shows a cross-sectional view taken along Fig.19 lines C-C' and D-D'. Fig.21A FIG. shows an enlarged cross-sectional view of a portion M shown in Fig. 20B . Fig. 21B FIG. shows an enlarged cross-sectional view of a portion N shown in Fig. 20B . In the following embodiments, detailed descriptions of technical features repeated with the semiconductor device discussed above will be omitted, and their differences will be discussed in detail. Figure 1 , FIG. 2A to FIG. 2C and Figure 3 will be omitted, and their differences will be discussed in detail.

[0096] Referring to Fig.19 , Fig. 20A , Fig. 20B , Fig.21A and Fig. 21B , the substrate 100 can be provided to include a first active region AR1 and a second active region AR2. In some embodiments, the first active region AR1 and the second active region AR2 can be logic unit regions on which logic transistors are provided.

[0097] The first active region AR1 and the second active region AR2 can be defined by a second trench TR2 formed on the upper portion of the substrate 100. A first active pattern AP1 can be provided on the first active region AR1. A second active pattern AP2 can be provided on the second active region AR2. The first trench TR1 can be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The first trench TR1 can be shallower than the second trench TR2. The device isolation layer ST can fill the first trench TR1 and the second trench TR2.

[0098] The first source / drain pattern SD1 may be disposed on the upper portion of the first active pattern AP1. The second source / drain pattern SD2 may be disposed on the upper portion of the second active pattern AP2. For example, the first source / drain pattern SD1 may have a first conductivity type (e.g., p-type), and the second source / drain pattern SD2 may have the same first conductivity type (e.g., p-type). As another example, the first source / drain pattern SD1 may have a first conductivity type (e.g., p-type), and the second source / drain pattern SD2 may have a second conductivity type (e.g., n-type). The first channel region CH1 may be interposed between a pair of the first source / drain patterns SD1. The second channel region CH2 may be interposed between a pair of the second source / drain patterns SD2.

[0099] The first gate electrode GE1 may be disposed to extend across the first active pattern AP1, and the second gate electrode GE2 may be disposed to extend across the second active pattern AP2. The first gate electrode GE1 and the second gate electrode GE2 may overlap the first channel region CH1 and the second channel region CH2, respectively, in the vertical direction.

[0100] The first gate electrode GE1 may include a work function metal pattern WF and an electrode pattern EL on the work function metal pattern WF. The second gate electrode GE2 may include a first work function metal pattern WF1, a second work function metal pattern WF2 on the first work function metal pattern WF1, and an electrode pattern EL on the second work function metal pattern WF2.

[0101] The work function metal pattern WF of the first gate electrode GE1 may include one or more of a metal nitride layer, a metal nitride layer doped with aluminum or silicon, and a metal oxide layer. Each of the first work function metal pattern WF1 and the second work function metal pattern WF2 of the second gate electrode GE2 may include one or more of a metal nitride layer, a metal nitride layer doped with aluminum or silicon, and a metal oxide layer. For example, the second work function metal pattern WF2 may include the same material as the work function metal pattern WF of the first gate electrode GE1. The thickness of the second work function metal pattern WF2 may be substantially the same as the thickness of the work function metal pattern WF of the first gate electrode GE1.

[0102] Return reference Fig.21A and Fig. 21B For the work function metal pattern WF of the first gate electrode GE1, it may substantially not contain impurities DPT. For example, the impurity concentration of the work function metal pattern WF of the first gate electrode GE1 may be less than the impurity concentration of the high-k dielectric layer HK.

[0103] The impurity concentration of the first work function metal pattern WF1 of the second gate electrode GE2 can be greater than the impurity concentration of the high-k dielectric layer HK. The second work function metal pattern WF2 of the second gate electrode GE2 can substantially not contain impurities DPT. For example, the impurity concentration of the second work function metal pattern WF2 can be less than the impurity concentration of the first work function metal pattern WF1. The impurity concentration of the first work function metal pattern WF1 of the second gate electrode GE2 can be greater than the impurity concentration of the work function metal pattern WF of the first gate electrode GE1.

[0104] Return reference Fig.19 、 Fig. 20A and Fig. 20B , the structure of the work function metal of the first gate electrode GE1 can be different from the structure of the work function metal of the second gate electrode GE2, so the threshold voltage of the transistor on the first active region AR1 can be different from the threshold voltage of the transistor on the second active region AR2.

[0105] Fig. 22 、 Fig.23 and Fig.24 show cross-sectional views taken along lines C-C' and D-D' of Fig.19 , showing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure. In the following embodiments, detailed descriptions of technical features repeated with the manufacturing methods discussed above with reference to Figures 1 to 14B will be omitted, and their differences will be discussed in detail.

[0106] Reference Fig.19 and Fig. 22 , an empty space EP can be formed to expose the first channel region CH1 and the second channel region CH2. A gate dielectric pattern GI can be formed on the exposed first channel region CH1 and second channel region CH2. A capping layer CAP and an impurity doping layer DDL can be sequentially formed on the gate dielectric pattern GI. The impurity doping layer DDL can undergo an annealing process to cause impurities to migrate from the impurity doping layer DDL to the high-k dielectric layer HK.

[0107] Reference Fig.19 and Fig.23 , the impurity doping layer DDL can be removed. Thereafter, a mask layer MAL can be formed to fill the empty space EP on the second active region AR2. The mask layer MAL can not fill the empty space EP on the first active region AR1. Thus, the mask layer MAL can expose the first active region AR1.

[0108] The exposed capping layer CAP on the first active region AR1 can be selectively removed. The capping layer CAP on the second active region AR2 can be protected by the mask layer MAL and thus can not be removed.

[0109] Reference Fig.19 and Fig.24 , the mask layer MAL may be removed. A work function metal layer WFL may be formed on the first active area AR1 and the second active area AR2. The work function metal layer WFL on the first active area AR1 may constitute a work function metal pattern WF of the first gate electrode GE1. The capping layer CAP on the second active area AR2 may constitute a first work function metal pattern WF1 of the second gate electrode GE2. The work function metal layer WFL on the second active area AR2 may constitute a second work function metal pattern WF2 of the second gate electrode GE2.

[0110] Fig.25 A plan view showing a semiconductor device according to some example embodiments of the present disclosure is shown. Fig.26A , Fig.26B and Fig.26C The Fig.25 In the following embodiments, the cross-sectional view taken along the lines A-A', B-B' and CC' will be omitted. Figure 1 , FIG. 2A to FIG. 2C as well as Figure 3 Detailed descriptions of technical features of the discussed semiconductor devices are repeated, and their differences will be discussed in detail.

[0111] refer to Fig.25 as well as FIG. 26A to FIG. 26C , the substrate 100 may be provided to include an active region AR. A device isolation layer ST may be provided on the substrate 100. The device isolation layer ST may define an active pattern AP on an upper portion of the substrate 100. The active patterns AP may each have a line shape or a bar shape extending along the first direction D1. The device isolation layer ST may fill the trench TR between a pair of adjacent active patterns AP. A top surface of the device isolation layer ST may be lower than a top surface of the active pattern AP.

[0112] A channel region CH and a pair of source / drain patterns SD may be disposed on each active pattern AP. The channel region CH may be interposed between the pair of source / drain patterns SD. The channel region CH may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked.

[0113] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a third direction D3 perpendicular to the top surface of the substrate 100. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may overlap each other in the vertical direction. Each source / drain pattern SD may be in direct contact with the sidewalls of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be a multi-bridge channel connecting a pair of source / drain patterns SD to each other.

[0114] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may have the same thickness as each other or different thicknesses from each other. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may have different maximum lengths in a second direction D2. For example, the first length may refer to the maximum length of the first semiconductor pattern SP1 in the second direction D2. The second length may refer to the maximum length of the second semiconductor pattern SP2 in the second direction D2. The first length may be greater than the second length.

[0115] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include one or more of silicon (Si), germanium (Ge), and silicon germanium (SiGe). In the present embodiment, the channel region CH is shown to include the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, but the number of semiconductor patterns is not particularly limited.

[0116] The source / drain pattern SD may be an epitaxial pattern formed from a seed layer or from the recess RS of the active pattern AP and from the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Each source / drain pattern SD may fill the recess RS of the active pattern AP. The recess RS may be defined on each side of the opposite side of the channel region CH. The bottom surface of the recess RS may be lower than the top surface of the active pattern AP.

[0117] The source / drain pattern SD may have a maximum width in the second direction D2 at its middle portion (see Fig.26A ). The width of the source / drain pattern SD in the second direction D2 may increase as it approaches the middle portion from its upper part. The width of the source / drain pattern SD in the second direction D2 may decrease as it approaches its lower part from the middle portion.

[0118] The gate electrode GE may be disposed to extend in the first direction D1 while crossing the channel region CH. The gate electrode GE may surround the first, second, and third semiconductor patterns SP1, SP2, and SP3 (see FIG. 2 ). Fig.26B For example, the gate electrode GE may surround top and bottom surfaces and opposite sidewalls of each of the first, second, and third semiconductor patterns SP1, SP2, and SP3. The transistor according to the present embodiment may be a gate-around field effect transistor.

[0119] The gate dielectric pattern GI may be interposed between the gate electrode GE and the active pattern AP and between the gate electrode GE and the channel region CH. The gate dielectric pattern GI may include an interface layer IL and a high-k dielectric layer HK between the interface layer IL and the gate electrode GE.

[0120] The interface layer IL may directly cover the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The interface layer IL may cover the upper portion of the active pattern AP vertically protruding from the device isolation layer ST. The interface layer IL may not cover the top surface of the device isolation layer ST. The high-k dielectric layer HK may be interposed between the interface layer IL and the gate electrode GE. Figure 3 As mentioned above, the high-k dielectric layer HK may include the impurities DPT.

[0121] The gate electrode GE may include a work function metal pattern WF and an electrode pattern EL. The electrode pattern EL may be disposed on the work function metal pattern WF. The work function metal pattern WF may include one or more of a metal nitride layer, a metal nitride layer doped with aluminum or silicon, and a metal oxide layer. In some embodiments, as described above with reference to Figure 3 As described above, the work function metal pattern WF may include an impurity DPT. In other embodiments, as described above with reference to Fig.21A As described above, the work function metal pattern WF may not substantially include the impurities DPT. The electrode pattern EL may include a metal having a low resistance.

[0122] A first space SA1 may be defined between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the channel region CH. For example, the first space SA1 may be defined between a pair of vertically adjacent semiconductor patterns among the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0123] The first space SA1 may be filled with the interface layer IL, the high-k dielectric layer HK, and the work function metal pattern WF. Each of the high-k dielectric layer HK and the work function metal pattern WF may conformally fill the first space SA1. The electrode pattern EL may completely fill the remaining portion of the first space SA1, which is the space not occupied by the interface layer IL, the high-k dielectric layer HK, and the work function metal pattern WF.

[0124] A second space SA2 may be defined on the uppermost semiconductor pattern or the third semiconductor pattern SP3 of the channel region CH. The second space SA2 may be surrounded by a pair of gate spacers GS, the gate capping pattern GP, ​​and the third semiconductor pattern SP3.

[0125] The second space SA2 may be filled with the interface layer IL, the high-k dielectric layer HK, the work function metal pattern WF, and the electrode pattern EL. The interface layer IL, the high-k dielectric layer HK, the work function metal pattern WF, and the electrode pattern EL may be sequentially stacked in the second space SA2.

[0126] The substrate 100 may be provided on the entire surface thereof with a first interlayer dielectric layer 110 and a second interlayer dielectric layer 120 on the first interlayer dielectric layer 110. An active contact AC may be provided to penetrate the first and second interlayer dielectric layers 110 and 120 and be electrically connected to the source / drain pattern SD.

[0127] Fig. 27 , Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 and Fig.39 A plan view illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure is shown. Fig.28 , Fig. 30A , Fig.32A , Fig.34A , Fig.36A , Fig.38A and Fig.40A The Fig. 27 , Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 and Fig.39 A cross-sectional view taken along line AA'. Fig. 30B , Fig.32B , Fig.34B , Fig.36B , Fig.38B and Fig.40B The Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 and Fig.39 Cross-sectional view taken along line B-B’ of Fig.32C , Fig.34C , Fig.36C , Figure 38C and Figure 40C respectively show cross-sectional views taken along line C-C’ of Figure 31 , Figure 33 , Figure 35 , Figure 37 and Figure 39 In the following embodiments, detailed descriptions of technical features that are repetitive of the manufacturing methods discussed above with reference to Figures 1 to 14B will be omitted, and their differences will be discussed in detail.

[0128] Referring to Figure 27 and Figure 28 , sacrificial layer SAC and semiconductor layer SEL can be alternately and repeatedly stacked on the entire surface of substrate 100. The semiconductor layer SEL is shown stacked three times repeatedly, but the present disclosure is not limited thereto. The sacrificial layer SAC can include, for example, a material having an etching selectivity with respect to the semiconductor layer SEL. In this sense, the semiconductor layer SEL can include a material that is substantially not etched in the process of etching the sacrificial layer SAC. For example, the sacrificial layer SAC can include silicon germanium (SiGe) or germanium (Ge), and the semiconductor layer SEL can include silicon (Si).

[0129] The sacrificial layer SAC can be formed thicker than the semiconductor layer SEL. The sacrificial layer SAC and the semiconductor layer SEL can be formed by an epitaxial growth process, where the substrate 100 serves as a seed layer. The sacrificial layer SAC and the semiconductor layer SEL can be successively formed in the same chamber. The sacrificial layer SAC and the semiconductor layer SEL can be conformally grown on the entire surface of the substrate 100.

[0130] Referring to Figure 29 , Figure 30A and Figure 30B , the sacrificial layer SAC and the semiconductor layer SEL can be patterned to form a preliminary pattern PAP on the active region AR of the substrate 100. When patterning the sacrificial layer SAC and the semiconductor layer SEL, the upper portion of the substrate 100 can be etched to form trenches TR that define the active pattern AP.

[0131] The trenches TR can extend in the second direction D2 and define the sidewalls of each active pattern AP in the second direction D2. For example, the trenches TR can be formed between a pair of active patterns AP adjacent to each other in the first direction D1.

[0132] The preliminary pattern PAP can be disposed on the active pattern AP. The preliminary pattern PAP can overlap with the active pattern AP in the vertical direction. For example, the planar shape of the preliminary pattern PAP can be substantially the same as the planar shape of the active pattern AP. The preliminary pattern PAP and the active pattern AP can each be formed to have a linear or strip shape extending along the second direction D2.

[0133] A device isolation layer ST can be formed to fill the trench TR. The formation of the device isolation layer ST can include: forming a dielectric layer on the entire surface of the substrate 100, and recessing the dielectric layer until the preliminary pattern PAP is completely exposed. The top surface of the device isolation layer ST can be lower than the top surface of the active pattern AP.

[0134] Reference Figure 31 And Figures 32A to 32C , a sacrificial pattern PP can be formed to extend across the preliminary pattern PAP. The sacrificial pattern PP can be formed to have a linear or strip shape extending along the first direction D1. A pair of gate spacers GS can be formed on the opposite sidewalls of the sacrificial pattern PP.

[0135] Reference Figure 33 And Figures 34A to 34C , the mask pattern MP and the gate spacers GS can be used as an etch mask to etch the preliminary pattern PAP to form the channel region CH. The semiconductor layer SEL of the preliminary pattern PAP can be patterned to form a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3. The channel region CH can include the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0136] The preliminary pattern PAP can be etched to form a pair of recesses on the opposite sides of the channel region CH. A source / drain pattern SD can be formed to fill the recesses RS. The formation of the source / drain pattern SD can include performing a selective epitaxial growth process, in which the active pattern AP and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 are used as seed layers.

[0137] Reference Figure 35 And Figures 36A to 36C , a first interlayer dielectric layer 110 can be formed on the substrate 100. Thereafter, a planarization process can be performed on the first interlayer dielectric layer 110 until the top surface of the sacrificial pattern PP is exposed. When planarizing the first interlayer dielectric layer 110, the mask pattern MP can also be removed.

[0138] The exposed sacrificial pattern PP can be selectively removed. Removing the sacrificial pattern PP can form an empty space between a pair of adjacent gate spacers GS. The empty space can expose the sacrificial layer SAC and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0139] A selective removal process can be performed on the sacrificial layer SAC exposed in the empty space. For example, when the sacrificial layer SAC includes silicon germanium (SiGe), and when the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 include silicon (Si), the selective removal process can use an etchant including peracetic acid. The etchant can also include a hydrofluoric acid (HF) solution and deionized water.

[0140] Selective removal of the sacrificial layer SAC can define a first space SA1 between a pair of vertically adjacent semiconductor patterns among the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, the first space SA1 can be defined between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. A second space SA2 can be defined on the topmost semiconductor pattern or the third semiconductor pattern SP3. The empty space can include the first space SA1 and the second space SP2. Selective removal of the sacrificial layer SAC can expose the top surface, the bottom surface, and the sidewalls of each semiconductor pattern among the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in the empty space.

[0141] Reference Figure 37 and Figures 38A to 38C , an interface layer IL can be conformally formed on the exposed first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and on the upper portion of the exposed active pattern AP. For example, the interface layer IL can be formed by performing an oxidation process on the exposed first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the exposed active pattern AP.

[0142] A high-k dielectric layer HK can be conformally formed on the entire surface of the substrate 100. The high-k dielectric layer HK can partially fill the first space SA1. The high-k dielectric layer HK can partially fill the second space SA2. A capping layer CAP can be formed on the high-k dielectric layer HK. The capping layer CAP can partially fill the first space SA1. The capping layer CAP can partially fill the second space SA2.

[0143] An impurity-doped layer DDL can be formed on the capping layer CAP. The impurity-doped layer DDL can be formed to completely fill the first space SA1. The impurity-doped layer DDL can partially fill the second space SA2.

[0144] According to some example embodiments of the present disclosure, the high-k dielectric layer HK can be doped through the impurity-doped layer DDL. The impurity-doped layer DDL can undergo an annealing process to migrate impurities from the impurity-doped layer DDL to the high-k dielectric layer HK.

[0145] Reference Figure 39 and Figures 40A to 40C , the impurity doping layer DDL can be selectively removed. A gate electrode GE can be formed to fill the first space SA1 and the second space SA2. A gate capping pattern GP can be formed on the gate electrode GE. The formation of the gate electrode GE can include: forming a work function metal pattern WF on the high-k dielectric layer HK, and forming an electrode pattern EL on the work function metal pattern WF.

[0146] In some embodiments, the capping layer CAP may not be removed but may be retained. The remaining capping layer CAP can constitute the work function metal pattern WF. In other embodiments, after removing the impurity doping layer DDL, the capping layer CAP can be selectively removed. The work function metal pattern WF and the electrode pattern EL can be sequentially formed on the exposed high-k dielectric layer HK.

[0147] Figure 41 A plan view showing a semiconductor device according to some example embodiments of the present disclosure is shown. Figure 42A A cross-sectional view taken along line Figure 41 A - A’ and B - B’ is shown. Figure 42B A cross-sectional view taken along line Figure 41 C - C’ and D - D’ is shown. In the following embodiments, the detailed description of the technical features repeated with the semiconductor device referred to above Figure 25 and Figures 26A to 26C will be omitted, and their differences will be discussed in detail.

[0148] Reference Figure 41 , Figure 42A and Figure 42B , the substrate 100 can be provided to include a first active region AR1 and a second active region AR2. A first active pattern AP1 can be provided on the first active region AR1, and a second active pattern AP2 can be provided on the second active region AR2.

[0149] A first channel region CH1 and a pair of first source / drain patterns SD1 can be provided on each first active pattern AP1. A second channel region CH2 and a pair of second source / drain patterns SD2 can be provided on each second active pattern AP2. Each of the first channel region CH1 and the second channel region CH2 can include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. Each first source / drain pattern SD1 can fill the first recess RS1 of the first active pattern AP1. Each second source / drain pattern SD2 can fill the second recess RS2 of the second active pattern AP2.

[0150] For example, the first source / drain pattern SD1 may have a first conductivity type (e.g., p-type), and the second source / drain pattern SD2 may have the same first conductivity type (e.g., p-type). As another example, the first source / drain pattern SD1 may have a first conductivity type (e.g., p-type), and the second source / drain pattern SD2 may have a second conductivity type (e.g., n-type).

[0151] The first gate electrode GE1 may be disposed to extend across the first channel region CH1, and the second gate electrode GE2 may be disposed to extend across the second channel region CH2. The first gate electrode GE1 may include a work function metal pattern WF and an electrode pattern EL on the work function metal pattern WF. The second gate electrode GE2 may include a first work function metal pattern WF1, a second work function metal pattern WF2 on the first work function metal pattern WF1, and an electrode pattern EL on the second work function metal pattern WF2.

[0152] The interface layer IL, the high-k dielectric layer HK, the first work function metal pattern WF1, and the second work function metal pattern WF2 may fill the first space SA1 on the second active region AR2. The electrode pattern EL of the second gate electrode GE2 may not fill the first space SA1. The electrode pattern EL of the second gate electrode GE2 may be disposed in the second space SA2 on the third semiconductor pattern SP3.

[0153] The work function metal pattern WF of the first gate electrode GE1 may include one or more of a metal nitride layer, a metal nitride layer doped with aluminum or silicon, and a metal oxide layer. Each of the work function metal patterns of the first work function metal pattern WF1 and the second work function metal pattern WF2 of the second gate electrode GE2 may include one or more of a metal nitride layer, a metal nitride layer doped with aluminum or silicon, and a metal oxide layer. For example, the second work function metal pattern WF2 may include the same material as the work function metal pattern WF of the first gate electrode GE1.

[0154] As referred to above Figure 21A and Figure 21B as described, the work function metal pattern WF of the first gate electrode GE1 may substantially not contain impurities DPT. The impurity concentration of the first work function metal pattern WF1 of the second gate electrode GE2 may be greater than the impurity concentration of the high-k dielectric layer HK. The second work function metal pattern WF2 of the second gate electrode GE2 may substantially not contain impurities DPT.

[0155] The structure of the work function metal of the first gate electrode GE1 may be different from the structure of the work function metal of the second gate electrode GE2, so the threshold voltage of the transistor on the first active region AR1 may be different from the threshold voltage of the transistor on the second active region AR2.

[0156] A semiconductor device according to an embodiment of the present disclosure may include a three-dimensional high-k dielectric layer covering a three-dimensional structure channel. Although the high-k dielectric layer of the present disclosure has a three-dimensional structure, the high-k dielectric layer may have a uniform impurity concentration. Therefore, current leakage through the high-k dielectric layer can be suppressed or even prevented, and the characteristics of the high-k dielectric layer can be improved. In summary, the performance and reliability of the semiconductor device can be improved.

[0157] Although some example embodiments of the present disclosure have been discussed with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure. Therefore, it should be understood that the above example embodiments are illustrative only and in no way restrictive.

Claims

1. A semiconductor device, comprising: a substrate having a first active region and a second active region; a first active pattern and a second active pattern respectively on the first active region and the second active region; a first gate electrode and a second gate electrode respectively extending across the first active pattern and the second active pattern; and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode, wherein: the first gate electrode comprises: a work function metal pattern on the high-k dielectric layer; and an electrode pattern on the work function metal pattern, the second gate electrode comprises: a first work function metal pattern on the high-k dielectric layer; a second work function metal pattern on the first work function metal pattern; and an electrode pattern on the second work function metal pattern, the first work function metal pattern contains impurities the same as those of the high-k dielectric layer, and the impurity concentration of the first work function metal pattern of the second gate electrode is greater than the impurity concentration of the work function metal pattern of the first gate electrode.

2. The semiconductor device according to claim 1, wherein, the threshold voltage of the transistor on the first active region is different from the threshold voltage of the transistor on the second active region.

3. The semiconductor device according to claim 1, wherein, the impurity concentration of the first work function metal pattern is greater than the impurity concentration of the high-k dielectric layer.

4. The semiconductor device according to claim 1, wherein, the impurities are selected from the group consisting of nitrogen N, fluorine F, phosphorus P, boron B, and combinations thereof.

5. The semiconductor device according to claim 1, wherein, the work function metal pattern of the first gate electrode includes one or more of a metal nitride layer, a metal nitride layer doped with aluminum or silicon, and a metal oxide layer, each work function metal pattern of the first work function metal pattern and the second work function metal pattern of the second gate electrode includes one or more of a metal nitride layer, a metal nitride layer doped with aluminum or silicon, and a metal oxide layer, and the second work function metal pattern of the second gate electrode includes the same material as the work function metal pattern of the first gate electrode.

6. The semiconductor device according to claim 1, wherein, the thickness of the work function metal pattern of the first gate electrode is the same as the thickness of the second work function metal pattern of the second gate electrode.

7. The semiconductor device according to claim 1, further comprising: a device isolation layer on the substrate and defining the first active pattern and the second active pattern, wherein the channel region of each of the first active pattern and the second active pattern protrudes vertically from the device isolation layer.

8. The semiconductor device according to claim 7, wherein, the high-k dielectric layer comprises: a first portion on the sidewall of the channel region; and a second portion on the top surface of the channel region, and the impurity concentration of the first portion is the same as the impurity concentration of the second portion.

9. The semiconductor device according to claim 1, further comprising: A plurality of semiconductor patterns vertically stacked on each of the first active pattern and the second active pattern, wherein: the semiconductor patterns are spaced apart from each other in a vertical direction, the high-k dielectric layer and the first gate electrode fill a first space between the semiconductor patterns on the first active pattern, and the high-k dielectric layer and the second gate electrode fill a second space between the semiconductor patterns on the second active pattern.

10. The semiconductor device according to claim 9, wherein, both the high-k dielectric layer and the work function metal pattern of the first gate electrode partially fill the first space.

11. A semiconductor device, comprising: a substrate; a device isolation layer on the substrate and defining active patterns, a channel region of the active patterns protruding vertically from the device isolation layer; a gate electrode extending across the channel region; and a high-k dielectric layer between the channel region and the gate electrode, wherein: the gate electrode includes: a work function metal pattern on the high-k dielectric layer; and an electrode pattern on the work function metal pattern, the high-k dielectric layer includes: a first portion on sidewalls of the channel region; and a second portion on a top surface of the channel region, the work function metal pattern and the high-k dielectric layer contain the same impurities, and an impurity concentration of the first portion of the high-k dielectric layer is less than an impurity concentration of the work function metal pattern.

12. The semiconductor device according to claim 11, wherein, the first portion extends from the second portion along the sidewalls of the channel region to a top surface of the device isolation layer.

13. The semiconductor device according to claim 11, wherein, the impurity concentration of the first portion is the same as the impurity concentration of the second portion.

14. The semiconductor device according to claim 11, wherein, the impurities are selected from the group consisting of nitrogen N, fluorine F, phosphorus P, boron B, and combinations thereof.

15. The semiconductor device according to claim 11, wherein, the work function metal pattern is in direct contact with the high-k dielectric layer.

16. A semiconductor device, comprising: a substrate; a first semiconductor pattern and a second semiconductor pattern vertically stacked on the substrate, the first semiconductor pattern and the second semiconductor pattern being vertically spaced apart from each other; a gate electrode on the first semiconductor pattern and the second semiconductor pattern; and a high-k dielectric layer between the gate electrode and the first semiconductor pattern, the second semiconductor pattern, wherein: the gate electrode includes: a first work function metal pattern on the high-k dielectric layer; and an electrode pattern on the first work function metal pattern, the high-k dielectric layer and the gate electrode fill a first space between the first semiconductor pattern and the second semiconductor pattern, the first work function metal pattern and the high-k dielectric layer contain the same impurities, and an impurity concentration of the high-k dielectric layer is less than an impurity concentration of the first work function metal pattern.

17. The semiconductor device according to claim 16, wherein, The high-k dielectric layer and the first work function metal pattern both partially fill the first space.

18. The semiconductor device according to claim 16, wherein, the gate electrode further includes a second work function metal pattern, and the high-k dielectric layer, the first work function metal pattern, the second work function metal pattern, and the electrode pattern sequentially fill a second space between a pair of gate spacers on the second semiconductor pattern.

19. The semiconductor device according to claim 18, wherein, the high-k dielectric layer, the first work function metal pattern, and the second work function metal pattern fill the first space, and the electrode pattern does not fill the first space.

20. The semiconductor device according to claim 16, wherein, the impurity is selected from the group consisting of nitrogen N, fluorine F, phosphorus P, boron B, and combinations thereof.

21. A method of manufacturing a semiconductor device, the method comprising: forming a device isolation layer defining an active pattern on a substrate; forming a high-k dielectric layer on an upper portion of the active pattern, the upper portion protruding from the device isolation layer; forming a silicon layer or a polysilicon layer on the high-k dielectric layer; injecting an impurity into the silicon layer or the polysilicon layer to form an impurity-doped layer containing the impurity on the high-k dielectric layer; performing an annealing process on the impurity-doped layer to inject the impurity from the impurity-doped layer into the high-k dielectric layer; selectively removing the impurity-doped layer; forming a work function metal pattern on the high-k dielectric layer; and forming an electrode pattern on the work function metal pattern, wherein the work function metal pattern and the high-k dielectric layer contain the same impurity, and wherein the impurity concentration of the high-k dielectric layer is less than the impurity concentration of the work function metal pattern.

22. The method according to claim 21, further comprising: forming a capping layer between the high-k dielectric layer and the impurity-doped layer, wherein during the annealing process, the impurity diffuses into the capping layer and the high-k dielectric layer.

23. The method according to claim 22, further comprising: forming the work function metal pattern on the capping layer.

24. The method according to claim 22, further comprising: selectively removing the capping layer; and forming the work function metal pattern on the high-k dielectric layer.

25. The method according to claim 21, wherein, the impurity is selected from the group consisting of nitrogen N, fluorine F, phosphorus P, boron B, and combinations thereof.

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