A New High-Speed ​​Optocoupler Integrated Circuit

Abstract

The present invention discloses a novel high-speed optocoupler integrated circuit, which is cascaded in sequence by a current bias circuit, a transimpedance circuit, a comparator circuit, and a shaping buffer circuit; the transimpedance circuit adopts a current multiplexing controllable common source and common gate transimpedance, including two parts that are symmetrical up and down, each part including: a transimpedance bias circuit, a transimpedance negative feedback, and a capacitor, the input stage of the transimpedance circuit is connected with the current bias circuit and the transimpedance negative feedback, and an AC coupling capacitor is connected between the mirror current circuit and the input stage; the comparator circuit includes: a bias circuit, an amplifier circuit, an active load is connected in series at the input stage of the comparator circuit, and the input end is connected with the amplifier circuit; the shaping circuit is composed of a two-stage inverter. The present invention applies the current multiplexing method to the RGC transimpedance amplifier, improves the mutual impedance performance and obtains higher responsiveness and overall system conversion gain, while achieving the same system bandwidth.

Description

Technical Field

[0001] The invention relates to the field of optoelectronic components, and in particular to a novel high-speed optoelectronic coupling integrated circuit. Background Art

[0002] The photocoupler is an electric-optical-electrical conversion device that uses light as a medium to transmit electrical signals. It consists of a light source and a light receiving device. The light source and the light receiving device are assembled in the same sealed housing and isolated from each other by a transparent insulator. The pin of the light source is the input end, and the pin of the light receiving device is the output end. According to the speed of change of the electrical signal transmitted by the photocoupler, the photocoupler can be divided into two categories: low-speed photocouplers and high-speed photocouplers.

[0003] The main structure of the optocoupler is composed of two modules packaged together. The pin of the electric-optical conversion module is brought out as the input end, and the pin of the optical-electrical conversion module is brought out as the output end. Figure 1 As shown in the figure, light-emitting diodes and other light-emitting elements are responsible for completing the conversion from electricity to light, and then the light-receiving element restores the light into an electrical signal to supply the subsequent signal processing circuit, and electrical insulation is achieved in the middle, such as Figure 2 shown.

[0004] Take the design of a typical digital optocoupler as an example, which is often used to transmit digital signals or switch circuits. First, the current of the front circuit passes through the light-emitting device. If an infrared light-emitting tube is used, the electrical signal will be converted into infrared light. The infrared light is irradiated on the photosensitive element to generate photogenerated carriers, completing the conversion of the optical signal back to the electrical signal. Since the photosensitive device provides a weak current signal, for the digital circuit, it needs to be converted into the required standard level signal, so a low-impedance and high-gain transimpedance amplifier circuit is required to be connected later. Usually, voltage parallel negative feedback is used to reduce the input impedance and determine the gain coefficient of the circuit. The output signal of the transimpedance amplifier will be compared with the reference voltage through a comparator. After comparison, the voltage signal will be transformed into a standard logic level signal through a shaping circuit.

[0005] like Figure 3 As shown, the existing photoelectric coupling circuit includes the following modules:

[0006] (1) Transimpedance amplifier module (TIA)

[0007] The input signal is often a weak current signal at the microampere level or even nanoampere level. It is necessary to use a transimpedance circuit to convert the weak photocurrent signal into a processable voltage signal, and amplify it at the same time to facilitate further processing of the signal by the subsequent circuit. The design requires as low input impedance and current utilization as possible, which is the core circuit of the optocoupler.

[0008] (2) Comparator module (COMP)

[0009] Since the optical receiver converts external optical signals into current, but not all inputs are valid actions, we set a threshold limit on the input signal. Only when it exceeds a certain value is it considered a valid action. Therefore, we compare the voltage signal output by the transimpedance amplifier with the threshold voltage signal V we set. th By comparison, converting the pulse signal into a switching signal not only helps to extract the useful signal, but also helps to eliminate the internal noise of the system and the interference signal that may be caused by the dark current of the photosensitive device.

[0010] (3) Shaping buffer circuit module (Filter, Open-drain output buffer)

[0011] The circuit is inevitably affected by non-ideal factors such as parasitic capacitance and inductance. The rising and falling edges of the output waveform will deviate from the ideal state and there will be a large delay time, which is not conducive to the control signal of the high-speed switch. Therefore, a shaping circuit is needed to shape the obtained switching signal, reduce the delay time, and further increase the operating frequency of the circuit.

[0012] (4) Current bias circuit module (Bias circuit)

[0013] Since there are multiple stages of amplifier circuits in the circuit, each stage of the amplifier circuit needs to work in the amplification area and needs to have a suitable DC operating point when static. Therefore, the current bias module is responsible for providing the bias voltage or bias current required by each module of the system.

[0014] Transimpedance amplifiers are an essential component of many of today’s optoelectronic systems and can be found in applications such as optical frequency synthesizers (OFS), local machine-to-machine communications, and radio-over-fiber networks, where transmission speeds would suffer significantly if electrical interconnects were used.

[0015] Traditional transimpedance amplifiers include common-source amplifiers, common-drain amplifiers, and common-source and common-gate amplifiers.

[0016] like Figure 4The topology of the controlled cascode (RGC) shown in Figure 1 is shown in Figure 2. The transimpedance amplifier of the RGC structure provides low input impedance, which is essential for achieving high bandwidth in optical receivers. The low input impedance is due to the use of negative feedback. M2 and M3 form a common source and common level structure (Cascode), where M2 is called the input device and M3 is called the common source and common gate device. Assuming that both M2 and M3 work in the saturation region and do not consider the channel length modulation effect, that is, λ = 0, λ represents the channel length modulation coefficient. It can be seen that all the leakage current generated by M2 flows into M3, so the gain of the common source and common gate is the same as the gain of the common source level. Without considering the input resistance of M1, the gain is shown in Formula 1:

[0017] I D3 =g m2 V in (1)

[0018] The current output by M3 flows into M1 and enters a common source stage with source stage negative feedback for amplification, and flows through R S The current is:

[0019] V in =V1+I OUT R S (2)

[0020] In R s The node current equation is

[0021]

[0022] The gain can be obtained as

[0023]

[0024] The total gain G m Equal to the product of the gains of the common-source and common-gate stages

[0025]

[0026] Since the RGC input stage is used as a current buffer, a second voltage gain stage is required. A common drain voltage gain stage is generally selected. The common drain voltage gain stage provides less parasitic capacitance at the drain than the common source voltage gain stage, which results in less bandwidth degradation. In addition, the common drain voltage gain stage can also adjust the DC level from the RGC input stage. However, the common drain voltage gain stage may reduce the overall open-loop gain and reduce the linearity of the circuit.

[0027] High-speed photocouplers are widely used in automatic control, medical communication and other fields due to their excellent electrical isolation characteristics. However, most of the existing photocoupler circuits are made of bipolar circuits, which have slow response speeds and low photocurrent utilization rates. They require strong incident light to ensure normal signal response, so they have problems such as slow response speeds, low photocurrent utilization rates and weak anti-interference capabilities. Summary of the invention

[0028] [Technical issues]

[0029] Existing photocouplers have slow response speed, low photocurrent utilization rate and weak anti-interference ability.

[0030] [Technical solution]

[0031] The present invention provides a novel high-speed photoelectric coupling integrated circuit, comprising: a current bias circuit, a transimpedance circuit, a comparator circuit, and a shaping buffer circuit; the current bias circuit, the transimpedance circuit, the comparator circuit, and the shaping buffer circuit are cascaded in sequence; the current bias circuit provides the bias voltage or bias current required by the transimpedance circuit, the comparator circuit, and the shaping buffer circuit; the transimpedance circuit converts a weak photocurrent signal into a processable voltage signal, and amplifies the signal at the same time to facilitate further processing of the signal by subsequent circuits; the comparator circuit is used to compare the voltage signal output by the transimpedance circuit with a set threshold voltage signal, and convert the pulse signal into a switch signal. signal; the shaping buffer circuit shapes the switch signal to reduce the delay time; the transimpedance circuit adopts a current multiplexing controllable common source and common gate transimpedance, including two symmetrical parts, each part including: a transimpedance bias circuit, a transimpedance negative feedback, and a capacitor. The input stage of the transimpedance circuit is connected with the current bias circuit and the transimpedance negative feedback. The transimpedance bias circuit is a mirror current circuit, and an AC coupling capacitor is connected between the mirror current circuit and the input stage; the comparator circuit includes: a bias circuit, an amplifier circuit, an active load is connected in series to the input stage of the comparator circuit, and the input end is connected to the amplifier circuit; the shaping circuit is composed of a two-stage inverter.

[0032] In one embodiment of the present invention, the transimpedance circuit includes a P-type transistor M P11 、M P12 、M P13 , N-type transistor M N11 、M N12 、M N13， AC coupling capacitors C1, C2 and transimpedance bias circuit; M P11 The drain terminal is connected to M N11 The drain terminal, M P11 The drain terminal and M N11 The drain end of M is connected to the output end respectively; P11 The source end, M P12The gate terminal, C1 and the transimpedance bias circuit are connected in pairs, and C1 is connected to the input terminal; M P11 The gate terminal, M N11 The gate terminal, M P13 and M N13 The drain ends of M are connected in pairs; P12 The source end of M is connected to the transimpedance bias circuit and the power supply respectively. P12 The drain terminal is connected to M P13 The source end; M P13 The gate terminal of MN13 is connected to the gate terminal of MN13 and the bias voltage respectively; the gate terminal of MN13 is connected to the bias voltage; N11 The source end, M N12 The gate terminal, C2 and the transimpedance bias circuit are connected in pairs; M N12 The drain terminal is connected to M N13 The source end, M N12 The source end of M is connected to the bias circuit and ground respectively; N13 The gate terminal is connected to a bias voltage.

[0033] In one embodiment of the present invention, the comparison circuit comprises: a P-type transistor M P21 、M P22 、M P23 、M P24 、M P25 、M P26 , N-type transistor M N21 、M N22 、M N23 、M N24 、M N25 ;M P21 、M P22 、M P23 、M P24 、M P25 、M P26 、M P27 The source ends of M are connected in pairs; P22 、M P23 、M P24 、M P25 、M P26 、M P27 The gate terminal, M P23 、M P24 、M P26 、M P27 、M N23 、M N24 The drain ends of M are connected in pairs; P21 The drain terminal and M N21 The drain connection, M P21 The drain terminal and M P21 The gate terminal connection; M P22 The drain terminal and M N22The drain and gate terminals of M are connected in pairs; P25 The drain terminal and M N25 Drain, output connection; M N21 The gate terminals are connected to M N21 The drain terminal, M N22 The source end, M N26 The gate terminal is connected to ground, M N21 The drain terminal and M N21 The gate terminal connection of N21 The source end, M N22 The source end, M N25 The source end, M N26 The source ends of M are connected in pairs and grounded; N22 The drain terminal, M N22 The gate terminal, M N23 The source end, M N24 The source end, M N25 The gate terminal, M N26 The drain ends of M are connected in pairs; N23 The gate terminal is connected to the reference voltage terminal; M N24 The gate terminal is connected to the voltage input terminal; M N25 The drain end is connected to the output end.

[0034] In one embodiment of the present invention, the shaping buffer circuit includes four P-type transistors M P31 、M P32 、M P33 、M P34 ;M P31 、M P32 The drain terminal, M P33 、M P34 The gate end of the four terminals is connected in pairs; M P31 The source connection M P33 The source end, M P31 、M P33 The source end of M is connected to the power supply voltage VDD; P32 The source connection M P34 The source end, M P32 、M P34 The source ends of M are grounded respectively; P31 、M P32 The gate terminals are connected to the input terminal, M P33 、M P34 The drain ends are connected to the output ends respectively.

[0035] In one embodiment of the present invention, the transimpedance bias circuit is a current mirror.

[0036] In one implementation of the present invention, the cut-off frequencies of the AC coupling capacitors C1 and C2 are both 30 MHz.

[0037] In one embodiment of the present invention, in the transimpedance circuit, the load resistance is a resistance R between the output terminal and the ground. L1 and R L2 Composition, the R L1 and R L2 in parallel.

[0038] In one embodiment of the present invention, the current bias circuit of the optocoupler integrated circuit is a current mirror of a transimpedance circuit.

[0039] In one embodiment of the present invention, the mirror current circuit includes: P31 、M N32 and M P33 、M N34 They respectively form a group of inverters.

[0040] In one embodiment of the present invention, the input signal of the photoelectric coupling integrated circuit is a 50mV sinusoidal current signal, and the high level swing of the output voltage reaches 5V.

[0041] [Beneficial Effects]

[0042] The present invention applies the current multiplexing method to the RGC transimpedance amplifier, further improves the mutual impedance performance and obtains higher responsiveness and overall system conversion gain, while achieving the same system bandwidth.

[0043] The present invention optimizes the circuit structure of the comparator, analyzes the effect of introducing local positive feedback to improve the flipping action of the signal, and effectively reduces the delay of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is the black box diagram of the optocoupler.

[0045] Figure 2 This is a schematic diagram of an optocoupler with a simple structure.

[0046] Figure 3 Design diagram for the system.

[0047] Figure 4 It is a controlled common source and common gate circuit structure.

[0048] Figure 5 This is the current multiplexing controllable common-source common-gate (CRRGC) transimpedance amplifier of Example 1.

[0049] Figure 6 This is the circuit structure of the transimpedance amplifier of Example 1.

[0050] Figure 7 This is the transient simulation of TIA of the CRRGC structure of Example 1.

[0051] Figure 8 This is the frequency simulation of the TIA of the CRRGC structure of Example 1.

[0052] Fig. 9 This is the circuit structure of the comparator of Example 1.

[0053] Fig.10 This is a transient simulation of the comparator of Example 1.

[0054] Fig.11 This is the circuit structure of the comparator with positive feedback of Example 1.

[0055] Fig.12 This is a transient simulation of the comparator with positive feedback in Example 1.

[0056] Fig.13 This is the structure of the shaping circuit of Example 1.

[0057] FIG14 is a simulation result of the shaping circuit of Example 1, (a) input signal; (b) shaped signal.

[0058] Fig.15 This is the overall circuit structure of Example 1.

[0059] Fig.16 This is the transient simulation of the overall circuit of Example 1.

[0060] Fig.17 This is the frequency domain simulation of the overall circuit of Example 1.

[0061] Fig.18 This is a noise simulation test of the overall circuit of Example 1. DETAILED DESCRIPTION

[0062] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0063] Example 1

[0064] This embodiment provides a photoelectric coupling integrated circuit, including: a current bias circuit, a transimpedance circuit, a comparator circuit, and a shaping buffer circuit; the current bias circuit, the transimpedance circuit, the comparator circuit, and the shaping buffer circuit are cascaded in sequence.

[0065] Transimpedance Circuit

[0066] The transimpedance circuit adopts a current multiplexing controllable common source and common gate (CRRGC) transimpedance amplifier, such as Figure 5As shown. In the case where the input signal is transmitted to the two input nodes, the device is not short-circuited in the DC path, so two AC coupling capacitors are provided at the input, and the size of the input coupling capacitor is designed for a lower 30MHz cutoff frequency. A lower cutoff frequency can be achieved by using a larger capacitor, for the same DC current, and by mirroring the original circuit with a PMOS to improve the device's transconductance and circuit gain. The following equations give the expressions for the transresistance and input impedance of the CRRGC, respectively:

[0067] Z T ≈R L1 PR L2 (6)

[0068]

[0069] Due to the increased transconductance of the PMOS device and the cascode feedback loop, the input impedance of the transimpedance amplifier can be further reduced for the same DC current. The reduction in input impedance is useful even in systems that do not necessarily require high bandwidth. Using a lower input impedance transimpedance amplifier, the optical receiver can use a larger photodiode (meaning a larger photodiode capacitance), which usually results in higher responsivity and overall system conversion gain while achieving the same system bandwidth.

[0070] The transimpedance circuit uses a balanced photodiode structure. The balanced PD structure converts the input optical signal into a current signal. The current signal then flows from C1 and C2 into the upper and lower paths, and then flows into the transimpedance amplifier to convert it into a voltage signal. The balanced structure can use two photodiodes to superimpose their photocurrents to achieve higher sensitivity and suppress common-mode optical noise. A biaser is set between the two to isolate the DC bias voltage and provide a DC return path for the photodiode. If the DC current flowing through the two photodiodes does not match due to manufacturing differences or lighting differences, the biaser can provide a backup DC loop. Important indicators of the transimpedance amplifier include transimpedance gain, bandwidth, and input impedance. The pole generated by the RC time constant generated by the photodiode capacitance and the transimpedance amplifier input impedance is usually the limiting factor of the optical receiver bandwidth.

[0071] The CRRGC topology can decouple the load impedance and voltage overhead. In the RGC circuit, R L The significant increase in R will lead to voltage overhead problems, thus limiting the size of the transresistance. The load resistance of the CRRGC of the present invention is composed of R between VDD and ground. L1 and R L2Because of the composition, high transimpedance values ​​can be achieved, and the parallel load resistor also helps to assist in DC biasing because the required voltage on the output node is approximately half of VDD. Higher transimpedance gain can be achieved by adding PMOS devices as well as increasing the load resistor value, which is also beneficial for suppressing noise. The initial stage has a higher gain, which can reduce the noise impact on subsequent stages such as the balanced-unbalanced transformer and output buffer. The additional PMOS devices added to implement the current reuse technique add a noise source to the circuit, but the additional gain achieved by each device helps to eliminate the increase in the equivalent input noise of the transimpedance amplifier. However, this increased transimpedance will produce a larger time constant, with the direct consequence that we need to balance the relationship with bandwidth. The total transimpedance limit of this structure is approximately r op1 ||r on1 , and in R L1 and R L2 It can be achieved when approaching an open circuit.

[0072] Take a specific CRRGC structure transimpedance amplifier as an example, Figure 6 As shown, M P1 ~M P6 As the bias circuit of the pull-up network RGC structure and providing a current source load for the back, M N1 、M N2 、M N3 To form a mirror current source, take the pull-up network as an example, M P2 and M P3 M is the second-stage common-source common-gate circuit P7 and M P9 Provide current bias, and the input photocurrent can all flow into the subsequent amplifier circuit, which improves the utilization rate and amplification factor of the photocurrent, M P7 、M P8 and M P9 A unilateral RGC structure is formed, which serves as the input of a transimpedance amplifier with low input impedance. Low input impedance is very important for small signals.

[0073] At the same time, the symmetrical structure of the CRRGC using current multiplexing technology is also conducive to reducing the input impedance of the circuit. P10 and M N7 Using a diode connection as a load between VCC and ground GND is beneficial to increase the transimpedance value, and the parallel load also helps to assist the DC bias because the required voltage on the output node is about half of VDD. By increasing the PMOS device and increasing the load resistance value, a higher transimpedance gain can be achieved, which is also beneficial for suppressing noise. P4 and M P11 and M P6 and M P13 As a voltage shift circuit.P12 and M N3 and M P5 and M N8 The two-stage common source amplifier circuit is constructed to improve the amplification factor of the overall circuit, where M N3 and M N8 As a current source load, since the output resistance of the current mirror is very high, the current basically flows into the subsequent circuit, which can significantly improve the circuit's amplification ability. The transient simulation results of the circuit are as follows: Figure 7-8 As shown in Figure 1, assuming that the output current of the photodiode is 50uA, it can be seen from the transient curve that the transimpedance of the transimpedance amplifier is about 22KΩ. At the same time, the circuit has a bandwidth of 100MHz. The test results of the frequency simulation are shown in Figure 1. Figure 7 shown.

[0074] Comparator

[0075] Since the optical receiver converts external optical signals into current, but not all inputs are valid actions, we set a threshold limit on the input signal. Only when it exceeds a certain value is it considered a valid action. Therefore, we compare the voltage signal output by the transimpedance amplifier with the threshold voltage signal V we set. th Comparison is performed to convert the pulse signal into a switching signal, which not only helps to extract useful signals, but also helps to eliminate the noise inside the system and the interference signal that may be caused by the dark current of the photosensitive device. The circuit structure of the existing comparator is as follows: Fig. 9 shown.

[0076] The comparison circuit compares the voltage signal output by the transimpedance amplifier with the preset threshold voltage. Once the threshold voltage is exceeded, the high and low level signals are flipped and output. The threshold voltage is set to 3.2V. The transient simulation results are as follows: Fig.10 shown.

[0077] It can be seen from the simulation results that when the input signal of the comparator crosses the threshold voltage, the output signal is flipped, but the waveform is not very good, the delay time is 2.3us, and the output high level is only 3.5V, which does not meet the standard high level requirement. Fig. 9 Based on this, local positive feedback is added to reduce the delay time and increase the high-level signal, such as Fig.11 shown.

[0078] Fig.11 The circuit is compared to Fig. 9 Added M P26 and M P27 As voltage parallel feedback, when the input voltage rises, the current I DP4 Increase, due to M P27 and M P24 When it is a mirror relationship, MP27 The drain current also increases, causing I DP3 Increase, while M P26 and M P23 It also forms a mirror relationship, M P26 The drain current increases, causing the current I DP4 Further increase constitutes positive feedback. Its transient simulation of delay characteristics is as follows Fig.12 As shown in the figure, the delay time is only 0.5us and the output high level is also pulled up to 4.5V.

[0079] Shaping circuit

[0080] The circuit is inevitably affected by non-ideal factors such as parasitic capacitance and inductance. The rising and falling edges of the output waveform deviate from the ideal state and have a large delay time, which is not good for the control signal of the high-speed switch. Therefore, it is necessary to use a shaping circuit to shape the obtained switch signal to reduce the delay time and further increase the operating frequency of the circuit. The present invention adopts a shaping module composed of two-stage inverters, which uses fewer tubes and the shaping effect meets the use of digital circuits. The circuit structure is as follows Fig.13 shown.

[0081] M P31 、M N32 and M P33 、M N34 They form a group of inverters respectively. Since only half of them are turned on and the other half are turned off most of the time, VDD and ground do not directly form a current path, thereby reducing the static power consumption of the circuit and the current tailing delay caused by the current storage effect. Taking the signal in Figure 14(a) as the shaped input signal, the transient simulation result is shown in Figure 14(b).

[0082] Overall circuit

[0083] The overall circuit structure of the present invention is as follows Fig.15 After the circuit simulation verification of each module is completed, the transient simulation results of the entire circuit are as follows Fig.16 As shown in the figure, assuming that the input signal is a 50mV sinusoidal current signal, it is sent to the upper and lower transimpedance amplifiers through capacitors C1 and C2. Since the current mirror provides bias, the input current flows into the back stage, and a voltage signal with an amplitude of about 2.2V is obtained. It is then sent to a comparator with local positive feedback and finally obtained through a shaping circuit to obtain a standard digital signal square wave. It can be seen that the high-level swing of the output voltage reaches 5V.

[0084] Frequency domain simulation test

[0085] In order to improve the bandwidth and gain, a balanced photodiode structure is adopted in the circuit, and the current multiplexing method is applied to the RGC transimpedance amplifier to further improve the mutual resistance performance and obtain higher responsiveness and overall system conversion gain, while achieving the same system bandwidth. However, because the RGC structure is used as a current buffer, a second-stage gain circuit is required, so the common drain voltage gain stage is selected as the post-gain stage. The parasitic capacitance provided at the drain is smaller than the common source voltage gain stage, so that the bandwidth is less degraded. In addition, it can also adjust the DC level from the RGC input stage, although it may reduce the overall open-loop gain and reduce the linearity of the circuit. The use of two larger AC coupling capacitors at the input can achieve a lower cutoff frequency. For the same DC current, the transconductance and circuit gain of the device can also be improved due to the use of PMOS to mirror the original circuit.

[0086] Perform frequency simulation on the entire circuit system and observe the bandwidth changes. The simulation results are as follows: Fig.17 As shown, the overall frequency domain response is the same as that of the transimpedance amplifier, the bandwidth remains at 100MHz, and the gain in the high frequency band still reaches 63dB. At low frequencies, the gain is reduced due to the influence of the amplifier and the shaping circuit.

[0087] Noise simulation test

[0088] The impact of noise on circuits is an uncertain process, because the value of noise cannot be accurately predicted at any time, which is also the main difference between deterministic phenomena and random phenomena. However, in most cases, for a circuit system, the expected power of input noise can be determined. For such a deterministic signal, the expected power can be calculated using Formula 8.

[0089]

[0090] The average power of the system includes the frequency components of the noise, so the concept of average power can be abstracted into a more widely applicable noise spectrum, also known as power density spectrum (PSD), which reflects the power of the signal at each individual frequency. The PSD of the noise waveform x(t), that is, S X (f) is defined as the average power of the noise signal within 1 Hz around a certain frequency.

[0091] This patent uses a balanced PD structure to design a transimpedance amplifier, which converts the input optical signal into a current signal. The current signal then flows from C1 and C2 into the upper and lower paths, and then into the transimpedance amplifier to convert it into a voltage signal. The balanced structure can use two photodiodes to superimpose their photocurrents to achieve higher sensitivity and help reduce common-mode noise signals. The noise simulation test results of the overall circuit are shown in Figure 2. Fig.18The simulation results show that the -3dB bandwidth of the transimpedance amplifier is 100MHz, the transimpedance gain is 22kΩ, and the bandwidth of the overall circuit test is slightly reduced. The level swing at the output end also reaches the power supply voltage.

[0092] The protection scope of the present invention is not limited to the above-mentioned embodiments. Any modifications, equivalent substitutions and improvements that can be made by professionals in the field within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A novel high-speed optocoupler integrated circuit, characterized in that: include: Current bias circuit, transimpedance circuit, comparator circuit, shaping buffer circuit; The current bias circuit, the transimpedance circuit, the comparator circuit, and the shaping buffer circuit are cascaded in sequence; The current bias circuit provides the bias voltage or bias current required by the transimpedance circuit, the comparator circuit, and the shaping buffer circuit; the transimpedance circuit converts the weak photocurrent signal into a processable voltage signal, and amplifies it at the same time to facilitate the subsequent circuit to further process the signal; the comparator circuit is used to compare the voltage signal output by the transimpedance circuit with the set threshold voltage signal, and convert the pulse signal into a switch signal; the shaping buffer circuit shapes the switch signal to reduce the delay time; The transimpedance circuit adopts a current multiplexing controllable common-source common-gate transimpedance, including two symmetrical parts, each of which includes: a transimpedance bias circuit, a transimpedance negative feedback, and a capacitor. The input stage of the transimpedance circuit is connected to the current bias circuit and the transimpedance negative feedback. The transimpedance bias circuit is a mirror current circuit, and an AC coupling capacitor is connected between the mirror current circuit and the input stage. The comparator circuit comprises: a bias circuit, an amplifier circuit, an input stage of the comparator circuit is connected in series with an active load, and the input stage of the comparator circuit is connected to the amplifier circuit; The shaping buffer circuit is composed of two stages of inverters; The transimpedance circuit includes a P-type transistor M P11 、M P12 、M P13 , N-type transistor M N11 、M N12 、M N13， AC coupling capacitors C1, C2 and transimpedance bias circuit; the transimpedance circuit adopts a balanced photodiode structure, which converts the input optical signal into a current signal. The current signal then flows from C1 and C2 into the upper and lower paths, and then flows into the transimpedance amplifier to convert it into a voltage signal. M P11 The drain terminal is connected to M N11 The drain terminal, M P11 The drain terminal and M N11 The drain end of M is connected to the output end respectively; P11 The source end, M P12 The gate terminal, C1 and the transimpedance bias circuit are connected in pairs, and C1 is connected to the input terminal; M P11 The gate terminal, M N11 The gate terminal, M P13 and M N13 The drain ends of M are connected in pairs; P12 The source end of M is connected to the transimpedance bias circuit and the power supply respectively. P12 The drain terminal is connected to M P13 The source end; M P13 The gate terminal of MN13 is connected to the gate terminal of MN13 and the bias voltage respectively; the gate terminal of MN13 is connected to the bias voltage; M N11 The source end, M N12 The gate terminal, C2 and the transimpedance bias circuit are connected in pairs; M N12 The drain terminal is connected to M N13 The source end, M N12 The source end of M is connected to the bias circuit and ground respectively; N13 The gate terminal is connected to a bias voltage.

2. A novel high-speed optocoupler integrated circuit as claimed in claim 1, characterized in that: The comparator circuit comprises: a P-type transistor M P21 、M P22 、M P23 、M P24 、M P25 、M P26 , N-type transistor M N21 、M N22 、M N23 、M N24 、M N25 ; M P21 、M P22 、M P23 、M P24 、M P25 、M P26 、M P27 The source ends are connected in pairs; M P22 、M P23 、M P24 、M P25 、M P26 、M P27 The gate terminal, M P23 、M P24 、M P26 、M P27 、M N23 、M N24 The drain ends of are connected in pairs; M P21 The drain terminal and M N21 The drain connection, M P21 The drain terminal and M P21 The gate terminal connection of P22 The drain terminal and M N22 The drain and gate terminals of M are connected in pairs; P25 The drain terminal and M N25 Drain, output connection; M N21 The gate terminals are connected to M N21 The drain terminal, M N22 The source end, M N26 The gate terminal is connected to ground, M N21 The drain terminal and M N21 The gate terminal connection of N21 The source end, M N22 The source end, M N25 The source end, M N26 The source ends are connected in pairs and are grounded; M N22 The drain terminal, M N22 The gate terminal, M N23 The source end, M N24 The source end, M N25 The gate terminal, M N26 The drain ends of M are connected in pairs; N23 The gate terminal is connected to the reference voltage terminal; M N24 The gate terminal is connected to the voltage input terminal; M N25 The drain end is connected to the output end.

3. A novel high-speed optocoupler integrated circuit as claimed in claim 2, characterized in that: The shaping buffer circuit includes four P-type transistors M P31 、M P32 、M P33 、M P34 ; M P31 、M P32 The drain terminal, M P33 、M P34 The gate end of the M P31 The source connection M P33 The source end, M P31 、M P33 The source end of M is connected to the power supply voltage VDD; P32 The source connection M P34 The source end, M P32 、M P34 The source ends of M are grounded respectively; P31 、M P32 The gate terminals are connected to the input terminal, M P33 、M P34 The drain ends are connected to the output ends respectively.

4. A novel high-speed optocoupler integrated circuit as claimed in claim 3, characterized in that: The transimpedance bias circuit is a current mirror.

5. A novel high-speed optocoupler integrated circuit as claimed in claim 4, characterized in that: The cut-off frequencies of the AC coupling capacitors C1 and C2 are both 30 MHz.

6. A novel high-speed optocoupler integrated circuit as claimed in claim 5, characterized in that: In the transimpedance circuit, the load resistance is composed of the resistance R between the output terminal and the ground. L1 and R L2 Composition, the R L1 and R L2 in parallel.

7. A novel high-speed optocoupler integrated circuit as claimed in claim 6, characterized in that: The current bias circuit of the photoelectric coupling integrated circuit is a current mirror of a transimpedance circuit.

8. A novel high-speed optocoupler integrated circuit as claimed in claim 7, characterized in that: The mirror current circuit includes: P31 、M N32 and M P33 、M N34 They respectively form a group of inverters.

9. A novel high-speed optocoupler integrated circuit as claimed in claim 8, characterized in that: The input signal of the photoelectric coupling integrated circuit is a 50mV sinusoidal current signal, and the high level swing of the output voltage reaches 5V.

Images