Memory device for processing operation and operation method thereof, and data processing system

Abstract

A memory device for processing operations, a data processing system including the memory device, and a method for operating the memory device are provided. The memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes an instruction memory that stores at least one instruction provided from a host. The PIM circuit is configured to process operations using data provided by the host or data read from the memory bank, and to store at least one instruction provided by the host. The control logic is configured to decode a command / address received from the host to generate a decoding result, and to perform a control operation based on the decoding result so as to perform one of the following: i) performing a memory operation on the memory bank, and ii) the PIM circuit performing a processing operation. In response to a command / address indicating the execution of a processing operation, a count value of a program counter indicating a location of the instruction memory is controlled.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of priority to U.S. Provisional Application No. 62 / 816,509, filed in the U.S. Patent and Trademark Office on March 11, 2019, and claims the benefit of priority to Korean Patent Application No. 10-2019-0161674, filed in the Korean Intellectual Property Office on December 6, 2019, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a memory device, and more particularly, to a memory device for processing operations, a data processing system including the memory device, and a method of operating the memory device. Background Art

[0004] Semiconductor memory devices are digital electronic semiconductor devices used for digital data storage, such as computer memory. The capacity and speed of semiconductor memory devices for high-performance operation are constantly increasing. Examples of semiconductor memory devices include volatile memories such as dynamic random access memory (DRAM), which determine data by charge stored in a capacitor.

[0005] Memory devices including DRAM can be used to store data that is operated on by various operations such as neural network operations or arithmetic operations. A processor in memory (PIM) circuit in the memory device can efficiently process a large number of operations. Summary of the invention

[0006] At least one embodiment of the inventive concept provides a memory device capable of improving operation efficiency and performance when processing operations using a processor in memory (PIM) circuit in the memory device, a data processing system including the memory device, and a method of operating the memory device.

[0007] According to an exemplary embodiment of the inventive concept, a memory device is provided, including: a memory including a memory bank having a storage unit; a processor in memory (PIM) circuit; and control logic. The PIM circuit includes an instruction memory that stores at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank, and to store at least one instruction provided by the host. The control logic is configured to decode a command / address received from the host to generate a decoding result, and to perform a control operation based on the decoding result so as to perform one of the following: i) performing a memory operation on the memory bank, and ii) the PIM circuit performing a processing operation. In response to a command / address indicating the execution of a processing operation, a count value of a program counter indicating a location of the instruction memory is controlled.

[0008] According to an exemplary embodiment of the inventive concept, a method for operating a memory device including a plurality of memory banks is provided. The method includes: storing a plurality of instructions corresponding to processing operations received from a host; decoding a command / address received from the host to determine whether the address belongs to one of a first range and a second range; when it is determined that the address corresponds to the first range, performing a memory operation corresponding to the received command / address; and when it is determined that the address belongs to the second range, reading an indicated instruction from the plurality of instructions, and performing a processing operation corresponding to the read instruction in a processor in memory (PIM) circuit provided in the memory device.

[0009] According to an exemplary embodiment of the inventive concept, a data processing system including a host is provided. The host includes an address mapping memory and a memory interface. The address mapping memory is configured to store a plurality of addresses belonging to a first range for indicating a memory operation performed on a memory device, and a plurality of addresses belonging to a second range, the first range being used to indicate a memory operation performed on a memory device, and the second range being used to indicate a processing operation performed using data read from a selected memory bank in a memory bank of the memory device. The memory interface is configured to indicate that a memory operation is performed by outputting an address belonging to the first range, and to indicate that a processing operation is performed by outputting an address belonging to the second range. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a data processing system including a memory device according to an exemplary embodiment of the inventive concept;

[0012] Figure 2 It is shown Figure 1A block diagram of an implementation example of a processor in memory (PIM) circuit of a memory device of FIG.

[0013] Figure 3 is a block diagram illustrating a data processing system including a memory device according to an exemplary embodiment of the inventive concept;

[0014] Figure 4 is a block diagram illustrating an implementation example of a data processing system according to an exemplary embodiment of the inventive concept;

[0015] Figure 5 is a block diagram illustrating an example in which a memory device according to an exemplary embodiment of the inventive concept includes a high bandwidth memory (HBM);

[0016] Figure 6 is a conceptual diagram illustrating an operation example of a storage system according to an exemplary embodiment of the inventive concept;

[0017] Figure 7 and Figure 8 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the inventive concept;

[0018] Fig. 9 is a block diagram illustrating an overall implementation example of a memory device according to an exemplary embodiment of the inventive concept;

[0019] Fig.10 is a block diagram showing an example implementation of address mapping provided in a host;

[0020] Fig.11 is a diagram illustrating an example in which a memory device according to an exemplary embodiment of the inventive concept performs a neural network operation;

[0021] Fig.12 is a block diagram illustrating an example of a transmission path of information in a memory device according to an exemplary embodiment of the inventive concept;

[0022] Fig.13A and Fig. 13B is a flowchart illustrating an implementation example of an instruction executed by a memory device according to an exemplary embodiment of the inventive concept and a method of operating a memory device according to an exemplary embodiment of the inventive concept;

[0023] Fig.14 is a flowchart illustrating an operation example of a memory device that executes a loop instruction according to an exemplary embodiment of the inventive concept;

[0024] Fig.15A and Fig. 15B is a diagram illustrating basic blocks and operation examples of instructions for executing a loop according to an exemplary embodiment of the inventive concept;

[0025] Fig.16A , Fig. 16B and Fig.17 are diagrams illustrating implementation examples of instructions according to an exemplary embodiment of the inventive concept and methods of operating instructions according to an exemplary embodiment of the inventive concept; and

[0026] Fig.18 is a block diagram illustrating a server system including a data processing system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0027] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating a data processing system 10 including a memory device according to an exemplary embodiment of the inventive concept.

[0029] Reference Figure 1 , the data processing system 10 includes a memory controller 100 (e.g., a control circuit) and a memory device 200. The memory controller 100 may include a memory interface 110 (e.g., an interface circuit) and an address map 120, and may provide various signals to the memory device 200 through the memory interface 110, and may control memory operations such as writing and reading. The address map 120 may be stored in a memory or a register of the memory controller 100. For example, the memory controller 100 may provide a command CMD and an address ADD to the memory device 200 to access data DATA of the memory device 200. The command CMD may include a write command WR requesting data to be written and a read command RD requesting data to be read.

[0030] The memory controller 100 can access the memory device 200 according to a request (e.g., a message or signal) from the host HOST (e.g., a host device), and the memory interface 110 can provide an interface with the memory device 200. The memory controller 100 can communicate with the host HOST by using various protocols. For example, the memory controller 100 can communicate with the host HOST by using an interface protocol such as peripheral component interconnect-express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), or serial connection SCSI (SAS). In addition, each of the other various interface protocols such as universal serial bus (USB), multimedia card (MMC), enhanced small disk interface (ESDI) and integrated drive electronics (IDE) can be used as a communication protocol between the host HOST and the memory controller 100. Alternatively, according to an exemplary embodiment, the memory controller 100 can correspond to the host HOST or a component included in the host HOST.

[0031] The memory device 200 includes a memory 210, a processor built in memory (PIM) circuit 220, and a control logic 230 (e.g., a logic circuit). The control logic 230 includes a command decoder 231 (e.g., a decoder circuit). In addition, the memory 210 includes a plurality of memory banks BANK 1 to BANK N, and each of the memory banks BANK 1 to BANK N may include a plurality of memory cells (or a cell array including memory cells). The memory bank may be defined differently. For example, the memory bank may be defined as a component including a memory cell, or a component including one or more peripheral circuits and a memory cell.

[0032] The memory bank to which data access is to be performed may be selected using the address ADD received from the memory controller 100. In addition, a memory cell in the memory bank may be selected. In addition, the command decoder 231 may perform a decoding operation on the command / address CMD / ADD received from the memory controller 100 to generate a decoding result, and the control logic 230 may perform an internal control operation on the memory device 200 so that a memory operation is performed according to the decoding result.

[0033] On the other hand, the memory device 200 may be a dynamic random access memory (DRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, or a bus dynamic random access memory (RDRAM). However, the embodiments of the inventive concept are not limited thereto. For example, the memory device 200 may be implemented by a non-volatile memory such as a flash memory, a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), or a resistive RAM (ReRAM).

[0034] In addition, the memory device 200 may correspond to a semiconductor chip or a channel including a plurality of channels having independent interfaces in the memory device. Alternatively, the memory device 200 may correspond to a memory module. Alternatively, the memory module may include a plurality of memory chips, and Figure 1 The memory device 200 may correspond to a memory chip mounted on a module board.

[0035] Hereinafter, according to an exemplary embodiment of the inventive concept, an example of a PIM circuit 220 processing operation of the memory device 200 is described. Various operation processing operations may be performed in the memory device 200. For example, with respect to artificial intelligence (AI), at least a portion of a neural network operation may be performed in the memory device 200. For example, the host HOST may control the memory device 200 through the memory controller 100 so that at least a portion of the neural network operation is performed by the memory device 200. In addition, in the following embodiments, the memory controller 100 will be described as controlling the memory device 200. However, the embodiments of the inventive concept are not limited thereto. For example, the memory controller 100 may correspond to a component included in the host HOST, wherein the host HOST controls the memory device 200.

[0036] The memory controller 100 may send one or more instructions Inst to the memory device 200 in order to use a data processing operation. The memory device 200 may receive a plurality of instructions Inst and may store the received instructions Inst therein. For example, the PIM circuit 220 may include one or more processing elements 221 (e.g., a processor or a logic circuit) and an instruction memory (not shown) for storing the instructions Inst. Then, upon receiving a command / address CMD / ADD indicating an operation to be processed from the memory controller 100, the processing element 221 may process an operation corresponding to the instruction Inst read from the instruction memory.

[0037] According to an exemplary embodiment of the inventive concept, the memory controller 100 may send multiple instructions Inst to the memory device 200, so that multiple operations may be processed serially. For example, before processing the operation, a mode (e.g., instruction loading mode) for loading multiple instructions Inst into an instruction memory (not shown) may be executed. In the instruction loading mode, multiple instructions Inst may be loaded into the instruction memory of the memory device 200.

[0038] On the other hand, the memory controller 100 may perform a control operation so that the memory device 200 processes the operation by using a command related to a normal memory operation. For example, the bit value of the address ADD provided by the memory controller 100 may be divided into a plurality of ranges. For example, according to the bit value, the address ADD may belong to a first range indicating a memory operation or a second range indicating an operation to be processed. The memory controller 100 may manage an address map 120. The address map 120 may manage addresses belonging to a first range and addresses belonging to a second range. In addition, information about the addresses included in the address map 120 may be stored in a specified memory in the memory controller 100.

[0039] The memory device 200 may selectively perform a memory operation or an operation processing operation in response to a command / address CMD / ADD from the memory controller 100. For example, the memory device 200 may process an operation in response to a data write or read command WR / RD from the memory controller 100.

[0040] As an operation example, the memory controller 100 may send an address ADD belonging to the first range together with a write command WR and data for writing or together with a read command RD to the memory device 200. In this case, the command decoder 231 of the memory device 200 may perform a decoding operation on the received command / address CMD / ADD, and when the value of the address ADD belongs to the first range, perform a memory operation of writing data DATA to a location indicated by the address ADD of a memory bank of the memory 210 or reading data DATA from a location indicated by the address ADD of a memory bank of the memory 210. On the other hand, when the value of the address ADD belongs to the second range, based on the result of decoding the command / address CMD / ADD, the PIM circuit 220 enters an operation processing mode and processes an operation. For example, the processing element 221 of the PIM circuit 220 may process an operation by using the data DATA provided by the memory controller 100 or the data DATA read from the memory bank of the memory 210.

[0041] In addition, for example, the address ADD includes a plurality of bits, and according to the value of at least one bit in a specific position among the plurality of bits, the address ADD may belong to the first range or the second range. In addition, at least some of the remaining bits other than the bit in the specific position of the address ADD may include information indicating the location of the data DATA (e.g., a row address (RA) and a column address (CA)). As an operation example, the PIM circuit 220 may read the data DATA through the information indicating the location in the memory bank of the memory 210 from the address ADD, and may process the operation by using the read data DATA.

[0042] According to the above-described embodiments of the inventive concept, since the PIM circuit 220 of the memory device 200 processes an operation independently of a request from the host HOST in response to a command / address CMD / ADD from the memory controller 100, it is possible to prevent a memory operation request from the memory controller 100 from conflicting with an operation processing operation of the memory device 200. For example, for a memory operation or operation processing, a row of memory banks of the memory 210 may be activated. The memory controller 100 may determine the timing of providing the command / address CMD / ADD for the memory operation and operation processing. In addition, the memory controller 100 may determine the location of the memory bank, the location of the activated row, and the location of the accessed column.

[0043] In addition, according to an embodiment of the inventive concept, when a transaction for a memory operation is generated by the memory controller 100 while the memory device 200 is processing an operation, the memory operation may be delayed until the operation processing has been completed, or the memory operation may be delayed by the time spent on stopping the operation processing. However, according to an embodiment of the inventive concept, since the memory controller 100 or the host HOST including the memory controller 100 can control the operation processing timing of the memory device 200, it is possible to prevent performance degradation due to the above reasons.

[0044] On the other hand, Figure 1 In the illustrated embodiment, the processing element 221 may include various numbers of processing elements. For example, each processing element 221 may be arranged to correspond to one memory bank or not less than two memory banks.

[0045] On the other hand, the location of the data DATA on which the operation process is to be performed may be indicated by various methods. For example, as described above, information about the selection of the storage bank may be included in the address ADD accompanying the command CMD for the operation process. Alternatively, information about the storage bank where the data DATA to be used for the operation is located may be included in each instruction Inst. Alternatively, the memory device 200 may be implemented so that the location of the data to be used for the operation process is indicated based on a combination of information stored in the instruction Inst and information stored in the address ADD.

[0046] Figure 2 It is shown Figure 1 2 is a block diagram of an implementation example of a processor-in-memory (PIM) circuit of a memory device 200.

[0047] Reference Figure 1 and Figure 2 , the PIM circuit 220 includes a processing element 221, a processing controller 222 (e.g., a control circuit), a program counter 223 (e.g., a counting circuit), and an instruction memory 224. For example, the processing element 221 may include a plurality of processing elements PE to correspond to a plurality of memory banks BANK 1 to BANK N, and may process an operation corresponding to an instruction Inst loaded in the instruction memory 224. In addition, each of the plurality of processing elements PE may include a register (not shown). An operand (operand) on which an operation process (or a processing operation) may be performed to generate an operation process result and / or the operation process result may be temporarily stored in the register.

[0048] On the other hand, the processing controller 222 may control the overall operation related to the operation processing in the memory device 200. The processing controller 222 may read the instruction Inst stored in the instruction memory 224 upon receiving a command / address CMD / ADD indicating an operation to be processed from the memory controller 100, and may control the processing element PE so that the operation corresponding to the read instruction Inst may be processed.

[0049] In an exemplary embodiment, a plurality of instructions Inst 0 to Inst n-1 may be stored in the instruction memory 224 or sequentially read from the instruction memory 224. As an operation example, the program counter 223 may indicate an instruction to be read from the memory 224 by performing a program count operation. For example, in response to a command / address CMD / ADD indicating an operation to be processed from the memory controller 100, an instruction in a position corresponding to a current count value of the program counter 223 is read, and the count value may be increased based on the program count operation. Alternatively, according to various embodiments, in response to a command / address CMD / ADD indicating an operation to be processed, the current count value of the program counter 223 is increased, and an instruction may be read from a position corresponding to the increased count value.

[0050] In terms of storing the plurality of instructions Inst 0 to Inst n-1 in the instruction memory 224, various methods may be applied. For example, an address is assigned to the instruction memory 224, and the assigned address may be provided by the memory controller 100 during the instruction loading process. For example, the memory controller 100 may provide the address and the instruction together to the memory device 200, the address indicating the location within the instruction memory 224 for storing the instruction. In addition, by applying a storage method based on a circular queue, the size of the instruction memory 224 may be reduced by overwriting instructions. For example, the instruction memory 224 may store a fixed number of instructions, and when a new instruction exceeding the fixed number is received, the oldest instruction or the least recently used instruction stored in the instruction memory 224 may be overwritten with the new instruction.

[0051] On the other hand, the processing controller 222 can control the route of the data DATA on which the operation processing is to be performed based on the decoded command / address CMD / ADD. For example, in the memory device 200, a circuit (not shown) for controlling the path of the data DATA provided to the memory bank of the memory 210 or the data DATA read from the memory bank of the memory 210 may be included, and the circuit may be controlled so that the data DATA to be used for the operation can be provided to the processing element PE. According to various embodiments, based on the control of the processing controller 222 or the control of the control logic 230, the data DATA from the host HOST may be provided to the processing element PE. Alternatively, the data DATA may be read from the location indicated by the address ADD of the memory bank of the memory 210, and the data DATA may be provided to the processing element PE.

[0052] As in Figure 2As in the embodiment shown in , multiple instructions for processing operations are preloaded, and in response to the command / address CMD / ADD indicating the operation to be processed from the host HOST, the operation corresponding to the read instruction can be processed. In addition, address information (e.g., row address and column address) for indicating the data DATA for the operation processing operation can be included in the command / address CMD / ADD indicating the operation to be processed from the host HOST. That is, when the memory device 200 processes the operation independently of the request from the host HOST, the address information needs to be pre-stored in the memory device 200 so as to process the operation according to the multiple instructions. However, according to at least one embodiment of the present invention, since the address information for processing the operation does not need to be pre-stored in the memory device 200, the size of the storage space required for the processing operation can be reduced.

[0053] According to the above-described embodiment, regardless of the order of the instructions Inst 0 to Inst n-1 provided by the host HOST, the instructions Inst 0 to Inst n-1 can be stored in the instruction memory 224. For example, when the instructions Inst 0 to Inst n-1 process the same type of operation, since the operands to be operated on can be indicated by the addresses indicated by the host HOST, regardless of the order in which the instructions Inst 0 to Inst n-1 are executed, the operations required by the host HOST can be processed to generate the operation results.

[0054] Figure 3 is a block diagram illustrating a data processing system 300 including a memory device according to an exemplary embodiment of the inventive concept. Figure 3 As shown in FIG. 3 , the data processing system 300 includes an application processor (AP) 310 and a memory device 320, and the application processor 310 includes a memory control module 311 that communicates with the memory device 320. For example, the application processor 310 and the memory device 320 may configure a memory system.

[0055] On the other hand, the application processor 310 can be used as Figure 1 The host HOST may include an address map 312 for managing a first address related to a memory operation and a second address related to an operation process according to the above-mentioned embodiment. Figure 3 , the address map 312 is shown as being provided outside the memory control module 311. However, as in the above-described embodiment, the address map 312 may be provided in the memory control module 311.

[0056] On the other hand, the application processor 310 can be implemented by a system on chip (SoC) including a system bus (not shown). As a standard specification of the system bus, the Advanced Microcontroller Bus Architecture (AMBA) protocol of an advanced RISC machine (ARM) can be used. The bus type of the AMBA protocol can be an advanced high-performance bus (AHB), an advanced peripheral bus (APB), an advanced extensible interface (AXI), AXI4 or an AXI consistency extension (ACE). In addition to the above-mentioned bus types, other types of protocols can also be used, such as SONICs Inc.'s uNetwork, IBM's on-chip interconnect bus (CoreConnect) or the open core protocol of OCP-IP.

[0057] The memory control module 311 may be used as the memory controller in the above-described embodiment, and may control a memory operation or an operation processing operation in the memory device 320 by sending a command / address CMD / ADD to the memory device 320. The memory device 320 includes a memory 321, a PIM circuit 322, and a control logic 323. The PIM circuit 322 includes a processing element 322_1, and the control logic 323 includes a command decoder 323_1. The application processor 310 may provide a plurality of instructions Inst to the memory device 320 in order to process the operation in the memory device 320, and the plurality of instructions Inst may be stored in an instruction memory (not shown) in the memory device 320. In addition, when a command / address CMD / ADD indicating an operation to be processed is provided to the memory device 320, the processing element 322_1 may process the operation by using data DATA from the application processor 310 and / or data DATA read from the memory 321.

[0058] Figure 4 is a block diagram illustrating an implementation example of a data processing system 400 according to an exemplary embodiment of the inventive concept.

[0059] Reference Figure 4 , the data processing system 400 includes a host 410 and a memory device 420. Figure 4 Although not shown in the figure, the host 410 may include a memory controller as in the above-mentioned embodiment, and further includes an address map 411. For example, the host 410 may manage an address range for indicating a memory operation and an address range for indicating an operation process as a row address. Therefore, the address map 411 may be referred to as a row address map. The address map 411 may be stored in a memory (not shown) provided in the host 410.

[0060] As in the above-described embodiment, a value of a row address in a first range for indicating a memory operation and a value of a row address in a second range for indicating an operation to be processed may be defined, and the host 410 may manage the row addresses in the first range and the second range. For example, the row address may include a plurality of bits, and the first range may be distinguished from the second range according to the value of at least one of the plurality of bits. In addition, the remaining bits of the plurality of bits may include information indicating the location of a row activated in a memory bank including a plurality of rows. In addition, according to an exemplary embodiment, the row addresses in the first range may be stored in one region (e.g., a bank region) of the address map 411, and the row addresses in the second range may be stored in another region (e.g., a PE region).

[0061] The host 410 can communicate with the memory device 420 through a plurality of buses BUS (e.g., a command / address bus CA BUS, a data bus DQ BUS for memory operations of a memory bank, and a data bus DQ BUS for operation processing operations of PE). The memory device 420 includes a memory 421, a command decoder (or control logic) 422, a processing element 423, a processing controller 424, a program counter 425, and an instruction memory 426. Figure 4 Some of the components shown may form the PIM circuits in the above-described embodiments.

[0062] The command decoder 422 may receive the command / address CMD / ADD and may perform a decoding operation on the command / address CMD / ADD. When the received address ADD corresponds to an address in the first range included in the body area, the memory device 420 may store the data DATA in the selected memory bank in the memory 421 based on the result of decoding the command / address CMD.

[0063] On the other hand, when the received address ADD corresponds to an address within the second range included in the PE area, the command decoder 422 may transmit the command / address CMD / ADD to the processing controller 424. According to various embodiments, the command decoder 422 may transmit the received command / address CMD / ADD to the processing controller 424, or may transmit the result of decoding the command / address CMD / ADD to the processing controller 424.

[0064] In an exemplary embodiment, after the process controller 424 receives the command / address CMD / ADD indicating the operation to be processed, the process controller 424 reads the instruction Inst stored in the area indicated by the program counter 425, and can control the counting operation of the program counter 425. In addition, the process controller 424 can select the processing element PE for the processing operation based on the command / address CMD / ADD and the instruction Inst, and can control the selected processing element PE. In addition, the data DATA received through the data bus DQ BUS for the operation processing operation of the PE is provided to the selected processing element PE, and the operation can be processed using the data DATA.

[0065] Alternatively, information indicating a storage location of data DATA on which an operation process is to be performed may be included in the received address ADD, and the processing controller 424 and / or the command decoder 422 may perform a control operation so that the data DATA read from the memory 421 by using the address ADD may be provided to the selected processing element PE through the internal bus. The processing element PE may store a result of a processing operation by using the data DATA provided by the host HOST or the data DATA read from the memory 421 in a register (not shown) therein.

[0066] Figure 5 is a block diagram illustrating an example in which a memory device according to an exemplary embodiment of the inventive concept includes a high bandwidth memory (HBM) 500 .

[0067] HBM 500 includes multiple channels with independent interfaces and can have increased bandwidth. Figure 5 , the HBM 500 may include a plurality of wafers, for example, a buffer wafer (or logic wafer) 510 and one or more core wafers 520 stacked on the buffer wafer (or logic wafer) 510. Figure 5 , an example is shown in which four core wafers are included in the HBM 500. However, the number of core wafers 520 may vary.

[0068] Additionally, each core wafer 520 may include one or more channels. Figure 5 In the example of FIG. 5 , when each core wafer 520 includes two channels, the HBM 500 includes eight channels CH1 to CH8. For example, the first core wafer may include the first channel CH1 and the third channel CH3, the second core wafer may include the second channel CH2 and the fourth channel CH4, the third core wafer may include the fifth channel CH5 and the seventh channel CH7, and the fourth core wafer may include the sixth channel CH6 and the eighth channel CH8.

[0069] The buffer chip 510 may include an interface (IF) circuit 511 that communicates with a host (or a memory controller), and may receive commands / addresses and data from the host through the interface circuit 511. The host may send commands / addresses and data through a bus arranged to correspond to a channel. The bus may be formed to correspond to a channel, or each of some buses may be shared by at least two channels. The interface circuit 511 may send commands / addresses and data to a channel requested by the host to perform a memory operation or a processing operation. In addition, according to an exemplary embodiment of the present invention, each core chip 520 and each channel may include a PIM circuit 521 and a command decoder 522, and the command decoder 522 may control the decoding operation performed on the received command / address.

[0070] The host may provide commands / addresses and data so that at least some of the plurality of operations may be processed by the HBM 500. These operations may be processed by the PIM circuit 521 of the channel indicated by the host. For example, according to the above-described embodiment, when the received command / address indicates a memory operation, an access operation may be performed on the data. On the other hand, when the received command / address indicates an operation to be processed, the PIM circuit 521 may process the operation by using data from the host and / or data read from the corresponding channel.

[0071] According to an exemplary embodiment, each channel may include a plurality of memory banks, and one or more processing elements may be provided in the PIM circuit 521 of each channel. For example, in each channel, the number of processing elements may be the same as the number of memory banks of the channel. Alternatively, when the number of processing elements is less than the number of memory banks, one processing element may be shared by at least two memory banks.

[0072] The buffer wafer 510 may further include a through silicon via (TSV) region 512, a physical (PHY) region 513, and a direct access (DA) region 514. Figure 5 Although not shown in the figure, a processor for controlling the overall operation of the HBM 500 (eg, control of a path of data) may also be included in the buffer wafer 510 .

[0073] In the TSV region 512, TSVs for communicating with the core wafer 520 are formed. In addition, the physical (PHY) region 513 may include a plurality of input and output circuits for communicating with an external host. For example, the physical (PHY) region 513 may include one or more ports for communicating with the host. On the other hand, the direct access (DA) region 514 may be arranged to communicate directly with an external tester (e.g., an external device for performing a test) through a conductive unit (e.g., a conductive pad) arranged on an outer surface of the HBM 500 in a test mode of the HBM 500.

[0074] Figure 6 2 is a conceptual diagram illustrating an example of the operation of a storage system according to an exemplary embodiment of the inventive concept. Figure 6 , an example in which a memory device communicates with a host HOST is shown, and in the host HOST, a memory controller (or memory control module) that communicates with the memory device may be provided.

[0075] Reference Figure 6 , the host HOST can control various operation modes of the memory device, and when the memory device operates in the instruction loading mode, the host HOST can send a plurality of instructions required for processing operations to the memory device. The sent instructions can be stored in the memory device. For example, various operations such as addition, subtraction, and multiplication can be processed by the memory device, and the PIM circuit can determine the type of operation by reading the instructions in the operation processing mode and decoding the read instructions.

[0076] The host HOST may perform a control operation to cause the memory device to operate in a normal mode. For example, the host HOST may send a command / address CMD / ADD including an address within a first range for indicating a memory operation to the memory device. The memory device may decode the received command / address CMD / ADD and may perform a memory operation in response to an address belonging to the first range. In addition, after the memory operation is fully processed to generate a memory operation result, the memory operation result may be output to the host HOST. For example, data read in response to a read command may be output to the host HOST. Alternatively, a response indicating that a data write operation has been completed may be output to the host HOST in response to a write command.

[0077] On the other hand, the host HOST may send a command / address CMD / ADD including an address within a second range for indicating an operation to be processed to the memory device. The memory device decodes the received command / address CMD / ADD and may enter an operation processing mode in response to an address belonging to the second range. For example, after receiving data from the host HOST together with the command / address CMD / ADD, the operation may be processed using the data received from the host HOST to generate an operation processing result. In addition, the operation processing result may be sent to the host HOST. For example, after the operation processing operation has been completed, the result may be sent to the host HOST. Alternatively, according to an exemplary embodiment, the operation processing result may be stored in a register located in a cell array of a processing element or a storage body, and the host HOST may send a command / address CMD / ADD for reading the operation processing result to the memory device.

[0078] Figure 7 and Figure 8 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the inventive concept.

[0079] Reference Figure 7 In operation S11, the memory device receives an instruction provided by the host in an instruction loading mode and stores the received instruction. The memory device can receive various commands from the host and can perform various functions by using the result of decoding the command. In operation S12, the memory device receives a write / read command WR / RD from the host and receives an address corresponding to the write / read command WR / RD. In addition, in operation S13, the memory device performs a decoding operation on the received command / address to generate a decoding result.

[0080] In operation S14, the memory device determines whether to operate in the operation processing mode or in the memory operation mode based on the decoding result. For example, the address received according to the above embodiment may have a bit value belonging to the first range or the second range, and when the bit value of the received address belongs to the first range, in operation S15, the memory device performs a normal write / read operation corresponding to the received command / address. For example, the memory device performs a normal write / read operation during the memory operation mode. On the other hand, when the bit value of the received address belongs to the second range, the memory device enters the operation processing mode. For example, a portion of the address having a bit value is called mode information, and the mode information is set to indicate one of the memory operation mode and the operation processing mode.

[0081] In the operation processing mode, the PIM circuit provided in the memory device may perform a single operation or a series of operations for processing operations. In operation S16, a command / address from a host may be provided to the PIM circuit, and the PIM circuit may read an instruction indicated by a program counter among instructions stored in an instruction memory and perform a program count operation. According to the above operation, instructions stored in the instruction memory may be sequentially read.

[0082] On the other hand, address information indicating a location where data to be used for an operation is stored may be included in a command / address for indicating an operation to be processed. Based on a control operation in the memory device, data is read from a location corresponding to the received address and may be provided to the PIM circuit in operation S17, and the PIM circuit processes the operation by using the read data in operation S18.

[0083] On the other hand, refer to Figure 8, various commands for operation processing operations may be defined between a host and a memory device, and in the process of processing the operation by using a write command and a read command, the operation processing method may be set differently according to the command.

[0084] According to an exemplary embodiment, in operation S21, the host provides a read command to the memory device as a command for processing an operation, and the memory device receives the read command and an address from the host. The memory device can process an operation based on a decoding operation of a command / address, and a command / address for entering an operation processing mode can be defined by various methods. For example, according to the above-described embodiment, when the bit value of the address may belong to a first range or a second range and an address belonging to the first range is provided to the memory device, the memory device can operate in the operation processing mode.

[0085] When a read command is provided to the memory device, an operation may be performed on the data read from the memory cell array. In the address accompanying the read command, information about the location where the data to be read from the memory cell array is stored (e.g., a bank address, a row address, and a column address) may be included. In operation S22, the memory device reads the data at the location corresponding to the received address, and in operation S23, after providing the read data to the PIM circuit, an operation is processed by using the read data.

[0086] On the other hand, when a write command is provided to the memory device, the memory device may be controlled so that an operation may be processed by using data provided by the host. For example, in operation S24, the memory device receives a write command and an address, and performs a decoding operation on the write command and the address. In operation S25, the memory device receives data from the host. The received data may be provided to the PIM circuit. In operation S26, the PIM circuit may process an operation (perform an operation) by using the data received from the host to generate an operation processing result. In addition, the operation processing result may be temporarily stored in a register of the PIM circuit.

[0087] According to an exemplary embodiment, in the address received together with the write command, information for indicating the location of the data may be included. For example, the memory device may be implemented so that when the write command is provided to the memory device, the memory device processes the operation by using the data from the host to generate a processing result, and the processing result is stored in the location indicated by the received address.

[0088] Fig. 9 is a block diagram illustrating an overall implementation example of a memory device 600 according to an exemplary embodiment of the inventive concept. Fig. 9 Some of the components shown are optional and may be deleted. Alternatively, in terms of functionality, Fig. 9Some components shown may be divided into at least two components. Alternatively, two or more components may be combined into one component. That is, the memory device according to the embodiment of the inventive concept may be implemented differently as long as the memory device performs the same function or a similar function.

[0089] Reference Fig. 9 , the memory device 600 includes a plurality of memory banks 610_1 to 610_N, and the plurality of memory banks 610_1 to 610_N may be connected to Figure 3 For example, the memory bank 610_1 includes a cell array 611, a row decoder 612 (e.g., a decoder circuit), a column decoder 613 (e.g., a decoder circuit), a sense amplifier / write driver 614, and a processing element 615. That is, each memory bank can be defined as including a memory cell and various peripheral circuits related to memory operation.

[0090] The memory device 600 also includes a command decoder 621 , a bank controller 622 , an address register 623 , a processing element controller 631 , a PE command queue 632 , a PE control register 633 , a data gating unit 641 (eg, a gating circuit), and a data buffer 642 . Fig. 9 The various components shown may correspond to the components in the above-described embodiments. For example, the command decoder 621, the memory bank controller 622, and the address register 623 may be provided in the control logic in the above-described embodiments, and the processing element controller 631 and / or the PE control register 633 may be provided in the PIM circuit in the above-described embodiments. On the other hand, the PE command queue 632 may correspond to the instruction memory in the above-described embodiments, and the PE command from the PE command queue 632 may correspond to the instruction in the above-described embodiments.

[0091] The row decoder 612 may select a row of the memory bank 610_1 through a word line WL, and the column decoder 613 may select a column of the memory bank 610_1 through a column selection line CSL. In addition, the sense amplifier / write driver 614 may access the memory cells of the cell array 611 through a global input and output line GIO, and write data and read data may be transmitted between the sense amplifier / write driver 614 and the data strobe unit 641.

[0092] According to an exemplary embodiment, the host provides an instruction (or PE command) through the data input and output pads DQ of the memory device 600. In addition, the host may provide various PE control information items regarding control of the operation of the processing element 615 to the memory device 600 through the data input and output pads DQ, and the processing element controller 631 may control the processing element 615 based on the information stored in the PE control register 633. In addition, based on the control of the processing element controller 631, the instructions stored in the PE command queue 632 may be provided to the processing element 615.

[0093] According to the above embodiments, based on the command / address CMD / ADD provided by the host, the command decoder 621 and / or the processing element controller 631 can control the overall operation of the memory device 600, so that the memory device 600 can operate in a normal mode or an operation processing mode.

[0094] Fig.10 is a block diagram showing an implementation example of address mapping provided in a host.

[0095] Reference Fig.10 , the host includes an address map (e.g., a row address map), and the row addresses for indicating various modes can be managed by the address map. The row address can belong to various ranges according to its bit value. In the above embodiment, the normal mode and the operation processing mode are shown. However, various modes can be executed by managing the address map.

[0096] For example, the range to which some bits (e.g., some high bits) of the row address belong can be set according to the values ​​of these bits. For example, by providing a row address in which the value of the bit corresponds to 00x0 by the host, the memory device can operate in a normal mode (e.g., a write operation and a read operation). In addition, in an exemplary embodiment, in an extended address mode, multiple memory banks of the memory device can be selected at the same time. For example, in order to perform a precharge operation on multiple memory banks, the extended address mode can be selected.

[0097] In addition, regarding the operation processing, the host can select a command register file (CRF) access mode, and can send multiple instructions to the memory device in the CRF access mode. For example, the CRF can correspond to the instruction memory storing instructions in the above-mentioned embodiment, and the host can access the CRF of the memory device. In addition, the host can provide an address so that the memory device operates in the operation mode. Therefore, the operation can be processed by the processing element provided in the memory device.

[0098] Fig.11 is a diagram illustrating an example in which a memory device according to an exemplary embodiment of the inventive concept performs a neural network operation.

[0099] Fig.11 The processing operations of the memory device 700 can use one or more neural network models to analyze input data to extract information. For example, the processing operations can use a deep learning algorithm to analyze the input data. The neural network operations can be performed by various hardware (or processors) such as general hardware or special hardware. General hardware may include a central processing unit (CPU) or a graphics processing unit (GPU). Special hardware can be optimized for specific software. For example, special hardware may include various hardware such as an application specific integrated circuit (ASIC), a neural processing unit (NPU), a tensor processing unit (TPU), and a neural engine.

[0100] According to an exemplary embodiment of the inventive concept, a data processing system may include a host (not shown) and a memory device 700. In the host executing the neural network, some operations may be processed by general hardware and / or dedicated hardware. According to an embodiment of the inventive concept, at least some operations included in the neural network may be processed by the memory device 700. In an alternative embodiment, all of the multiple operations included in the neural network are processed by the memory device 700.

[0101] Reference Fig.11 , the memory device 700 includes a cell array 710, a processing element 711, a processing controller 712, and an instruction memory 713. For example, the processing element 711, the processing controller 712, and the instruction memory 713 may be included in the PIM circuit in the above-mentioned embodiment. In addition, according to various embodiments, components may be implemented at various locations in the memory device 700. For example, the memory cell array 710 and the processing element 711 may be included in the same memory bank.

[0102] Neural network operations may include operations using data DATA and weights. Various information items used for the operations may be provided by the host HOST or may be stored in a memory device. For example, in Fig.11 In the embodiment, data DATA is provided by the host HOST, and weights are stored in the memory bank of the cell array 710. However, embodiments of the inventive concept are not limited thereto. For example, data DATA may be stored in the cell array 710 or may be read from the cell array 710 for operation, and weights may be provided by the host HOST.

[0103] Whenever a command / address for a processing operation is received, a program count operation for selecting an instruction stored in the instruction memory 713 is performed, and according to the instruction, the processing element 711 can process the operation by using the data DATA and the weight to generate an operation result Res_P. In addition, the operation result Res_P can be stored in a register of the PIM circuit. For example, in Fig.11, the register is shown as being included in processing element 711.

[0104] According to an exemplary embodiment, the memory device 700 includes a plurality of processing elements corresponding to a plurality of memory banks, and operations may be performed in parallel by the plurality of processing elements. As an operation example, a neural network operation may operate on the same data DATA using a plurality of different weights, and the different weights may be stored in the plurality of memory banks, respectively. In addition, the data DATA (e.g., data provided by a host) may be provided in common to the plurality of processing elements. Therefore, the plurality of processing elements may operate on the same data DATA in parallel using different weights.

[0105] Fig.12 is a block diagram illustrating an example of a transmission path of information in a memory device according to an exemplary embodiment of the inventive concept.

[0106] Reference Fig.12 , the data processing system 800 includes a host 810 and a memory device 820, and the host 810 includes a memory controller MC and can communicate with the memory device 820. In addition, the memory device 820 includes at least one memory bank 821, a PIM circuit 822, and a multiplexer MUX as a route selector 823. The memory device 820 may also include various components for memory operations and operation processing operations. However, for convenience, these components are not shown.

[0107] An example of an information transmission path between the host 810 and the memory device 820 will be described below. In the route selector 823, a switch (not shown) for controlling the connection relationship between the plurality of buses included in the memory device 820 may be included. The switch may be controlled by a component in the memory device 820. For example, the switch may be controlled based on a control operation of a command decoder (not shown) in the PIM circuit 822 in the memory device 820 and / or a processing controller.

[0108] The information read from the memory 821 may correspond to common data, operation processing results, or information for processing operations in the above-mentioned embodiments (e.g., weight information). In addition, the data provided by the host 810 may be stored in the memory 821, or may be directly provided to the PIM circuit 822 for processing operations.

[0109] In an exemplary embodiment, a command / address is provided from the host 810 to the memory device 820, a decoding operation is performed on the command / address in the memory device 820 to generate a decoding result, and according to the decoding result, the switch state of the switch of the route selector 823 may be changed. For example, when the command / address corresponds to a read request to the memory bank 821, data read from the memory bank 821 may be provided to the host 810 through the route a. On the other hand, when the command / address corresponds to an operation processing request performed by using data stored in the memory bank 821, data read from the memory bank 821 may be provided to the PIM circuit 822 through the route b.

[0110] On the other hand, when the command / address corresponds to a write request to the memory bank 821, data from the host 810 may be provided to the memory bank 821 through the route c. On the other hand, when the command / address corresponds to an operation processing request by using data from the host 810, data from the host 810 may be provided to the PIM circuit 822 through the route d.

[0111] On the other hand, the command / address may correspond to information (e.g., operation processing results) stored in the PIM circuit 822. In this case, the information stored in the PIM circuit 822 may be provided to the host 810 through the route f. On the other hand, the command / address may correspond to a request in the PIM circuit 822 to store information in the memory bank 821. In this case, the information stored in the PIM circuit 822 may be provided to the memory bank 821 through the route e.

[0112] Fig.13A and Fig. 13B is a flowchart illustrating an implementation example of an instruction executed by a memory device according to an exemplary embodiment of the inventive concept and a method of operating a memory device according to an exemplary embodiment of the inventive concept.

[0113] Various instructions may be provided. For example, a loop instruction for executing a loop may be defined, or a branch instruction for branching to a different instruction sequence may be defined. At this time, in the process of processing the loop instruction, an additional waiting time overhead for processing the branch condition may be generated, which reduces the efficiency of executing the instruction. For example, satisfying the branch condition may result in utilizing additional time to execute the loop of the loop instruction. On the other hand, when loop unrolling is applied to the execution instruction, the size of the memory storing the instruction increases because the size of the loop basic block increases.

[0114] According to an exemplary embodiment, an instruction standard architecture (ISA) is provided that is related to the processing of loop instructions. Fig.13A, the loop instruction may include various fields. According to an exemplary embodiment of the inventive concept, the loop instruction includes an FJUMP field representing the loop instruction, a times field representing the number of repetitions of the loop, and a target field representing the position of the instruction to be moved. By including the above-mentioned field information items, a determined number of loops can be executed. For example, each instruction in the loop can be executed continuously until the last instruction in the loop is reached, and then execution can be restored to the first instruction in the loop associated with the position stored in the target field.

[0115] Reference Fig. 13B , shows an operation example of the memory device 900 related to the execution of the loop instruction in the above example. The memory device 900 includes a processing controller 910, an instruction memory 920, and a program counter 930. In the instruction memory 920, the first instruction Inst 0 to the nth instruction Inst n-1 are stored. In addition, the current program count value corresponds to 1. Therefore, in response to the command / address CMD / ADD, the second instruction Inst1 is read. According to the current embodiment, together with the second instruction Inst1, the third instruction Inst2 corresponding to the loop instruction indicated by the next program count value (e.g., PC=2) is read.

[0116] The processing controller 910 includes an instruction decoder 911 for performing a decoding operation on the instruction and a loop counter 912 for generating a loop count value. The instruction decoder 911 can perform a pre-decoding operation on the read third instruction Inst2. In addition, since the third instruction Inst2 corresponds to a loop instruction, the loop count value is set to correspond to the information in the number field representing the number of loops. Whenever a loop is executed, the loop counter 912 can increase or decrease the loop count value. For example, in the case where the loop counter 912 performs a counting operation based on a down-counting operation, the loop count value is reduced by 1 whenever a loop is executed.

[0117] The processing controller 910 can determine that the instruction to be read is a loop instruction based on the pre-decoding result, and can control the program counter 930 so that the program count value indicates the instruction corresponding to the target. Therefore, when the command / address CMD / ADD indicating the next operation to be processed is received, the loop can be executed by indicating the instruction corresponding to the target without reading and executing the third instruction Inst2.

[0118] Fig.14 is a flowchart illustrating an operation example of a memory device that executes a loop instruction according to an exemplary embodiment of the inventive concept.

[0119] Reference Fig.14, instructions can be read based on the program count operation according to the above-described embodiment. For example, in operation S31, instructions stored in the instruction memory are read based on a command / address from a host for processing an operation. In addition, an instruction indicated by the next program count value is read in advance, and a pre-decoding operation can be performed on the instruction. In operation S32, it is determined whether the next instruction corresponds to the instruction FJUMP for executing a loop. When it is determined that the next instruction is not the instruction FJUMP for executing a loop, in operation S33, the program count value (e.g., the current program count value) is set to a value indicating the next instruction. Therefore, when a command / address indicating the next operation to be processed is received, the next instruction can be processed subsequently.

[0120] On the other hand, when it is determined that the next instruction is the instruction FJUMP, in operation S34, an operation of checking the loop counter is performed to determine the number of executions of the loop, and in operation S35, it is determined whether the loop count value LC corresponds to 0. When it is determined that the loop count value LC does not correspond to 0, a down-counting operation of the loop counter is performed, and thus, in operation S36, the loop count value LC is decreased, and in operation S37, the program count value indicates an instruction corresponding to the target included in the loop instruction. Therefore, when a command / address indicating the next operation to be processed is received, the instruction corresponding to the target can be executed without executing the loop instruction.

[0121] On the other hand, when it is determined that the loop count value LC corresponds to 0, this means that the loop has been executed a determined number of times. Therefore, in operation S38, the program counter value may be changed to indicate the next instruction.

[0122] Fig.15A and Fig. 15B is a diagram illustrating basic blocks and operation examples of instructions for executing a loop (execute loop instruction) according to an exemplary embodiment of the inventive concept.

[0123] Reference Fig.15A , a basic block (e.g., a code block) includes one or more instructions. For example, in a basic block, a first instruction Inst0 for executing a first function Function A, a second instruction Inst 1 for executing a second function Function B, and a third instruction Inst2 for executing a move function JFUMP to execute a loop may be included. In addition, information @0 about the location of a target and information n indicating the number of loops may be included in the third instruction Inst2. In addition, according to the above embodiment, when the current program count value is 1, together with the second instruction Inst1, the third instruction Inst2 is read and a pre-decoding operation may be performed.

[0124] On the other hand, Fig. 15B, a case where an instruction including a loop instruction is processed in a general case and a case where an instruction including a loop instruction is processed according to an exemplary embodiment of the inventive concept are shown.

[0125] Reference Fig. 15B , in the implementation of the general method Fig.15A When the basic block is executed, one instruction is read from each operation timing, so the first function Function A, the second function Function B and the move function JUMP can be sequentially executed. On the other hand, according to an exemplary embodiment of the inventive concept, when the current program count value indicates the second instruction Inst1, the pre-decoding operation is performed on the third instruction Inst2. Therefore, without additionally executing the move function JUMP, the first function FUNC A and the second function FUNC B can be repeatedly executed a determined number of times.

[0126] Fig.16A , Fig. 16B and Fig.17 1 is a diagram showing an implementation example of an instruction according to an embodiment of the inventive concept and a method of operating an instruction according to an embodiment of the inventive concept. Fig.16A , Fig. 16B and Fig.17 , an instruction (eg, a multi-cycle NOP instruction) is shown that executes a no operation (NOP) instruction a determined number of times.

[0127] Reference Fig.16A , a basic block includes one or more instructions. For example, in a basic block, a first instruction Inst0 for executing a first function Function A, a second instruction Inst1 for executing a second function Function B, and a third instruction Inst2 for executing NOP (MNOP4) during multiple cycles are included. In addition, the third instruction Inst2 may include information indicating a NOP instruction and information indicating the number of cycles to execute NOP. Fig.16A In the example, NOP is executed in four cycles. Fig.16A When the basic blocks shown are read, the pre-decoding operation according to the above-described embodiments may be applied, or only one instruction may be read in one operation processing cycle.

[0128] Compared with the case where multiple instructions are stored in memory so that NOPs are executed in multiple cycles, in the case where multiple instructions are stored in memory so that NOPs are executed in multiple cycles, Fig.16A When the illustrated embodiment defines a multi-cycle NOP instruction, the size of the basic block can be reduced. For example, NOP can be executed for various purposes (e.g., to provide a specified delay to instruction processing). Therefore, it is necessary to store multiple instructions for executing NOP multiple times. However, by defining a multi-cycle NOP instruction according to an embodiment of the present invention, the instruction memory can be used effectively.

[0129] on the other hand, Fig. 16B An example of executing NOP multiple times according to a multi-cycle NOP instruction is shown. After executing the first function Function A and the second function Function B, NOP can be executed multiple times. As an operation example, the processing controller keeps the current program count value for a specified number of times without increasing the program count value based on the result of decoding the multi-cycle NOP instruction. Therefore, NOP can be executed in multiple cycles.

[0130] Fig.17 An example of operation of a memory device according to a multi-cycle NOP instruction is shown. For example, in operation S41, an instruction indicated by a current program counter is read and decoded, and in operation S42, it is determined whether the current instruction corresponds to a multi-cycle NOP instruction MNOP. When the current instruction does not correspond to a multi-cycle NOP instruction MNOP, in operation S43, a program counter (PC) value (e.g., a current program counter value) has a value indicating a next instruction. Therefore, when a command / address instruction for a next operation to be processed is received, the next instruction can be subsequently executed.

[0131] On the other hand, when the current instruction corresponds to a multi-cycle NOP instruction, in operation S44, an operation of checking the loop counter to determine the number of executions of the NOP is performed, and in operation S45, it is determined whether the loop count value LC corresponds to 0. When it is determined that the loop count value LC does not correspond to 0, in operation S46, the loop count value LC is reduced based on a down-counting operation, and in operation S47, the program count value is maintained at the current value by executing the NOP. When it is determined that the loop count value LC corresponds to 0, this indicates that the NOP has been executed a determined number of times. Therefore, in operation S48, the program count value is changed to indicate the next instruction.

[0132] Fig.18 is a block diagram illustrating a server system 1000 including a data processing system according to an exemplary embodiment of the inventive concept.

[0133] Reference Fig.18 , the server system 1000 includes a manager 1010 (e.g., a controller or a control circuit) and a plurality of servers 1020_1 to 1020_K. Each of the plurality of servers 1020_1 to 1020_K may correspond to the data processing system described in the above embodiments. The plurality of servers 1020_1 to 1020_K are connected to each other via a bus supporting a prescribed protocol (e.g., PCI or PCIe). For example, the plurality of servers 1020_1 to 1020_K may communicate with each other via a P2P connection structure based on the control of the manager 1010.

[0134] Referring to a server (e.g., the first server 1020_1), the first server 1020_1 includes a host HOST according to the above-described embodiment, and one or more memory devices MEM can process various operations according to the functions of the first server 1020_1 to generate processing results and can store the processing results. According to an embodiment, the first server 1020_1 includes an address map ADD Map in the host and a memory device MEM. The memory device MEM may include a processing element according to the above-described embodiment, and the host may control the operation processing timing of the memory device MEM. In addition, according to the above-described embodiment, the memory device MEM may determine the operation processing timing by decoding a command / address from the host. In at least one exemplary embodiment, the server system 1000 corresponds to a neural network server system, and the first server 1020_1 controls the memory device MEM so that at least a portion of a large number of neural network operations can be processed by the memory device MEM.

[0135] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A memory device, comprising: A memory including a memory bank having memory cells; a processor circuit in memory configured to process an operation using data provided by a host or data read from the memory bank, the processor circuit in memory comprising an instruction memory storing at least one instruction provided from the host; and a control logic configured to decode a command / address received from the host to generate a decoding result, and to perform a control operation based on the decoding result so as to perform one of the following: i) perform a memory operation on the memory bank, and ii) the memory built-in processor circuit performs a processing operation, wherein, in response to the command / address indicating execution of the processing operation, a count value of a program counter indicating a location of the instruction memory is controlled, Wherein, address information indicating data for the processing operation is included in the command / address indicating the operation to be processed from the host.

2. The memory device according to claim 1, wherein: The memory device performs the memory operation when the bit value of the address belongs to a first range, and performs the processing operation when the bit value of the address belongs to a second range different from the first range.

3. The memory device according to claim 2, wherein: The address includes mode information indicating a memory operation mode or an operation process mode and address information indicating a location of the memory bank, and According to the bit value of the mode information, the address belongs to the first range or the second range.

4. The memory device according to claim 1, wherein: The command is a read command or a write command.

5. The memory device according to claim 4, in, When the command corresponds to the read command, the memory built-in processor circuit performs the processing operation by using data read from a location corresponding to the address of the memory bank, and Wherein, when the command corresponds to the write command, the memory built-in processor circuit uses the data provided by the host to perform the processing operation.

6. The memory device according to claim 1, wherein: The address includes a row address indicating a row of the memory bank and a column address indicating a column of the memory bank, and the memory built-in processor circuit performs the processing operation using data read from a location indicated by the row address and the column address.

7. The memory device according to claim 1, wherein: The memory built-in processor circuit also includes: a processing controller configured to perform a control operation so as to process an instruction operation corresponding to an instruction indicated by a count value of the program counter; and At least one processing element is configured to execute the instruction operation based on the control of the processing controller.

8. The memory device according to claim 7, wherein: The at least one processing element includes a plurality of processing elements, the memory includes a plurality of memory banks having the memory banks, and the plurality of processing elements are respectively arranged to correspond to the plurality of memory banks.

9. The memory device according to claim 8, wherein: Each processing element of the plurality of processing elements is shared by at least two memory banks of the plurality of memory banks.

10. The memory device according to claim 1, wherein: Upon receiving the command / address indicating execution of the processing operation, reading together a first instruction indicated by a current count value of the program counter and a second instruction indicated by a next count value of the program counter, and A pre-decoding operation is performed on the second instruction.

11. The memory device according to claim 10, wherein: When the second instruction corresponds to a loop instruction, the second instruction includes information about a position of a third instruction to be moved, and Wherein, upon receiving a command / address indicating a next operation to be processed, the in-memory processor circuit executes the third instruction instead of the second instruction.

12. The memory device according to claim 1, wherein: The operations are for neural network processing, and the in-memory processor circuit performs the processing operations using data from the host and weight information in the memory bank.

13. A method of operating a memory device comprising a plurality of memory banks, the method comprising the steps of: storing a plurality of instructions corresponding to processing operations received from a host; decoding a command / address received from the host to determine whether the address belongs to one of a first range and a second range; upon determining that the address corresponds to the first range, performing a memory operation corresponding to the received command / address; and When it is determined that the address belongs to the second range, reading the indicated instruction among the plurality of instructions, and executing a processing operation corresponding to the read instruction in a memory built-in processor circuit provided in the memory device, Wherein, address information indicating data for the processing operation is included in the command / address indicating the operation to be processed from the host.

14. The method according to claim 13, wherein: The step of reading the instruction comprises: checking a count value of a program counter, the count value indicating a location in an instruction memory where the plurality of instructions are stored, and Counting of the program counter is performed in response to the command / address instructing execution of the processing operation.

15. The method according to claim 13, wherein: At least some bits of the address include address information regarding a location of data stored in a memory bank among the plurality of memory banks, and wherein the processing operation is performed by using data read from a location indicated by the address information.

16. The method according to claim 13, wherein: The processing operation is performed by using the data provided by the host and the command / address.

17. The method according to claim 13, wherein: The command is a read command or a write command.

18. The method according to claim 13, wherein: Weight information regarding neural network operations is stored in the plurality of memory banks, and wherein the step of performing processing operations comprises: reading weight information items having different values ​​from the plurality of memory banks; and The weight information items are used to operate in parallel on the data provided by the host.

19. A data processing system comprising a host, wherein the host comprises: an address mapping memory configured to store a plurality of addresses belonging to a first range for indicating memory operations to be performed on a memory device, and a plurality of addresses belonging to a second range for indicating processing operations to be performed using data read from a selected memory bank of a plurality of memory banks of the memory device; and a memory interface configured to instruct execution of the memory operation by outputting an address belonging to the first range, and configured to instruct execution of the processing operation by outputting an address belonging to the second range, Wherein, address information indicating data for the processing operation is included in the address indicating the operation to be processed from the host.

20. The data processing system according to claim 19, wherein: When instructing the memory operation and the processing operation, the host also outputs a write command or a read command.

21. The data processing system according to claim 19, further comprising: The memory device comprising the plurality of memory banks, wherein the memory device comprises: a memory built-in processor circuit configured to process an operation by using at least one of data provided by the host and data read from the plurality of memory banks; and A control logic is configured to decode a command / address received from the host to generate a decoding result, and perform a control operation based on the decoding result so as to perform one of the following: i) perform a memory operation on the plurality of memory banks, and ii) the memory built-in processor circuit performs the processing operation.

22. The data processing system according to claim 21, wherein: The memory built-in processor circuit comprises: an instruction memory configured to store a plurality of instructions provided by the host; and a program counter configured to output a count value indicating a location of the instruction memory, and Wherein, counting of the program counter is performed in response to the command / address instructing execution of the processing operation.

23. The data processing system according to claim 21, wherein: In the command / address instructing execution of the processing operation, address information about the location of data stored in the selected memory bank is included in the address, and The memory built-in processor circuit performs the processing operation by using data read from a location corresponding to an address of the selected memory bank.

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