A system that uses multiple lightweight processors to implement asymmetric algorithm multi-core parallel architecture using a single instruction memory

Abstract

The present invention discloses a system for implementing an asymmetric algorithm multi-core parallel architecture using a single instruction memory for multiple lightweight processors. The system comprises an AXI bus, an interface terminal, an ultra-high-speed interface, a high-speed interface, a master processor, an instruction register, an asymmetric key memory, and multiple lightweight processors. Each lightweight processor is connected to an asymmetric algorithm core and an asymmetric interface memory, and each lightweight processor is connected to the instruction register and the asymmetric key memory. The asymmetric key memory, asymmetric interface memory, interface terminal, ultra-high-speed interface, high-speed interface, and master processor are all connected to the AXI bus. Advantages of the system include: using one instruction memory to provide instruction reading for multiple lightweight processors and one asymmetric key memory to provide asymmetric keys for multiple lightweight processors to implement an asymmetric algorithm chip with a reduced area, thereby reducing costs and preventing excessive heat generation during chip operation.

Description

Technical Field

[0001] The present invention relates to the technical field of digital IC circuit design, and in particular to a system for implementing an asymmetric algorithm multi-core parallel architecture using multiple lightweight processors using a single instruction memory. Background Art

[0002] Existing security chips using asymmetric algorithms are mostly used in eSIM cards, bank cards, and application terminals. These chips place high demands on area and power consumption, resulting in limited performance. To achieve high performance, many solutions rely on hardware-based firmware implementations, but these solutions are limited by power consumption and low main frequency, resulting in suboptimal performance. Asymmetric security chips used on servers are relatively insensitive to area and power consumption. Some existing technologies utilize multi-core technology, asymmetric algorithms ranging from international algorithms like ECC and RSA to domestic algorithms like SM2 and SM9. Each algorithm core implements firmware in hardware, preventing algorithm reconfiguration. This results in large asymmetric chip area, fixed algorithms, inflexible reconfiguration, high cost, and significant heat generation. Other server-side security chips utilize multiple lightweight processors in parallel, each requiring a dedicated instruction memory. The more lightweight processors used, the more instruction memory space is required, which similarly results in large asymmetric chip area, high cost, and high heat generation, as well as cumbersome debugging. Summary of the Invention

[0003] The object of the present invention is to provide a system that uses a single instruction memory to implement an asymmetric algorithm multi-core parallel architecture using multiple lightweight processors, thereby solving the above-mentioned problems existing in the prior art.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0005] A system for implementing an asymmetric algorithm multi-core parallel architecture using a single instruction memory for multiple lightweight processors includes an AXI bus, an interface terminal, an ultra-high-speed interface, a high-speed interface, a master processor, an instruction register, an asymmetric key memory, and multiple lightweight processors; each lightweight processor is connected to an asymmetric algorithm core and an asymmetric interface memory, and each lightweight processor is connected to the instruction register and the asymmetric key memory; the asymmetric key memory, asymmetric interface memory, interface terminal, ultra-high-speed interface, high-speed interface, and master processor are all connected to the AXI bus; the instruction register provides instruction reading for multiple lightweight processors, and the asymmetric key memory provides asymmetric keys for multiple lightweight processors.

[0006] Preferably, each lightweight processor processes the asymmetric algorithm data required by the interface terminal, the high-speed interface, the ultra-high-speed interface and the main control processor in parallel.

[0007] Preferably, the workflow of the system is:

[0008] The interface terminal and / or the high-speed interface and / or the ultra-high-speed interface and / or the main control processor sends the data to be calculated to the asymmetric interface memory via the AXI bus;

[0009] The asymmetric interface memory caches the data that needs to be calculated;

[0010] The lightweight processor reads the data to be calculated from the asymmetric interface memory cache, the algorithm library in the instruction register, and the key at the specified address in the asymmetric key memory through the internal private bus, calls the asymmetric algorithm core to perform the calculation, and sends the calculation result data after the calculation is completed to the asymmetric interface memory;

[0011] Asymmetric interface memory caches operation result data;

[0012] The interface terminal and / or the high-speed interface and / or the ultra-high-speed interface and / or the main control processor reads the operation result data cached in the asymmetric interface memory through the AXI bus.

[0013] The beneficial effects of the present invention are: using a lightweight processor to realize the reconfiguration of the asymmetric algorithm library, using an instruction memory to provide instruction reading for multiple lightweight processors and an asymmetric key memory to provide asymmetric keys for multiple lightweight processors to jointly realize the asymmetric algorithm chip area reduction and multi-core parallel solution, thereby reducing costs and preventing the chip from generating excessive heat when working. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the structure of the system in the embodiment of the present invention. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0016] like Figure 1As shown, this embodiment provides a system for implementing an asymmetric algorithm multi-core parallel architecture using a single instruction memory with multiple lightweight processors, including an AXI bus, an interface terminal, an ultra-high-speed interface, a high-speed interface, a master processor, an instruction register, an asymmetric key memory, and multiple lightweight processors; each of the lightweight processors is connected to an asymmetric algorithm core and an asymmetric interface memory, and each of the lightweight processors is connected to the instruction register and the asymmetric key memory; the asymmetric key memory, asymmetric interface memory, interface terminal, ultra-high-speed interface, high-speed interface, and master processor are all connected to the AXI bus; the instruction register provides instruction reading for multiple lightweight processors, and the asymmetric key memory provides asymmetric keys for multiple lightweight processors.

[0017] When large server security chips use multiple lightweight processors, each processor requires a dedicated instruction memory to enable parallel operation. The more lightweight processors used, the more instruction memories are needed, and the larger the instruction memory space used. The system provided by the present invention uses the instruction memory of a single lightweight processor, utilizing multiple read channels to address multiple lightweight processors. This solves the problem of each lightweight processor requiring a dedicated instruction memory, reduces instruction memory space, minimizes chip area, and lowers costs.

[0018] In this embodiment, multiple control master ends (interface terminals, ultra-high-speed interfaces, high-speed interfaces, and master control processors) use a high-speed AXI bus, multiple lightweight processors process asymmetric algorithms in parallel, and a single custom instruction memory is used to provide an algorithm library for multiple lightweight processors. At the same time, an asymmetric key memory is used to provide asymmetric operation keys to multiple lightweight processors; thereby realizing a high-performance asymmetric algorithm chip, which can effectively improve performance, reduce chip area and heat generation, and reduce costs.

[0019] Combined with attachment Figure 1 ,The lightweight processor is connected to the asymmetric algorithm core, ,instruction memory, asymmetric key memory, and asymmetric interface memory through an ,internal private bus.

[0020] The asymmetric interface memory is a dual-end memory, one end of which is connected to the AXI bus and the other end is connected to the lightweight processor through a private bus.

[0021] The interface terminal, the high-speed interface, the ultra-high-speed interface, and the main control processor are all connected to the AXI bus.

[0022] The asymmetric key memory is a dual-terminal memory, one end of which is connected to the AXI bus and the other end is connected to the lightweight processor through a private bus.

[0023] The instruction memory is a customized multi-port read-only memory, with each read channel connected to a lightweight processor.

[0024] In this embodiment, each lightweight processor processes the asymmetric algorithm data required by the interface terminal, the high-speed interface, the ultra-high-speed interface, and the main control processor in parallel.

[0025] The system's workflow is:

[0026] 1. The interface terminal and / or the high-speed interface and / or the ultra-high-speed interface and / or the main control processor sends the data to be calculated to the asymmetric interface memory via the AXI bus;

[0027] 2. Asymmetric interface memory caches data that needs to be calculated;

[0028] 3. The lightweight processor reads the data to be calculated from the asymmetric interface memory cache, the algorithm library in the instruction register, and the key at the specified address in the asymmetric key memory through the internal private bus, calls the asymmetric algorithm core to perform the calculation, and sends the calculation result data to the asymmetric interface memory;

[0029] 4. Asymmetric interface memory caches operation result data;

[0030] 5. The interface terminal and / or the high-speed interface and / or the ultra-high-speed interface and / or the main control processor reads the calculation result data cached in the asymmetric interface memory through the AXI bus.

[0031] The system provided by the present invention uses a lightweight processor to solve the problem of asymmetric algorithm reconstruction, uses an instruction memory to provide instruction reading for multiple lightweight processors and an asymmetric key memory to provide asymmetric keys for multiple lightweight processors to jointly solve the problems of large asymmetric algorithm chip area and low performance, thereby solving the problems of high cost and huge heat generation.

[0032] By adopting the above technical solution disclosed in the present invention, the following beneficial effects are obtained:

[0033] The present invention provides a system that uses a single instruction memory to implement an asymmetric algorithm multi-core parallel architecture with multiple lightweight processors, uses lightweight processors to realize reconfigurable asymmetric algorithm libraries, uses an instruction memory to provide instruction reading for multiple lightweight processors and an asymmetric key memory to provide asymmetric keys for multiple lightweight processors to jointly realize asymmetric algorithm chip area reduction and multi-core parallel solutions, thereby reducing costs and preventing the chip from generating excessive heat when working.

[0034] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A system that uses multiple lightweight processors to implement an asymmetric algorithm multi-core parallel architecture using a single instruction memory, characterized by: The invention comprises an AXI bus, an interface terminal, an ultra-high-speed interface, a high-speed interface, a master processor, an instruction register, an asymmetric key memory, and a plurality of lightweight processors; each lightweight processor is connected to an asymmetric algorithm core and an asymmetric interface memory, and each lightweight processor is connected to the instruction register and the asymmetric key memory; the asymmetric key memory, the asymmetric interface memory, the interface terminal, the ultra-high-speed interface, the high-speed interface, and the master processor are all connected to the AXI bus; the instruction register provides instruction reading for the plurality of lightweight processors, and the asymmetric key memory provides asymmetric keys for the plurality of lightweight processors; Multiple control masters use a high-speed AXI bus, and multiple lightweight processors process asymmetric algorithms in parallel. A single custom instruction memory provides algorithm libraries for multiple lightweight processors, and an asymmetric key memory provides asymmetric operation keys for multiple lightweight processors. The system's workflow is: The interface terminal and / or the high-speed interface and / or the ultra-high-speed interface and / or the main control processor sends the data to be calculated to the asymmetric interface memory via the AXI bus; The asymmetric interface memory caches the data that needs to be calculated; The lightweight processor reads the data to be calculated from the asymmetric interface memory cache, the algorithm library in the instruction register, and the key at the specified address in the asymmetric key memory through the internal private bus, calls the asymmetric algorithm core to perform the calculation, and sends the calculation result data after the calculation is completed to the asymmetric interface memory; Asymmetric interface memory caches operation result data; The interface terminal and / or the high-speed interface and / or the ultra-high-speed interface and / or the main control processor reads the operation result data cached in the asymmetric interface memory through the AXI bus.

2. The system of claim 1 wherein multiple lightweight processors use a single instruction memory to implement an asymmetric algorithm multi-core parallel architecture, characterized in that: Each lightweight processor processes in parallel the asymmetric algorithm data required by the interface terminal, the high-speed interface, the ultra-high-speed interface, and the main control processor.

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