Adaptive nvm read method and apparatus therefor

Abstract

The application discloses an adaptive NVM reading method and a device thereof. The reading device is a medium interface controller, which comprises a medium interface, a local cache, a micro instruction memory, an error correction code decoder and a cache management unit. The medium interface is coupled with the micro instruction memory, the local cache and the cache management unit. The cache management unit is further coupled with the local cache, and the cache management unit provides a reading pause signal to the medium interface according to the available space size in the local cache. The cache management unit of the application manages the operation related to the use of the local cache in a manner independent of the micro instruction, thereby avoiding introducing excessive complexity due to the expansion of the micro instruction.

Description

TECHNICAL FIELD

[0001] The present application relates to storage device technology, and in particular, to a method for adaptively reading data from NVM in a storage device and an apparatus implementing the method. BACKGROUND

[0002] Figure 1 A block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capability to the host. The host and the storage device 102 can be coupled in various ways, including but not limited to connecting the host and the storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device through the above-mentioned ways, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs. The data stored in the NVMs can be damaged to some extent, and to overcome such problems, the data stored in the NVMs is usually protected by an error correction code (ECC) when the NVMs are accessed. Common error correction codes include BCH code, LDPC, RS code, etc.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is configured to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and is also configured to perform storage management, mapping of host logical addresses to flash physical addresses, wear leveling, bad block management, etc. The control component 104 can be implemented in various manners, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data of the DRAM 110. The DRAM can store the FTL table and / or buffered IO command data.

[0006] The control component 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) coupled to the NVM chip 105 and issuing commands to the NVM chip 105 in a manner complying with an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive results of execution of the commands output from the NVM chip 105. Known NVM chip interface protocols include “Toggle”, “ONFI”, etc.

[0007] The NVM chip includes one or more LUNs (Logic Units). The NVM chip package can include one or more dies. Typically, a LUN corresponds to a single die. A LUN can include multiple planes. Multiple planes within a LUN can be accessed in parallel, while multiple LUNs within the NVM chip can independently execute commands and report status. In the case of a 3D NAND flash, a LUN can correspond to a single 3D NAND die, and a plane can correspond to a single layer of the 3D NAND die.

[0008] The meaning of target, logical unit, and Plane is provided in "Open NAND Flash Interface Specification (Revision 3.0)" available at http: / / www.micron.com / ~ / media / Documents / Products / Other%20Documents / ONFI3_0Gold.ashx, which is part of the prior art.

[0009] NVM chips typically store and read data in pages. Data is erased in blocks. A block (also referred to as a physical block) contains multiple pages (also referred to as physical pages). A physical page has a fixed size, for example, 17664 bytes. A physical page can also have other sizes.

[0010] Figure 2 A detailed block diagram of the control component of the storage device is shown.

[0011] The host accesses the storage device with IO commands following a storage protocol. The control component generates one or more storage commands based on the IO commands from the host and provides the storage commands to the media interface controller. The media interface controller generates storage media access commands (e.g., program command, read command, erase command) following an interface protocol of the NVM chip based on the storage commands. The control component also tracks that all storage commands generated from an IO command are completed and indicates the processing result of the IO command to the host.

[0012] Referring to Figure 2 , the control component includes, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface obtains IO commands provided by the host and generates storage commands to the storage command processing unit. The storage commands, for example, access storage space of the same size, for example, 4KB. A data unit of data recorded in the NVM chip corresponding to the data accessed by one storage command is referred to as a data frame. A physical page records one or more data frames. For example, the size of a physical page is 17664 bytes and the size of a data frame is 4KB, one physical page can store 4 data frames.

[0013] The smallest unit of data protected by the data correction code is referred to as an ECC block. An ECC block includes user data and check data, and has different sizes. The ratio of the size of the user data unit to the size of the ECC block is referred to as the code rate of the ECC. The code rate of the ECC reflects the error correction capability of the ECC. Generally speaking, the lower the code rate, the stronger the error correction capability. In one example, the size of the user data in an ECC block is the size of a data frame, and the size of the check data is 15 bytes. In another example, the size of the user data in an ECC block is 512 bytes, and the size of the check data is 8 bytes, so that one data frame can accommodate multiple ECC blocks.

[0014] The storage medium management unit maintains the conversion of logical addresses to physical addresses for each storage command. For example, the storage medium management unit includes an FTL table. For a read command, the storage medium management unit outputs the physical address corresponding to the logical address accessed by the storage command, and for a write command, the storage medium management unit allocates an available physical address therefor and records the mapping relationship between the logical address accessed thereby and the physical address allocated thereby. The storage medium management unit also maintains functions required for managing the NVM chip, such as garbage collection, wear leveling, and the like.

[0015] The storage command processing unit operates the medium interface controller to issue a storage medium access command to the NVM chip according to the physical address provided by the storage medium management unit. For the purpose of clarity, the command sent by the storage command processing unit to the medium interface controller is referred to as a medium interface command, and the command sent by the medium interface controller to the NVM chip is referred to as a storage medium access command. The storage medium access command complies with the interface protocol of the NVM chip. Taking a read command as an example, the read commands supported by the NVM chip are divided into multiple types according to the size of the data read, such as a read command for reading a complete physical page, a read command for reading one, two, or more data frames, a read command for reading multiple planes, a read command for reading multiple physical pages of a word line, and the like.

[0016] The medium interface command corresponds to the storage medium access command, so that the medium interface controller determines the type of the storage medium access command generated according to the type of the medium interface command.

[0017] Figure 3 A schematic diagram of a storage medium access (read) command according to the ONFI protocol is shown.

[0018] The control component is coupled to the NVM chip through multiple leads, and the signals carried on the leads include the DQ signals for transmitting addresses and data, and also include the SR (state) signals. Figure 3 In the diagram, the direction to the right is the direction of the passage of time, Figure 3 The first row of the diagram is indicated by the legend of “Cycle Type” indicating the meaning of the signals transmitted on the DQ signals below.

[0019] Referring to Figure 3 To send a storage media access (read) command to the NVM chip, the control component sends a "00h" signal (cycle type is CMD) followed by "C1", "C2", "R1", "R2", and "R3" signals (cycle type is ADDR) representing the address, and a "30H" signal (cycle type is CMD) on the DQ pins. Subsequently, the NVM chip indicates that it is processing the read command via the SR signal, and after a time tR, the NVM chip indicates that it has completed processing the read command via the SR signal. Next, the NVM chip outputs data "D0", "D1", "D2",... (cycle type is DOUT) read in response to the read command on the DQ pins, and the control component captures the data to obtain the results of processing the read command.

[0020] Figure 4 A waveform diagram illustrating a storage media access (read) command is shown.

[0021] Also referring to Figure 3 In the transmission of the cycle type "DOUT" phase, the control component provides a plurality of "read enable" signals to the NVM chip via a pin (e.g., the RE signal according to the ONFI protocol). The NVM chip outputs one byte or two bytes of data on the DQ pins in response to each read enable signal. Figure 4 In the example of FIG. 5, "output data" indicates that one byte of data is output in response to each read enable signal, while "output data 2" indicates that two bytes of data are output in response to each read enable signal. The ONFI protocol defines a plurality of operating modes (SDR, NV-DDR, NV-DDR2, etc.), and also defines the number of bytes output in response to each read enable signal in each operating mode. In some operating modes defined by the ONFI protocol, the control component also uses, for example, a CLK (clock) signal to cause the NVM chip to output data instead of a read enable signal.

[0022] Figure 5 A block diagram of a media interface controller of the prior art is shown.

[0023] The media interface controller of the control component includes a media interface, a local cache, and an ECC decoder. The media interface is coupled to the NVM chip to provide storage media access commands to the NVM chip and to obtain the results of processing the commands. The media interface is also coupled to a microinstruction memory to generate media interface commands based on microinstructions obtained from the microinstruction memory. The media interface stores data output by the NVM chip in the local cache. The ECC decoder obtains an ECC block from the local cache, performs ECC decoding on the ECC block, and records the results of the decoding in a read data cache. The read data cache is a DRAM coupled to the control component or an SRAM integrated in the control component.

[0024] The local cache holds the complete data outputted by the NVM chip according to the media interface command, which has the size of a data frame or a physical page, for example. As an example, the data read out by one media interface (read) command includes multiple ECC blocks. The ECC decoder fetches one ECC block from the local cache at a time. SUMMARY

[0025] The media interface controller reads out a data frame or a whole physical page data from the NVM chip using a media interface command. The read out data needs to be buffered by the media interface controller and ECC decoding is performed. To improve the data read speed, the media interface controller provides a local cache integrated in the chip to buffer the data read out from the NVM chip and to be ECC decoded. When a data frame or a whole physical page data read out from the NVM chip includes N (N is a positive integer) ECC blocks, and the bandwidth of the ECC decoder can not be able to handle N ECC blocks at the same time, resulting in one or more ECC blocks waiting in the local cache of the media interface controller to be ECC decoded. Further, the time of the ECC blocks staying in the local cache is increased, which reduces the utilization of the local cache. To ensure the read data bandwidth, the capacity of the local cache needs to be increased, which results in the cost and power consumption of the control component and even the storage device rising. It is desirable to reduce the time of the ECC blocks staying in the local cache to improve the utilization of the local cache.

[0026] The media interface controller controls the generation of the media interface command by executing microinstructions. The capability of the microinstructions is limited, and it is difficult to extend the microinstructions to manage the use of the local cache. It is also desirable to manage the operations related to the use of the local cache in a manner independent of the microinstructions to avoid introducing too much complexity due to the extension of the microinstructions.

[0027] According to a first aspect of the present application, there is provided a first media interface controller according to the first aspect of the present application, comprising a media interface, a local cache, a microinstruction memory, an error correction code decoder and a cache management unit; the media interface is coupled with the microinstruction memory, the local cache and the cache management unit; the media interface is used to be coupled with a non-volatile memory chip and to output a storage media access command to the non-volatile memory chip; the microinstruction memory stores microinstructions, and the media interface executes the microinstructions to output the storage media access command; the media interface stores data fetched from the non-volatile memory chip according to the storage media access read command in the local cache; the error correction code decoder is coupled with the local cache, and the error correction code decoder performs error correction decoding on the error correction code blocks provided by the local cache; the cache management unit is also coupled with the local cache, and the cache management unit provides a read pause signal to the media interface according to the available space size in the local cache.

[0028] The first medium interface controller according to the first aspect of the present application provides a second medium interface controller according to the first aspect of the present application, wherein the cache management unit outputs a read pause signal to the medium interface in response to the available space in the local cache being less than the threshold.

[0029] The first or second medium interface controller according to the first aspect of the present application provides a third medium interface controller according to the first aspect of the present application, wherein the cache management unit withdraws the read pause signal provided to the medium interface in response to the available space in the local cache not being less than the threshold.

[0030] The first to third medium interface controllers according to the first aspect of the present application provide a fourth medium interface controller according to the first aspect of the present application, wherein the medium interface acquires the data output by the non-volatile memory chip according to the read command accessing the storage medium in response to not receiving the read pause signal.

[0031] The first to fourth medium interface controllers according to the first aspect of the present application provide a fifth medium interface controller according to the first aspect of the present application, wherein the medium interface instructs the non-volatile memory chip to pause outputting the data to be acquired according to the read command accessing the storage medium in response to receiving the read pause signal.

[0032] The fifth medium interface controller according to the first aspect of the present application provides a sixth medium interface controller according to the first aspect of the present application, wherein the medium interface instructs the non-volatile memory chip to pause outputting the data to be acquired according to the read command accessing the storage medium by pausing or withdrawing the read enable signal or the clock signal provided to the non-volatile memory chip.

[0033] The fifth medium interface controller according to the first aspect of the present application provides a seventh medium interface controller according to the first aspect of the present application, wherein the medium interface instructs the non-volatile memory chip to pause outputting the data to be acquired according to the read command accessing the storage medium by generating a signal to put the non-volatile memory chip into a pause state.

[0034] The fifth to seventh medium interface controllers according to the first aspect of the present application provide an eighth medium interface controller according to the first aspect of the present application, wherein in a state where the medium interface instructs the non-volatile memory chip to pause outputting the data to be acquired according to the read command accessing the storage medium, the medium interface instructs the non-volatile memory chip to continue outputting the data to be acquired according to the read command accessing the storage medium in response to receiving the withdrawn read pause signal or no longer receiving the read pause signal.

[0035] The eighth medium interface controller according to the first aspect of the present application provides the ninth medium interface controller according to the first aspect of the present application, wherein the medium interface instructs the non-volatile memory chip to continue outputting the data to be acquired by the storage medium access read command by restoring the read enable signal or the clock signal provided to the non-volatile memory chip.

[0036] The eighth medium interface controller according to the first aspect of the present application provides the tenth medium interface controller according to the first aspect of the present application, wherein the medium interface instructs the non-volatile memory chip to continue outputting the data to be acquired by the storage medium access read command by withdrawing the signal that puts the non-volatile memory chip into the suspended state.

[0037] The first to tenth medium interface controllers according to the first aspect of the present application provide the eleventh medium interface controller according to the first aspect of the present application, wherein the cache management unit manages the local cache according to the size of the error correction code block.

[0038] The eleventh medium interface controller according to the first aspect of the present application provides the twelfth medium interface controller according to the first aspect of the present application, wherein the cache management unit generates and provides the read suspend signal to the medium interface when the available space of the local cache is insufficient to accommodate the specified number of error correction code blocks.

[0039] The eleventh or twelfth medium interface controller according to the first aspect of the present application provides the thirteenth medium interface controller according to the first aspect of the present application, wherein the read suspend signal is not provided to the medium interface or the read suspend signal provided to the medium interface is withdrawn when the available space of the local cache is sufficient to accommodate the specified number of error correction code blocks.

[0040] The first to thirteenth medium interface controllers according to the first aspect of the present application provide the fourteenth medium interface controller according to the first aspect of the present application, wherein the local cache provides the complete error correction code block to the error correction code decoder for error correction code decoding in response to the local cache being filled with the complete error correction code block.

[0041] The first to fourteenth medium interface controllers according to the first aspect of the present application provide the fifteenth medium interface controller according to the first aspect of the present application, wherein the error correction code block is removed from the local cache in response to the error correction code block being provided to the error correction code decoder.

[0042] The twelfth to thirteenth medium interface controllers according to the first aspect of the present application provide the sixteenth medium interface controller according to the first aspect of the present application, wherein the specified number is less than the number of error correction code blocks included in the data frame to be read out from the non-volatile memory chip by the storage medium access read command.

[0043] The twelfth to sixteenth media interface controllers according to the first aspect of the present application provide the seventeenth media interface controller according to the first aspect of the present application, wherein the specified number is 1.

[0044] The first to seventeenth media interface controllers according to the first aspect of the present application provide the eighteenth media interface controller according to the first aspect of the present application, wherein the media interface comprises a microinstruction execution unit, a signal driver; the microinstruction execution unit executes a microinstruction, and the signal driver is driven according to a signal driving signal indicated by the microinstruction; the signal driver generates a specified signal on a lead wire to which the media interface is coupled to the non-volatile memory chip; and the microinstruction execution unit generates a signal sequence conforming to the interface protocol of the non-volatile memory chip by executing the microinstruction.

[0045] The eighteenth media interface controller according to the first aspect of the present application provides the nineteenth media interface controller according to the first aspect of the present application, wherein the microinstruction comprises a count value, indicating that the specified signal is repeatedly driven multiple times; the media interface further comprises a counter, and the microinstruction execution unit sets the counter according to the count value; the counter drives the signal driver to repeatedly drive the lead wire for a specified number of times.

[0046] The eighteenth or nineteenth media interface controller according to the first aspect of the present application provides the twentieth media interface controller according to the first aspect of the present application, wherein the media interface further comprises a data conversion unit; the signal driver collects signals from the lead wire and provides the collected signals to the data conversion unit.

[0047] The twentieth media interface controller according to the first aspect of the present application provides the twenty-first media interface controller according to the first aspect of the present application, wherein the data conversion unit obtains valid data from the signals collected from the lead wire and fills the local cache.

[0048] The eighteenth to twenty-first media interface controllers according to the first aspect of the present application provide the twenty-second media interface controller according to the first aspect of the present application, wherein the read pause signal provided by the cache management unit is coupled to the counter.

[0049] The twenty-second media interface controller according to the first aspect of the present application provides the twenty-third media interface controller according to the first aspect of the present application, wherein the counter stops counting in response to the read pause signal being valid.

[0050] The twenty-second or twenty-third media interface controller according to the first aspect of the present application provides the twenty-fourth media interface controller according to the first aspect of the present application, wherein the counter resumes counting in response to the read pause signal being invalid or being revoked.

[0051] The nineteenth to twenty-fifth media interface controllers according to the first aspect of the present application provide a twenty-sixth media interface controller according to the first aspect of the present application, wherein the read-pause signal further instructs the signal driver to generate a signal on a lead coupled to the non-volatile memory chip indicating an invalid or withdrawn read enable signal to instruct the non-volatile memory chip to suspend data transfer.

[0052] The nineteenth to twenty-sixth media interface controllers according to the first aspect of the present application provide a twenty-seventh media interface controller according to the first aspect of the present application, wherein the read-pause signal further instructs the signal driver to generate a signal on a lead coupled to the non-volatile memory chip indicating the non-volatile memory chip to enter a suspended state.

[0053] The nineteenth to twenty-sixth media interface controllers according to the first aspect of the present application provide a twenty-seventh media interface controller according to the first aspect of the present application, wherein the read-pause signal further instructs the signal driver to generate a signal on a lead coupled to the non-volatile memory chip indicating the non-volatile memory chip to enter a suspended state.

[0054] The first to twenty-seventh media interface controllers according to the first aspect of the present application provide a twenty-eighth media interface controller according to the first aspect of the present application, wherein the read-pause signal is only valid for instructing execution of a micro-instruction instructing the non-volatile memory chip to read out data from the lead.

[0055] The nineteenth to twenty-sixth media interface controllers according to the first aspect of the present application provide a twenty-ninth media interface controller according to the first aspect of the present application, wherein the media interface yields in response to receiving the read-pause signal.

[0056] The twenty-ninth media interface controller according to the first aspect of the present application provides a thirtieth media interface controller according to the first aspect of the present application, wherein the media interface suspends execution of a current micro-instruction sequence and saves a partial or full execution state of the current micro-instruction sequence in response to receiving the read-pause signal.

[0057] The twenty-ninth or thirtieth media interface controller according to the first aspect of the present application provides a thirty-first media interface controller according to the first aspect of the present application, wherein the media interface executes other micro-instruction sequences to send storage media access read commands to other non-volatile memory chips or other logical units of the non-volatile memory chip after suspending execution of the current micro-instruction sequence.

[0058] The thirty-first media interface controller according to the first aspect of the present application provides the thirty-second media interface controller according to the first aspect of the present application, wherein after the read pause signal is cancelled, and the media interface finishes processing the other microinstruction sequence or yields again, the partial or entire execution state of the microinstruction sequence previously saved is restored, and the microinstruction sequence whose execution state is previously saved is continued to be processed.

[0059] The nineteenth to thirty-sixth media interface controllers according to the first aspect of the present application provide the thirty-third media interface controller according to the first aspect of the present application, wherein the media interface collects the signal from the lead line once or multiple times in each cycle.

[0060] The first to thirty-third media interface controllers according to the first aspect of the present application provide the thirty-fourth media interface controller according to the first aspect of the present application, wherein even if the complete data size to be read out by the storage media access read command is greater than the available space size of the local cache, the media interface provides the storage media access command to the non-volatile memory chip.

[0061] The first to thirty-fourth media interface controllers according to the first aspect of the present application provide the thirty-fifth media interface controller according to the first aspect of the present application, wherein if there is available space in the local cache to accommodate the error correction code block, the media interface executes the microinstruction to drive the lead line to obtain the data output by the non-volatile memory chip from the DQ signal and write into the local cache.

[0062] The first to thirty-fifth media interface controllers according to the first aspect of the present application provide the thirty-sixth media interface controller according to the first aspect of the present application, wherein if there is available space in the local cache to accommodate the error correction code block, the media interface continues to drive the lead line to obtain the data output by the non-volatile memory chip from the DQ signal and write into the local cache.

[0063] The first to thirty-sixth media interface controllers according to the first aspect of the present application provide the thirty-seventh media interface controller according to the first aspect of the present application, wherein if there is no available space in the local cache to accommodate the error correction code block, the cache management unit outputs the read pause signal, and the media interface pauses to collect the data from the DQ signal.

[0064] According to the first aspect of the present application, the first to thirty-seventh media interface controllers are provided, and the thirty-eighth media interface controller according to the first aspect of the present application is provided, wherein if the locally buffered error correction code block is provided to the error correction code decoder so that there is available space to accommodate a new error correction code block, the buffer management unit cancels the read pause signal, and the media interface continues to drive the lead line to obtain the data output by the non-volatile memory chip from the DQ signal and write into the local buffer.

[0065] According to the second aspect of the present application, the storage device according to the second aspect of the present application is provided, comprising the above-mentioned media interface controller. BRIEF DESCRIPTION OF DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0067] Figure 1 A block diagram of a prior art storage device is shown;

[0068] Figure 2 A detailed block diagram of a control part of a storage device is shown;

[0069] Figure 3 A schematic diagram of a storage media access (read) command according to the ONFI protocol is shown;

[0070] Figure 4 A waveform diagram of a storage media access (read) command is shown;

[0071] Figure 5 A block diagram of a prior art media interface controller is shown;

[0072] Figure 6 A block diagram of a media interface controller according to an embodiment of the present application is shown;

[0073] Figure 7 A detailed block diagram of a media interface according to an embodiment of the present application is shown;

[0074] Figure 8 And 9 A waveform diagram according to an embodiment of the present application is shown;

[0075] Figure 10 A schematic diagram according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0076] With reference to the drawings and embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of the present application.

[0077] Figure 6 A block diagram of a media interface controller according to an embodiment of the present application is shown.

[0078] The media interface controller of the control component includes a microinstruction memory, a media interface, a local cache and an ECC decoder. The media interface is coupled with the NVM chip, the microinstruction memory and the local cache. The microinstruction memory stores microinstructions, and the media interface executes the microinstructions to output a storage media access command to the NVM chip and store data obtained from the NVM chip according to the storage media access read command in the local cache. The ECC decoder is coupled with the local cache, performs ECC decoding on an ECC block provided by the local cache, and records the decoding result in a read data cache. The read data cache is, for example, a DRAM coupled to the control component or an SRAM integrated in the control component.

[0079] The media interface controller according to an embodiment of the present application further includes a cache management unit coupled with the local cache and the media interface. The cache management unit provides a signal (referred to as a read pause signal) indicating to pause reading data to the media interface according to the size of the available space in the local cache. For example, in response to the available space in the local cache being less than a threshold value, the cache management unit outputs the read pause signal to the media interface, and in response to the available space in the local cache not being less than the threshold value, the cache management unit withdraws the read pause signal provided to the media interface.

[0080] When the media interface is working normally, it reads data from the NVM chip according to the storage media access read command in a conventional manner in response to not receiving the read pause signal. For example, also referring to Figure 4 , the media interface provides a plurality of continuous read enable signals to the NVM chip for reading data from the NVM chip.

[0081] According to embodiments of the present application, the media interface, in response to receiving the read stall signal, stalls or withdraws the read enable signal or the CLK signal provided to the NVM chip to instruct the NVM chip to stall output of data to be fetched according to the media access read command. It is appreciated that the media interface instructs the NVM chip to stall output of data to be fetched according to the media access read command by other means according to various NVM chip interface protocols followed by the media interface commands, or various operating modes defined by the interface protocols. For example, the media interface instructs the NVM chip to stall output of data to be fetched according to the media access read command by generating a signal to put the NVM chip into a stall state. In turn, in the state where the media interface instructs the NVM chip to stall output of data, the media interface resumes the read enable signal or the CLK signal provided to the NVM chip, or withdraws the signal to put the NVM chip into the stall state, in response to receiving the withdrawn read stall signal, or no longer receiving the read stall signal, to instruct the NVM chip to continue output of data to be fetched according to the media access read command.

[0082] The monitoring of the local cache capacity by the cache management unit and the generation of the read stall signal in turn are independent of the microinstructions executed by the media interface, so that the microinstructions, the execution unit thereof, and the microinstruction sequence for generating the media interface commands do not need to be modified. By instructing the NVM chip to stall output of data to be fetched according to the media access read command when the available space of the local cache is insufficient, a smaller capacity of the local cache can be used in the media interface controller, and / or the capability of the media interface controller to process the media interface (read) commands is improved, e.g., a larger number of media interface (read) commands can be processed concurrently without reducing the capacity of the local cache.

[0083] In an optional implementation, the local cache is managed according to the size of the ECC block. The local cache accommodates a number of ECC blocks. The cache management unit generates the read stall signal and provides it to the media interface when the available space of the local cache is insufficient to accommodate a specified number (e.g., one) of ECC blocks. The cache management unit does not provide the read stall signal to the media interface, or withdraws the read stall signal provided to the media interface, when the available space of the local cache is sufficient to accommodate a specified number (e.g., at least one) of ECC blocks. Further, in response to the local cache being filled with a complete ECC block, the complete ECC block is provided to the ECC decoder for ECC decoding. And in response to the ECC block being provided to the ECC decoder, the ECC block is removed from the local cache so that the storage space occupied by the ECC block becomes available space.

[0084] As an example, a data frame to be read out from the NVM chip by a storage media access read command includes 4 ECC blocks. If the available space in the local cache is not enough to accommodate 1 ECC block, the cache management unit provides a read pause signal to the media interface, so that the media interface instructs the NVM chip not to start or to pause outputting the data to be acquired by the storage media access read command. When the available space in the local cache is enough to accommodate at least 1 ECC block, even if the available space in the local cache is not enough to accommodate the complete data frame to be read out, the cache management unit does not provide or withdraws the read pause signal to the media interface, so that the media interface instructs the NVM chip to start or to continue outputting the data to be acquired by the storage media access read command. Thus, the data output of the NVM chip to the storage media access read command can be started earlier. In the case that the media interface controller concurrently processes multiple media interface (read) commands, the number of the concurrently processed media interface (read) commands can be increased.

[0085] It can be appreciated that the read pause signal can be replaced by a read enable signal having similar semantics. In response to receiving the read enable signal, the media interface instructs the NVM chip to output the data to be acquired by the storage media access read command, and vice versa.

[0086] Figure 7 A detailed block diagram of the media interface according to an embodiment of the present application is shown.

[0087] The media interface includes a micro instruction execution unit, a signal driver, a counter and a data conversion unit. The micro instruction execution unit executes a sequence of micro instructions, instructs the signal driver to generate a specified signal on a lead coupled between the media interface and the NVM chip according to a signal driving signal indicated by the sequence of micro instructions, and generates a sequence of signals conforming to the interface protocol of the NVM chip by executing the sequence of micro instructions.

[0088] Some micro instructions further include a count value indicating that the specified signal is to be driven repeatedly for a number of times. For example, if 1 byte of data is acquired from the DQ lead each time, 1 K times of data acquisition from the DQ lead is required for acquiring 4 KB of data read out from the NVM chip. The micro instruction execution unit sets the counter according to the count value, and the counter drives the signal driver to drive the specified lead for the number of times.

[0089] The signal driver further acquires signals from the DQ lead and provides the acquired signals from the DQ lead to the data conversion unit. In some operation modes (e.g., SDR mode) of the ONFI protocol, 8 bits of data are transmitted from the DQ lead each cycle, while in other modes (e.g., NV-DDR2), 16 bits of data are transmitted from the DQ lead each cycle. The data conversion unit acquires valid data from the signals acquired from the DQ lead and fills the acquired valid data into the local cache according to the current operation mode.

[0090] According to embodiments of this application, a read pause signal provided by the cache management unit is coupled to a counter. In response to a valid read pause signal, the counter stops counting. In response to an invalid or revoked read pause signal, the counter resumes counting. When the counter stops counting, the signal driver also stops driving, for example, the DQ lead to instruct the NVM chip to pause data transmission. Optionally or further, the read pause signal also instructs the signal driver to generate a read enable signal indicating invalidation or revocation on the lead coupled to the NVM chip to instruct the NVM chip to pause data transmission. Still optionally, the read pause signal also instructs the signal driver to generate a signal on the lead coupled to the NVM chip indicating that the NVM chip has entered a pause state.

[0091] Therefore, according to embodiments of this application, the read pause signal suspends the execution of microinstructions, and the execution of microinstructions can continue after the read pause signal is removed. Optionally, the read pause signal is only effective for the execution of microinstructions that indicate the acquisition of data from the NVM chip via the DQ lead, and does not affect the execution of other microinstructions.

[0092] According to another embodiment of this application, in response to receiving a read pause signal, the media interface, for example, yields. As an example, in response to receiving a read pause signal, the media interface pauses the execution of the current microinstruction sequence and saves, for example, part or all of the execution state of the microinstruction sequence. After the media interface pauses the execution of the current microinstruction sequence, it can then execute other microinstruction sequences to send storage media access read commands to other NVM chips or other LUNs (Logical Units) of the NVM chip. And after the read pause signal is revoked, and the media interface has completed processing other microinstruction sequences or yielded again, it restores, for example, part or all of the previously saved execution state of the microinstruction sequence and continues processing the microinstruction sequence for which the execution state was previously saved.

[0093] Figure 8 and 9 A waveform diagram according to an embodiment of this application is shown.

[0094] Figure 8 The waveforms of the read enable signal and the DQ signal are shown in the image. Figure 8 In the example, the NVM chip transmits 8 bits of data via the DQ signal in response to each cycle of the read enable (RE) signal. To read multi-byte data, the media interface (see also...) Figure 6 The NVM chip provides multiple consecutive read enable (RE) signals. In response to each cycle of the RE signal, the NVM chip outputs 8 bits of data on the DQ signal.

[0095] The cache management unit provides an active read stall signal to the media interface at time Tl (810), in response, the media interface outputs an inactive read enable signal (RE). Since the inactive read enable signal (RE) is not received, the NVM chip also stops outputting the active DQ signal. After time t (t = T2 - Tl), the cache management unit withdraws the read stall signal at time T2 (820). In response, the media interface resumes outputting the active read enable signal (RE), and the NVM chip also outputs the active DQ signal.

[0096] Figure 9 The waveforms shown are substantially the same in principle. The difference is that, Figure 8 The waveforms shown are substantially the same in principle. The difference is that, Figure 9 In the waveforms shown in FIG. 10, the NVM chip outputs 16 bits of data in response to each cycle of the read enable signal (RE). The DQ signal uses 8 pins, and the media interface samples the DQ signal twice in each cycle to obtain 16 bits of data.

[0097] Figure 10 A schematic diagram is shown according to an embodiment of the application.

[0098] As an example, the local cache holds up to 4 ECC blocks, and the reference numerals A (1020), B (1022), C (1024), and D (1026) indicate the ECC blocks held in the local cache at different times. The local cache holding a complete ECC block, as indicated by the hatched square, should be transferred to the ECC decoder. The local cache holding an incomplete ECC block, as indicated by the vertical hatching, should continue to receive data read from the NVM chip. The empty square indicates available local cache (not yet written with data read from the NVM chip).

[0099] As an example, the media interface executes the microinstruction to provide a storage media access read command to the NVM chip. The storage media access read command is to read data including multiple ECC blocks from the NVM chip. Optionally, the media interface provides the storage media access read command to the NVM chip even if the complete data size to be read by the storage media access read command is greater than the available space size of the local cache. Thus, according to embodiments of the application, the processing of the storage media access read command can be initiated even if the local cache does not have enough available space to store the complete data to be read by the storage media access read command, by providing the storage media access read command to the NVM chip through the media interface.

[0100] Continuing to see Figure 10 At time A, there is available space in the local cache (1020) to hold an ECC block, and the media interface executes the microinstruction to drive the pins to sample the DQ signal to obtain the data output by the NVM chip, and to write the data into the local cache.

[0101] In period B, the local cache (1022) has stored a complete ECC block, also includes an incomplete ECC block, and has available space to accommodate a new ECC block. Thus the complete ECC block in the local cache is provided to the ECC decoder. The cache management unit does not output the read stall signal, and the media interface continues to drive the leads to obtain the data output from the NVM chip from the DQ signals and write into the local cache.

[0102] In period C, the local cache (1024) has stored a complete ECC block, but has no available space to accommodate a new ECC block. Thus the complete ECC block in the local cache is provided to the ECC decoder. The cache management unit outputs the read stall signal, and the media interface stalls to collect data from the DQ signals.

[0103] In period D, part of the ECC block in the local cache (1026) is provided to the ECC decoder, thus has available space to accommodate a new ECC block. Thus the complete ECC block in the local cache is continued to be provided to the ECC decoder. The cache management unit cancels the read stall signal, and the media interface continues to drive the leads to obtain the data output from the NVM chip from the DQ signals and write into the local cache.

[0104] The cache management unit of the present application manages the operations related to the use of the local cache in a manner independent of the microinstructions, avoiding introducing excessive complexity due to the expansion of the microinstructions. Also, the read stall signal provided by the cache management unit reduces the time for the ECC block to stay in the local cache, to improve the utilization of the local cache.

[0105] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such variations and modifications as fall within the scope of the application. It should be apparent that the application can be embodied in a variety of forms other than the specific embodiments described and that the "specific embodiments" have been used only for the purposed of exemplification. Accordingly, the application is not limited to the specific embodiments described. Rather, it is intended to cover all modifications and alternatives falling within the scope of the application.

Claims

1. A media interface controller, characterized in that, It includes a media interface, local cache, microinstruction memory, error correction code decoder, and cache management unit; The media interface is coupled to the microinstruction memory, local cache, and cache management unit. The media interface is used to couple with the non-volatile memory chip and output storage media access commands to the non-volatile memory chip; The microinstruction memory stores microinstructions, and the media interface executes the microinstructions to output storage media access commands. The media interface stores the data obtained from the non-volatile memory chip according to the storage media access read command in the local cache; The error correction code decoder is coupled to the local cache, and the error correction code decoder performs error correction decoding on the error correction code block provided by the local cache; The cache management unit is also coupled to the local cache, and the cache management unit provides a read pause signal to the media interface according to the available space in the local cache; wherein, the read pause signal pauses the execution of microinstructions, and the execution of microinstructions can continue after the read pause signal is removed; the read pause signal is only effective for the execution of microinstructions that indicate the acquisition of data from the NVM chip from the DQ lead, and does not affect the execution of other microinstructions; In response to the available space in the local cache being less than a threshold, the cache management unit outputs a read pause signal to the media interface; in response to the available space in the local cache being not less than the threshold, the cache management unit cancels the read pause signal provided to the media interface. In response to receiving a read pause signal, the media interface pauses the execution of the current microinstruction sequence and saves part or all of the execution state of the current microinstruction sequence. After the media interface pauses the execution of the current microinstruction sequence, it executes other microinstruction sequences to send storage medium access read commands to other non-volatile memory chips or other logic units of non-volatile memory chips. After the read pause signal is revoked, and the media interface has completed processing other microinstruction sequences or has yielded again, it restores part or all of the previously saved execution state of the microinstruction sequence and continues to process the microinstruction sequences whose execution state was previously saved. The cache management unit's monitoring of the local cache capacity and its subsequent generation of read pause signals are independent of the microinstructions executed by the media interface.

2. The media interface controller as described in claim 1, characterized in that, The media interface, in response to receiving a read pause signal, instructs the non-volatile memory chip to pause outputting the data to be obtained according to the read command accessing the storage medium.

3. The media interface controller as described in claim 2, characterized in that, When the media interface instructs the non-volatile memory chip to pause outputting the data to be acquired by the storage medium access read command, in response to receiving a canceled read pause signal or no longer receiving a read pause signal, the media interface instructs the non-volatile memory chip to continue outputting the data to be acquired by the storage medium access read command.

4. The media interface controller as described in any one of claims 1-3, characterized in that, When the cache management unit identifies that the available space in the local cache is insufficient to accommodate a specified number of error correction code blocks, it generates a read pause signal and provides it to the media interface.

5. The media interface controller as described in claim 4, characterized in that, When the available space in the local cache is sufficient to accommodate a specified number of error correction code blocks, a read pause signal is not provided to the media interface or the read pause signal provided to the media interface is withdrawn.

6. The media interface controller as described in any one of claims 1-3 and 5, characterized in that, The media interface includes a microinstruction execution unit and a signal driver; The microinstruction execution unit executes microinstructions and drives the signal driver according to the signals indicated by the microinstructions. The signal driver generates a specified signal on the lead of the medium interface coupled to the non-volatile memory chip. Furthermore, the microinstruction execution unit generates a signal sequence that conforms to the non-volatile memory chip interface protocol by executing microinstructions.

7. The media interface controller as described in claim 6, characterized in that, The microinstruction includes a counter value indicating that a specified signal is driven repeatedly multiple times; The media interface also includes a counter, the microinstruction execution unit sets the counter according to the count value, and the counter drives the signal driver to repeatedly drive the lead a specified number of times.

8. A storage device comprising a media interface controller as described in any one of claims 1-7.

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