Instruction transmission processing device and method of sequential multi-transmission processor

Abstract

The invention discloses an instruction transmission processing device and an instruction transmission processing method of a sequential multi-transmission processor. The device comprises an instruction extraction unit, an instruction processing unit and a processing unit, wherein the instruction extraction unit is used for reading an instruction block from an instruction memory and pre-decoding the instruction block to form a transmittable instruction block; the instruction decoding module is used for decoding the instruction blocks received from the instruction extraction unit to obtain information of each instruction to be processed; the instruction emission validity arbitration module adopts a full associative storage structure and comprises a plurality of entries, and state information of an instruction is stored in each entry; the emission queue module is connected with the instruction emission validity arbitration module and is used for caching the to-be-emitted instruction passing arbitration; the execution unit is connected with the emission queue module and is used for executing the instruction and writing an execution result back to a corresponding entry of the instruction emission validity arbitration module; the hardware area is small, the processing efficiency is high, and pipeline pause can be avoided by distinguishing processing according to the type of the preorder instruction.

Description

Technical Field

[0001] This invention relates to sequential multiple issue processors, and more particularly to an instruction issue processing apparatus and method for a sequential multiple issue processor. Background Technology

[0002] Sequential multiple-issue processors are widely used in edge computing and terminal devices, and their design requires a balance between performance, power consumption, and area (PPA). Traditional sequential single-issue processors have insufficient performance, while out-of-order multiple-issue processors have excessive hardware overhead and are not suitable for embedded scenarios. Therefore, sequential multiple-issue architecture becomes a compromise.

[0003] In the prior art, Chinese invention patent CN115576610A discloses an instruction dispatching method and apparatus suitable for general-purpose sequential issue processors. The instruction dispatching apparatus has its front end connected to the processor's instruction fetching unit and its back end connected to the processor's execution unit. The instruction dispatching apparatus includes an instruction decoding module, an instruction execution status tracking module, an operand queue module, a write-back data forwarding module, a data hazard and resource conflict detection module, and an instruction dispatching module. The front end of the instruction decoding module is connected to the instruction fetching unit, and its back end is connected to the instruction execution status tracking module and the operand queue module, respectively. The instruction execution status tracking module is connected to the write-back data forwarding module and the data hazard and resource conflict detection module, respectively. The operand queue module is connected to the instruction dispatching module, and the instruction dispatching module and the write-back data forwarding module are connected to the execution unit, respectively. This invention can significantly improve instruction scheduling efficiency and processor execution efficiency, and reduce the overhead of the compiler in instruction arrangement.

[0004] The above solution has the following technical problems:

[0005] Structural redundancy: The state table and operand queue are stored separately, resulting in information duplication and overhead in maintaining consistency;

[0006] Low indexing efficiency: It requires indirect access to the state table through an operand queue, resulting in significant latency on the critical path;

[0007] The processing of indefinite-cycle instructions is rough: it fails to distinguish between fixed-cycle and indefinite-cycle instructions, and adopts a conservative waiting strategy for fixed-cycle instructions, resulting in pipeline bubbles.

[0008] Lack of front-end filtering: The instruction extraction unit does not preprocess non-parallel instruction combinations, causing the back-end arbitration module to process invalid instruction combinations, wasting hardware resources.

[0009] The aforementioned issues result in larger hardware footprint, difficulty in timing convergence, and limited dynamic execution efficiency, making it difficult to meet the demand for extreme energy efficiency in edge computing scenarios. Summary of the Invention

[0010] Purpose of the invention: The purpose of this invention is to provide an instruction dispatch processing apparatus and method for sequential multi-issue processors that has a small hardware area, high processing efficiency, and can distinguish processing based on the type of preceding instructions to avoid pipeline stalls.

[0011] Technical solution: The instruction issuance processing apparatus for a sequential multiple-issue processor according to the present invention includes:

[0012] Instruction fetch unit: used to read instruction blocks from instruction memory and pre-decode the instruction blocks to identify and process instructions that cannot be issued in the same cycle, forming an issueable instruction block;

[0013] Instruction decoding module: used to decode the instruction blocks received from the instruction extraction unit to obtain the category information, source and destination register information and execution delay information of each instruction to be processed;

[0014] Instruction issuance validity arbitration module: adopts a fully associative memory structure, including multiple entries, each of which stores the status information of the instruction, and the entries are directly indexed by register addresses;

[0015] The launch queue module is connected to the command launch validity arbitration module and is used to cache commands that have passed arbitration and are ready to be launched.

[0016] An execution unit, connected to the launch queue module, is used to execute instructions and write the execution results back to the corresponding entry in the instruction launch validity arbitration module;

[0017] The instruction decoding module sends the register address that the instruction to be processed needs to access to the instruction issuance validity arbitration module. The instruction issuance validity arbitration module accesses the corresponding entry based on the register address and determines whether the current instruction to be processed has a data hazard or resource conflict based on the previous instruction status information stored in the entry. If neither exists, the current instruction information is written into the entry and the current instruction is sent to the issuance queue module.

[0018] The instruction fetching unit of this invention performs pre-decoding, preventing instructions that cannot be processed simultaneously from being sent to subsequent units at the same time, thus ensuring instruction feasibility. The state storage and arbitration decision-making functions are highly integrated into a single module—the instruction issue validity arbitration module—directly eliminating complex interconnections, control logic, and additional circuitry required to maintain state consistency between multiple modules, significantly reducing hardware area and power consumption. Entries in the instruction issue validity arbitration module are directly indexed through register addresses, rather than indirectly mapped and queried through a separate operand queue. This allows the decoded instruction to obtain all necessary dependent state information via the shortest path (similar to accessing the register file), greatly shortening the critical timing path from instruction decoding to hazard detection, which is beneficial for increasing processor clock speed. The instruction issue validity arbitration module integrates the final judgment logic for data hazards and resource conflicts, forming a unified decision center. This centralized arbitration avoids the broadcasting and synchronization of state information among multiple distributed units, making scheduling decisions faster and more consistent, providing a foundation for efficient utilization of multi-issue hardware resources.

[0019] Preferably, each entry of the instruction issuance validity arbitration module contains N independent and parallel-accessible sub-slots, where N is equal to the designed instruction issuance width; each sub-slot independently stores the status information of an instruction, which includes at least: instruction execution function, fixed-period execution count, variable-period execution flag, and write-back data.

[0020] Each subslot independently stores the status information of one instruction, natively supporting parallel status tracking and management of the entire group of instructions issued within a clock cycle from the hardware architecture. The independent and parallel subslot design ensures that the status updates and queries of different instructions issued within the same cycle do not interfere with each other, ensuring the determinism and high reliability of the multi-issue scheduling process.

[0021] Preferably, the instruction issuance validity arbitration module determines that the current instruction does not have a data hazard or resource conflict if the corresponding entry is empty when the register address to be accessed by the instruction to be processed is indexed to the empty entry; otherwise, the following judgment is required:

[0022] When the execution cycle of the preceding instruction is not fixed: by scanning the set status of the corresponding variable period execution flag in the entry, it is determined whether the preceding instruction has been executed. After confirming that the execution has been completed, it is determined that the current instruction does not have data hazards or resource conflicts.

[0023] When the execution cycle of a preorder instruction is fixed:

[0024] If the current instruction to be executed is a read operation, and the remaining execution cycle of the previous instruction is less than or equal to the read operation delay of the current instruction or the previous instruction has been completed, it is determined that the current instruction does not have data hazards or resource conflicts.

[0025] If the current instruction to be executed is a write operation, and the remaining execution cycle of the previous instruction is less than or equal to the write operation delay of the current instruction or the completion of the previous instruction, it is determined that the current instruction does not have data hazards or resource conflicts.

[0026] For instructions with indefinite execution cycles, a robust strategy of waiting for completion is adopted. For instructions with fixed execution cycles, a quantitative comparison is made based on the precise remaining execution cycle and the operation delay of the current instruction. This differentiated processing overcomes the shortcomings of a one-size-fits-all conservative waiting approach and allows for more refined pipeline utilization. For fixed-cycle instructions, subsequent instructions can be issued earlier if specific delay relationships are met. This allows for partial overlap in execution time between the current instruction and the preceding instruction, improving pipeline efficiency.

[0027] Preferably, if the preceding instruction has been executed but the result data has not been written back, based on the preceding instruction status information stored in the entry of the instruction transmission validity arbitration module, then the result data is forwarded.

[0028] This forwarding mechanism is directly determined and triggered by the integrated arbitration module, and is tightly coupled with the arbitration decision-making process. Compared to the schemes in the background technology that require a separate forwarding module for secondary arbitration, the path is shorter and the response is faster. It can directly use data that has been generated but not yet written back for subsequent instructions, eliminating pipeline bubbles that occur at least once per clock cycle while waiting for data to be written back to the register and then read, thus directly improving performance.

[0029] Preferably, the pre-decoding process performed by the instruction extraction unit includes: identifying branch instructions or multi-cycle calculation instructions in the instruction block, and ensuring that the two types of instructions are sent to the instruction decoding module in different cycles.

[0030] By proactively filtering out high-risk instruction combinations that cannot be issued in parallel through pre-decoding, this invention eliminates such risks before the instruction stream enters subsequent modules. This frees the backend arbitration module from handling such complex exceptions, allowing it to focus on optimizing the determination of data hazards and resource conflicts, thereby simplifying the design of the arbitration logic. Simultaneously, this ensures that the instruction blocks of the delivery validity arbitration module have higher potential for parallel issuance, improving the overall determinism and robustness of subsequent scheduling efficiency.

[0031] The instruction issuance processing method for a sequential multiple-issue processor according to the present invention includes the following steps:

[0032] S1. The instruction decoding module decodes the instruction block received from the instruction extraction unit and extracts the category information, source and destination register information and execution delay information of each instruction to be processed.

[0033] S2. Using the target register address of the instruction to be processed as an index, access the corresponding entry in the instruction issue validity arbitration module; if the entry is empty, execute S4, otherwise execute S3.

[0034] S3. Read the status information of the preceding instruction in this entry and determine whether the execution cycle of the preceding instruction is fixed. If the execution cycle of the preceding instruction is not fixed, wait for it to finish executing before executing S4. If the execution cycle of the preceding instruction is fixed, determine whether the current instruction has a data hazard or resource conflict based on the operation type to be executed by the current instruction. If neither exists, then execute S4. If either of the above two conditions is not met, the current instruction must be paused until the conditions are met.

[0035] S4. Write the current instruction information into this entry and send the instruction to the launch queue module;

[0036] S5. The launch queue module sends instructions to the execution unit for execution in sequence;

[0037] S6. After the execution unit completes its execution, it writes the execution result back to the corresponding entry in the instruction issuance validity arbitration module.

[0038] Preferably, in step S3, when the execution cycle of the preceding instruction is fixed, the following sub-steps are performed:

[0039] If the current instruction to be executed is a read operation, and the remaining execution cycle of the previous instruction is less than or equal to the read operation delay of the current instruction or the previous instruction has been completed, it is determined that the current instruction does not have data hazards or resource conflicts.

[0040] If the current instruction to be executed is a write operation, and the remaining execution cycle of the previous instruction is less than or equal to the write operation delay of the current instruction or the completion of the previous instruction, it is determined that the current instruction does not have data hazards or resource conflicts.

[0041] Preferably, in step S3, when the execution cycle of the current instruction is not fixed, all indefinite period execution flags in the entry are scanned. If any flag is set, it indicates that the corresponding indefinite period instruction has not been completed and the current instruction must be paused. Step S4 can only be executed when all relevant flag bits in the entry are cleared.

[0042] Preferably, a data forwarding judgment step is included between steps S4 and S5: when the entry shows that the execution result data of the preceding instruction is ready but has not yet been written to the register file, the result data of the preceding instruction is directly forwarded to the execution unit of the current instruction.

[0043] Beneficial Effects: This invention replaces the traditional discrete scheduling architecture by constructing a novel device and corresponding method centered on a fully associative memory, register-direct-indexed instruction issue validity arbitration module. The highly integrated design significantly simplifies the circuit structure, reduces area and power consumption, and the direct indexing shortens the critical path, which is beneficial for increasing frequency. The validity arbitration module efficiently manages the state of multiple issue instructions through its embedded parallel sub-slot junctions matched to the issue width, and runs a set of arbitration logic that distinguishes between fixed and indefinite periods. This reduces invalid waiting caused by data dependencies, and data pre-progression further compresses operand ready time. Therefore, while maintaining the simplicity of sequential issue, it improves instruction throughput and the overall energy efficiency of the processor. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the overall microarchitecture design of this device;

[0045] Figure 2 A schematic diagram of the internal main structure of the command issuance validity arbitration module;

[0046] Figure 3 A schematic diagram illustrating the operation flow of the instruction issuance validity arbitration module;

[0047] Figure 4 This is a schematic diagram of the internal structure of the launch queue module. Detailed Implementation

[0048] like Figure 1 As shown, the instruction issuance processing apparatus for a sequential multiple-issue processor according to the present invention includes:

[0049] Instruction fetch unit: Used to read instruction blocks from instruction memory and pre-decode the instruction blocks to identify and process instructions that cannot be issued in the same cycle, forming an issueable instruction block.

[0050] Instruction decoding module: used to decode the instruction blocks received from the instruction extraction unit to obtain the category information, source and destination register information and execution delay information of each instruction to be processed.

[0051] Instruction issuance validity arbitration module: It adopts a fully associative memory structure, including multiple entries. Each entry stores the status information of the instruction, and the entries are directly indexed by register addresses.

[0052] Launch queue module: Connected to the command launch validity arbitration module, used to cache commands that have passed arbitration and are ready to be launched.

[0053] The execution unit, connected to the launch queue module, is used to execute instructions and write the execution results back to the corresponding entry in the instruction launch validity arbitration module.

[0054] Based on a three-issue design, the processor fetches instructions in the Instruction Fetch Unit (IFU) and, after pre-decoding to handle special cases where instructions cannot be sent simultaneously (e.g., branch instructions and multi-cycle computation instructions cannot be issued at the same time to ensure execution efficiency), sends the three instructions to the instruction decoder and dispatch unit. The three decoders then decode the instructions to obtain the current instruction type information (opcode), source and destination operand register information, and instruction execution delay information. The instructions are then dispatched to different execution pipelines according to their type. The processor also checks the availability of data in the registers that the current instruction needs to access by accessing the instruction issue validity arbitration module until the corresponding operands are available or there is no possibility of data hazards.

[0055] Once register resources (data) become available, instructions enter the corresponding issue queue and are executed by subsequent functional units. The execution result is written to the target register in the register file. In this example, the three instructions issued by the processor correspond to fixed-point, floating-point, and memory access functions in the execution unit, respectively. These three correspond to different execution pipelines, and their corresponding hardware resources and execution latencies differ. An important consideration in processor design is how to efficiently utilize the hardware resources of the execution unit, minimizing idle components or pipeline interruptions, and reducing hardware resource conflicts. This is the significance of dynamic instruction issue scheduling design.

[0056] like Figure 2 and 3 As shown, the internal structure of the instruction issue validity arbitration module is a fully associative memory structure similar to a general-purpose register file. In practical designs, its capacity can be equal to the number of available resources in the general-purpose registers, and the order of entries corresponds to the order of entries in the general-purpose registers. Therefore, after the current instruction is decoded to obtain the register information that needs to be read or written (subsequently), the corresponding entry in the internal memory of the instruction issue validity arbitration module can be accessed through the register information. The specific storage content of the entry is as follows... Figure 2 As shown on the right, the information includes three instructions (equal to the instruction issue width designed by the processor; if the issue width is designed to be two, the corresponding content will only contain the information of instruction 1 and instruction 2), including: execution function, fixed period (delay) execution count, variable period (delay) execution count, and write-back data. The three instructions correspond to the same storage information category and are independent of each other.

[0057] The function of instruction issuance validity arbitration can be mainly described as follows: After decoding the instruction block received from the instruction fetching unit, the instruction decoding and dispatch module summarizes the instruction and its corresponding information (instruction execution function, operand type, address of the register to be accessed, and number of execution cycles), and indexes the corresponding entry of the instruction issuance validity arbitration module using the address of the register to be accessed. If the corresponding entry is empty, it means that there is no data dependency issue with the registers to be read or written by the current instruction execution, and the corresponding information can be stored in the entry of the corresponding instruction number, and then the current instruction is sent to its corresponding issuance queue. If the entry corresponding to the instruction issuance validity arbitration module is not empty, the information stored therein needs to be retrieved for comparison.

[0058] 1) If the execution cycle of the preceding instruction in the pipeline corresponding to the entry is not fixed, the current instruction can only continue execution (enter its corresponding issue queue) after the preceding instruction has completed execution and updated the value of the target register. The relevant information of the current instruction (instruction execution function, number of execution cycles, and write-back data) will be stored in the entry of the corresponding instruction. The execution status of the (indefinite cycle) preceding instruction is determined by scanning the real-time updated flag of the instruction's indefinite cycle execution. If the instruction has completed execution or is not executed in an indefinite cycle, the flag will be zero.

[0059] 2) If the execution cycle of the preceding instruction in the pipeline corresponding to the entry is fixed, the execution status of the preceding instruction needs to be determined by scanning the value of the instruction fixed-cycle execution counter, which is updated in real time. If the current instruction performs a write operation on the target register on which it depends, and the current instruction's write delay is greater than or equal to the read / write delay of the remaining data of the preceding instruction, the entry corresponding to the instruction issue validity arbitration module can be updated based on the current instruction's decoding information, or the preceding instruction can be completed. The current instruction can then be sent to its corresponding issue queue. Otherwise, the above conditions must be met before further operation can be performed on the current instruction.

[0060] If the current instruction performs a read operation on the target register on which it depends, it is also necessary to first determine the execution status of the preceding instruction by scanning the value of the instruction fixed-cycle execution counter that is updated in real time: if the remaining execution cycle of the preceding instruction (determined by the fixed-cycle (delay) execution count) is less than or equal to the read operation delay of the current instruction or the preceding instruction has been completed, the entry corresponding to the instruction issue validity arbitration module can be updated according to the decoding information of the current instruction, and the current instruction can be sent to its corresponding issue queue; otherwise, it is necessary to wait for the above conditions to be met before further operation can be performed on the current instruction.

[0061] If the preceding instruction has finished executing and the data is ready, but the data cannot be written back to the target register in the register file until the next cycle, a result data forwarding operation can be performed. This avoids waiting for the data to be stored in the register file and performing an additional read operation, which is beneficial for both performance improvement and power consumption reduction. When the current instruction can obtain the latest data from the required register, the relevant information of the current instruction (instruction execution function, number of execution cycles, and data to be written back) is stored in the entry of the corresponding instruction number, and the current instruction is sent to its corresponding issue queue.

[0062] If a processor decodes and executes instructions using a direct issue method, data-dependent instructions can cause issue blocking, becoming a performance bottleneck. Issue queuing is a technique to avoid this and improve sustained issue rate. It applies two concepts: decoupling source operand checking from instruction issue, and widening the instruction window scanned in each clock cycle to capture more executable instructions. Figure 4 As shown, each entry in the issue queue of this invention includes an opcode, a destination register index, a source register index, and a corresponding validity flag. During instruction dispatch, the opcode and destination register index of the dispatch instruction are distributed from the issue queue to the relevant execution unit, and the source register index is passed to the register file. After the operands are retrieved, the source operands are sent to the corresponding execution unit.

[0063] The instruction issuance processing method for a sequential multiple-issue processor according to the present invention includes the following steps:

[0064] S1. The instruction decoding module decodes the instruction block received from the instruction extraction unit and extracts the category information, source and destination register information and execution delay information of each instruction to be processed.

[0065] S2. Using the target register address of the instruction to be processed as an index, access the corresponding entry in the instruction issue validity arbitration module; if the entry is empty, execute S4, otherwise execute S3.

[0066] S3. Read the status information of the preceding instruction in the entry and determine whether the execution cycle of the preceding instruction is fixed. If the execution cycle of the preceding instruction is not fixed, wait for it to finish executing before executing S4.

[0067] Specifically, when the execution cycle of the current instruction is not fixed, all indefinite-cycle execution flags in the scan entry are checked. If any flag is set, it indicates that the corresponding indefinite-cycle instruction has not been completed and the current instruction must be paused. Step S4 can only be executed when all relevant flag bits in the entry are cleared.

[0068] If the execution cycle of the preceding instructions is fixed, it is necessary to determine whether the current instruction has a data hazard or resource conflict based on the operation type to be executed. If neither exists, then S4 will be executed.

[0069] Specifically, when the execution cycle of the preceding instruction is fixed, the following sub-steps are executed:

[0070] If the current instruction to be executed is a read operation, and the remaining execution cycle of the previous instruction is less than or equal to the read operation delay of the current instruction or the previous instruction has been completed, it is determined that the current instruction does not have data hazards or resource conflicts.

[0071] If the current instruction to be executed is a write operation, and the remaining execution cycle of the previous instruction is less than or equal to the write operation delay of the current instruction or the completion of the previous instruction, it is determined that the current instruction does not have data hazards or resource conflicts.

[0072] If either of the conditions for the preceding instructions is not met in either of the two cases mentioned above, the current instruction must be paused until the condition is met.

[0073] S4. Write the current instruction information into this entry and send the instruction to the launch queue module;

[0074] Before proceeding to step S5, a data forwarding judgment step is also included: when the entry shows that the execution result data of the preceding instruction is ready but has not yet been written to the register file, the result data of the preceding instruction is directly forwarded to the execution unit of the current instruction.

[0075] S5. The launch queue module sends instructions to the execution unit for execution in sequence;

[0076] S6. After the execution unit completes its execution, it writes the execution result back to the corresponding entry in the instruction issuance validity arbitration module.

Claims

1. An instruction issuance processing apparatus for a sequential multiple-issue processor, characterized in that, include: Instruction fetch unit: used to read instruction blocks from instruction memory and pre-decode the instruction blocks to identify and process instructions that cannot be issued in the same cycle, forming an issueable instruction block; Instruction decoding module: used to decode the instruction block received from the instruction extraction unit to obtain the category information, source and destination register information and execution delay information of each instruction to be processed; Instruction issuance validity arbitration module: adopts a fully associative memory structure, including multiple entries, each of which stores the status information of the instruction, and the entries are directly indexed by register addresses; The launch queue module is connected to the command launch validity arbitration module and is used to cache commands that have passed arbitration and are ready to be launched. An execution unit, connected to the launch queue module, is used to execute instructions and write the execution results back to the corresponding entry in the instruction launch validity arbitration module; The instruction decoding module sends the register address that the instruction to be processed needs to access to the instruction issuance validity arbitration module. The instruction issuance validity arbitration module accesses the corresponding entry based on the register address and determines whether the current instruction to be processed has a data hazard or resource conflict based on the previous instruction status information stored in the entry. If neither exists, the current instruction information is written into the entry and the current instruction is sent to the issuance queue module.

2. The apparatus according to claim 1, characterized in that, Each entry in the command issuance validity arbitration module contains N independent and parallel-accessible sub-slots, where N is equal to the designed command issuance width; Each sub-slot independently stores the status information of one instruction. The status information includes at least: instruction execution function, fixed-period execution count, variable-period execution flag, and write-back data.

3. The apparatus according to claim 1, characterized in that, The instruction issuance validity arbitration module determines that the current instruction does not have a data hazard or resource conflict if the corresponding entry is empty when the register address to be accessed by the instruction to be processed is indexed. Otherwise, the following judgment must be made: When the execution cycle of the preceding instruction is not fixed: by scanning the set status of the corresponding variable period execution flag in the entry, it is determined whether the preceding instruction has been executed. After confirming that the execution has been completed, it is determined that the current instruction does not have data hazards or resource conflicts. When the execution cycle of a preorder instruction is fixed: If the current instruction to be executed is a read operation, and the remaining execution cycle of the previous instruction is less than or equal to the read operation delay of the current instruction or the previous instruction has been completed, it is determined that the current instruction does not have data hazards or resource conflicts. If the current instruction to be executed is a write operation, and the remaining execution cycle of the previous instruction is less than or equal to the write operation delay of the current instruction or the completion of the previous instruction, it is determined that the current instruction does not have data hazards or resource conflicts.

4. The apparatus according to claim 1, characterized in that: If, based on the preceding instruction status information stored in the entry of the instruction launch validity arbitration module, it is determined that the preceding instruction has been executed but the result data has not been written back, then the result data is forwarded.

5. The apparatus according to claim 1, characterized in that, The pre-decoding process performed by the instruction extraction unit includes: identifying branch instructions or multi-cycle calculation instructions in the instruction block, and ensuring that the two types of instructions are sent to the instruction decoding module in different cycles.

6. A method for issuing instructions to a sequential multiple-issue processor, characterized in that, Includes the following steps: S1. The instruction decoding module decodes the instruction block received from the instruction extraction unit and extracts the category information, source and destination register information and execution delay information of each instruction to be processed. S2. Using the target register address of the instruction to be processed as an index, access the corresponding entry in the instruction issue validity arbitration module; if the entry is empty, execute S4, otherwise execute S3. S3. Read the status information of the preceding instruction in this entry and determine whether the execution cycle of the preceding instruction is fixed. If the execution cycle of the preceding instruction is not fixed, wait for it to finish executing before executing S4. If the execution cycle of the preceding instruction is fixed, determine whether the current instruction has a data hazard or resource conflict based on the operation type to be executed by the current instruction. If neither exists, then execute S4. If either of the above two conditions is not met, the current instruction must be paused until the conditions are met. S4. Write the current instruction information into this entry and send the instruction to the launch queue module; S5. The launch queue module sends instructions to the execution unit for execution in sequence; S6. After the execution unit completes its execution, it writes the execution result back to the corresponding entry in the instruction issuance validity arbitration module.

7. The method according to claim 6, characterized in that, In step S3, when the execution cycle of the preceding instruction is fixed, the following sub-steps are executed: If the current instruction to be executed is a read operation, and the remaining execution cycle of the previous instruction is less than or equal to the read operation delay of the current instruction or the previous instruction has been completed, it is determined that the current instruction does not have data hazards or resource conflicts. If the current instruction to be executed is a write operation, and the remaining execution cycle of the previous instruction is less than or equal to the write operation delay of the current instruction or the completion of the previous instruction, it is determined that the current instruction does not have data hazards or resource conflicts.

8. The command transmission processing method according to claim 6, characterized in that: In step S3, when the execution cycle of the current instruction is not fixed, all indefinite period execution flags in the scan entry are scanned. If any flag is set, it indicates that the corresponding indefinite period instruction has not been completed and the current instruction must be paused. Step S4 can only be executed when all relevant flag bits in the entry are cleared.

9. The command transmission processing method according to claim 6, characterized in that, Between steps S4 and S5, there is also a data forwarding judgment step: when the entry shows that the execution result data of the preceding instruction is ready but has not yet been written to the register file, the result data of the preceding instruction is directly forwarded to the execution unit of the current instruction.

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