Performance counting device and chip

Abstract

The present disclosure relates to a performance counting device and a chip, the performance counting device comprising: a performance statistics module, configured to receive at least one instruction memory address from a program counter associated therewith, and obtain a statistics value of a performance signal of the at least one instruction memory address located in an instruction memory address interval according to the at least one instruction memory address and the pre-configured instruction memory address interval; a storage module, configured to store the statistics value of the performance signal of the at least one instruction memory address of the performance statistics module; a write control module, configured to write the statistics value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the storage module; and a configuration module, configured to configure the instruction memory address interval of the performance statistics module. The present disclosure helps to improve the flexibility of the configuration of performance statistics, and on this basis, the performance statistics of multiple specified program segments can be implemented at the same time, and then the parallel processing of performance statistics and the accurate positioning of program segments can be realized.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a performance counting device and a chip. BACKGROUND

[0002] One feature of a processor is to support multi-task processing, which can process multiple program or instruction streams simultaneously. When multiple programs run, due to rich instruction sets, or due to strong interdependence, resource conflicts, etc., the assembly instruction execution time is different. When analyzing the performance of a processor program segment, the hardware needs to be able to count the performance of the program segment during execution. In the performance debugging process of the processor, it is often necessary to count the instruction segments that spend the most absolute time or time proportion during program execution of each thread or thread bundle, in order to locate the performance bottleneck, and then perform targeted instruction optimization on the program to improve the program execution performance.

[0003] In related technologies, the performance of a program segment is usually counted by using a performance counter (PFC) mechanism, which counts various events during program execution, such as the number of instructions, the number of clock cycles, the number of cache misses, etc. By configuring the related registers of the performance counter, the type of performance to be counted can be selected.

[0004] This way has limited flexibility in configuration, can only count a limited number of performance events, cannot count multiple parallel programs at the same time, and can only perform the increment operation of the related counter when the event occurs, the statistical interval is single, and lacks dynamic and accurate capture of the processor program segment. In addition, the related technology cannot configure the source of the program segment performance, and cannot accurately control the performance data generated by a specified module. When specific performance data generated by a specific module, a specific program, and a specific time needs to be accurately determined, it is difficult to accurately locate and trace the source. SUMMARY

[0005] Therefore, the present disclosure provides a performance counting device and a chip to help improve the flexibility of performance statistics configuration, and to simultaneously count the performance of multiple specified program segments, and to realize parallel processing of performance statistics and accurate positioning of program segments.

[0006] According to an aspect of an embodiment of the present disclosure, a performance counting device is provided, comprising:

[0007] A performance statistics module is configured to receive at least one instruction memory address from a program counter associated therewith, and obtain a statistical value of a performance signal of the at least one instruction memory address located in a pre-configured instruction memory address interval according to the at least one instruction memory address and the pre-configured instruction memory address interval.

[0008] a storage module, configured to store the statistical value of the performance signal of the at least one instruction memory address of the performance statistics module;

[0009] a write control module, coupled to the performance statistics module and the storage module, configured to write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the storage module;

[0010] a configuration module, coupled to the performance statistics module, configured to configure the instruction memory address interval of the performance statistics module.

[0011] In a possible implementation, the performance statistics module comprises:

[0012] an interval comparison sub-module, coupled to the configuration module, configured to obtain the instruction memory address interval from the configuration module, receive the at least one instruction memory address from the program counter associated with the performance statistics module, and compare each of the received instruction memory addresses with the instruction memory address interval respectively;

[0013] at least one counter, coupled to the interval comparison sub-module, the at least one counter respectively one-to-one corresponding to at least one instruction memory address in the instruction memory address interval, wherein when the instruction memory address received by the interval comparison sub-module from the program counter is within the instruction memory address interval, the interval comparison sub-module triggers the performance signal counting accumulation of the counter corresponding to the instruction memory address to obtain the statistical value of the performance signal associated with the instruction memory address;

[0014] at least one counting register, respectively one-to-one coupled to the at least one counter, each of the at least one counting register respectively used to temporarily store the statistical value of the performance signal associated with the instruction memory address obtained by the counter corresponding thereto.

[0015] In a possible implementation, the configuration module is configured to configure the instruction memory address interval of the performance statistics module as: comprising at least two instruction memory addresses with continuous addresses, or comprising at least two instruction memory addresses with a span interval step.

[0016] In a possible implementation, the configuration module comprises:

[0017] a count mode register configured to configure a count mode of the instruction memory address interval, the count mode being any one of a contiguous interval mode and a stride mode, the instruction memory address interval comprising at least two instruction memory addresses that are contiguous in address when the count mode is the contiguous interval mode, the instruction memory address interval comprising at least two instruction memory addresses that have a stride interval apart in address when the count mode is the stride mode;

[0018] a start address register configured to configure a start address of the instruction memory address interval;

[0019] a stop address register configured to configure a stop address of the instruction memory address interval;

[0020] a stride interval register configured to configure the stride interval apart in address when the count mode is the stride mode.

[0021] In a possible implementation, the performance signal is a high level signal triggered when a program segment to be statistically profiled falls into the instruction memory address interval.

[0022] In a possible implementation, there are at least one performance statistics module and at least one program counter.

[0023] The performance counting apparatus further comprises:

[0024] a crossbar module coupled to the at least one performance statistics module and the configuration module, configured to establish an association between the performance statistics module and the program counter under the configuration of the configuration module;

[0025] The configuration module is further configured to configure a thread bundle identification number and an execution unit identification number, and associate the program counter containing the configured thread bundle identification number and execution unit identification number with the performance statistics module.

[0026] In a possible implementation, the configuration module comprises:

[0027] a thread bundle identification number register configured to configure the thread bundle identification number;

[0028] an execution unit identification number register configured to configure the execution unit identification number.

[0029] In a possible implementation, the configuration module is further configured to configure a number of storage slots of the storage module.

[0030] The write control module is further configured to write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into a current storage slot of the storage module according to the configuration of the storage slot quantity of the storage module by the configuration module, and write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into a next storage slot when a storage slot write transfer condition is reached.

[0031] The storage slot write transfer condition includes at least one of a write duration of a storage slot reaching a preset duration threshold and a data amount written into a storage slot reaching a preset data amount threshold.

[0032] In a possible implementation, the configuration module includes:

[0033] A storage slot quantity register configured to configure the storage slot quantity in the storage module.

[0034] In a possible implementation, the performance counting device further includes:

[0035] A readout control module coupled to the storage module and the configuration module, configured to periodically read out and dump performance data in the storage module to a data storage device outside the performance counting device according to a configured dump time interval.

[0036] The configuration module is further configured to configure the dump time interval.

[0037] In a possible implementation, the configuration module includes:

[0038] A dump time interval register configured to configure the dump time interval.

[0039] In a possible implementation, the configuration module includes:

[0040] A switch control register configured to configure a switch of the performance statistics module.

[0041] According to another aspect of the embodiments of the present disclosure, a chip is provided, including the performance counting device as described in any of the above.

[0042] From the above scheme, it can be seen that the performance counting device and the chip of the present disclosure associate the performance statistics module with the program counter, and since the program counter corresponds to the thread or the thread bundle, the present disclosure realizes the targeted performance statistics of the specified thread or the thread bundle. In addition, since the performance statistics module is pre-configured with the instruction memory address interval, the obtained performance signal statistics value of the instruction memory address is located in the pre-configured instruction memory address interval, so that the accurate positioning of the program segment (the instruction memory address in the thread or the thread bundle located in the instruction memory address interval) is realized. The performance counting device of the present disclosure can replace the performance counter in the related art to perform the performance statistics of the program. The performance counting device of the present disclosure can also flexibly configure the instruction memory address interval of the performance statistics module through the configuration module, so as to further improve the configuration flexibility of the performance statistics, and meet the performance statistics requirements of different application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 FIG. 1 is a first embodiment structure schematic diagram of a performance counting device according to an illustrative embodiment;

[0044] Figure 2 FIG. 2 is a second embodiment structure schematic diagram of a performance counting device according to an illustrative embodiment;

[0045] Figure 3 FIG. 3 is a structure schematic diagram of a performance statistics module according to an illustrative embodiment;

[0046] Figure 4 FIG. 4 is a third embodiment structure schematic diagram of a performance counting device according to an illustrative embodiment.

[0047] In the drawings, the component names represented by the respective reference numerals are as follows:

[0048] 100, performance counting device,

[0049] 11, performance statistics module,

[0050] 11_1, first performance statistics module,

[0051] 11_2, second performance statistics module,

[0052] 11_N, Nth performance statistics module,

[0053] 111, interval comparison submodule,

[0054] 112_1, first counter,

[0055] 112_2, second counter,

[0056] 112_K, Kth counter,

[0057] 113_1, a first count register,

[0058] 113_2, a second count register,

[0059] 113_K, a Kth count register,

[0060] 12, a storage module,

[0061] 13, a write control module,

[0062] 14, a configuration module,

[0063] 15, a crossbar module,

[0064] 16, a read control module,

[0065] 2, a program counter,

[0066] 2_1, a first program counter,

[0067] 2_2, a second program counter,

[0068] 2_M, an Mth program counter,

[0069] 3, a data storage device. DETAILED DESCRIPTION

[0070] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments.

[0071] It should be noted that the terms “first”, “second”, and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence.

[0072] “Coupled (or connected)” used in the specification and claims of the present disclosure can refer to any direct or indirect connection means, for example, a first device coupled (or connected) to a second device should be interpreted as that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or certain connection means.

[0073] The embodiment of the present disclosure provides a performance counting device and a chip comprising the same, which realizes flexible, concurrent and traceable statistics of the performance of a specific program segment of a processor through precise configuration and linkage logic at a hardware level, and realizes periodic performance data dumping by using instruction memory addresses of a program counter (PC) as performance data, and through controllable switch control of the opening and closing of the performance counting device, and supports the implementation of performance counting of multiple program segments by configuring specific single or multiple hardware forms of performance statistics modules, so as to solve the problems of insufficient configuration flexibility and weak performance data traceability in traditional performance statistics techniques, and realize precise statistics of the performance of a processor program segment.

[0074] Figure 1 is a first embodiment structure schematic diagram of a performance counting device according to an illustrative embodiment, as shown in Figure 1 In the illustrative embodiment, the performance counting device 100 of the first embodiment comprises a performance statistics module 11, a storage module 12, a write control module 13 and a configuration module 14. The performance statistics module 11 is configured to receive at least one instruction memory address from the program counter 2 associated therewith, and obtain a statistical value of a performance signal of the at least one instruction memory address located in an instruction memory address interval according to the at least one instruction memory address and the pre-configured instruction memory address interval. The storage module 12 is configured to store the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module 11. The write control module 13 is coupled to the performance statistics module 11 and the storage module 12, and is configured to write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module 11 into the storage module 12. The configuration module 14 is coupled to the performance statistics module 11, and is configured to configure the instruction memory address interval of the performance statistics module 11.

[0075] The program counter is an important register in a processor (for example, a central processing unit), and is configured to store an instruction memory address, wherein the instruction memory address refers to the location of an instruction in a memory. The instruction can be an instruction in a program run by the processor. In an artificial intelligence (AI) computing device, a computing program usually comprises multiple threads or warps, and different threads or warps correspond to different program counters, that is, different program counters store instruction memory addresses of different threads or warps.

[0076] The performance counting device 100 of this embodiment associates the performance statistics module 11 with the program counter 2. Since the program counter 2 corresponds to a thread or thread bundle, the performance counting device 100 of this embodiment achieves targeted performance statistics for a specified thread or thread bundle. Furthermore, because the performance statistics module 11 pre-configures an instruction memory address range, the statistical value of the obtained instruction memory address performance signal is located within the pre-configured instruction memory address range, thus achieving precise location of the statistically analyzed program segment (the instruction memory address within the instruction memory address range in the thread or thread bundle). The performance counting device 100 of this embodiment can replace the performance counter in related technologies.

[0077] In order to associate the performance statistics module 11 with the program counter 2, improve the flexibility of performance statistics configuration, and perform performance statistics on multiple specified program segments simultaneously, in the illustrative embodiment, there is at least one performance statistics module 11 and at least one program counter 2. The association between the performance statistics module 11 and the program counter 2 can be achieved through a cross switch module.

[0078] Figure 2 This is a schematic diagram illustrating a second embodiment of a performance counting device according to an illustrative embodiment. The performance counting device 100 of the second embodiment includes at least one performance statistics module (e.g., Figure 2 The first performance statistics module 11_1, the second performance statistics module 11_2, ..., the Nth performance statistics module 11_N shown can be associated with different program counters according to the configuration. Based on this, the number of program counters is at least one (e.g., Figure 2 The program counters shown are 1st program counter 2_1, 2nd program counter 2_2, ..., Mth program counter 2_M, where N and M can be the same or different. Depending on the configuration, at least one performance statistics module from 1st performance statistics module 11_1 to Nth performance statistics module 11_N can be associated with at least one program counter from 1st program counter 2_1 to Mth program counter 2_M in a first one-to-one relationship. For example... Figure 2 As shown, the performance counting device 100 in the second embodiment also includes a cross switch module 15. The cross switch module 15 is coupled to at least one performance statistics module (e.g., Figure 2The performance statistics module (e.g., the first performance statistics module 11_1 to the Nth performance statistics module 11_N) and the configuration module 14 are configured to establish a one-to-one association between the performance statistics module and the program counter under the configuration of the configuration module 14. The configuration module 14 is further configured to configure a thread bundle identification number (ID) and an execution unit identification number, and associate the program counter containing the configured thread bundle identification number and the execution unit identification number with the performance statistics module. The thread bundle identification number is used to uniquely identify a thread bundle in a program, and the instruction to be statistically analyzed can be locked through the thread bundle identification number. In the illustrative embodiment, the execution unit identification number is used to uniquely identify the execution unit of the thread bundle (instruction), and the specified thread bundle executed by the specified execution unit can be configured by configuring the thread bundle identification number (ID) and the execution unit identification number, so that the performance counting device of the present embodiment can statistically analyze the execution of the specified thread bundle (corresponding to the specified program segment) by the specified execution unit, which helps to improve the configuration flexibility of performance statistics. In the scenario of applying to an artificial intelligence computing device, the execution unit refers to an execution unit (EU) of the artificial intelligence chip that executes the instructions of the thread bundle.

[0079] Because the configuration of the hardware can be realized by using the register, based on this, in the illustrative embodiment, the configuration module can include a thread bundle identification number register and an execution unit identification number register. The thread bundle identification number register is configured to configure the thread bundle identification number, and the execution unit identification number register is configured to configure the execution unit identification number. On this basis, the crossbar module establishes a one-to-one association between the performance statistics module and the program counter according to the configuration value of the thread bundle identification number register and the configuration value of the execution unit identification number register.

[0080] Figure 3 is a structural schematic diagram of the performance statistics module according to an illustrative embodiment, Figure 3 The specific structure of the performance statistics module 11 shown is the specific structure of any one of the performance statistics modules involved in the present embodiment, for example, can be Figure 1 The performance statistics module 11 shown, Figure 2 The specific structure of any one of the first performance statistics module 11_1 to the Nth performance statistics module 11_N shown and any one of the performance statistics modules involved in the subsequent description. As Figure 3As shown, in the illustrative embodiment, the performance statistics module 11 comprises an interval comparison sub-module 111, a plurality of counters and a plurality of count registers. The interval comparison sub-module 111 is coupled to the configuration module 14 for obtaining the instruction memory address interval from the configuration module 14, receiving at least one instruction memory address from the program counter 2 associated with the performance statistics module 11, and comparing each received instruction memory address with the instruction memory address interval respectively. The plurality of counters is at least one, for example Figure 3 The at least one counter (the first counter 112_1, the second counter 112_2,..., the Kth counter 112_K) is coupled to the interval comparison sub-module 111, and the at least one counter (the first counter 112_1, the second counter 112_2,..., the Kth counter 112_K) corresponds to the at least one instruction memory address in the instruction memory address interval respectively. When the instruction memory address received from the program counter 2 by the interval comparison sub-module 111 is within the instruction memory address interval, the interval comparison sub-module 111 triggers the counter corresponding to the instruction memory address to count the performance signal and obtain the statistical value of the performance signal associated with the instruction memory address. The plurality of count registers is at least one, for example Figure 3 The at least one count register (the first count register 113_1, the second count register 113_2,..., the Kth count register 113_K) is coupled to the at least one counter (the first counter 112_1, the second counter 112_2,..., the Kth counter 112_K) respectively, for example Figure 3 As shown, the first count register 113_1 is coupled to the first counter 112_1, the second count register 113_2 is coupled to the second counter 112_2, and the Kth count register 113_K is coupled to the Kth counter 112_K. Each of the at least one count register is used to temporarily store the statistical value of the performance signal associated with the instruction memory address obtained by the counter coupled thereto respectively, for example Figure 3In the shown embodiment, the first count register 113_1 is configured to temporarily store the statistical value of the performance signal associated with the instruction memory address obtained by the first counter 112_1, the second count register 113_2 is configured to temporarily store the statistical value of the performance signal associated with the instruction memory address obtained by the second counter 112_2, and so on, and the Kth count register 113_K is configured to temporarily store the statistical value of the performance signal associated with the instruction memory address obtained by the Kth counter 112_K. The write control module 13 is coupled to the count registers in the performance statistics module 11 and is configured to write the statistical values of the performance signals associated with the instruction memory addresses temporarily stored in the count registers into the storage module. Specifically, the write control module 13 is coupled to the first count register 113_1 to the Kth count register 113_K and is configured to write all the statistical values of the performance signals associated with the instruction memory addresses temporarily stored in the first count register 113_1 to the Kth count register 113_K into the storage module.

[0081] Based on Figure 3 In the shown embodiment, each of the first counter 112_1 to the Kth counter 112_K is associated with a different instruction memory address, and therefore the first count register 113_1 to the Kth count register 113_K temporarily store the statistical values of the performance signals associated with the different instruction memory addresses respectively associated with the first counter 112_1 to the Kth counter 112_K.

[0082] The performance counting device 100 of the embodiments of the present disclosure can flexibly configure the instruction memory address interval of the performance statistics module 11 through the configuration module 14, thereby further improving the configuration flexibility of the performance statistics and meeting the performance statistics requirements of different application scenarios. In an illustrative embodiment, the configuration module 14 is configured to configure the instruction memory address interval of the performance statistics module 11 to include at least two instruction memory addresses that are continuous in address, or to include at least two instruction memory addresses that have a span interval step.

[0083] In an illustrative embodiment, in the case where the configuration module 14 configures the instruction memory address interval of the performance statistics module 11 to include K continuous instruction memory addresses, in the performance statistics module 11, the statistical values of the performance signals obtained by the first counter 112_1 to the Kth counter 112_K are the statistical values of the performance signals of the K continuous instruction memory addresses.

[0084] In an illustrative embodiment, in the case where the configuration module 14 configures the instruction memory address interval of the performance statistics module 11 to include K instruction memory addresses that have a span interval step, in the performance statistics module 11, the statistical values of the performance signals obtained by the first counter 112_1 to the Kth counter 112_K are the statistical values of the performance signals of the K instruction memory addresses that have a span interval step.

[0085] It should be noted that the above is an example of K instruction memory addresses. The performance statistics module 11 includes K counters, and the number of instruction memory addresses in the instruction memory address interval to which the performance statistics module 11 is configured can be less than K. The K counters included in the performance statistics module 11 indicate that the maximum number of instruction memory addresses that the performance statistics module 11 can count can be K, and not only K instruction memory addresses. In the case where the number of instruction memory addresses in the instruction memory address interval to which the performance statistics module 11 is configured is less than K, the performance statistics module 11 only uses counters corresponding to the number of instruction memory addresses in the instruction memory address interval to count the corresponding performance signals.

[0086] Based on the manner of configuring hardware by using registers, in the illustrative embodiment, the configuration module 14 can include a count mode register, a start address register, an end address register, and an interval step register. The count mode register is used to configure the count mode of the instruction memory address interval, and the count mode is any one of the continuous interval mode and the step mode. When the count mode is the continuous interval mode, the instruction memory address interval includes at least two instruction memory addresses that are continuous in address. When the count mode is the step mode, the instruction memory address interval includes at least two instruction memory addresses that span an interval step. The start address register is used to configure the start address of the instruction memory address interval. The end address register is used to configure the end address of the instruction memory address interval. The interval step register is used to configure the interval step when the count mode is the step mode.

[0087] When the count mode is the continuous interval mode, the instruction memory address interval can be determined by the value of the start address register and the value of the end address register. At this time, the instruction memory address interval is a continuous interval of memory addresses. When the count mode is the step mode, the instruction memory address interval is determined by the value of the start address register, the value of the end address register, and the value of the interval step register. At this time, the instruction memory address interval is in a form in which each memory address is discrete from each other.

[0088] In the illustrative embodiment, the performance signal is a high-level signal triggered when the program segment of the desired statistical performance falls into the instruction memory address interval. In this way, the clock cycles consumed by a certain instruction (program segment) can be counted (no performance signal is generated or the performance signal remains low when the program segment does not fall into the instruction memory address interval, and the performance signal is triggered and generated by the clock signal when the program segment falls into the instruction memory address interval (i.e., the performance signal), and the total number of clock cycles during which the high-level signal is maintained (i.e., the statistical value) reflects the clock cycles consumed by the instruction (program segment)). Thus, the time consumed by the relevant instruction in the software can be analyzed, and the instruction with abnormal time consumption can be analyzed from the statistical results of all performance signals according to the corresponding screening conditions. In combination with the corresponding thread bundle identification number and execution unit identification number, the instruction memory address of the abnormal instruction, the thread bundle in which the abnormal instruction is located, and the relevant execution unit that executes the abnormal instruction can be located, thereby improving the degree of accurate positioning of the abnormal program segment (instruction).

[0089] In order to reasonably arrange the storage and dumping of the statistical values of the performance signals of a large number of instruction memory addresses by the storage module 12, the storage module 12 stores the statistical values of the performance signals of the instruction memory addresses in batches in the form of storage slots. The storage module 12 is divided into a plurality of storage slots according to the configuration, and the statistical values of the performance signals of the instruction memory addresses obtained at different times can be stored in different storage slots. In this way, when the statistical values of the performance signals of the instruction memory addresses are written into a certain storage slot, the data in the storage slots in which the statistical values of the performance signals of the instruction memory addresses have been written can also be dumped to a data storage device other than the performance counting device 100, thereby realizing the uninterrupted cyclic storage of the storage module 12.

[0090] Based on this, in the illustrative embodiment, the configuration module 14 is further configured to configure the number of storage slots of the storage module 12. The write control module 13 is further configured to write the statistical values of the performance signals of at least one instruction memory address obtained by the performance statistical module 11 into the current storage slot of the storage module 12 according to the configuration of the number of storage slots of the storage module 12 by the configuration module 14, and write the statistical values of the performance signals of at least one instruction memory address obtained by the performance statistical module 11 into the next storage slot when the storage slot write transfer condition is reached (satisfied) (the storage slot write transfer condition can be understood as the state of reaching the storage slot write transfer condition from the state of not satisfying the storage slot write transfer condition to the state of satisfying the storage slot write transfer condition). The storage slot write transfer condition includes at least one of the write duration of the storage slot reaching a preset duration threshold and the data amount written into the storage slot reaching a preset data amount threshold.

[0091] Based on the way of configuring hardware by using registers, in the illustrative embodiment, the configuration module 14 comprises a number of storage registers. The number of storage registers is used to configure the number of storages in the storage module 12.

[0092] Figure 4 is a third embodiment structure schematic diagram of a performance counting device according to an illustrative embodiment, as Figure 4 As shown, in order to realize the control of data dump in the storage module 12, in the illustrative embodiment, the performance counting device 100 of the present disclosure also comprises a readout control module 16. The readout control module 16 is coupled to the storage module 12 and the configuration module 14, and is used to regularly read out the performance data (including the statistical value of the performance signal of at least one instruction memory address) in the storage module 12 to the data storage device 3 outside the performance counting device 100 according to the configured dump time interval. The configuration module 14 is also used to configure the dump time interval.

[0093] Based on the way of configuring hardware by using registers, in the illustrative embodiment, the configuration module 14 comprises a dump time interval register. The dump time interval register is used to configure the dump time interval.

[0094] In actual application scenarios, there are cases of not performing performance counting, and there are also cases of only counting the performance signal of a small number of instruction memory addresses. Based on this, in order to save power consumption, the configuration module 14 is also used to control the on-off state of each performance counting module 11. When not performing performance counting, all performance counting modules 11 are turned off, and when only counting the performance signal of a small number of instruction memory addresses, only a part of the performance counting modules 11 are turned on, so as to achieve the purpose of saving power consumption.

[0095] Based on the way of configuring hardware by using registers, in the illustrative embodiment, the configuration module 14 comprises a switch control register. The switch control register is used to configure the on-off of each performance counting module 11.

[0096] In the illustrative embodiment, the relevant registers in the configuration module 14 can be written with relevant configuration parameters by software or driver, and the performance counting device 100 realizes corresponding performance counting based on the configuration parameters.

[0097] In one specific application scenario, the dump time interval register can be named as Dump_interval_config, which is used to configure the time interval of periodically dumping the performance data in the storage module 12 to the external data storage device 3, and the unit of the time interval is clock cycle. The bit width of the dump time interval register can be set as needed, for example, the bit width can be set to 14. When configuring, the software or the driver writes an unsigned integer of 14 bits into the dump time interval register, which indicates how many clock cycles apart to dump the performance data in the storage module 12.

[0098] In one specific application scenario, the storage slot number register can be named as Storage_slot_cnt, which is used to configure the number of storage slots of the storage module 12, and the limited resources of the storage module 12 are evenly divided into each storage slot to facilitate data dumping. The configuration value of the storage slot number register represents the maximum number of cacheable dump data blocks (storage slots). The bit width of the storage slot number register can be set as needed, for example, the bit width can be set to 8.

[0099] In one specific application scenario, the counting mode register can be named as PC_dump_mode, which is used to configure the counting mode of the instruction memory address interval. The bit width of the counting mode register can be set as needed, for example, the bit width can be set to 1.

[0100] In one application example, the counting mode register is configured as 0, indicating a continuous interval mode. In this mode, the instruction memory address interval of the performance statistics module 11 includes at least two instruction memory addresses with continuous addresses, wherein the start address register is configured with the start address of the instruction memory address interval, and the end address register is configured with the end address of the instruction memory address interval.

[0101] In one application example, the counting mode register is configured as 1, indicating a step mode. In this mode, the instruction memory address interval of the performance statistics module 11 includes at least two instruction memory addresses with a span interval step, wherein the start address register is configured with the start address of the instruction memory address interval, the end address register is configured with the end address of the instruction memory address interval, and the interval step register is configured with the span interval step between the instruction memory addresses in the instruction memory address interval.

[0102] In one specific application scenario, the start address register can be named as PC_min, which is used to configure the start address of the instruction memory address interval. The bit width of the start address register can be set as needed, for example, the bit width can be set to 64.

[0103] In one specific application scenario, the termination address register can be named as PC_max, which is used to configure the termination address of the instruction memory address interval. The bit width of the termination address register can be set as needed, for example, the bit width can be set to 64.

[0104] In one specific application scenario, the interval step register can be named as PC_step, which is used to configure the interval step when the count mode is the step mode. The value of the interval step register is only effective when the value of the count mode register is 1. The bit width of the interval step register can be set as needed, for example, the bit width can be set to 8.

[0105] In one specific application scenario, the switch control register can be named as PFC_count_en, which is used to configure the switch of the performance statistics module 11. The number of the switch control register is determined according to the number of the performance statistics module 11, for example, when the number of the performance statistics module 11 is N, the number of the switch control register is N, each switch control register corresponds to the switch of one performance statistics module 11, and the bit width of the switch control register can be set to 1. When the value of the switch control register is 1, the corresponding performance statistics module 11 is started, and when the value of the switch control register is 0, the corresponding performance statistics module 11 is closed.

[0106] In one specific application scenario, the thread bundle identification number register can be named as Warp_id, which is used to configure the thread bundle identification number. The number of the thread bundle identification number register is determined according to the number of the performance statistics module 11, for example, when the number of the performance statistics module 11 is N, the number of the thread bundle identification number register is N, and each thread bundle identification number register corresponds to each performance statistics module 11. The bit width of the thread bundle identification number register is determined according to the bit width of the thread bundle identification number.

[0107] In one specific application scenario, the execution unit identification number register can be named as EU_id, which is used to configure the execution unit identification number. The number of the execution unit identification number register is determined according to the number of the performance statistics module 11, for example, when the number of the performance statistics module 11 is N, the number of the execution unit identification number register is N, and each execution unit identification number register corresponds to each performance statistics module 11. The bit width of the execution unit identification number register is determined according to the bit width of the execution unit identification number.

[0108] In the performance counting device 100, the performance data of the multiple program counters 2 is routed by the crossbar module 15 and distributed to different performance statistics modules 11 to realize concurrent statistics support of the multiple program counters 2 (corresponding to multiple threads or multiple thread bundles). The performance data of the corresponding configuration mode obtained by each performance statistics module 11 is written to the storage module 12 by the write control module 13, and the performance data in the storage module 12 is regularly read out and dumped to the data storage device 3 outside the performance counting device 100 as the output of the performance statistics results by the read control module 16.

[0109] The performance counting device 100 of the embodiment of the present disclosure supports regular dumping, and the time interval of each dumping can be configured by a dumping time interval register. The performance counting device 100 of the embodiment of the present disclosure can also configure the number of storage slots in the storage module 12 by a storage slot number register. The performance counting device 100 can configure counting modes, including counting of performance signals of continuous instruction memory addresses between a configured start address and a termination address, and counting of performance signals of discrete instruction memory addresses according to a specified interval step. When the value of the switch control register corresponding to a certain performance statistics module 11 is 1, the performance statistics module 11 performs counting, otherwise it does not count. Flexible counting can be performed on specific program segments according to the multiple execution unit identification numbers and thread bundle identification numbers configured by the configuration module 14.

[0110] In each performance statistics module 11, an interval comparison sub-module 111, multiple counters and a counting register for storing counting results are included. The program counter 2 associated with the performance statistics module 11 inputs instruction memory addresses to the performance statistics module 11 for counting according to performance signals. The interval comparison sub-module 111 compares the instruction memory addresses input by the program counter 2 according to the values of the counting mode register, the start address register, the termination address register and the interval step register configured by the configuration module 14, and judges whether the instruction memory addresses input by the program counter 2 fall into the instruction memory address interval determined by the values of the counting mode register, the start address register, the termination address register and the interval step register. When the instruction memory addresses input by the program counter 2 fall into the instruction memory address interval, the corresponding counter is triggered to count. The instruction memory addresses input by the program counter 2 are all operated in this way. The counting results (statistics values) of each counter are temporarily stored in the corresponding counting register, and are written to the storage module 12 by the write control module 13.

[0111] The performance counting device 100 of the embodiment of the present disclosure mainly includes the following three working stages.

[0112] Stage one: configuration stage (initialization stage).

[0113] The configuration information is written into the configuration module 14 through an external interface (such as a PCIe interface) by software or a driver (which can be software or a driver running on a central processing unit), and the parameter initialization of the performance counting device 100 is completed, and the specific configuration actions are as follows.

[0114] The dump time interval is written into the Dump_interval_config, which represents the processor clock cycle interval required to trigger a performance data dump; the storage slot count is written into the Storage_slot_cnt, for example, 0x08 is written, which means that the storage module 12 can buffer up to 8 dump data blocks.

[0115] 0 or 1 is written into the PC_dump_mode to specify the counting mode. If the counting mode is specified as a continuous interval mode, 0 is written into the PC_dump_mode, and the start address of the instruction memory address interval is written into the PC_min, for example, 0x0007FFF00001000, and the end address of the instruction memory address interval is written into the PC_max, for example, 0x0007FFF00001FFF.

[0116] If the counting mode is specified as a step mode, 1 is written into the PC_dump_mode, and the start address of the instruction memory address interval is written into the PC_min, and the step size across the interval is written into the PC_step, such as 0x02, that is, every 2 instruction memory addresses are selected as an instruction memory address, and the adjacent instruction memory addresses are counted with two instruction memory addresses not counted in between.

[0117] Each performance counting module 11 corresponds to one thread bundle of one execution unit, and the execution unit and the thread bundle are determined by the EU_id and the Warp_id. The performance counting module 11 includes K counters, which can support up to K instruction memory addresses for simultaneous counting. The instruction memory address corresponding to each counter is [PC_min+step k, PC_min+step (k+1)), where k ∈ 0, 1, …, K-1.

[0118] At least one thread bundle identification number is written into the Warp_id, for example, 0x000A is written, which means that the thread bundle with identification number 10 is counted. The execution unit identification number is written into the EU_id, for example, 0x0003 is written, which means that the instruction performance of the 3rd execution unit is counted. The Warp_id and the EU_id are combined to indicate the performance of the 3rd execution unit executing the thread bundle with identification number 10.

[0119] Write 1 to PFC_count_en to start counting, and write 0 to PFC_count_en to end counting.

[0120] Phase two: hardware concurrent counting phase (counting phase).

[0121] After the performance counting device 100 is initialized, the real-time counting phase is entered, and the hardware modules (crossbar module 15, performance counting module 11, interval comparison submodule 111) automatically work according to the configuration of the related registers in the configuration module 14.

[0122] The program counters 2 of the plurality of thread bundles in the processor input instruction memory addresses to the performance counting device 100 in real time, and the crossbar module 15 screens the instruction memory addresses of the corresponding program counters 2 according to the configuration of the Warp_id and EU_ID, and only sends the instruction memory addresses of the program counters 2 that meet the conditions of the Warp_id and EU_ID to the corresponding performance counting module 11, to realize accurate positioning and counting for the specified Warp_id and EU_ID.

[0123] The interval comparison submodule 111 in the performance counting module 11 compares the instruction memory addresses received from the crossbar module 15 with the instruction memory address interval configured by the PC_dump_mode, PC_min, PC_max and PC_step in the configuration module 14:

[0124] In the continuous interval mode (PC_dump_mode=0): if the received current instruction memory address is an address in the range of [PC_min, PC_max], the counter corresponding to the current instruction memory address is triggered to start counting (for example, the number of instruction executions, the number of clock cycles, etc.), and when the next instruction memory address is received, the counting of the counter corresponding to the current instruction memory address is stopped;

[0125] In the case of the step mode (PC_dump_mode = 1), if the received current instruction memory address falls in any discrete interval of PC_min, PC_min + PC_step, PC_min + 2*PC_step,..., PC_min + (PC_count_times - 1)*PC_step, the counter corresponding to the current instruction memory address is triggered to count, and the counting of the counter corresponding to the current instruction memory address is stopped when the next instruction memory address is received. Wherein, PC_count_times is the number of jumps, PC_count_times is determined by PC_min, PC_max and PC_step, wherein (PC_count_times - 1)*PC_step is within the range of [PC_min, PC_max], and (PC_count_times)*PC_step is outside the range of [PC_min, PC_max].

[0126] The K counters of the first counter 112_1 to the Kth counter 112_K in the performance statistics module 11 periodically pack the K counting results (statistical values of the performance signals of the instruction memory addresses) and send them to the write control unit. In an embodiment, the write control unit polls, arbitrates and processes the write requests of the N performance statistics modules 11_1 to 11_N, and then writes the counting results from each performance statistics module 11 into the storage interval corresponding to each performance statistics module 11 in the storage module 12. When any one of the performance statistics modules 11 next writes the counting results into the storage module 12, the corresponding storage interval in the storage module 12 does not overwrite the previous counting results, but records the next counting results after the storage position of the previous counting results; the program counter 2 associated with the performance statistics module 11 counts and accumulates the performance signals of the corresponding program segment to obtain the statistical values of the performance signals, which can be post-processed by related software after being dumped to the external data storage device 3. In another embodiment, the write control module 13 first reads out and adds the counting results of the performance statistics module 11 and the counting results already stored in the storage module 12, and then writes them into the storage module 12, which can save the internal storage space of the storage module 12.

[0127] Stage three: regular dumping stage.

[0128] After the configuration is completed, if the performance statistics module 11 is in the open state, the data in the storage module 12 is automatically periodically dumped to the external data storage device 3 through the readout control module 16. The dumping from the storage module 12 to the external data storage device 3 is automatically triggered according to the interval configured by Dump_interval_config, and the performance data of N performance counting modules stored in the storage slots of the storage module 12 configured by Storage_slot_cnt are periodically dumped into the external data storage device 3 and the data in the storage slots is emptied to prevent counting errors caused by data overflow.

[0129] The performance counting device of the embodiment of the present disclosure is flexible in configuration, strong in adaptability, can configure multi-dimensional parameters, and flexibly adjusts according to different scenarios. When the instruction memory address received from the program counter enters the pre-configured instruction memory address interval, the associated performance statistics module is triggered to perform statistical counting. The instruction memory address interval can be configured as needed, and the instruction memory address interval can be configured as a continuous interval mode and a step mode as needed. The instruction memory address corresponding to the instruction segment with relatively high absolute time or time proportion spent in the program execution process can be accurately located, so that the program performance bottleneck can be accurately located.

[0130] The performance counting device of the embodiment of the present disclosure supports parallel counting of multiple performance statistics modules, and can simultaneously count the program execution conditions of threads or thread bundles. Each performance statistics module can be configured to correspond to a thread or a thread bundle. The program execution conditions of more threads or thread bundles can be sampled by means of time division multiplexing using fewer performance statistics modules, for example, associating the performance statistics module with a part of the program counters to sample the program execution conditions of a part of the threads or thread bundles in a certain period of time, and associating the performance statistics module with another part of the program counters to sample the program execution conditions of another part of the threads or thread bundles in another period of time.

[0131] The counting results of each performance statistics module of the performance counting device of the embodiment of the present disclosure are periodically written to the storage module. By setting, the writing period can be less than the maximum counting value of the counter, thereby avoiding overflow of the counter, which helps to realize miniaturization of the counter. In addition, the data in the storage module is periodically dumped to the external data storage device according to the configuration. By configuring, the dumping period is less than the time when the storage module is full, thereby realizing miniaturization of the storage module capacity. Thus, it is helpful to reduce the related hardware overhead and to reduce the chip area occupied by the performance counting device of the embodiment of the present disclosure.

[0132] In the illustrative embodiment, the implementation of at least one of the performance statistics module 11, the storage module 12, the write control module 13, the configuration module 14, the crossbar module 15, the interval comparison sub-module 111, the counter, the count register, and the readout control module 16 can be in the form of a combination of hardware, firmware, and software (i.e., a program) according to different designs.

[0133] In hardware form, at least one of the performance statistics module 11, the storage module 12, the write control module 13, the configuration module 14, the crossbar module 15, the interval comparison sub-module 111, the counter, the count register, and the readout control module 16 can be implemented as logic circuitry on an integrated circuit, e.g., various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units, for performing the functions of at least one of the performance statistics module 11, the storage module 12, the write control module 13, the configuration module 14, the crossbar module 15, the interval comparison sub-module 111, the counter, the count register, and the readout control module 16. The functions of at least one of the performance statistics module 11, the storage module 12, the write control module 13, the configuration module 14, the crossbar module 15, the interval comparison sub-module 111, the counter, the count register, and the readout control module 16 can be implemented in hardware circuitry, e.g., various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0134] In software or firmware form, the functions of at least one of the performance statistics module 11, the storage module 12, the write control module 13, the configuration module 14, the crossbar module 15, the interval comparison sub-module 111, the counter, the count register, and the readout control module 16 can be implemented as programming codes. For example, at least one of the performance statistics module 11, the storage module 12, the write control module 13, the configuration module 14, the crossbar module 15, the interval comparison sub-module 111, the counter, the count register, and the readout control module 16 can be implemented using a general programming language (e.g., C, C++, or assembly language) or other suitable programming language. The programming codes can be recorded, stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and / or a storage device. An electronic device (e.g., a CPU, a hardware controller, a microcontroller, a hardware processor, or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the functions of at least one of the performance statistics module 11, the storage module 12, the write control module 13, the configuration module 14, the crossbar module 15, the interval comparison sub-module 111, the counter, the count register, and the readout control module 16.

[0135] In illustrative embodiments, the performance counting apparatus of the present disclosure is applicable to a SoC chip, etc., where the SoC chip can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit).

[0136] In illustrative embodiments, a chip is also provided, which includes the performance counting apparatus as described in any one of the above embodiments.

[0137] The above merely provides preferred embodiments of the present disclosure, and is not used to limit the present disclosure. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A performance counter device, characterized by, The performance counting device comprises: a performance statistics module, configured to receive at least one instruction memory address from a program counter associated with the performance statistics module, and obtain a statistics value of a performance signal of the at least one instruction memory address located in a pre-configured instruction memory address interval according to the at least one instruction memory address and the instruction memory address interval, wherein different program counters store instruction memory addresses of different threads or thread bundles respectively, and the instruction memory address refers to a location where an instruction is stored in a memory; a storage module, configured to store the statistics value of the performance signal of the at least one instruction memory address obtained by the performance statistics module; a write control module, coupled to the performance statistics module and the storage module, and configured to write the statistics value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the storage module; and a configuration module, coupled to the performance statistics module, and configured to configure the instruction memory address interval of the performance statistics module.

2. The performance counting device of claim 1, wherein, The performance statistics module comprises: an interval comparison sub-module, coupled to the configuration module, and configured to obtain the instruction memory address interval from the configuration module, receive the at least one instruction memory address from the program counter associated with the performance statistics module, and compare each of the received instruction memory addresses with the instruction memory address interval respectively; at least one counter, coupled to the interval comparison sub-module, wherein the at least one counter one-to-one corresponds to at least one instruction memory address in the instruction memory address interval, and when the instruction memory address received by the interval comparison sub-module from the program counter is located in the instruction memory address interval, the interval comparison sub-module triggers the counter corresponding to the instruction memory address to perform performance signal counting accumulation, so as to obtain a statistics value of a performance signal associated with the instruction memory address; at least one counting register, one-to-one coupled to the at least one counter respectively, and each of the at least one counting register is configured to temporarily store the statistics value of the performance signal associated with the instruction memory address obtained by the counter corresponding thereto.

3. The performance counting device according to claim 1, wherein: the configuration module is configured to configure the instruction memory address interval of the performance statistics module as at least two instruction memory addresses with continuous addresses or at least two instruction memory addresses with a span interval step.

4. The performance counting device of claim 3, wherein, The configuration module comprises: a counting mode register, configured to configure a counting mode of the instruction memory address interval, wherein the counting mode is any one of a continuous interval mode and a step mode, when the counting mode is the continuous interval mode, the instruction memory address interval comprises at least two instruction memory addresses with continuous addresses, and when the counting mode is the step mode, the instruction memory address interval comprises at least two instruction memory addresses with a span interval step; a start address register, configured to configure a start address of the instruction memory address interval; a termination address register, configured to configure a termination address of the instruction memory address interval. a stride register configured to configure a stride of the span when the count mode is the stride mode.

5. The performance counting device of claim 1, wherein: the performance signal is a high level signal triggered when a program segment to be counted enters the instruction memory address interval.

6. The performance counting device of claim 1, wherein: the performance counting module is at least one, and the program counter is at least one; the performance counting device further comprises: a crossbar module coupled to the performance counting module and the configuration module, configured to establish an association between the performance counting module and the program counter under the configuration of the configuration module; the configuration module is further configured to configure a thread bundle identification number and an execution unit identification number, and associate the program counter containing the configured thread bundle identification number and execution unit identification number with the performance counting module.

7. The performance counting device of claim 6, wherein, the configuration module comprises: a thread bundle identification number register configured to configure the thread bundle identification number; an execution unit identification number register configured to configure the execution unit identification number.

8. The performance counting device of claim 1, wherein: the configuration module is further configured to configure a number of storage slots of the storage module; the write control module is further configured to write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance counting module into a current storage slot of the storage module according to the configuration of the number of storage slots of the storage module by the configuration module, and write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance counting module into a next storage slot when a storage slot write transfer condition is reached; wherein the storage slot write transfer condition comprises at least one of a write duration of a storage slot reaching a preset duration threshold, and a data amount written into a storage slot reaching a preset data amount threshold.

9. The performance counting device of claim 8, wherein, the configuration module comprises: a storage slot number register configured to configure the number of storage slots in the storage module.

10. The performance counting device of claim 1, wherein, the performance counting device further comprises: a readout control module coupled to the storage module and the configuration module, configured to periodically read out and dump performance data in the storage module to a data storage device outside the performance counting device according to a configured dumping time interval; the configuration module is further configured to configure the dumping time interval.

11. The performance counting device of claim 10, wherein, the configuration module comprises: a dumping time interval register configured to configure the dumping time interval.

12. The performance counting device of claim 1, wherein, the configuration module comprises: a switch control register configured to configure a switch of the performance counting module.

13. A chip, characterized by a performance counting device as claimed in any one of claims 1 to 12.

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