Memory device

Abstract

A memory device includes an instruction memory and a plurality of micro-control units. The instruction memory outputs a plurality of instruction codes at predetermined time intervals according to a plurality of address signals and a plurality of divided clock signals. The plurality of micro-control units are coupled to each of the plurality of memory regions, provide each of the plurality of address signals to the instruction memory according to each of the plurality of divided clock signals, and perform an operation according to a corresponding instruction code among the plurality of instruction codes.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0165087, filed on November 19, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The various embodiments of this disclosure generally relate to a semiconductor device, and more specifically, to a memory device with a shared instruction memory. Background Technology

[0004] Typical memory devices include, for example, multiple memory regions across multiple planes, microcontroller units for controlling the multiple planes, and instruction memory for storing instruction codes related to control operations. Memory devices support Plane Interleaved Read (PIR) mode, which allows read operations to be interleaved across multiple planes.

[0005] However, due to the high integration of typical memory devices, there are space constraints caused by the arrangement and wiring of multiple planes connecting to the microcontroller and instruction memory, and there is an increase in peak current due to the interleaved read patterns of the planes. Furthermore, there is an increase in area due to the multiple instruction memories, and concerns about reduced yield due to the increased probability of defects proportional to the number of instruction memories. Summary of the Invention

[0006] In embodiments of this disclosure, a memory device may include an instruction memory and a plurality of microcontroller units. The instruction memory may output a plurality of instruction codes at predetermined time intervals based on a plurality of address signals and a plurality of divided clock signals. The plurality of microcontroller units may be coupled to each of a plurality of memory regions, may provide each of a plurality of address signals to the instruction memory based on each of the plurality of divided clock signals, and may execute operations based on the corresponding instruction code among the plurality of instruction codes.

[0007] In embodiments of this disclosure, a memory device may include multiple planes, input / output pad circuitry, data input / output circuitry, an instruction memory, and multiple memory operation control-related circuits. The input / output pad circuitry may include multiple pads. The data input / output circuitry may be connected to the input / output pad circuitry. The instruction memory may output multiple instruction codes at predetermined time intervals based on multiple address signals and multiple divided clock signals. The multiple memory operation control-related circuits may be commonly connected to the data input / output circuitry, may be connected one-to-one to multiple planes, may provide each of the multiple address signals to the instruction memory based on each of the multiple divided clock signals, and may execute operations based on the corresponding instruction code among the multiple instruction codes. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating the configuration of a data storage device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a diagram illustrating the configuration of a memory device according to an embodiment of the present disclosure.

[0010] Figure 3 It is shown Figure 2 A diagram showing the configuration of the first plane and the peripheral circuitry.

[0011] Figure 4 It is shown Figure 2 A diagram illustrating the configuration of the memory operation control circuitry.

[0012] Figure 5 This is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0013] Figure 6 This is a diagram illustrating the configuration of a memory device according to an embodiment of the present disclosure.

[0014] Figure 7 It is shown Figure 6 A diagram illustrating the configuration of the memory operation control circuitry.

[0015] Figure 8 It is shown Figure 6 A diagram showing the configuration of the frequency divider circuit.

[0016] Figure 9 and Figure 10 It is shown Figure 8 A diagram illustrating the operation of a frequency divider circuit.

[0017] Figure 11 It is shown Figure 6 A diagram illustrating the configuration of the instruction memory.

[0018] Figure 12 It is shown Figure 11 A diagram illustrating the configuration of the memory kernel.

[0019] Figure 13 It is shown Figure 11 A diagram showing the configuration of the output control circuit.

[0020] Figure 14 It is shown Figure 11 A diagram showing the configuration of the command output circuit.

[0021] Figure 15 It is shown Figure 11 A diagram showing the configuration of the control signal generation circuit.

[0022] Figure 16 and Figure 17 It is shown Figure 15 A diagram illustrating the operation of the control clock generation circuit.

[0023] Figure 18 and Figure 19 It is shown Figure 15 A diagram illustrating the operation of the control signal generation unit.

[0024] Figure 20 This is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0025] Various embodiments of this disclosure can reduce circuit area and current consumption, and increase system efficiency and reliability.

[0026] In the following, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0027] Figure 1 This is a diagram illustrating the configuration of the data storage device 1 according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The data storage device 1 can be connected to the host 2. The data storage device 1 can send data DATA to or receive data DATA from the host 2 in response to commands (i.e., requests) received from the host 2. The data storage device 1 may include a memory device 1-1 and a controller 1-2.

[0029] The memory device 1-1 may include a plurality of logic units LU0 to LUn. The logic unit LU may be a unit used to separate and manage an entire memory region of the data storage device 1. Each of the plurality of logic units LU0 to LUn may include at least one memory chip.

[0030] Controller 1-2 can generate multiple control signals CRTLs and commands CMDi in response to command CMDe and provide them to memory device 1-1. Controller 1-2 can send data DATA to / receive data DATA from memory device 1-1 according to read and write operations. The multiple control signals CRTLs may include clock signals, signals related to memory chip activation, and signals related to read and write operations.

[0031] Figure 2 This is a diagram illustrating the configuration of a memory device 10 according to an embodiment of the present disclosure.

[0032] Reference Figure 2 The memory device 10 may include multiple memory regions such as multiple planes PL1 to PLn, multiple memory operation control related circuits 11-1 to 11-n, input / output pad circuits 12, data input / output circuits 13, and an oscillator (OSC) 14.

[0033] Each of the plurality of planes PL1 to PLn may include an array of memory cells. The plurality of memory cells included in the array of memory cells may include non-volatile memory cells.

[0034] The input / output pad circuit 12 may include multiple pads 12-1, which are used to receive commands CMDi, clock signals CKL and addresses, and to input and output data DQ.

[0035] The data input / output circuit 13 can be commonly connected between multiple memory operation control related circuits 11-1 to 11-n and the input / output pad circuit 12 to perform data input and output operations.

[0036] Oscillator 14 can generate clock signal CKL.

[0037] Multiple memory operation control related circuits 11-1 to 11-n can be connected between multiple planes PL1 to PLn and the data input / output circuit 13. These circuits can be connected one-to-one with each plane. For example, the first memory operation control related circuit 11-1 can be connected between the first plane PL1 and the data input / output circuit 13, the second memory operation control related circuit 11-2 can be connected between the second plane PL2 and the data input / output circuit 13, and the nth memory operation control related circuit 11-n can be connected between the nth plane PLn and the data input / output circuit 13.

[0038] Multiple memory operation control related circuits 11-1 to 11-n can be configured identically to each other. For example, the first memory operation control related circuit 11-1 may include an instruction memory (ISTM), a microcontroller unit (MCU), and peripheral circuitry (PER). The instruction memory (ISTM) can store data related to the operation of the memory device 10 (hereinafter referred to as instruction data), and can output at least one instruction data corresponding to an external access from the stored instruction data as instruction code. The instruction memory (ISTM) can be configured using a read-only memory (ROM).

[0039] Instruction data may include information directly related to the operation of memory device 10, i.e., information used to instruct the circuitry of memory device 10 regarding operations such as programming / erasing / reading. Instruction data may also include information independent of data stored in the multiple planes PL1 to PLn.

[0040] The peripheral circuitry (PER) may include circuitry related to data input and output to the first plane, such as circuitry configurations for controlling programming, reading, and erasing operations. The microcontroller unit (MCU) may control the operation of the PER based on the results of decoding instruction codes provided from the instruction memory (ISTM).

[0041] Figure 3 It is shown Figure 2 A diagram showing the configuration of the first plane PL1 and the peripheral circuit PER.

[0042] Reference Figure 3 The peripheral circuit PER may include an address decoder (i.e., a row decoder) 51, a voltage generator 52, and a read and write circuit 53. The read and write circuit 53 may include multiple page buffers PB1 to PBm. The peripheral circuit PER is coupled to a first plane PL1 and can drive the first plane PL1 to perform programming operations, read operations, and erase operations.

[0043] The first plane PL1 may include a memory cell array and is connected to the address decoder 51 via word lines WL and to the read and write circuitry 53 via bit lines BL1 to BLm. The first plane PL1 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 51 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to the read and write circuitry 53 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The multiple memory cells may be non-volatile memory cells. Each of the multiple memory blocks BLK1 to BLKz may include multiple pages. Among the multiple memory cells, memory cells connected to the same word line can be defined as pages.

[0044] Address decoder 51 can be connected to first plane PL1 via word line WL. Address decoder 51 can select at least one of a plurality of memory blocks BLK1 to BLKz based on the result of decoding an address provided to memory device 10 by an external device (e.g., a host). Address decoder 51 can select at least one word line of the selected memory block by applying a voltage generated from voltage generator 52 to at least one word line WL of the selected memory block. Address decoder 51 can perform a programming operation by applying a programming voltage to the selected word line and a pass voltage lower than the programming voltage to an unselected word line. Address decoder 51 can perform a read operation by applying a read voltage to the selected word line and a pass voltage higher than the read voltage to an unselected word line. Address decoder 51 can perform an erase operation by applying a ground voltage to the word line connected to the selected memory block and applying an erase voltage to the bulk region forming the selected memory block.

[0045] Voltage generator 52 can generate various voltages required for the operation of memory device 10, such as read voltage, pass voltage, program voltage and erase voltage, and provide the voltages to address decoder 51.

[0046] Multiple page buffers PB1 to PBm can be connected to the first plane PL1 via the first to m-th bit lines BL1 to BLm, respectively. The multiple page buffers PB1 to PBm can communicate with the data input / output circuit 13.

[0047] Figure 4 It is shown Figure 2 A diagram illustrating the configuration of the memory operation control related circuits 11-1 to 11-n.

[0048] Reference Figure 4 The first memory operation control related circuit 11-1 connected to the first plane PL1 may include an instruction memory (ISTM) 20-1, a microcontroller unit (MCU) 30-1, and a peripheral circuit (PER) 40-1.

[0049] Peripheral circuit 40-1 may include reference Figure 3 The configuration described. Peripheral circuitry 40-1 may further include components for controlling the reference. Figure 3 The logic circuitry described in the configuration operation.

[0050] Instruction memory 20-1 can receive clock signal CKL and address signal RMADD1 <n-1:0>It can also output instruction code RINST1. Instruction memory 20-1 can store instruction data related to various functions of peripheral circuit 40-1. Instruction memory 20-1 can select the instruction data corresponding to address signal RMADD1 from multiple instruction data according to clock signal CKL. <n-1:0>The instruction data is output as instruction code RINST1.

[0051] The microcontroller unit 30-1 can control the peripheral circuit 40-1 according to the clock signal CKL and the instruction code RINST1. The microcontroller unit 30-1 may include a fetch register (FTR) 31-1, a decoder (DEC) 32-1, an run register (EXR) 33-1, a program counter (PGMCNT) 34-1, an address register (ADDR) 35-1, and command processing logic (CPL) 36-1.

[0052] The fetch register 31-1 can store the instruction code RINST1 in response to the clock signal CKL. The decoder 32-1 can output the result of decoding the instruction code RINST1 stored in the fetch register 31-1. The run register 33-1 can store the output of the decoder 32-1 according to the clock signal CKL and provide this output to the peripheral circuit 40-1. Based on the output of the run register 33-1, the logic circuit of the peripheral circuit 40-1 can be selectively controlled. The program counter 34-1 can change the value of the internal address ADD-INT1 according to the output of the decoder 32-1. The address register 35-1 can use the internal address ADD-INT1 changed by the program counter 34-1 as the address signal RMADD1 according to the clock signal CKL. <n-1:0>Store and assign the address signal RMADD1 <n-1:0>The instruction memory 20-1 is provided. The command processing logic 36-1 can control the program counter 34-1 in response to the command CMDi.

[0053] The nth memory operation control related circuitry 11-n, connected to the nth plane PLn, may include an instruction memory 20-n, a microcontroller unit (MCU) 30-n, and peripheral circuitry (PER) 40-n.

[0054] The peripheral circuit 40-n can be configured similarly to the peripheral circuit 40-1.

[0055] Instruction memory 20-n can receive clock signal CKL and address signal RMADDn <n-1:0>It outputs the instruction code RINSTn. Instruction memory 20-n can store the same instruction data as instruction memory 20-1, and can output the corresponding address signal RMADDn according to the clock signal CKL. <n-1:0>The instruction data is output as instruction code RINSTn. Instruction memory 20-n can be configured similarly to instruction memory 20-1.

[0056] The microcontroller unit 30-n can control the peripheral circuit 40-n according to the clock signal CKL and the instruction code RINSTn. The microcontroller unit 30-n can have the same configuration as the microcontroller unit 30-1.

[0057] Figure 4 Only a portion of the memory operation control related circuits 11-1 to 11-n are shown, and the memory operation control related circuits 11-1 to 11-n can be configured identically to each other.

[0058] Figure 5 This is a diagram illustrating the operation of a memory device 10 according to an embodiment of the present disclosure.

[0059] The memory device 10 supports Plane Interleaved Read (PIR) mode. Plane Interleaved Read mode is an operation mode in which multiple planes perform read operations at defined time intervals.

[0060] For ease of description, there are three planes PL1 to PLn (n=3), and the plane interleaved read operations of memory device 10 will be described.

[0061] In the first plane PL1 to the third plane PL3, address signals RMADD1 with different values ​​are sequentially provided to the first plane PL1 based on the rising edge of the clock signal CKL.

[0062] Based on the address signal RMADD1 with different values, instruction code RINST1 with different values ​​is generated sequentially.

[0063] The instruction codes RINST1 with different values ​​are stored in the fetch register FTR at 1tCK intervals relative to the input timing of the address signal RMADD1. 1tCK represents one cycle of the clock signal CKL.

[0064] The instruction code RINST1 with different values ​​is decoded sequentially by the decoder DEC.

[0065] The output of the decoder DEC is timed relative to the input of the fetch register FTR, stored in the run register 33-1 at 1tCK intervals, and provided to the peripheral circuit 40-1.

[0066] The third plane PL3 can perform the same operation as the first plane PL1 at intervals of 1tCK relative to the first plane PL1.

[0067] The second plane PL2 can perform the same operation as the third plane PL3 at intervals of 2tCK relative to the third plane PL3.

[0068] The order of operations and / or the time intervals between operations between each plane are merely exemplary and may be varied depending on the design and operation.

[0069] Figure 6 This is a diagram illustrating the configuration of a memory device 100 according to an embodiment of the present disclosure.

[0070] Reference Figure 6 The memory device 100 may include multiple planes PL1 to PLn, multiple memory operation control related circuits 110-1 to 110-n, input / output pad circuits 120, data input / output circuits 130, oscillator (OSC) 140, frequency divider circuit (DIV) 500, and instruction memory (ISTM) 600.

[0071] Each of the plurality of planes PL1 to PLn may include an array of memory cells. The plurality of memory cells included in the array of memory cells may include non-volatile memory cells.

[0072] The input / output pad circuit 120 may include multiple pads 120-1, which are used to receive commands CMDi and to input and output data DQ.

[0073] The data input / output circuit 130 can be commonly connected between multiple memory operation control related circuits 110-1 to 110-n and the input / output pad circuit 120 to perform data input and output operations.

[0074] Multiple memory operation control circuits 110-1 to 110-n can be connected between multiple planes PL1 to PLn and the data input / output circuit 130. These circuits can control operations related to data input and output of the planes PL1 to PLn, such as programming, reading, and erasing operations. Each circuit can be connected one-to-one to a plane PL1 to PLn and can also be connected to the data input / output circuit 130. A first memory operation control circuit 110-1 can be connected between the first plane PL1 and the data input / output circuit 130, a second memory operation control circuit 110-2 can be connected between the second plane PL2 and the data input / output circuit 130, and an nth memory operation control circuit 110-n can be connected between the nth plane PLn and the data input / output circuit 130.

[0075] Multiple memory operation control related circuits 110-1 to 110-n can be configured identically to each other. The first memory operation control related circuit 110-1 may include a microcontroller unit MCU1 and a peripheral circuit PER1. The peripheral circuit PER1 may include data input and output related circuitry for the first plane PL1, i.e., circuitry configured to control programming, reading, and erasing operations. The microcontroller unit MCU1 can control the operation of the peripheral circuit PER1 based on the result of decoding instruction codes provided by the instruction memory 600. The second memory operation control related circuit 110-2 may include a microcontroller unit MCU2 and a peripheral circuit PER2, and the nth memory operation control related circuit 110-n may include a microcontroller unit MCUn and a peripheral circuit PERn.

[0076] The frequency divider circuit 500 can receive the clock signal CKH and the plane interleaved readout mode setting signal PIRFLG, and generate multiple frequency-divided clock signals CKD. <n:1>The frequency divider circuit 500 can divide the clock signal CKH to generate multiple divided clock signals CKD. <n:1>The frequency divider circuit 500 can adjust multiple divided clock signals CKD according to the planar interleaved readout mode setting signal PIRFLG. <n:1>The phase.

[0077] The instruction memory 600 can receive multiple divided clock signals CKD <n:1>The instruction memory 600 includes a planar interleaved read mode setting signal PIRFLG, a timing adjustment signal TT<2:1>, and multiple address signals, and outputs multiple instruction codes. The instruction memory 600 can be shared by multiple microcontrollers MCU1 to MCUn. The instruction memory 600 can be configured based on the planar interleaved read mode setting signal PIRFLG and multiple frequency-divided clock signals CKD. <n:1>The system outputs multiple instruction codes at predetermined time intervals. The term "predetermined" as used herein with respect to parameters such as predetermined timing, time, or voltage levels means that the value of the parameter has been determined before it is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm, but before the parameter is used in the process or algorithm.

[0078] Oscillator 140 can generate a clock signal CKH. The clock signal CKH has a frequency corresponding to the number of memory operation control-related circuits 110-1 to 110-n, i.e., a frequency corresponding to the number of microcontrollers MCU1 to MCUn. For example, when the memory device 100 includes three microcontrollers, compared to when the memory device 100 includes only one microcontroller, oscillator 140 can generate a clock signal CKH with a frequency up to three times higher. In another example, when the memory device 100 includes four microcontrollers, compared to when the memory device 100 includes only one microcontroller, oscillator 140 can generate a clock signal CKH with a frequency up to four times higher. When the memory device 100 includes only one microcontroller, the frequency of the clock signal CKH can be compared to a reference... Figure 2 The clock signal CKH used in the described memory device 10 has the same frequency. When the memory device 100 includes three microcontrollers, the frequency of the clock signal CKH can be a reference frequency. Figure 2 The frequency of the clock signal CKL used in the described memory device 10 is three times that of the clock signal CKL.

[0079] Figure 7 It is shown Figure 6 A diagram illustrating the configuration of the memory operation control related circuits 110-1 to 110-n.

[0080] Reference Figure 7 The instruction memory 600 can receive multiple divided clock signals CKD. <n:1>The signal PIRFLG sets the interleaved read mode, the timing adjustment signal TT<2:1> and multiple address signals RMADD. <n:1> <n-1:0>And output multiple instruction codes RINST <n:1>The instruction memory 600 can store instruction data related to the operation of the memory device 100.

[0081] Instruction data may include information directly related to the operation of memory device 100, i.e., information used to instruct the corresponding circuits regarding programming / erasing / reading operations, etc. Instruction data may include information independent of data stored in the multiple planes PL1 to PLn.

[0082] The instruction memory 600 can retrieve the RMADD corresponding to multiple address signals from the stored instruction data. <n:1> <n-1:0>The instruction data is used as multiple instruction codes RINST <n:1>Output. The instruction memory 600 can respond to multiple divided clock signals CKD. <n:1>Each of these, at predetermined time intervals, will send multiple instruction codes RINST. <n:1>Each of them is provided to each of the multiple microcontrollers MCU1 to MCUn.

[0083] The first memory operation control related circuit 110-1 connected to the first plane PL1 may include a microcontroller unit (MCU1) 300-1 and a peripheral circuit (PER1) 400-1.

[0084] Peripheral circuit 400-1 may include reference Figure 3 The configuration described. The peripheral circuitry 400-1 may further include features for controlling the reference. Figure 3 The logic circuitry described in the configuration operation.

[0085] The microcontroller unit 300-1 can receive multiple instruction codes RINST. <n:1>The first instruction code RINST1 and multiple frequency-divided clock signals CKD are in the middle. <n:1>The first divided clock signal CKD1 outputs multiple address signals RMADD. <n:1> <n-1:0>The first address signal RMADD1 <n-1:0>And control the peripheral circuit 400-1.

[0086] The microcontroller unit 300-1 may include an extract register (FTR) 310-1, a decoder (DEC) 320-1, an run register (EXR) 330-1, a program counter (PGMCNT) 340-1, an address register (ADDR) 350-1, and command processing logic (CPL) 360-1.

[0087] The fetch register 310-1 can store the first instruction code RINST1 according to the first divided clock signal CKD1. The decoder 320-1 can output the result of decoding the first instruction code RINST1 stored in the fetch register 310-1. The run register 330-1 can store the output of the decoder 320-1 according to the first divided clock signal CKD1 and provide the output to the peripheral circuit 400-1. Based on the output of the run register 330-1, the logic circuit in the peripheral circuit 400-1 can be selectively controlled. The program counter 340-1 can change the value of the internal address ADD-INT1 in response to the output of the decoder 320-1. The address register 350-1 can use the internal address ADD-INT1 changed by the program counter 340-1 as the first address signal RMADD1 according to the first divided clock signal CKD1. <n-1:0>Store, and store the first address signal RMADD1 <n-1:0>The instruction memory 600 is provided. The command processing logic 360-1 can control the program counter 340-1 in response to the command CMDi.

[0088] The nth memory operation control related circuit 110-n connected to the nth plane PLn may include a microcontroller unit (MCUn) 300-n and peripheral circuits (PERn) 400-n.

[0089] Peripheral circuit 400-n can have the same configuration as peripheral circuit 400-1.

[0090] The microcontroller unit 300-n can receive multiple instruction codes RINST <n:1>The nth instruction code RINSTn and multiple frequency-divided clock signals CKD <n:1>The nth frequency division clock signal CKDn outputs multiple address signals RMADD. <n:1> <n-1:0>The nth address signal RMADDn <n-1:0>It also controls the peripheral circuits 400-n. The microcontroller unit 300-n can have the same configuration as the microcontroller unit 300-1.

[0091] Figure 7 Only a portion of the memory operation control related circuits 110-1 to 110-n are shown, and the memory operation control related circuits 110-1 to 110-n can be configured identically to each other.

[0092] Figure 8 It is shown Figure 6 A diagram showing the configuration of the frequency divider circuit 500. Figure 9 and Figure 10 It is shown Figure 8 A diagram illustrating the operation of the frequency divider circuit 500. Figure 8 An example is shown in which the memory device 100 includes three planes PL1 to PL3 and three memory operation control related circuits 110-1 to 110-3, and the frequency divider circuit 500 is configured to generate a first divided clock signal to a third divided clock signal CKD<3:1> accordingly.

[0093] In the following text, reference will be made to Figures 8 to 10 Describe the configuration and operation of the frequency divider circuit 500.

[0094] In the following description, the activation / deactivation of a circuit configuration indicates that the circuit configuration is in an operable / inoperable state, and the activation / deactivation of a signal indicates that the logic level of the signal is high / low or low / high.

[0095] Reference Figure 8 The frequency divider circuit 500 may include a multiphase signal generator 510, a pre-division clock generator 520, an activation control circuit 540, and multiple multiplexers 531 to 533.

[0096] The multiphase signal generator 510 can receive a reset signal RST and a clock signal CKH as inputs, and output multiphase signals CK-PH0 to CK-PH2. The reset signal RST can be activated at a low level during a predetermined time during the initial operation of the data storage device 1 and upon request from the host 2, and can be deactivated at a high level during other operation intervals.

[0097] The multiphase signal generator 510 may include a first flip-flop 511, a second flip-flop 512, and a logic gate 513. The first flip-flop 511 can output the first phase signal CK-PH0 latched to the rising edge of the clock signal CKH as the second phase signal CK-PH1. The second flip-flop 512 can output the second phase signal CK-PH1 latched to the rising edge of the clock signal CKH as the third phase signal CK-PH2. The logic gate 513 can output the result of a NOR operation performed on the second phase signal CK-PH1 and the third phase signal CK-PH2 as the first phase signal CK-PH0. When the reset signal RST is high, the first flip-flop 511 and the second flip-flop 512 can be activated to perform the above operations, and when the reset signal RST is low, their outputs can be reset. Figure 9 and Figure 10 As shown, polyphase signals CK-PH0 to CK-PH2 can be generated with a predetermined phase difference.

[0098] The prescaler clock generator 520 can receive multiphase signals CK-PH0 to CK-PH2 and clock signal CKH as inputs, and output multiple prescaler clock signals CKD-PRE1 to CKD-PRE3. The prescaler clock generator 520 may include a first flip-flop 521 to a sixth flip-flop 526 and a first logic gate 527 to a third logic gate 529. The first flip-flop 521 can output a signal that latches the first phase signal CK-PH0 to the rising edge of the clock signal CKH. The second flip-flop 522 can output a signal that latches the second phase signal CK-PH1 to the rising edge of the clock signal CKH. The third flip-flop 523 can output a signal that latches the third phase signal CK-PH2 to the rising edge of the clock signal CKH. The fourth flip-flop 524 can output a signal that latches the output of the first flip-flop 521 to the falling edge of the clock signal CKH. The fifth flip-flop 525 can output a signal that latches the output of the second flip-flop 522 to the falling edge of the clock signal CKH. The sixth flip-flop 526 can output a signal that latches the output of the third flip-flop 523 to the falling edge of the clock signal CKH. The first logic gate 527 can output the first prescaler clock signal CKD-PRE1 as the result of performing an OR operation on the outputs of the first flip-flop 521 and the fourth flip-flop 524. The second logic gate 528 can output the second prescaler clock signal CKD-PRE2 as the result of performing an OR operation on the outputs of the second flip-flop 522 and the fifth flip-flop 525. The third logic gate 529 can output the third prescaler clock signal CKD-PRE3 as the result of performing an OR operation on the outputs of the third flip-flop 523 and the sixth flip-flop 526.

[0099] The activation control circuit 540 can selectively activate the prescaler clock generator 520 in response to a reset signal RST and multiple activation signals ACT-PL<3:1>. The activation control circuit 540 may include first logic gates 541 to fourth logic gates 544. First logic gate 541 can invert the reset signal RST and output an inverted reset signal. Second logic gate 542 can activate flip-flops 521 and 524 of the prescaler clock generator 520 based on the result of a NOR operation performed on the output of first logic gate 541 and the inverted first activation signal ACT-PL1. Third logic gate 543 can activate flip-flops 522 and 525 of the prescaler clock generator 520 based on the result of a NOR operation performed on the inverted second activation signal ACT-PL2 and the output of first logic gate 541. Fourth logic gate 544 can activate flip-flops 523 and 526 of the prescaler clock generator 520 based on the result of a NOR operation performed on the inverted third activation signal ACT-PL3 and the output of first logic gate 541. Multiple activation signals ACT-PL<3:1> can be signals activated in response to a read command for a corresponding plane. The first activation signal ACT-PL1 can be a signal activated by a read command for a first plane PL1, the second activation signal ACT-PL2 can be a signal activated by a read command for a second plane PL2, and the third activation signal ACT-PL3 can be a signal activated by a read command for a third plane PL3.

[0100] According to the planar interleaved read mode setting signal PIRFLG, multiple multiplexers 531 to 533 can optionally output multiple prescaled clock signals CKD-PRE1 to CKD-PRE3 as multiple divided clock signals CKD<3:1>. When the read operation mode of the memory device 100 is set to planar interleaved read mode, the planar interleaved read mode setting signal PIRFLG can be activated; otherwise, it is deactivated. The first multiplexer 531 can output the first prescaled clock signal CKD-PRE1 as the first divided clock signal CKD1 independently of the planar interleaved read mode setting signal PIRFLG. When the planar interleaved read mode setting signal PIRFLG is deactivated, the second multiplexer 532 can output the first prescaled clock signal CKD-PRE1 as the second divided clock signal CKD2, and when the planar interleaved read mode setting signal PIRFLG is activated, it can output the second prescaled clock signal CKD-PRE2 as the second divided clock signal CKD2. When the Plane Interleaved Read Mode Setting Signal PIRFLG is disabled, the third multiplexer 533 can output the first prescaled clock signal CKD-PRE1 as the third prescaled clock signal CKD3. When the Plane Interleaved Read Mode Setting Signal PIRFLG is activated, it can output the third prescaled clock signal CKD-PRE3 as the third prescaled clock signal CKD3.

[0101] like Figure 9 As shown, when the Plane Interleaved Read Mode Setting Signal PIRFLG is activated because the read operation mode of the memory device 100 is set to Plane Interleaved Read Mode, the frequency divider circuit 500 can generate multiple frequency-divided clock signals CKD<3:1> with a predetermined phase difference.

[0102] On the other hand, such as Figure 10 As shown, when the planar interleaved read mode setting signal PIRFLG is deactivated because the read operation mode of the memory device 100 is set to normal read mode, the frequency divider circuit 500 can generate multiple frequency-divided clock signals CKD<3:1> with the same phase.

[0103] Figure 11 It is shown Figure 6 A diagram illustrating the configuration of the instruction memory 600.

[0104] Reference Figure 11 The instruction memory 600 may include a memory core 601, an output control circuit 602, a command output circuit 603, and a control signal generation circuit 604.

[0105] The memory core 601 can receive the integrated address signal ADD. <n-1:0>The word line enable signal WLEN is used as input, and instruction data IDATA can be output. <m-1:0>When the word line enable signal WLEN is activated, the memory core 601 can output the integrated address signal ADD from the stored instruction data. <n-1:0>Instruction data IDATA <m-1:0>.

[0106] The output control circuit 602 can receive multiple address signals RMADD<3:1> <n-1:0>It takes multiple preliminary word line control signals RWLEN<3:1> as inputs and outputs the integrated address signal ADD. <n-1:0>The word line enable signal is WLEN.

[0107] Command output circuit 603 can receive command data IDATA <m-1:0>It also includes multiple load control signals RLDEN<3:1> and outputs multiple instruction codes RINST<3:1>. <m-1:0>.

[0108] The control signal generation circuit 604 can receive multiple frequency division clock signals CKD<3:1>, planar interleaved read mode setting signal PIRFLG, and timing adjustment signal TT<2:1>, and output multiple preliminary word line control signals RWLEN<3:1> and multiple load control signals RLDEN<3:1>.

[0109] Figure 12 It is shown Figure 11 A diagram illustrating the configuration of the memory core 601.

[0110] Reference Figure 12 The memory core 601 may include a memory cell array, a word line driver (WLD) 611, a bit line driver (BLD) 612, an address decoder (ADEC) 613, and a sense amplifier array 614.

[0111] The memory cell array may include memory cells MC connected to multiple word lines WL and multiple bit lines BL.

[0112] Address decoder 613 can output the integrated address signal ADD. <n-1:0>The result of decoding.

[0113] When the word line enable signal WLEN is activated, the word line driver 611 can activate the word line among multiple word lines WL that corresponds to the output of the address decoder 613.

[0114] Bit line driver 612 can be connected between multiple bit lines BL and global line GBL. Bit line driver 612 can transmit the signal on the bit line BL that corresponds to the output of address decoder 613 to global line GBL.

[0115] The sense amplifier array 614 may include multiple sense amplifiers SA. The sense amplifier array 614 may amplify the result of comparing the level of the signal transmitted to the global line GBL with the reference signal RBL, and use the amplified result as instruction data IDATA. <m-1:0>Output.

[0116] Figure 13 It is shown Figure 11 A diagram showing the configuration of the output control circuit 602.

[0117] Reference Figure 13 The output control circuit 602 may include multiple buffer arrays 621 to 623, a first logic gate 624 and a second logic gate 625, and a pull-down driver 626.

[0118] When the first preliminary word line control signal RWLEN1 is activated, the first buffer array 621 can release the first address signal RMADD1. <n-1:0>As an integrated address signal ADD <n-1:0>Output. The first buffer array 621 may include the first address signal RMADD1. <n-1:0>The number of buffers is the same as the number of bits in the buffer.

[0119] When the second preliminary word line control signal RWLEN2 is activated, the second buffer array 622 can transmit the second address signal RMADD2. <n-1:0>As an integrated address signal ADD <n-1:0>Output. The second buffer array 622 may include the second address signal RMADD2. <n-1:0>The number of buffers is the same as the number of bits in the buffer.

[0120] When the third preliminary word line control signal RWLEN3 is activated, the third buffer array 623 can transmit the third address signal RMADD3. <n-1:0>As an integrated address signal ADD <n-1:0>Output. The third buffer array 623 may include the third address signal RMADD3. <n-1:0>The number of buffers is the same as the number of bits in the buffer.

[0121] The first logic gate 624 can output the result of performing a NOR operation on multiple preliminary word line control signals RWLEN<3:1>.

[0122] The second logic gate 625 can output the inverted output of the first logic gate 624 as the word line enable signal WLEN.

[0123] When any one of the multiple preliminary word line control signals RWLEN<3:1> is activated, the first logic gate 624 and the second logic gate 625 can activate the word line enable signal WLEN.

[0124] The pull-down driver 626 can initialize the integrated address signal ADD based on the output of the first logic gate 624. <n-1:0>The pull-down driver 626 may include an integrated address signal ADD. <n-1:0>The number of bits in the driver is the same. Pull-down driver 626 can initialize the integrated address signal ADD by pulling down the outputs of multiple buffer arrays 621 to 623 to ground voltage levels. <n-1:0>.

[0125] When all the multiple preliminary word line control signals RWLEN<3:1> are disabled, the output control circuit 602 can initialize the integrated address signal ADD. <n-1:0>Furthermore, when any one of the multiple preliminary word line control signals RWLEN<3:1> is activated, the output control circuit 602 can respond according to the multiple address signals RMADD<3:1> <n-1:0>To generate integrated address signal ADD <n-1:0>.

[0126] Figure 14 It is shown Figure 11 A diagram illustrating the configuration of the command output circuit 603.

[0127] Reference Figure 14 The command output circuit 603 may include multiple buffer arrays 631 to 633 and multiple latch arrays 634 to 636.

[0128] When the first load control signal RLDEN1 is activated, the first buffer array 631 can process the instruction data IDATA. <m-1:0>Invert and output. The first buffer array 631 may include instruction data IDATA. <m-1:0>The number of buffers is the same as the number of bits.

[0129] When the second load control signal RLDEN2 is activated, the second buffer array 632 can process the instruction data IDATA. <m-1:0>Invert and output. The second buffer array 632 may include instruction data IDATA. <m-1:0>The number of buffers is the same as the number of bits.

[0130] When the third load control signal RLDEN3 is activated, the third buffer array 633 can process the instruction data IDATA. <m-1:0>Invert and output. The third buffer array 633 may include instruction data IDATA. <m-1:0>The number of buffers is the same as the number of bits.

[0131] The first latch array 634 can latch the output of the first buffer array 631 and use the output as the first instruction code RINST1. <m-1:0>Output. The first latch array 634 may include the first instruction code RINST1. <m-1:0>A latch with the same number of bits as the number of bits in the middle.

[0132] The second latch array 635 can latch the output of the second buffer array 632 and use the output as the second instruction code RINST2. <m-1:0>Output. The second latch array 635 may include the second instruction code RINST2. <m-1:0>A latch with the same number of bits as the number of bits in the middle.

[0133] The third latch array 636 can latch the output of the third buffer array 633 and use this output as the third instruction code RINST3. <m-1:0>Output. The third latch array 636 may include the third instruction code RINST3. <m-1:0>A latch with the same number of bits as the number of bits in the middle.

[0134] Figure 15 It is shown Figure 11 A diagram showing the configuration of the control signal generation circuit 604. Figure 16 and Figure 17 It is shown Figure 15 A diagram illustrating the operation of the control clock generation circuit 640, and Figure 18 and Figure 19 It is shown Figure 15 A diagram illustrating the operation of the control signal generation unit 650.

[0135] In the following text, reference will be made to Figures 15 to 19 Describe the configuration and operation of the control signal generation circuit 604.

[0136] Reference Figure 15 The control signal generation circuit 604 may include a control clock generation circuit 640 and multiple control signal generation units (i.e., control signal generation logic) 650 to 670.

[0137] The control clock generation circuit 640 can receive multiple frequency division clock signals CKD<3:1> and planar interleaved readout mode setting signal PIRFLG as inputs, and output multiple control clock signals RMCK<3:1>.

[0138] The control clock generation circuit 640 may include multiple logic gates 641 to 646. The first logic gate 641 outputs the result of a NAND operation performed on the first divided clock signal CKD1 and the first power supply voltage VCCI. The second logic gate 642 outputs the result of a NAND operation performed on the second divided clock signal CKD2 and the plane interleaved readout mode setting signal PIRFLG. The third logic gate 643 outputs the result of a NAND operation performed on the third divided clock signal CKD3 and the plane interleaved readout mode setting signal PIRFLG. The fourth logic gate 644 outputs the result of a NAND operation performed on the inverted output of the first logic gate 641 and the output of the second logic gate 642 as the first control clock signal RMCK1. The fifth logic gate 645 outputs the result of a NAND operation performed on the inverted output of the second logic gate 642 and the output of the third logic gate 643 as the second control clock signal RMCK2. The sixth logic gate 646 outputs the result of a NAND operation performed on the inverted output of the third logic gate 643 and the output of the first logic gate 641 as the third control clock signal RMCK3.

[0139] Reference Figure 16 When in normal read mode, i.e., when the planar interleaved read mode setting signal PIRFLG is disabled and the second control clock signal RMCK2 and the third control clock signal RMCK3 are fixed at a low level, the control clock generation circuit 640 outputs the first divided clock signal CKD1 as the first control clock signal RMCK1. Therefore, when not in planar interleaved read mode, embodiments of this disclosure can prevent unnecessary power consumption by fixing the second control clock signal RMCK2 and the third control clock signal RMCK3, which are independent of the planar interleaved read mode, at a low level.

[0140] Reference Figure 17 When the planar interleaved readout mode setting signal PIRFLG is activated, the control clock generation circuit 640 outputs a signal with a high-level interval corresponding to the phase difference between the first divided clock signal CKD1 and the second divided clock signal CKD2 as the first control clock signal RMCK1, a signal with a high-level interval corresponding to the phase difference between the second divided clock signal CKD2 and the third divided clock signal CKD3 as the second control clock signal RMCK2, and a signal with a high-level interval corresponding to the phase difference between the third divided clock signal CKD3 and the first divided clock signal CKD1 as the third control clock signal RMCK3. When the planar interleaved readout mode setting signal PIRFLG is deactivated, the first control clock signal RMCK1 has a high-level interval corresponding to 1.5 cycles of the clock signal CKH. When the planar interleaved readout mode setting signal PIRFLG is activated, the first control clock signal RMCK1 has a high-level interval corresponding to 1 cycle of the clock signal CKH.

[0141] Reference Figure 15 , Figure 18 and Figure 19 Multiple control signal generation units 650 to 670 can generate multiple preliminary word line control signals RWLEN<3:1> and multiple load control signals RLDEN<3:1> by combining the delay signals of each of the multiple control clock signals RMCK<3:1>.

[0142] The first control signal generation unit 650 can receive the first control clock signal RMCK1 and the timing adjustment signal TT<2:1>, and output the first preliminary word line control signal RWLEN1 and the first load control signal RLDEN1.

[0143] The first control signal generation unit 650 may include a first delay circuit 651 to a third delay circuit 653, a first logic gate 654, and a second logic gate 655. The first delay circuit 651 can delay the first control clock signal RMCK1 by a set amount of time to generate a first delayed signal DEL1. The second delay circuit 652 can delay the first delayed signal DEL1 by a time adjusted by the timing adjustment signal TT1 to generate a second delayed signal DEL2. The third delay circuit 653 can delay the second delayed signal DEL2 by a time adjusted by the timing adjustment signal TT2 to generate a third delayed signal DEL3. The first logic gate 654 can output the result of an AND operation performed on the second delayed signal DEL2 and the third delayed signal DEL3 as a first preliminary word line control signal RWLEN1. The second logic gate 655 can output the result of an AND operation performed on the first delayed signal DEL1 and the third delayed signal DEL3 as a first load control signal RLDEN1.

[0144] The second control signal generation unit 660 can receive the second control clock signal RMCK2 and the timing adjustment signal TT<2:1>, and output the second preliminary word line control signal RWLEN2 and the second load control signal RLDEN2. The second control signal generation unit 660 can have the same configuration as the first control signal generation unit 650.

[0145] The third control signal generation unit 670 can receive the third control clock signal RMCK3 and the timing adjustment signal TT<2:1>, and output the third preliminary word line control signal RWLEN3 and the third load control signal RLDEN3. The third control signal generation unit 670 can have the same configuration as the first control signal generation unit 650.

[0146] Figure 20 This is a diagram illustrating the operation of a memory device 100 according to an embodiment of the present disclosure.

[0147] In the following text, refer to Figures 6 to 20 The planar interleaved read operation of memory device 100 will be described. For ease of description, the plurality of planes PL1 to PLn are three (n=3). When the planar interleaved read mode is activated, read operations on the first plane PL1 to the third plane PL3 can be performed in a preset order. An embodiment of the present disclosure will be described, wherein when the planar interleaved read mode is activated, the read operation is set to be performed in the order of the first plane PL1, the third plane PL3, and the second plane PL2.

[0148] First, as referenced Figure 8 When a read command for the first plane PL1 is input, the first activation signal ACT-PL1 can be activated, and the first frequency divider clock signal CKD1 can be activated accordingly.

[0149] The microcontroller unit 300-1, which is connected to the first plane PL1, provides an address signal RMADD1 with a different value to the instruction memory 600 based on each rising edge of the first frequency-divided clock signal CKD1.

[0150] The instruction memory 600 sequentially generates instruction codes RINST1 with different values ​​based on the address signal RMADD1. The instruction codes RINST1 with different values ​​can be generated at one cycle time interval of the clock signal CKH, relative to the input timing of the address signal RMADD1.

[0151] With respect to the input timing of the address signal RMADD1, instruction codes RINST1 with different values ​​are stored in the fetch register FTR at a time interval of one cycle of the first divided clock signal CKD1.

[0152] The instruction code RINST1, which extracts different values ​​stored in the FTR register, can be decoded by the decoder DEC.

[0153] The instruction code RINST1 with different values ​​is input to the fetch register FTR and simultaneously provided to the timing of the peripheral circuit PER1. The output of the decoder DEC is stored in the run register EXR at a time interval of one cycle of the first divided clock signal CKD1.

[0154] The operation of the peripheral circuit PER1 is controlled according to the output of the run register EXR, and the read operation of the first plane PL1 is executed accordingly.

[0155] Subsequently, when a read command for the third plane PL3 is input, the third activation signal ACT-PL3 can be activated, and the third divider clock signal CKD3 can be activated accordingly.

[0156] The microcontroller unit 300-3, which is connected to the third plane PL3, provides address signals RMADD3 with different values ​​to the instruction memory 600 based on each rising edge of the third frequency divider clock signal CKD3.

[0157] The instruction memory 600 sequentially generates instruction codes RINST3 with different values ​​based on the address signal RMADD3. The instruction codes RINST3 with different values ​​can be generated at one cycle time interval of the clock signal CKH, relative to the input timing of the address signal RMADD3.

[0158] Relative to the input timing of the address signal RMADD3, instruction codes RINST3 with different values ​​are stored in the fetch register FTR at a time interval of one cycle of the third frequency divider clock signal CKD3.

[0159] The instruction code RINST3, which extracts different values ​​stored in the FTR register, can be decoded by the decoder DEC.

[0160] The instruction code RINST3 with different values ​​is input to the fetch register FTR and simultaneously provided to the timing of the peripheral circuit PER3. The output of the decoder DEC is stored in the run register EXR at one cycle time interval of the third divided clock signal CKD3.

[0161] The operation of the peripheral circuit PER3 is controlled according to the output of the run register EXR, and the read operation of the third plane PL3 is executed accordingly.

[0162] When a read command for the second plane PL2 is input, the second activation signal ACT-PL2 can be activated, and the second frequency divider clock signal CKD2 can be activated accordingly.

[0163] The microcontroller unit 300-2, which is connected to the second plane PL2, provides address signals RMADD2 with different values ​​to the instruction memory 600 based on each rising edge of the second frequency-divided clock signal CKD2.

[0164] The instruction memory 600 sequentially generates instruction codes RINST2 with different values ​​based on the address signal RMADD2. The instruction codes RINST2 with different values ​​can be generated at one cycle time interval of the clock signal CKH, relative to the input timing of the address signal RMADD2.

[0165] With respect to the input timing of the address signal RMADD2, instruction codes RINST2 with different values ​​are stored in the fetch register FTR at a time interval of one cycle of the second divided clock signal CKD2.

[0166] The instruction code RINST2, which extracts different values ​​stored in the FTR register, can be decoded by the decoder DEC.

[0167] The instruction code RINST2 with different values ​​is input to the fetch register FTR and simultaneously provided to the timing of the peripheral circuit PER2. The output of the decoder DEC is stored in the run register EXR at one cycle time interval of the second divided clock signal CKD2.

[0168] Based on the output of the run register EXR, the operation of the peripheral circuit PER2 is controlled, and the read operation of the second plane PL2 is executed accordingly, thereby completing the interleaved plane read operation.

[0169] The embodiments of the present disclosure described above allow multiple microcontrollers MCU1 to MCUn connected to each of the multiple planes PL1 to PLn to share a single instruction memory 600. Compared to using multiple instruction memories, this reduces circuit area, simplifies signal routing for easier circuit design, and increases layout margin.

[0170] Because multiple microcontrollers MCU1 to MCUn are based on clock signals with different phases (CKD) <n:1>One of them operates, so multiple microcontrollers MCU1 to MCUn can freely access instruction memory 600 to perform planar interleaved read operations without overlapping with the timing of accessing instruction memory 600.

[0171] Furthermore, since the timing of multiple microcontrollers MCU1 to MCUn accessing the instruction memory 600 does not overlap, the peak current of each plane does not overlap, which reduces current consumption and increases the reliability of read operations.

[0172] The concepts have been disclosed in conjunction with examples and embodiments of this disclosure. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions are possible without departing from the scope and concept of this disclosure. The embodiments disclosed in this disclosure should be considered from an illustrative rather than restrictive perspective. Therefore, the scope of this disclosure is not limited to the provided implementations. All variations within the meaning and scope of the equivalents of the claims are included within the scope of the claims. Furthermore, these embodiments can be combined to form other embodiments. < / n:1> < / n:1> < / n:1> < / n:1>

Claims

1. A memory device, comprising: The instruction memory outputs multiple instruction codes at predetermined time intervals based on multiple address signals and multiple divided clock signals; as well as Multiple microcontrollers are connected to each of multiple memory regions, provide each of the multiple address signals to the instruction memory according to each of the multiple divided clock signals, and perform operations according to the corresponding instruction code among the multiple instruction codes.

2. The memory device according to claim 1, further comprising a frequency divider circuit, the frequency divider circuit dividing the clock signal to generate the plurality of frequency-divided clock signals.

3. The memory device according to claim 2, wherein, The frequency divider circuit generates multiple frequency-divided clock signals with a predetermined phase difference when the planar interleaved readout mode setting signal is activated, and generates multiple frequency-divided clock signals with the same phase when the planar interleaved readout mode setting signal is deactivated.

4. The memory device according to claim 2, wherein, The frequency divider circuit includes: A multiphase signal generator receives the clock signal and outputs a multiphase signal; A prescaler clock generator receives the multiphase signal and the clock signal to output multiple prescaler clock signals; The activation control circuit, in response to a reset signal and a plurality of activation signals corresponding to each of the plurality of memory regions, selectively activates the prescaler clock generator; and Multiple multiplexers selectively output the multiple pre-divided clock signals as the multiple divided clock signals according to the planar interleaved read mode setting signal.

5. The memory device of claim 2, further comprising an oscillator that generates a clock signal having a frequency corresponding to the number of the plurality of microcontrollers.

6. The memory device according to claim 1, wherein, The instruction memory includes: The memory core, when the word line enable signal is activated, outputs the instruction data corresponding to the integrated address signal from the stored instruction data; The output control circuit receives multiple preliminary word line control signals and the multiple address signals to output the integrated address signal and the word line enable signal; The command output circuit receives multiple load control signals and the instruction data to output the multiple instruction codes; and The control signal generation circuit receives the plurality of frequency-divided clock signals and the plane interleaved readout mode setting signal to output the plurality of preliminary word line control signals and the plurality of load control signals.

7. The memory device according to claim 6, wherein, The memory core includes: A memory cell array, comprising memory cells connected to multiple word lines and multiple bit lines; The address decoder outputs the result of decoding the integrated address signal; A word line driver that, when the word line enable signal is activated, activates the word line among the plurality of word lines that corresponds to the output of the address decoder; Bit line drivers are connected between the plurality of bit lines and the global line, and transmit the signals of the bit lines corresponding to the output of the address decoder to the global line; and The sensing amplifier array amplifies the result of comparing the signal transmitted to the global line with the reference signal, and outputs the amplified result as the command data.

8. The memory device according to claim 6, wherein, The output control circuit includes: Multiple buffer arrays, when one of the multiple preliminary word line control signals is activated, output the corresponding address signal from the multiple address signals as the integrated address signal; and At least one logic gate activates the word line enable signal when any one of the plurality of preliminary word line control signals is activated.

9. The memory device according to claim 6, wherein, The command output circuit includes: Multiple buffer arrays, when one of the multiple load control signals is activated, invert and output the instruction data; and Multiple latch arrays latch the outputs of the multiple buffer arrays to output the outputs as the multiple instruction codes.

10. The memory device according to claim 6, wherein, The control signal generation circuit includes: A control clock generation circuit receives the plurality of frequency-divided clock signals and the plane interleaved readout mode setting signal to output a plurality of control clock signals; and Multiple control signal generation logic generates the multiple preliminary word line control signals and the multiple load control signals by combining the delay signals of each of the multiple control clock signals.

11. The memory device according to claim 10, wherein, When the planar interleaved readout mode setting signal is disabled, the control clock generation circuit outputs the first frequency-divided clock signal among the plurality of frequency-divided clock signals as the first control clock signal among the plurality of control clock signals, and fixes the remaining control clock signals other than the first control clock signal to a low level.

12. A memory device, comprising: Multiple planes; Input / output pad circuitry, including multiple pads; The data input / output circuit is connected to the input / output pad circuit. The instruction memory outputs multiple instruction codes at predetermined time intervals based on multiple address signals and multiple divided clock signals; as well as Multiple memory operation control-related circuits are connected together to the data input / output circuit, and one-to-one with the multiple planes. They provide each of the multiple address signals to the instruction memory according to each of the multiple frequency division clock signals, and execute operations according to the corresponding instruction code among the multiple instruction codes.

13. The memory device according to claim 12, wherein, The instruction memory includes: The memory core, when the word line enable signal is activated, outputs the instruction data corresponding to the integrated address signal from the stored instruction data; The output control circuit receives multiple preliminary word line control signals and the multiple address signals to output the integrated address signal and the word line enable signal; The command output circuit receives multiple load control signals and the instruction data to output the multiple instruction codes; and The control signal generation circuit receives the plurality of frequency-divided clock signals and the plane interleaved readout mode setting signal to output the plurality of preliminary word line control signals and the plurality of load control signals.

14. The memory device according to claim 12, wherein, The memory core includes: A memory cell array, comprising memory cells connected to multiple word lines and multiple bit lines; The address decoder outputs the result of decoding the integrated address signal; A word line driver that, when the word line enable signal is activated, activates the word line among the plurality of word lines that corresponds to the output of the address decoder; Bit line drivers are connected between the plurality of bit lines and the global line, and transmit the signals of the bit lines corresponding to the output of the address decoder to the global line; and The sensing amplifier array amplifies the result of comparing the signal transmitted to the global line with the reference signal, and outputs the amplified result as the command data.

15. The memory device according to claim 13, wherein, The output control circuit includes: Multiple buffer arrays, when one of the multiple preliminary word line control signals is activated, output the corresponding address signal from the multiple address signals as the integrated address signal; and At least one logic gate activates the word line enable signal when any one of the plurality of preliminary word line control signals is activated.

16. The memory device according to claim 13, wherein, The command output circuit includes: Multiple buffer arrays, which invert and output the instruction data when one of the multiple load control signals is activated; and Multiple latch arrays latch the outputs of the multiple buffer arrays to output the outputs as the multiple instruction codes.

17. The memory device according to claim 13, wherein, The control signal generation circuit includes: A control clock generation circuit receives the plurality of frequency-divided clock signals and the plane interleaved readout mode setting signal to output a plurality of control clock signals; and Multiple control signal generation logic generates the multiple preliminary word line control signals and the multiple load control signals by combining the delay signals of each of the multiple control clock signals.

18. The memory device of claim 17, wherein, When the planar interleaved readout mode setting signal is disabled, the control clock generation circuit outputs the first frequency-divided clock signal among the plurality of frequency-divided clock signals as the first control clock signal among the plurality of control clock signals, and fixes the remaining control clock signals other than the first control clock signal to a low level.

19. The memory device according to claim 12, wherein, The multiple memory operation control circuits control the programming and reading operations of the multiple planes.

20. The memory device according to claim 12, wherein, Each of the plurality of memory operation control-related circuits includes: Peripheral circuitry controls the programming and reading operations of corresponding planes among the plurality of planes; and The microcontroller provides each of the plurality of address signals to the instruction memory according to each of the plurality of divided clock signals, and controls the operation of the peripheral circuits according to the result of decoding the instruction code corresponding to the peripheral circuits.

21. The memory device of claim 12, further comprising a frequency divider circuit that divides the clock signal to generate the plurality of frequency-divided clock signals.

22. The memory device of claim 21, wherein, The frequency divider circuit generates multiple frequency-divided clock signals with a predetermined phase difference when the planar interleaved readout mode setting signal is activated, and generates multiple frequency-divided clock signals with the same phase when the planar interleaved readout mode setting signal is deactivated.

23. The memory device according to claim 21, wherein, The frequency divider circuit includes: A multiphase signal generator receives the clock signal and outputs a multiphase signal; A prescaler clock generator receives the multiphase signal and the clock signal to output multiple prescaler clock signals; The activation control circuit, in response to a reset signal and a plurality of activation signals corresponding to each of the plurality of memory regions, selectively activates the prescaler clock generator; and Multiple multiplexers selectively output the multiple pre-division clock signals as the multiple divided clock signals according to the planar interleaved read mode setting signal.

24. The memory device of claim 21, further comprising an oscillator that generates a clock signal having a frequency corresponding to the number of the plurality of memory operation control associated circuits.

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