Coprocessor and operating system for implementing elliptic curve cryptography

Abstract

A kind of coprocessor and operation system for implementing elliptic curve cryptography algorithm, the coprocessor includes instruction memory and multiple microcode type coprocessor cores, instruction memory is used to store instruction flow written according to preset instruction set, and the instruction set is the set of instructions that microcode type coprocessor core can identify and execute;Multiple microcode type coprocessor cores are used to obtain instruction flow, and the mathematical operation required by elliptic curve cryptography algorithm is executed in parallel according to the instruction in instruction flow.This application can be written according to the algorithm needs instruction flow, improve the algorithm flexibility;Multiple microcode type coprocessor cores parallel operation, improve the algorithm performance.

Description

Technical Field

[0001] This application relates to the field of digital logic circuit technology, and more specifically, to a coprocessor and computing system for implementing elliptic curve cryptography algorithms. Background Technology

[0002] Elliptic Curve Cryptography (ECC) is a public-key cryptography technique based on elliptic curve theory. It leverages the difficulty of solving discrete logarithms using the Abelian Group formed by points on an elliptic curve over a finite field, enabling encryption, decryption, and digital signatures. By correlating the addition operation in elliptic curves with the modular multiplication operation in discrete logarithms, a corresponding cryptosystem based on elliptic curves can be established.

[0003] The ECC algorithm has the following characteristics: (1) High security strength: The security of the ECC algorithm is based on the difficulty of solving the elliptic curve discrete logarithm problem, which has a higher security strength than algorithms such as RSA; (2) Short key length: Under the same encryption strength, the key length of the ECC algorithm is shorter than that of algorithms such as RSA, which is beneficial to key management and storage; (3) Fast operation speed: The operation speed of the ECC algorithm is faster than that of algorithms such as RSA, which is beneficial to improving the speed of encryption and decryption. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the shortcomings of existing technologies, the first aspect of this application proposes a coprocessor for implementing elliptic curve cryptography algorithms. The coprocessor includes an instruction memory and multiple microcode-based coprocessor cores, wherein:

[0006] The instruction memory is used to store instruction flows written according to a preset instruction set, which is a set of instructions that the microcode coprocessor core can recognize and execute.

[0007] The multiple microcode-based coprocessor cores are used to acquire the instruction flow and to perform the mathematical operations required by the elliptic curve cryptography algorithm in parallel according to the instructions in the instruction flow.

[0008] In one embodiment, each of the plurality of microcode coprocessor cores includes a controller, a memory, and an arithmetic unit. The controller is used to retrieve the instruction flow from the instruction memory, control the arithmetic unit to perform mathematical operations required by the elliptic curve cryptography algorithm according to the instruction flow, access the memory, and return the operation results. The memory is used to store the operation data of the arithmetic unit.

[0009] In one embodiment, a plurality of the microcode coprocessors are used to start sequentially to perform the mathematical operations required by the elliptic curve cryptography algorithm in parallel, or a plurality of the microcode coprocessor cores are used to start randomly to perform the mathematical operations required by the elliptic curve cryptography algorithm in parallel.

[0010] In one embodiment, the plurality of microcode-based coprocessor cores are used to perform mathematical operations required by the elliptic curve cryptography algorithm in parallel according to the instructions in the instruction flow, including:

[0011] Multiple microcode-based coprocessor cores are used to execute mathematical operations corresponding to the same instruction flow in parallel, and / or,

[0012] One or more first microcode coprocessor cores among the plurality of microcode coprocessor cores are used to execute mathematical operations corresponding to the first instruction flow, while one or more second microcode coprocessor cores among the plurality of microcode coprocessor cores are used to execute mathematical operations corresponding to the second instruction flow.

[0013] In one embodiment, the instruction memory includes non-volatile memory and random access memory. The non-volatile memory is used to store the instruction flow and transfer the instruction flow to the random access memory. The controller of the microcode coprocessor core obtains the instruction flow from the random access memory.

[0014] In one embodiment, the structure of the instructions in the instruction set includes an instruction code, a control word, a data source address, and a data destination address;

[0015] The instruction code indicates the function that the microcode-type coprocessor core needs to execute, the control word identifies the characteristics of instruction execution, and the data source address and the data target address are instruction operands.

[0016] In one embodiment, the microcode-based coprocessor core is also used to provide feedback on the operating status to the central processing unit via interrupt instructions.

[0017] In one embodiment, the coprocessor further includes registers, the registers including at least one of a parameter register, a control register, and a status register, wherein:

[0018] The parameter register is used to store parameters of instructions mapped to the instruction set, and the microcode-based coprocessor core is used to execute operations corresponding to the instructions according to the parameters;

[0019] The control register is used to configure the execution start address, and the microcode-based coprocessor core is used to start computation execution from different locations in the instruction memory according to the execution start address;

[0020] The status register is used to provide the central processing unit with the operation execution status and operation results of the microcode-based coprocessor core.

[0021] Another embodiment of this application provides a computing system for implementing elliptic curve cryptography algorithms, including a central processing unit and a coprocessor as described above. The central processing unit is used to issue a computing request for elliptic curve cryptography algorithms to the coprocessor. After receiving the computing request, the coprocessor performs the computing and feeds back the computing result to the central processing unit.

[0022] Another aspect of this application provides an intelligent connected vehicle, including the computing system described above for implementing elliptic curve cryptography algorithms.

[0023] This application proposes a coprocessor, computing system, and intelligent connected vehicle for implementing elliptic curve cryptography algorithms. It designs a microcode-based coprocessor core using reconfigurable algorithm technology, and the instruction flow stored in the instruction memory can be written according to the required high-level ECC algorithm, thus improving algorithm performance and solving the problem of algorithm flexibility. Furthermore, it employs multi-core architecture technology to achieve multi-core parallel computing, significantly improving algorithm performance and meeting the computational speed requirements of applications such as intelligent connected vehicles. Attached Figure Description

[0024] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain the application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0025] Figure 1 The implementation hierarchy of elliptic curve cryptography algorithms is shown;

[0026] Figure 2 This is a schematic block diagram of a coprocessor for implementing an elliptic curve cryptography algorithm according to an embodiment of this application;

[0027] Figure 3This is a schematic block diagram of a microcode-based coprocessor core according to an embodiment of this application;

[0028] Figure 4 This is a schematic diagram illustrating the correspondence between memory access logical addressing and physical addressing according to an embodiment of this application;

[0029] Figure 5 This is a schematic diagram of parallel operation of multiple microcode-based coprocessor cores according to an embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application more apparent, exemplary embodiments according to this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein. Based on the embodiments of this application described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of this application.

[0031] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0032] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] To fully understand this application, a detailed structure will be presented in the following description to illustrate the technical solution proposed in this application. Optional embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0035] like Figure 1 As shown, the implementation layers of the ECC algorithm include an elliptic curve algorithm implementation layer, an elliptic curve computation layer, and a support layer. The elliptic curve algorithm implementation layer implements high-level algorithms such as the Elliptic Curve Digital Signature Algorithm (ECDSA), encryption / decryption algorithms, and key exchange algorithms. The elliptic curve computation layer calculates kG fixed-point multiplication, kP variable-point multiplication, point addition, and point doubling. The support layer implements random number generation, hash algorithms, and large number operations, including modular multiplication, modular addition, modular subtraction, and modular inverse.

[0036] The core ECC algorithm (fixed-point multiplication, variable-point multiplication, etc.) consists of numerous large-number operations (modular multiplication, modular addition, modular subtraction, etc.). To meet the speed requirements, a coprocessor is needed to implement the ECC algorithm. A coprocessor assists the central processing unit (CPU) in completing specific processing tasks, especially those that the CPU cannot execute efficiently. By offloading the CPU's workload, the coprocessor improves the overall processing efficiency and performance of the system.

[0037] There are two ways to implement the ECC algorithm in a coprocessor: one is a fully hardware implementation where the entire algorithm flow is controlled by a hardware state machine, and the other is a combination of hardware and software.

[0038] In the all-hardware implementation, the entire process of the ECC algorithm is implemented in hardware. During the hardware design process, in addition to implementing the basic algorithm, mechanisms such as state machines are also used to implement higher-level algorithms. The all-hardware implementation has the following problems: (1) Poor flexibility: The algorithm function is fixed in the chip design process and cannot be adjusted or improved according to the needs during chip application; (2) Complex chip design and high cost: The algorithm process is implemented using mechanisms such as state machines. Hardware engineers not only need hardware design and implementation capabilities, but also algorithm implementation capabilities, which places high demands on the capabilities of hardware designers; In addition, the all-hardware implementation has the problem of high digital circuit manufacturing costs.

[0039] In the hardware-software hybrid implementation, the high-level algorithm flow of ECC is implemented in software. The hardware design implements the basic algorithms (modular multiplication, modular addition, modular subtraction, etc.). However, implementing the algorithm flow in software suffers from performance deficiencies and high power consumption. Although this approach offers high flexibility, the algorithm operation process requires the CPU to participate throughout, making parallel computing impossible. Furthermore, the limitations imposed by the relatively low operating frequency of the security chip platform result in poor overall algorithm performance, failing to meet the performance requirements of intelligent connected vehicle security chips.

[0040] To address the aforementioned issues, this application provides a coprocessor for implementing elliptic curve cryptography algorithms. It employs a reconfigurable algorithm technology to design a microcode-based coprocessor core, improving algorithm performance while resolving the flexibility problem. Furthermore, it utilizes a multi-core architecture to achieve parallel computation across multiple cores, significantly enhancing algorithm performance and meeting the computational speed requirements of intelligent connected vehicle security chips.

[0041] See Figure 2 This illustrates a coprocessor 200 for implementing elliptic curve cryptography algorithms according to an embodiment of this application. Figure 2 As shown, the coprocessor 200 for implementing elliptic curve cryptography in this embodiment includes multiple microcode coprocessor cores 210 and an instruction memory 220, wherein: the instruction memory 220 is used to store instruction flows written according to a preset instruction set, the instruction set being a set of instructions that the microcode coprocessor cores 210 can recognize and execute; the multiple microcode coprocessor cores 210 are used to retrieve instruction flows from the instruction memory 220, and to execute the mathematical operations required by the elliptic curve cryptography algorithm in parallel according to the instructions in the instruction flows.

[0042] like Figure 3 As shown, each microcode-based coprocessor core 210 includes a controller 2101, a memory 2102, and an arithmetic unit 2103. The controller 2101 is used to retrieve the instruction flow from the instruction memory 220, control the arithmetic unit 2103 to perform the mathematical operations required by the elliptic curve cryptography algorithm according to the instruction flow, access the memory 2102, and provide feedback on the operation results. The memory 2102 is used to store the operation data of the arithmetic unit 2103.

[0043] The microcode-based coprocessor core 210 is an algorithm coprocessor core capable of executing microcode, representing an algorithm reconfiguration technology. Microcode refers to the decomposition of complex machine instructions into a series of simple operations. Its function is to separate machine instructions from related circuit implementations, thereby making instruction design and modification more flexible while reducing circuit complexity. The microcode originates from the instruction set involved in the embodiments of this application. The instruction set is a collection of instructions that the microcode-based coprocessor core 210 can recognize and execute. The instruction flow written according to the instruction set can be recognized and executed by the microcode-based coprocessor core 210. For example, multiple instructions required to implement a certain elliptic curve cryptography algorithm can be sorted according to the order of operations to obtain the instruction flow. After chip production, the algorithm flow implemented by the coprocessor 200 can be adjusted at any time by changing the instruction flow, thereby greatly improving the algorithm flexibility.

[0044] Multiple microcode coprocessor cores 210 can perform operations in parallel. The ECC core algorithm consists of numerous large number operations, some of which exceed the representation range of basic numerical data types in computers. Designing multiple microcode coprocessor cores 210 can decompose large numbers and perform operations in parallel, thereby improving the computational speed.

[0045] The instruction set in this embodiment is a set of instructions that a pre-configured microcode-based coprocessor core 210 can recognize and execute to complete the algorithm flow. In one example, the structure of the instructions in the instruction set includes instruction code, control word, data source address, and data destination address; the instructions can be read and executed in 32-bit format, and their structure is described as follows:

[0046] BIT31-BIT24 BIT23-BIT16 BIT15-BIT8 BIT7-BIT0 Instruction code control word Data source address Data target address

[0047] The instruction code indicates the functions that the microcode-based coprocessor core 210 needs to execute. Instruction code categories may include jump instructions, memory access instructions, and large number mathematical and logical operation instructions.

[0048] Control words identify the characteristics of instruction execution, enabling different functions under the same instruction code. In the embodiments of this application, different control words are used to represent direct or indirect addressing of the data source and data target.

[0049] The data source address and data destination address are instruction operands. Embodiments of this application support addressing source and destination data using both immediate addressing and register value indirect addressing.

[0050] When implementing high-level ECC algorithms (such as ECDSA, SM2 signatures, etc.), it is necessary to write the instruction flow using the above instruction set according to the algorithm flow and store it in the instruction memory 220. Users can modify the instruction flow stored in the instruction memory 220 according to the algorithm requirements to improve the flexibility of the coprocessor.

[0051] For example, instruction memory 220 includes non-volatile memory (NVM) and random access memory (RAM).

[0052] The NVM stores the binary algorithm flow written according to the instruction set and algorithm; RAM is the source of instructions directly read by the coprocessor during runtime. The RAM is a multi-port RAM shared by multiple microcode-based coprocessor cores 210. Before the coprocessor 200 starts working, the instruction flow stored in the NVM is moved to RAM. When the coprocessor 200 starts working, it directly fetches and executes instructions from RAM. This solves the problem of the NVM's inability to read quickly, improving the instruction fetching and execution speed of the coprocessor 200.

[0053] The coprocessor 200 also includes a DMA module 230 for transferring instructions from the NVM to RAM. The DMA module, or Direct Memory Access (DMA) module, is used to copy data from one address space to another, providing high-speed data transfer between memories. Optionally, in addition to transferring instructions from the NVM instruction memory to the RAM instruction memory, the DMA module also provides coprocessor RAM-to-RAM data transfer functionality.

[0054] The instruction flow stored in instruction memory 220 can be executed by multiple microcode-based coprocessor cores 210. For example... Figure 3 As shown, each of the multiple microcode-based coprocessor cores 210 includes an independent controller 2101, a memory 2102, and an arithmetic logic unit (ALU) 2103. The controller 2101 retrieves the instruction flow written according to the instruction set from the instruction memory 220 and performs the corresponding flow control. The controller 2101 also implements the access function of the memory 2102 and provides a function to provide feedback on the calculation results. The memory 2102 is the data storage area for the current core's computation, used to store the calculation parameters, intermediate results, and calculation results of the ALU 2103. The ALU 2103 implements the mathematical operation functions required by the algorithm, including basic operations such as modular multiplication, modular addition, modular subtraction, and modular inversion.

[0055] For example, memory 2102 is a RAM memory, which includes a data storage area for storing computational data during the computation process. To reduce the complexity of data operations in the algorithm implementation, in this embodiment, controller 2101 accesses memory 2102 using a logical address mapping method. Specifically, the data storage area of ​​memory 2102 is logically addressed according to data blocks, that is, the storage space of memory 2102 is divided into logically addressed units of the same size, each such unit is called a block. This addressing method can ensure the uniform allocation and efficient utilization of storage space. During instruction execution, data operations are performed according to blocks, supporting reading source data according to blocks and writing destination data according to blocks. For example, each block occupies 8 words, and each word consists of several bytes. The coprocessor supports 4KB RAM access, and during memory access, logical addresses are used to implement data operations. The correspondence between memory access logical addressing and physical address is as follows: Figure 4 As shown.

[0056] Each microcode coprocessor core 210 provides a hardware-software interface through registers and interrupt instructions. Specifically, the microcode coprocessor core 210 can report its operating status to the central processing unit (CPU) via interrupt instructions. The CPU processes the operational feedback from each microcode coprocessor core 210 in its interrupt handler. The CPU can remain in sleep mode and be woken up in response to an interrupt instruction, eliminating the need for real-time register lookups and thus saving power.

[0057] The coprocessor also includes registers, including at least one of a parameter register, a control register, and a status register. The parameter register stores parameters for instructions mapped to the instruction set, and the microcode-based coprocessor core 210 executes the corresponding operation based on these parameters. The control register configures the start address (START BIT), and the microcode-based coprocessor core 210 initiates execution from different locations in the instruction memory based on the start address. The status register provides the CPU with the execution status and results of the microcode-based coprocessor core 210. Specifically, when the CPU receives an interrupt instruction, it can query the status register to obtain the execution status and results.

[0058] When the coprocessor 200 operates, it uses a parallel computing mode. Multiple microcode coprocessor cores 210 can be used to execute mathematical operations corresponding to the same instruction flow in parallel, thereby improving the computation speed of these mathematical operations. The multiple microcode coprocessor cores 210 can also be used to execute mathematical operations corresponding to different instruction flows in parallel. Specifically, one or more first microcode coprocessor cores among the multiple microcode coprocessor cores 210 are used to execute mathematical operations corresponding to the first instruction flow, while one or more second microcode coprocessor cores among the multiple microcode coprocessor cores 210 are used to execute mathematical operations corresponding to the second instruction flow. For example, while one or more first microcode coprocessor cores are performing signature operations, one or more second microcode coprocessor cores are performing signature verification operations, allowing the coprocessor to perform different functions simultaneously. Figure 5 As shown, the operation flow of coprocessor 200 is as follows: When coprocessor 200 receives a computation request, it selects an idle microcode coprocessor core 210 to perform the computation based on the operating status of each microcode coprocessor core 210; after the computation begins, coprocessor 200 can handle other computation requests. The number of microcode coprocessor cores 210 executing the computation can be determined based on the computational load.

[0059] For example, multiple microcode-based coprocessor cores 210 can be started sequentially to perform the mathematical operations required by the elliptic curve cryptography algorithm in parallel. For instance, upon receiving a computation request, it first checks if Core1 is idle; if Core1 is idle, then Core1 performs the computation. It then checks if Core2 is idle; if Core2 is idle, then Core2 and Core1 perform the computation in parallel. It then checks if Core3 is idle, and so on. Alternatively, the multiple microcode-based coprocessor cores 210 can be randomly started to perform the mathematical operations required by the elliptic curve cryptography algorithm in parallel, thereby avoiding frequent startup of the microcode-based coprocessor cores 210 that could affect their startup lifespan. Multiple idle microcode-based coprocessor cores 210 can factorize large numbers, with each microcode-based coprocessor core 210 performing computations on a portion of the data. The CPU then combines the computation results from the multiple microcode-based coprocessor cores 210 to obtain the final computation result. Parallel execution of computations by multiple microcode-based coprocessor cores 210 can significantly improve computation speed.

[0060] In summary, the coprocessor 200 for implementing elliptic curve cryptography algorithms according to the embodiments of this application has the advantages of high flexibility and excellent performance:

[0061] I. High flexibility:

[0062] This application employs reconfigurable algorithm technology to design a microcode-based coprocessor core, which implements the algorithm flow by executing the coprocessor instruction set, greatly improving flexibility. After chip production, the algorithm flow implemented by the coprocessor can be adjusted at any time by changing the instruction flow stored in the instruction memory. In the coprocessor's hardware-software interface, different microcode-based coprocessor cores can be configured with different execution start addresses to enable different cores to run different algorithm flows.

[0063] II. Excellent performance:

[0064] Compared to the hardware-software combined implementation of the algorithm, the coprocessor in this application embodiment has superior performance; the ECC algorithm process does not require CPU participation throughout, avoiding the impact of frequent CPU scheduling on performance; it is multi-core architecture friendly, and can easily implement a SOC architecture combining a single CPU and a multi-core coprocessor, improving computing power by multiple times.

[0065] This application also provides a computing system for implementing elliptic curve cryptography algorithms, including a coprocessor and a central processing unit (CPU) as described above. The CPU sends computing requests to the coprocessor, which performs the computing upon receiving the request and then returns the computing result to the CPU. By offloading the CPU's workload, the coprocessor improves the overall processing efficiency and effectiveness of the system.

[0066] This application also provides an intelligent connected vehicle, including the computing system described above for implementing the elliptic curve cryptography algorithm. Intelligent connected vehicles refer to the organic integration of vehicle-to-everything (V2X) networks and intelligent vehicles. They are equipped with advanced onboard sensors, controllers, actuators, and other devices, integrating modern communication and network technologies to achieve intelligent information exchange and sharing between vehicles, people, roads, and backend systems. They are characterized by safety, comfort, energy efficiency, and high efficiency.

[0067] In intelligent connected vehicles, the ECC algorithm is mainly used for secure communication, digital signatures, and authentication. ECC's security is based on the difficulty of the elliptic curve discrete logarithm problem, allowing for shorter keys to be used at the same security level, thus reducing computational and storage requirements. The application of the ECC algorithm in the vehicle field ensures communication security, data integrity, and user authentication, thereby improving the overall security of intelligent connected vehicles.

[0068] In the application scenarios of intelligent connected vehicles, there are performance requirements for the ECC algorithm of security chips in terms of the number of signatures and verifications. The intelligent connected vehicle embodiment of this application uses a reconfigurable algorithm microcode coprocessor with a multi-core architecture, which has the advantages of high flexibility and excellent performance, and can meet the algorithm performance requirements of intelligent connected vehicle security chips.

[0069] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0070] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0071] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0072] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0073] Similarly, it should be understood that, for the purpose of simplification and aiding understanding of one or more aspects of the application, features of the application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of the application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, the point of application is that the corresponding technical problem can be solved with fewer features than all of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the application.

[0074] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0075] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0076] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some modules according to the embodiments of this application. This application can also be implemented as an apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0077] It should be noted that the above embodiments are illustrative of this application and not limiting of it, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0078] The above description is merely a specific embodiment or illustration of the embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.

Claims

1. A coprocessor for implementing elliptic curve cryptography algorithms, characterized in that, The coprocessor includes an instruction memory and multiple microcode-based coprocessor cores, wherein: The instruction memory is used to store instruction flows written according to a preset instruction set, which is a set of instructions that the microcode coprocessor core can recognize and execute. The multiple microcode-based coprocessor cores are used to acquire the instruction flow and to perform the mathematical operations required by the elliptic curve cryptography algorithm in parallel according to the instructions in the instruction flow.

2. The coprocessor according to claim 1, characterized in that, Each of the plurality of microcode coprocessor cores includes a controller, a memory, and an arithmetic unit. The controller is used to retrieve the instruction flow from the instruction memory, control the arithmetic unit to perform the mathematical operations required by the elliptic curve cryptography algorithm according to the instruction flow, access the memory, and return the operation results. The memory is used to store the computational data of the arithmetic unit.

3. The coprocessor according to claim 1, characterized in that, The plurality of said microcode coprocessors are used to start sequentially to execute the mathematical operations required by the elliptic curve cryptography algorithm in parallel, or the plurality of said microcode coprocessor cores are used to start randomly to execute the mathematical operations required by the elliptic curve cryptography algorithm in parallel.

4. The coprocessor according to claim 1, characterized in that, The multiple microcode-based coprocessor cores are used to perform the mathematical operations required by the elliptic curve cryptography algorithm in parallel according to the instructions in the instruction flow, including: Multiple microcode-based coprocessor cores are used to execute mathematical operations corresponding to the same instruction flow in parallel, and / or, One or more first microcode coprocessor cores among the plurality of microcode coprocessor cores are used to execute mathematical operations corresponding to the first instruction flow, while one or more second microcode coprocessor cores among the plurality of microcode coprocessor cores are used to execute mathematical operations corresponding to the second instruction flow.

5. The coprocessor according to claim 1, characterized in that, The instruction memory includes non-volatile memory and random access memory. The non-volatile memory is used to store the instruction flow and transfer the instruction flow to the random access memory. The controller of the microcode coprocessor core obtains the instruction flow from the random access memory.

6. The coprocessor according to claim 1, characterized in that, The structure of the instructions in the instruction set includes instruction code, control word, data source address, and data destination address; The instruction code indicates the function that the microcode-type coprocessor core needs to execute, the control word identifies the characteristics of instruction execution, and the data source address and the data target address are instruction operands.

7. The coprocessor according to claim 1, characterized in that, The microcode-based coprocessor core is also used to provide feedback on the operating status to the central processing unit via interrupt instructions.

8. The coprocessor according to claim 1, characterized in that, The coprocessor further includes registers, which include at least one of a parameter register, a control register, and a status register, wherein: The parameter register is used to store parameters of instructions mapped to the instruction set, and the microcode-based coprocessor core is used to execute operations corresponding to the instructions according to the parameters; The control register is used to configure the execution start address, and the microcode-based coprocessor core is used to start computation execution from different locations in the instruction memory according to the execution start address; The status register is used to provide the central processing unit with the operation execution status and operation results of the microcode-based coprocessor core.

9. A computational system for implementing elliptic curve cryptography algorithms, characterized in that, The system includes a central processing unit and a coprocessor as described in any one of claims 1-8. The central processing unit is configured to issue a computation request for an elliptic curve cryptography algorithm to the coprocessor. Upon receiving the computation request, the coprocessor performs the computation and feeds back the computation result to the central processing unit.

10. An intelligent connected vehicle, characterized in that, Includes the computing system for implementing elliptic curve cryptography algorithms as described in claim 9.

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