Processor architecture for processing multiple instructions in parallel

Abstract

This provides a processor and processor architecture adapted to parallelize multiple instructions moving between two poles (strict allocation used in SIMD / MIMD architectures) at a user-defined granularity, by making the wall between instruction slots and PEs fluid. [Solution] The processor includes an instruction memory, a decoder that converts instructions into opcodes and enable signals, a controller that provides instructions to the decoder, and a plurality of processing elements that operate according to the operation codes provided to the input of a target processing element during a time slot to apply mathematical operations to input data elements and generate output data elements. The enable signals control the assignment of opcodes to the processing elements. The interconnection circuit is adapted to provide one of the opcodes to any of the processing elements in each time slot and operates according to the enable signals.

Description

Technical Field

[0001] Various exemplary embodiments generally relate to processors and processor architectures adapted to process multiple instructions in parallel.

Background Art

[0002] Various types of processor architectures may be used, including SIMD (Single Instruction Multiple Data), SISD (Single Instruction Single Data), MIMD (Multiple Instruction Multiple Data), and MISD (Multiple Instruction Single Data). Each of these types of processor architectures includes a processing element, and instructions may be assigned to the processing element according to a given set of rules.

[0003] In SISD, a scalar processing element operates on data elements in each time slot according to an instruction from a given instruction slot, whereby the scalar processing element is configured to process a single data element stream over time according to a single instruction stream.

[0004] In SIMD, a vector processing element operates on multiple data elements in each time slot according to an instruction from a given instruction slot, whereby the vector processing element is configured to process multiple data element streams over time according to a single instruction stream.

[0005] In MISD, compared to SISD, multiple instruction slots operate in parallel to provide multiple instructions in each time slot, and each scalar processing element is assigned to a given instruction slot, whereby the processor can process multiple instruction streams in parallel, and each scalar processing element is configured to process one single instruction stream from a given instruction slot.

[0006] In MIMD, compared to SIMD, multiple instruction slots operate in parallel, providing multiple instructions in each time slot, and each vector processing element is assigned to a given instruction slot, thereby allowing the processor to process multiple instruction streams in parallel, with each vector processing element configured to process one single instruction stream from a given instruction slot.

[0007] While MIMD architectures can be very powerful and efficient for some use cases, in many other use cases they result in dark silicon, meaning that some processing elements remain unused when instructions assigned to them are not available. For example, in matrix operations, the proportion of dark silicon can exceed 90% of the total number of processing elements in a MIMD architecture. This makes the processor inefficient and therefore too costly compared to its use.

[0008] Processor designs can be optimized for target use cases, for example, by incorporating thousands of multipliers and multiple instruction slots within the processor design. However, efficiently designing and dimending a processor for all target use cases can be challenging. Covering different use cases with different dimensions increases the area of ​​dark silicon and the amount of time spent in the dark. [Overview of the project]

[0009] The scope of protection is presented by the appended claims. Any embodiments, examples, and features described herein that do not fall within the scope of protection of the independent claims should be construed as useful examples for understanding the various embodiments or examples that do fall within the scope of protection.

[0010] According to the first aspect, the processor includes: a program memory for storing instructions; a decoder adapted to translate instructions into their respective operation codes and enable signals; a controller including an instruction word consisting of a plurality of instruction slots for providing instructions to the decoder; a plurality of processing elements, each configured to operate in accordance with an operation code provided to the input of a target processing element during a time slot to apply mathematical operations to input data elements and generate output data elements, wherein the instructions provided via the instruction slots identify one or more target processing elements to be used to execute the instruction, and the enable signals are adapted to control the assignment of operation codes to processing elements; and interconnection circuitry adapted to provide one of the operation codes to any of the processing elements in each time slot and configured to operate in accordance with the enable signals.

[0011] The processor may operate according to a very long instruction word operation mode. The instruction word may be a very long instruction word.

[0012] The interconnection circuit can be adapted to provide a given operation code to any number of processing elements in each time slot.

[0013] The processor may include a stitching control circuit and at least one hardware stitch, each of which is configured to connect or disconnect at least two processing elements, and the stitching control circuit is adapted to open or close at least one stitch according to a stitching signal generated from instructions distributed to at least two processing elements.

[0014] The interconnection circuit may include a multiplexer adapted to provide operation codes to processing elements according to an enable signal.

[0015] Multiple processing elements may be scalar processing elements.

[0016] Multiple processing elements may include one or more scalar processing elements.

[0017] Multiple processing elements may include one or more vector processing elements. These vector processing elements may have different lengths.

[0018] In one or more embodiments, at least one first processing element among the plurality of processing elements may support at least one first type of mathematical operation, and at least one second processing element among the processing elements may support at least one second type of mathematical operation, wherein the first type of mathematical operation is separate from the second type of mathematical operation.

[0019] In one or more embodiments, at least one third processing element among the plurality of processing elements supports at least one first data type, and at least one fourth processing element among the processing elements supports at least one second data type, wherein the first data type is distinct from the second data type.

[0020] According to a second aspect, the compiler is configured to compile program code to generate instructions to be processed by the processor described in any of the prior claims, the compiler is configured to distribute the instructions to the respective processing elements and instruction slots of the processor, each instruction specifying one or more target processing elements to be used to execute the instruction in question, and the compiler is adapted to distribute any of the instructions to any of the processing elements in each time slot.

[0021] The compiler can be adapted to distribute any of the instructions to any number of processing elements in each time slot.

[0022] The compiler can be configured to ensure that a processing element is not assigned to two or more instructions within the same time slot by checking for possible conflicts with other instructions assigned to the same processing element within the same time slot.

[0023] Exemplary embodiments will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only and thus are not limitations of the present disclosure.

Brief Description of the Drawings

[0024] [Figure 1] A diagram showing the architecture of a processor according to an example. [Figure 2] A diagram showing an interconnect circuit adapted for a processor according to an example. [Figure 3] A diagram showing the assignment of instructions to processing elements according to exemplary use case #1. [Figure 4] A diagram showing the assignment of instructions to processing elements according to exemplary use case #2. [Figure 5] A diagram showing the assignment of instructions to processing elements according to exemplary use case #3. [Figure 6] A diagram showing the assignment of instructions to processing elements according to exemplary use case #4. [Figure 7] A diagram showing the assignment of instructions to processing elements according to exemplary use case #5. [Figure 8] A diagram showing the assignment of instructions to processing elements according to exemplary use case #6.

Modes for Carrying Out the Invention

[0025] It should be noted that these drawings are intended to illustrate various aspects of the devices, methods, and structures used in the exemplary embodiments described herein. Similar or identical reference numerals in the various drawings are intended to indicate the presence of similar or identical elements or features.

[0026] Detailed exemplary embodiments are disclosed herein. However, certain structural and / or functional details disclosed herein are provided solely for the purpose of illustrating exemplary embodiments and providing a clear understanding of the underlying principles. However, these exemplary embodiments may be carried out without these specific details. These exemplary embodiments may be embodied in many alternative forms with various modifications and should not be construed as being limited only to the embodiments described herein. In addition, the figures and descriptions may have been simplified to illustrate elements and / or aspects relevant to a clear understanding of the invention, while excluding many other elements that may be well known in the art or are not relevant to understanding the invention for the sake of clarity.

[0027] The principle of one embodiment of the processor architecture is schematically shown in Figure 1. This architecture can be used in various types of computers.

[0028] The processor 1000 includes multiple processing elements (PEs) #0 to #15. These multiple PEs #0 to #15 may correspond to vector lanes 100.

[0029] The processor 1000 further includes a program memory 120 configured to store instructions executed by a plurality of PE#0 to #15.

[0030] Each of PE#0 through #15 is configured to operate according to the operation code (or opcode) provided to the target PE, applying mathematical operations to input data elements from the input data stream and generating output data elements from the output data stream during a time slot. The time slot may correspond, for example, to a clock cycle of the processor clock.

[0031] The addresses of input and output data may be defined in registers, for example, in a register file.

[0032] The mathematical operations performed by PE#0~#15 may be any type of basic operation, such as multiplication, addition, division, trigonometric functions, shifts, logical operations (e.g., XOR, AND, OR, NOR, etc.), or combinations thereof.

[0033] Each of PE#0 to #15 may be configured (and optimized) to apply one or more of the mathematical operations of the types described above. PEs may be configured to operate on one or more specific data types, such as integer values ​​of various lengths, floating-point values ​​of various lengths, and binary values. PEs may be configured (optimized) to operate only on specific data types.

[0034] In computation, an opcode (short for operation code, also called instruction machine code or instruction code) is part of a machine language instruction that specifies the operation to be performed.

[0035] The processor may include a decoder 140 and a controller 130. The controller 130 includes a plurality of instruction slots 131 to 134 for providing the decoder 140 with their respective instructions in each time slot.

[0036] A fetch unit (e.g., a program counter) 135 within the controller may be configured to fetch instructions from the program memory 120 and provide them to the decoder 140 through a set of instruction slots 131-134.

[0037] Instruction slots 131-134 enable parallel processing of instructions provided by these instruction slots. Each of instruction slots 131-134 may be configured to provide its own instruction to decoder 140. One instruction is provided per instruction slot, per time slot (i.e., per clock cycle). The set of instruction slots 131-134 may form an instruction word (e.g., a very long instruction word, VLIW).

[0038] In the simplified diagram of Figure 1, a pool of 16 PEs and 4 instruction slots is shown, but the principles disclosed herein are applicable to any number of PEs and any number of instruction slots.

[0039] The decoder 140 is configured to translate the fetched instructions into their respective operation codes and enable signals, the enable signals being configured to control the assignment of the operation codes to the PE.

[0040] The decoder 140 may be adapted to convert instructions into their respective operation codes OP1, OP2, OP3, OP4 and enable signals EN1, EN2, EN3, EN4. Each instruction provided by instruction slots 131-134 may be converted into one operation code and one or more enable signals. In embodiments, each instruction provided by instruction slots 131-134 may be converted into one or more operation codes and one or more enable signals.

[0041] Within each time slot, each of PE#0 to PE#15 can be flexibly allocated to one of instruction slots 131 to 134 so as to receive the corresponding operation code decoded from the corresponding instruction. Thus, PE#0 to PE#15 are completely isolated from instruction slots 131 to 134. There is no fixed allocation of PE#0 to PE#15 to different instruction slots 131 to 134, as in a typical MIMD processor.

[0042] As a result of this flexible allocation, a single PE may be allocated to only one single instruction slot #1 at any given point in time, but over time it may be allocated to either the same instruction slot as instruction slot #1 or a different instruction slot. For example, the exact same PE may be used by an instruction in instruction slot #1 at time slot t1, but that exact same PE may be used by an instruction in instruction slot #2 at time slot t2.

[0043] Furthermore, a given instruction slot can be allocated to any PE and any number of PEs.

[0044] Each of these flexibly scalable PEs is referred to herein as "Atomic PE" or "VALUTA," which stands for "Vector Arithmetlic Logic Unit Transaction Atomic." A VALUTA corresponds to the smallest level or granularity at which a PE is available and the processor can be programmed. The proposed architecture is called the VALUTA architecture.

[0045] To handle the distribution in a flexible manner, an interconnection circuit 150 is provided between the decoder and multiple PEs. Operation codes and enable signals decoded from a given instruction fetched via instruction slots 131-134 are provided to the interconnection circuit 150 by the decoder (for example, by each decoder slot 141-144).

[0046] The interconnect circuit 150 is adapted to provide one of the operation codes OP1, OP2, OP3, or OP4, converted from the instruction from the instruction slot, to one of PE#0 to #15 in each time slot. The interconnect circuit 150 is configured to operate according to the enable signals EN1, EN2, EN3, or EN4 generated by the decoder 140.

[0047] The enable signal may be, for example, a binary signal that controls the operation of the interconnection circuit 150. The enable signal may also be a signal that controls one or more target PEs.

[0048] As shown in Figure 2, the interconnection circuit 150 may include, for example, a multiplexer adapted to provide operation codes OP1, OP2, OP3, and OP4 to the PEs according to enable signals EN1, EN2, EN3, and EN4. Any other type of circuit adapted to receive multiple operation codes and multiple enable signals and to control the supply of operation codes to multiple PEs according to the enable signals may be used.

[0049] As shown in Figure 2, the interconnection circuit 150 may include, for each of PE#0 to #15, respective operation selection circuits OpSel0 to OpSel15, each operation selection circuit being adapted to select an operation code assigned to the associated PE and provide the selected operation code to the associated PE based on one or more enable signals EN1, EN2, EN3, and EN4.

[0050] This processor architecture can handle a variety of use cases in a more efficient way by using a pool of PEs (Primary Energy) while reducing dark silicon.

[0051] Each PE may be a scalar PE or a vector PE. Any combination of scalar and vector PEs can be used as needed. This provides additional design possibilities and flexible assignment capabilities to suit various use cases.

[0052] Similarly, the vector PEs, if any, may be of the same length, or they may have different lengths to accommodate different numbers of scalar data input streams. This provides additional design possibilities and flexible allocation options to suit various use cases.

[0053] The processor may include combinations of different types of scalar PEs. For example, one or more PEs may support a first type of mathematical operation, and one or more PEs may support a second type of mathematical operation, where the first type of mathematical operation is distinct from the second type. For example, one or more PEs may support a first data type, and one or more PEs may support at least one second data type, where the first data type is distinct from the second data type.

[0054] By separating this PE from the instruction slot, it becomes possible to aggregate atomic PEs in a completely flexible manner. The aggregated atomic PE may be a scalar PE, a vector PE, or any combination of a scalar PE and a vector PE. By aggregating scalar PEs, a vector PE or a matrix PE can be created as needed. This aggregation corresponds to the stitching of the input data elements of the PE at the software or logical level and can be controlled by the allocation of instruction slots (or equivalently, instructions) to the PE.

[0055] The stitching at the software level may, for example, be an aggregation of the output data elements produced by each scalar PE into a vector or matrix.

[0056] For example, several scalar PEs may be aggregated so that they are controlled by the same instruction from a given instruction slot in the same time slot, thereby causing the aggregated scalar PEs to behave effectively as a SIMD architecture. In another extreme example, each scalar PE may be controlled by its own instruction from an instruction slot, thereby causing several scalar PEs to be aggregated so that they are controlled by the same instruction from an instruction slot, resulting in the scalar PEs being controlled by instructions from their respective parallel instruction slots and behaving effectively like MISD or MIMD.

[0057] In embodiments, there may be one or more hardware stitches (e.g., hardware stitches including hardware wiring or connections) used to stitch the PE at the hardware level, each stitch being configured to connect or disconnect two PEs to perform hardware stitching on the connected PEs. Each hardware stitch is configured to be opened or closed under the control of a stitch control circuit. In embodiments, the stitch control circuit may be part of the interconnection circuit 150 or may be a separate circuit. The stitch control circuit may be configured to control opening or closing the hardware stitches according to stitch signals. Stitch signals for stitching the PE may be generated by the stitch control circuit according to corresponding instructions provided to the target PE.

[0058] Stitching (whether at the software or hardware level) may be performed before or after the execution of calculations by the PE, and the stitching may be applied to either the input data elements of the PE or the output data elements of the PE. Stitching on input data elements may be used in combination with stitching on output data elements.

[0059] The stitching function performed by stitching (whether at the software or hardware level) can be identified by the instructions assigned to the target PE. For example, the instructions may include information (e.g., instruction bits) that identifies the type of stitching function to be performed (e.g., Hadamard product, dot product, etc.). This information can be used to generate the stitching signal, if any, used to control hardware stitching.

[0060] Software-level stitching and hardware-level stitching may be used in combination.

[0061] This, in contrast to the rigid allocation used in typical SIMD / MIMD architectures, makes the wall between instruction slots and PEs fluid, resulting in increased flexibility—that is, the ability to move between the two poles at a user-defined granularity.

[0062] Programmers may learn about the potential of proposed architectures in order to take full advantage of new possibilities. This is no different from programming a GPU, DSP, or CPU using vector units.

[0063] The proposed allocation mechanism may run within a single hardware thread, enabling more efficient use of one or more sets of PEs within a single thread. The proposed allocation mechanism avoids the complex logic and architecture associated with multiple hardware threads, reducing silicon overhead and providing increased flexibility without loss of multithreaded performance. This avoids the additional programming complexity of multithreaded solutions. The proposed architecture enables efficient use of wide vector widths (e.g., SIMD vector lanes in VLIW processors).

[0064] Parallelization and / or hardware multithreading may be added on top of the proposed allocation mechanism by providing several sets of PEs, each controlled in parallel according to the principles disclosed herein. In such a case, the sets of PEs may be controlled by each set of instruction slots.

[0065] A flexible allocation mechanism is illustrated by the use cases in Figures 3 to 7.

[0066] In these examples, each instruction is provided by its own instruction slot. Each instruction (or, equivalently, each instruction slot) is assigned to one or more PEs.

[0067] The specific instruction "nop," which instructs the PE to do nothing, can be used when there are no operations to be performed by the PE during a given instruction slot.

[0068] Figure 3 shows the assignment of an instruction to a PE in a given time slot, according to exemplary use case #1. In this example, - Instruction #1 is assigned to PE #12~#15, - Instruction #2 is assigned to PE #8~#11, - Instruction #3 is assigned to PE #4~#7, - Instruction #4 is assigned to PE #0~#3.

[0069] Figure 4 shows the assignment of an instruction to the PE in a given time slot, according to exemplary use case #2. In this example, - Instruction #1 is assigned to PE #12~#14, - Instruction #2 is assigned to PE #8~#9, - Instruction #3 is assigned to PE #4~#5, - Instruction #4 is assigned to PE #0~#3, - No-operation instructions or "nop" instructions are assigned to PE#6, #7, #10, #11, and #15.

[0070] Use cases #1 and #2 are use cases that can be executed by a MIMD architecture of four instructions, each having four data streams, as indicated by the dashed rectangles.

[0071] Figure 5 shows the assignment of an instruction to a PE in a given time slot, according to exemplary use case #3. In this example, - Instruction #1 is assigned to PE #8, - Instruction #2 is not assigned to any of these PEs, - Instruction #3 is assigned to PE #0~#6, - Instruction #4 is assigned to PE #11~#15, - A no-operation instruction or "nop" instruction is assigned to the other PE#9, #10, and #7.

[0072] The program for use case #3 includes a first operation, e.g., a matrix operation, executed by seven PEs #0 to #6; a second operation, e.g., another matrix operation, executed by five PEs #11 to #15; and a third operation, e.g., a scalar operation, executed by a single PE #8. All of these operations can be mapped to parallel instruction slots by the compiler in this case. Other mappings of operations to PEs are also possible. In this use case, three PEs #9, #10, and #7 are not used / needed by the program and are idle, representing dark silicon when this use case is applied.

[0073] Figure 6 shows the assignment of an instruction to a PE in a given time slot, according to exemplary use case #4. In this example, - Instruction #2 is assigned to PE #0~#15, - Instructions #1, #3, or #4 are not assigned to any of the PEs.

[0074] In use case #4, the maximum number of PEs #0 through #15 are allocated to a single instruction. The instruction executed by the PE is instruction #2 from instruction slot #2. Other instruction slots may be inactive because there are no available PEs to execute them in a given clock cycle. There is no dark silicon in this use case.

[0075] Figure 7 shows the assignment of an instruction to a PE in a given time slot, according to exemplary use case #5. In this example, - Instruction #1 is assigned to PE #14, - Instruction #2 is assigned to PE #15, - Instruction #3 is assigned to PE #0~#13, - Instruction #4 is not assigned to any of these PEs.

[0076] Use case #5 demonstrates an example with two scalar operations and one vector operation. For the first scalar operation, PE #15 is mapped to instruction slot #2, which provides instruction #2. For the other scalar operation, PE #14 is mapped to instruction slot #1, which provides instruction #1. For the vector operation, PEs #0 through #13 are mapped to instruction slot #3, which provides instruction #3. There is no dark silicon in this use case.

[0077] Use cases #3, #4, and #5 cannot be executed on a single processor using MIMD, SIMD, SISD, or MISD architecture due to the "walls" maintained between or between groups of PEs in the strict assignment of instruction slots.

[0078] As shown in Figures 3 to 7, the proposed architecture enables decoupling between PEs and instruction slots. This decoupling allows for the flexible allocation of any PE and any number of aggregated PEs, which are then allocated to any of the instruction slots available by the compiler that generates the instructions.

[0079] These use cases demonstrate the proposed architecture's capacity for efficiently allocating PEs from the PE pool to either instruction slots or instructions.

[0080] Assuming the same number of PEs for each processor architecture, the proposed VALUTA architecture can handle a wider range of use cases in a more efficient way by reusing PEs and reducing dark silicon, compared to, for example, existing processors (e.g., MIMD processors). Designers are free to apply this benefit, for example, by choosing higher performance / throughput for a given problem at the same silicon and power cost, or by choosing the same performance / throughput for a given problem at a lower silicon and power cost.

[0081] In processors implementing the proposed VALUTA architecture, the total data path width, i.e., the number of data streams that can be handled by enabled PEs per instruction slot, may be wider, allowing PEs not used by some instructions to be used by others, thereby reducing dark silicon and increasing the use of excess data paths. This performance increase reduces the relative cost of other processor components such as decoders, controllers, program memory, and data memory, because these items do not need to scale with the performance improvement.

[0082] The allocation of PEs from this pool to instruction slots / instructions, combined with an efficient mapping by the compiler that orders / schedules the instructions executed by the PE pool, can be controlled by the programmer, much like a programmer writes program variables and determines their size.

[0083] At the programming level, the mode of operation can be as follows: When a programmer implements a use case, the necessary variables are declared in their appropriate types and allocated to available PEs. The programmer then continues writing a C / C++ program to implement the use case.

[0084] The compiler is configured to distribute instructions to the respective processing elements and instruction slots of the processor, with each instruction identifying one or more target processing elements to be used to execute the instruction, and the compiler is adapted to distribute any of the instructions to any of the processing elements in each time slot. The compiler may distribute any of the instructions to any number of processing elements in each time slot.

[0085] The compiler allocates available PE to instruction slots in the most efficient way to maximize throughput, utilizing the maximum amount of PE in each time slot while leaving the minimum amount of dark silicon.

[0086] The compiler also ensures that a PE is not allocated to two or more instructions in the same time slot by checking for potential conflicts with other operations performed by the same processing element during the same time slot.

[0087] In particular, the "programmer view" and "hardware view" may be used to control the mapping of instructions to atomic PEs in the VALUTA architecture.

[0088] The programmer view allows the programmer to use any type of available atomic PE (i.e., vectors / scalars of any size enabled by the atomic PE) associated with an operation. The compiler is configured to map statements in program code to appropriate instructions available in any of the instruction slots, as described by the processor model. This mapping is performed by the compiler based on the programmer view.

[0089] The selected instruction may also have an associated hardware view, which stitches together the atomic PEs required by the types of variables used in the program statement and corresponds to the programmer view of the mapped instruction. This hardware view ensures that the atomic PEs remain unique and are reused wherever needed by the program without causing atomic PE duplication. To enable this uniqueness of atomic PEs (and avoid hardware duplication), all atomic PEs may be used in all instruction slots that provide VALUTA-related instructions.

[0090] To simplify the stitching (at the software or hardware level) of atomic PEs to certain types of vector PEs, all atomic PEs may have fixed left and right neighboring elements.

[0091] Depending on the type used in the program, hardware stitching / connections between atomic PEs may be opened or closed, for example, by a stitching control circuit.

[0092] Stitching, in this context, refers to combining (at a software or hardware level) input data elements and / or partial results from different data streams, as opposed to element-wise operations on vectors. Stitching can be performed by the PE before or after the generation of the output data (for example, in the case of a dot product, stitching must be performed after the element-wise multiplication).

[0093] These programmable hardware stitches / connections allow the use of different data types and different operations linked / associated with different vector widths. For other use cases, different “stitching” functions may be provided at design time, and hardware stitches may be opened and closed at compile time.

[0094] Figure 8 shows the assignment of instructions to the aggregated atomic PE in a given time slot, according to exemplary use case #6 adapted for executing programs A and B, respectively.

[0095] As an example, let program A include a vector multiplication X·Y (also called the dot product) with a vector width of eight scalars. Program B includes two vector operations: the Hadamard product X1*Y1 using a vector width of six scalars, and the sum of elements in a vector of two scalars X2+Y2. For the purposes of this example, all scalars in programs A and B are integers, but can generally be of any type.

[0096] In pseudocode, programs A and B are as follows: Program A: V8int X; V8int Y; int Z; Z = X·Y; Program B: V6int X1; V6int Y1; V6int Z1; V2int X2; V2int Y2; V2int Z2; Z1 = X1 * Y1; Z² = X² + Y²;

[0097] In the declarations of variables X, Y, and Z in program A, and variables X1, X2, Y1, Y2, Z1, and Z2 in program B, "VNint" specifies a vector of N integers (for example, V8int is of type 8 integers).

[0098] The allocation of operations to the PEs is shown in Figure 8, where the PEs are numbered #0 to #15 from right to left. The PEs used in program A are collectively specified by reference numeral 80A, and the PEs used in program B are collectively specified by reference numeral 80B.

[0099] The operation programmed in program A is a dot product corresponding to the element-wise multiplication of the elements of vectors X and Y, followed by the sum of the products.

[0100] For example, the dot product of two V8int vectors X=[x1,x2,...,x8] and Y=[y1,y2,...,y8] is:

[0101]

number

[0102] In the example in Figure 8, this dot product can be performed by stitched atomic PE0-7 mapped to instruction #2 from the corresponding instruction slot. See hardware stitch 85 schematically shown in Figure 8.

[0103] In program B, element-wise multiplication (Hadamard product, Z1=X1*Y1) is performed, followed by element-wise summation (Z2=X2+Y2). In the example in Figure 8, this Hadamard product is performed by atomic PE0-5, which are mapped to instruction #2. The output is aggregated to produce a 6-element output vector, and the sum is performed by atomic PE6-7, which are mapped to instruction #3, and the output is aggregated to produce a 2-element output vector. Hardware stitching is not required here.

[0104] In the pseudo-programmer view code, Program A and Program B would look like this: Program A: Q8[0]=dot8int(VL8[0],V8R[0]); Program B: Q6[0]=mul6int(VL6[0],VR6[0]); Q2[3]=add2int(VL2[3],VR2[3]);

[0105] These are omitted in this view because they would be obvious if we were looking at the registers used. The Hadamard vector multiplication of N integers compiles to "mulNint", and the dot vector product of N integers compiles to "dotNint".

[0106] In program A, the compiler selects a first available 8-element vector PE (e.g., an 8-integer vector) formed by aggregating PE#0~#7. Each PE has a right input data VR, a left input data VL, and an output data Q. The associated registers are specified by VL8[0], VR8[0], and Q8[0], respectively, where, for example, VL8[i] represents the left input data of the 8-element PE starting at index i. Multiplication is compiled into the intrinsic function dot8int, which is an element-wise vector multiplication of the 8 integer elements, followed by the sum of these products. The result is written to the Q output vector, whose element 0 contains only the final scalar value which is the result of the dot product. The other elements of vector Q contain no useful data and may be assigned 0.

[0107] In program B, the compiler selects a first available 6-element vector PE (e.g., a vector of 6 integers) formed by aggregating the relevant registers VL6[0], VR6[0], and Q6[0] with PE#0~#5. The compiler also selects a first available 2-element vector PE (e.g., a vector of 2 integers) by aggregating the relevant registers VL2[3], VR2[3], and Q2[3] with PE#6~#7. Note that VL2[0]~VL2[2], VR1[0]~VR2[2], etc., have already been taken up by the 6-element vectors VL6[0] and VR6[0]. Multiplication is compiled into the mul6int intrinsic function, and summation is compiled into the add2int intrinsic function.

[0108] In the pseudo-hardware view, programs A and B appear as follows: Program A: (Q1[7],Q1[6],Q1[5],Q1[4],Q1[3],Q1[2],Q1[1],Q1[0])= dotstitch8( mul1int(VL1[7],VR1[7]), mul1int(VL1[6],VR1[6]), mul1int(VL1[5],VR1[5]), mul1int(VL1[4],VR1[4]), mul1int(VL1[3],VR1[3]), mul1int(VL1[2],VR1[2]), mul1int(VL1[1],VR1[1]), mul1int(VL1[0],VR1[0]) ); Program B: (Q1[5],Q1[4],Q1[3],Q1[2],Q1[1],Q1[0])= hadstitch6( mul1int(VL1[5],VR1[5]), mul1int(VL1[4],VR1[4]), mul1int(VL1[3],VR1[3]), mul1int(VL1[2],VR1[2]), mul1int (VL1[1],VR1[1]), mul1int(VL1[0],VR1[0]) ); (Q1[7],Q1[6])= hadstitch2( add1int(VL1[7],VR1[7]), add1int(VL1[6],VR1[6]) );

[0109] In program A, in the hardware view, the allocated 8-element vector PE can be divided into its atomic PEs, for example, 8 PEs #0 to #7. The dot8int function can also be divided into atomic operations (in this case, 8 element-wise operations) so that 8 products are obtained. The products of the atomic operations are summed by a stitching function dotstitch8, which can be performed at the hardware level (for example, by additional wiring). For the dot product, the stitching function dotstitch8 sums all element-wise products resulting from the element-wise multiplication operations. The sum calculation can be performed in the same time slot as the product calculation.

[0110] In the case of program B, since all element-wise operations are independent of each other when Hadamard product and Hadamard addition are used, the stitching functions hadstitch6 and hadstitch2 may be performed at the software level only on the input and output data elements of PE, and are simply aggregates of the individual output data elements resulting from the element-wise operations to generate the output vector Z1 or Z2.

[0111] For program B, a 6-element vector PE may use 6 aggregated atomic PEs, e.g., PE#0 to #5, and a 2-element vector PE may use 2 available aggregated atomic PEs, e.g., PE#6 to #7.

[0112] Note that in these programs, all operations can use atomic PEs from the same pool for that operation. Atomic PEs from a single pool can be mapped to any instruction slot as needed. When several atomic PEs are mapped to the same instruction slot, software-level stitching is achieved for the data elements of the PEs. This approach leads to greater flexibility with less hardware.

[0113] The compiler is configured to allocate data elements and instructions to hardware resources (e.g., instruction slots and PEs). The compiler tracks availability and dependencies. For each program, the compiler ensures that only available / free atomic PEs are used for each vector variable without duplication. While these variables persist in the program, the associated atomic PEs are linked to their respective vectors and cannot be used by other operations on other vectors. The compiler recognizes this by how vectors are composed of atomic PEs.

[0114] In the hardware view, individual atomic registers may be defined, and vector PEs of all widths may be specified as "aliases" of aggregates of atomic PEs (e.g., int PE). For example, in a pseudo-hardware description, - "define PE

[16] type int" specifies an array of 16 integer atomic PEs, in this case an array of PEs for processing integer data elements. - The `define PE[2] type int8` specifies an array of 2x8 element vectors PE using 16 integer atomic PEs. In this case, the first vector PE may use PE#0 to #7, and the second vector PE may use PE#8 to #15.

[0115] In this way, the compiler is configured to know which atomic PEs are linked to which variables and which PEs are still free / unallocated. The compiler is configured to protect and ensure that those variables are not unintentionally overwritten within the program.

[0116] These examples demonstrate that various aggregation / stitching schemes can be used to process input data in parallel, according to the parallel instructions available in a given time slot within the instruction slot.

[0117] Suitable memory for storing program instructions readable by the processor may include, for example, random access memory (RAM), read-only memory (ROM), persistent mass storage devices such as disk drives, hard disk drives (HDDs), solid-state drives (SSDs), memory cards, core memory, flash memory, or any combination thereof. Static random access memory (SRAM) may also be used. SRAM-based memory is fast and flexible and can load programs residing in non-volatile memory at startup.

[0118] The term "circuit" may refer to one, more, or all of the following: (a) Hardware-only circuit embodiments (such as embodiments consisting only of analog and / or digital circuits), and (b) Combinations of hardware circuits and software (where applicable): (i) combinations of analog and / or digital hardware circuits and software / firmware, and (ii) any part of a hardware processor having software (including a digital signal processor), software, and memory that works together with it, (c) A processor, such as a microprocessor or part of a microprocessor, which requires hardware circuitry and / or software (e.g., firmware) for operation, but may not be present when the software is not required for operation.

[0119] As a further example, the term "circuit" can also encompass a mere hardware circuit or processor (or multiple processors), or a part of a hardware circuit or processor, as well as embodiments of its (or their) accompanying software and / or firmware.

[0120] Terms such as "first," "second," etc., may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be called a second element, and similarly, a second element may be called a first element. Where the terms "and / or" as used herein are used in a list of items, it is implied that the list may include any or all of one or more of the listed items in question.

[0121] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context specifically indicates otherwise. It should be further understood that the terms “equip,” “equip,” “contain,” and / or “contain,” when used herein, indicate the presence of the mentioned feature, integer, step, action, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or sets thereof.

[0122] While embodiments have been described with reference to specific examples, these embodiments should be understood as merely illustrative of the principles and uses of the present disclosure. Therefore, numerous modifications may be made to the exemplary embodiments, and other configurations may be devised without departing from the spirit and scope of the present disclosure, as described pursuant to the claims and any equivalents thereof. [Explanation of Symbols]

[0123] List of common abbreviations ASIP (Application-Specific Instruction Set Processor) CPU (Central Processing Unit) DU Distributed Unit FFT (Fast Fourier Transform) FIR finite impulse response GPU (Graphics Processing Unit) HW Hardware L1 Layer 1 MIMD Multiple Instruction Multiple Data MISD (Multiple Instruction Single Data) No NOP operation PE processing element SIMD Single Instruction Multiple Data SISD Single Instruction Single Data SW software VALUTA Vector Arithmetic Logic Unit Transaction Atomic VLIW very long instruction word

Claims

1. Program memory that stores instructions, A decoder adapted to convert the aforementioned instructions into their respective operation codes and enable signals, A controller comprising an instruction word consisting of multiple instruction slots for providing the instruction to the decoder, A plurality of processing elements, each processing element configured to operate during a time slot according to an operation code provided to the input of the target processing element, to apply mathematical operations to input data elements and generate output data elements, wherein an instruction provided via an instruction slot identifies one or more target processing elements to be used to execute the instruction, and the enable signal is adapted to control the assignment of the operation code to the processing element, An interconnect circuit, configured to be adapted to provide one of the operation codes to any of the processing elements in each time slot and to operate according to the enable signal, A processor equipped with the following features.

2. The processor according to claim 1, wherein the interconnection circuit is adapted to provide a given operation code to any number of processing elements in each time slot.

3. A processor according to claim 1 or 2, comprising a stitch control circuit and at least one hardware stitch, each of which is configured to connect or disconnect at least two processing elements, and the stitch control circuit is adapted to open or close the at least one stitch according to stitch signals generated from instructions distributed to the at least two processing elements.

4. The processor according to any one of claims 1 to 3, wherein the interconnection circuit comprises a multiplexer configured to provide operation codes to the processing elements in accordance with the enable signal.

5. The processor according to any one of claims 1 to 4, wherein the plurality of processing elements include one or more scalar processing elements.

6. The processor according to any one of claims 1 to 5, wherein the plurality of processing elements include one or more vector processing elements.

7. The processor according to claim 6, wherein the vector processing elements have different lengths.

8. The processor according to any one of claims 1 to 7, wherein at least one first processing element among the processing elements supports at least one first type of mathematical operation, and at least one second processing element among the processing elements supports at least one second type of mathematical operation, and the first type of mathematical operation is separate from the second type of mathematical operation.

9. The processor according to any one of claims 1 to 8, wherein at least one third processing element among the processing elements supports at least one first data type, and at least one fourth processing element among the processing elements supports at least one second data type, the first data type being separate from the second data type.

10. A processor according to any one of claims 1 to 9, which operates in accordance with an extra-long instruction word operation mode.

11. The processor according to any one of claims 1 to 10, wherein the instruction word is an extra-long instruction word.

12. A compiler configured to compile program code to generate instructions to be processed by a processor according to any one of claims 1 to 11, wherein the compiler is configured to allocate the instructions to the respective processing elements and instruction slots of the processor, each instruction specifying one or more target processing elements to be used to execute the instruction in question, and the compiler is adapted to allocate any of the instructions to any of the processing elements in each time slot.

13. The compiler according to claim 12, which is adapted to distribute any of the instructions to any number of processing elements in each time slot.

14. The compiler according to claim 12 or 13, configured to ensure that a processing element is not allocated to two or more instructions within the same time slot by checking for possible conflicts with other instructions allocated to the same processing element within the same time slot.

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