Memory systems and methods for operating memory systems

Abstract

A memory system and a method for operating the memory system are disclosed. A memory controller is configured to: perform first error-correcting code (ECC) encoding on a plurality of first frames of data; generate a plurality of incremental check sub-units corresponding to the plurality of first frames of data respectively; generate incremental check codewords by performing second ECC encoding on the plurality of incremental check sub-units, wherein the incremental check codewords include one or more redundant data units; perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits; determine a second vector of bits such that the second vector of bits is added to the first vector of bits to form a combination vector of bits, wherein the combination vector of bits is an ECC codeword with an incremental check, the value of which is pre-fixed based on at least one of the one or more redundant data units.

Description

[0001] This application claims the benefit of U.S. Patent Application No. 16 / 352,052, filed March 13, 2019, with the United States Patent and Trademark Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to the technical field of data storage, and more specifically, to methods and apparatus for storing data using error correction codes (ECC). Background Technology

[0003] Errors can occur when data is stored in and retrieved from a memory device. Various error-correcting codes can be used to detect and correct such errors. These codes may include Reed-Solomon (RS) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, and Hamming product codes (HPC).

[0004] As the quality of data (e.g., bit error rate) improves, the performance of error-correcting codes can also improve. However, for some error-correcting codes, there is a point where the rate of improvement in performance decreases or flattens out. This phenomenon is called error flooring. Summary of the Invention

[0005] According to at least some example embodiments of the inventive concept, a memory system includes a memory controller and a memory device. According to at least some example embodiments of the inventive concept, the memory controller is configured to: perform first error correction code (ECC) encoding on a plurality of first frames of data; generate a plurality of incremental check sub-units corresponding to the plurality of first frames of data respectively; generate incremental check sub-codewords by performing second ECC encoding on the plurality of incremental check sub-units, wherein the incremental check sub-codewords include the one or more redundant data units; perform third error correction code (ECC) encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits; determine a second vector of bits such that the second vector of bits is added to the first vector of bits to generate a combination vector of bits, and the value of the incremental check sub-unit generated based on the combination vector of bits is pre-fixed based on at least one of the one or more redundant data units; and generate the combination vector of bits.

[0006] According to at least some exemplary embodiments of the inventive concept, a memory system includes a memory controller and a memory device. According to at least some exemplary embodiments of the inventive concept, the memory controller is configured to: read a plurality of frames of data from the memory device; correct errors in one or more frames of data among the plurality of frames by performing a first error correction code (ECC) decoding on the plurality of frames of data; after the first ECC decoding, identify a plurality of correct frames and at least one erroneous frame among the plurality of frames of data; generate a plurality of incremental check sub-units corresponding to the plurality of correct frames respectively; generate an incremental check ECC codeword including information bits and redundant bits based on the plurality of incremental check sub-units, such that the redundant bits of the incremental check ECC codeword are bits of at least one of the generated incremental check sub-units, and the information bits of the incremental check ECC codeword are bits of one or more of the generated incremental check sub-units other than the at least one incremental check sub-unit; and recover the incremental check sub-unit corresponding to the at least one erroneous frame by performing a second ECC decoding on the incremental check ECC codeword.

[0007] According to at least some exemplary embodiments of the present invention, a method of operating a memory system including a memory controller and a memory device includes: performing first error correction code (ECC) encoding on a plurality of first frames of data; generating a plurality of incremental check sub-units corresponding to the plurality of first frames of data respectively; generating incremental check sub-codewords by performing second ECC encoding on the plurality of incremental check sub-units, wherein the incremental check sub-codewords include one or more redundant data units; performing third error correction code (ECC) encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits; determining a second vector of bits such that the second vector of bits is added to the first vector of bits to generate a combination vector of bits, and the value of the incremental check sub-unit generated based on the combination vector of bits is pre-fixed based on at least one of the one or more redundant data units; and generating the combination vector of bits. Attached Figure Description

[0008] The above and other features and advantages of the inventive concept will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings. The drawings are intended to describe exemplary embodiments of the inventive concept and should not be construed as limiting the intended scope of the claims. Unless explicitly stated otherwise, the drawings should not be considered to be drawn to scale.

[0009] Figure 1 This is a diagram illustrating a memory system according to at least one example embodiment of the inventive concept.

[0010] Figure 2Examples of product codewords according to at least some exemplary embodiments of the inventive concept are shown.

[0011] Figures 3A to 3F The operation for performing the projected BCH encoding algorithm is illustrated according to at least some example embodiments of the inventive concept.

[0012] Figure 4 This is a block diagram illustrating a computer system including a memory system according to an example embodiment of the inventive concept.

[0013] Figure 5 This is a block diagram illustrating a memory card according to at least one example embodiment of the inventive concept.

[0014] Figure 6 This is a block diagram illustrating an example network system including a memory system according to at least one example embodiment of the inventive concept. Detailed Implementation

[0015] As is customary in the field of inventive conception, embodiments are described in accordance with functional blocks, units, and / or modules, and are illustrated in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.), wherein the electronic (or optical) circuitry may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or the like, they may be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Optionally, each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the scope of the inventive conception, each block, unit, and / or module of the embodiments may be physically divided into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules.

[0016] I. Overview

[0017] According to at least some example embodiments, as discussed in more detail below, using a projected BCH encoding operation during the ECC encoding process of Hamming product code (HPC) codewords can improve the error plane associated with the ECC decoding process of the HPC codewords. For example, as discussed in more detail below, by generating delta syndromes for the HPC codeword frames, performing ECC encoding on the generated delta syndromes themselves, and storing redundant data resulting from encoding the delta syndromes, lost delta syndromes can be recovered during the decoding process of the HPC codewords. For example, as discussed in more detail below, when decoding the HPC codewords, the recovered delta syndromes can be used during the decoding operation to improve the error correction capability of the ECC codes used to encode the HPC codewords. Therefore, the error plane associated with the ECC decoding operation can be improved.

[0018] Furthermore, according to at least some exemplary embodiments of the inventive concept, as discussed in more detail below, the selected frame of the HPC codeword can be encoded such that the incremental checksum corresponding to the selected frame has a desired or pre-fixed value. Therefore, by selecting a pre-fixed value for the value of the redundant data generated from encoding the incremental checksums of other frames, the redundant data is substantially embedded in the incremental checksum generated for the selected frame. Thus, the need to store the redundant data separately is reduced or optionally eliminated. Therefore, the storage space requirements associated with encoding the HPC codeword using a projected BCH can be advantageously reduced.

[0019] The example memory system 900 for performing the above-described encoding and / or decoding operations is discussed in more detail below in Part II of this disclosure. The example Hamming product code (HPC) encoding operation is discussed in more detail below in Part III of this disclosure. The example projected Bosch-Joherry-Hokvenheim (BCH) encoding operation is discussed in more detail below in Part IV of this disclosure. The example method for generating BCH codewords with pre-fixed increment checksum values ​​is discussed in more detail below in Part V of this disclosure. The example decoding operation is discussed in more detail below in Part VI of this disclosure. The implementation example corresponding to the memory system 900 is discussed in more detail below in Part VII of this disclosure.

[0020] A memory system 900 according to at least some exemplary embodiments of the inventive concept will now be discussed in Part II of this disclosure below.

[0021] II. Example Memory System

[0022] Figure 1 This is a diagram illustrating a memory system 900 according to at least one exemplary embodiment of the inventive concept. (Refer to...) Figure 1 The storage system 900 includes a memory controller 1000 and a non-volatile memory device 2000.

[0023] The non-volatile memory device 2000 may be, but is not limited to, flash memory devices, NAND flash memory devices, phase-change RAM (PRAM), ferroelectric RAM (FRAM), magnetic RAM (MRAM), etc. According to at least one exemplary embodiment of the inventive concept, the non-volatile memory device 2000 may include multiple NAND flash memory devices. The non-volatile memory device 2000 may have a planar structure or a three-dimensional (3D) memory cell structure with stacked memory cells.

[0024] The memory device 2000 may include a memory cell array 2100, an X decoder 121, a voltage generator 125, an I / O buffer 124, a page buffer 123, and control logic 126, wherein each of the memory cell array 2100, the X decoder 121, the voltage generator 125, the I / O buffer 124, the page buffer 123, and the control logic 126 may be implemented as one or more circuits. The memory device may also include input / output (I / O) pads (also known as pads or solder pads) 127.

[0025] The memory cell array 2100 includes multiple word lines and multiple bit lines. Each memory cell in the memory cell array 2100 can be implemented as a non-volatile memory cell. For example, each memory cell in the memory cell array 2100 can have a floating gate or a charge storage layer (such as a charge trapping layer).

[0026] Memory cell array 2100 may include multiple blocks and multiple pages. A block includes multiple pages. A page can be a unit for programming and reading operations, and a block can be a unit for erasing operations. For example, memory cell array 2100 includes a first block 2120 and a second block 2130. Figure 1 As shown, the first block 2120 includes pages 1 to N, and the second block 2130 includes pages 1 to N, where N is a positive integer greater than 1.

[0027] Control logic 126 controls the overall operation of memory device 2000. When a command CMD is received from memory controller 1000, control logic 126 interprets the command CMD and controls memory device 2000 to perform operations (e.g., programming operation, read operation, read retry operation, or erase operation) according to the interpreted command CMD.

[0028] According to at least one example embodiment, control logic 126 may include a hardware-implemented processor configured to execute commands based on command CMD. According to at least one example embodiment of the inventive concept, in addition to the processor, control logic 126 may also include a storage unit for storing instructions, wherein the processor performs a specific operation when the steps are executed by the processor included in control logic 126. According to at least one example embodiment of the inventive concept, any operation performed by the memory device 2000 described herein may be performed by control logic 126 (e.g., by a processor included in control logic 126 that drives firmware stored in the storage unit included in control logic 126), or may be performed under the control of control logic 126. Optionally, control logic 126 may be circuitry (e.g., an application-specific integrated circuit (ASIC)) physically programmed according to hardware to perform or control any operation performed by the memory device 2000 described herein.

[0029] The X decoder 121 is controlled by control logic 126 and drives at least one word line of multiple word lines in the memory cell array 2100 according to the row address.

[0030] Voltage generator 125 is controlled by control logic 126 to generate one or more voltages required for write, read, or erase operations, and provides the generated voltages to one or more rows selected by X decoder 121.

[0031] Register 128 is controlled by control logic 126. Register 128 is a space for storing information input from memory controller 1000 and may include multiple latches. For example, register 128 may group read voltage (and / or reference voltage) information and store the information in tabular form.

[0032] Page buffer 123 is controlled by control logic 126 and operates as a sense amplifier or write driver depending on the operating mode (e.g., read operation or write operation).

[0033] I / O pads 127 and I / O buffers 124 can be used as I / O paths for data exchange between an external device (e.g., memory controller 1000 or a host) and memory device 2000. I / O pads 127 are connected to memory controller 1000 via the memory system bus. Data and / or commands can be output from memory device 2000 to memory controller 1000, or received at memory device 2000 from memory controller 1000, via I / O pads 127 and the memory system bus.

[0034] According to at least some exemplary embodiments of the inventive concept, the memory device 2000 operates in response to commands and / or control signals generated by the memory controller 1000. Therefore, the operations performed, operated, or controlled by the memory device 2000 as described in this disclosure may additionally or optionally be referred to as operations performed, operated, or controlled by the memory controller 1000.

[0035] The memory controller 1000 may include a microprocessor 111, a read-only memory (ROM) 113, a random access memory (RAM) 112, an encoder 1100, a decoder 1200, a memory interface 116, and a controller bus 118. The components 111 to 116 of the memory controller 1000 may be electrically connected to each other via the controller bus 118.

[0036] Microprocessor 111 controls the overall operation of memory system 900, including memory controller 1000. Microprocessor 111 controls the circuitry of other components by generating control signals. When power is supplied to memory system 900, microprocessor 111 drives firmware (e.g., stored in ROM 113) on RAM 112 to operate memory system 900, thereby controlling the overall operation of memory system 900. According to at least one example embodiment of the inventive concept, microprocessor 111 may also issue commands or output control signals to control the operation of other components of memory controller 1000 (including, for example, some or all of ROM 113, RAM 112, encoder 1100, decoder 1200, memory interface 116, and control bus 118). According to at least one example embodiment of the inventive concept, any operation performed by memory controller 1000 described herein may be performed by microprocessor 111 (e.g., by a microprocessor driving the aforementioned firmware) or performed under the control of microprocessor 111.

[0037] Although the driver firmware code for the memory system 900 is stored in ROM 113, one or more exemplary embodiments of the inventive concept are not limited thereto. The firmware code may also be stored in a portion of the memory system 900 other than ROM 113. Therefore, control or intervention of the microprocessor 111 may include not only direct control of the microprocessor 111, but also intervention by firmware as software driven by the microprocessor 111.

[0038] Alternatively, the microprocessor 111 may be a circuit (e.g., an ASIC) that is physically programmed according to hardware to perform or control any operations performed by the memory controller 1000 as described herein.

[0039] RAM 112, serving as a buffer, can store initial commands, data, and various variables input from the host or microprocessor 111, or data output from the memory device 2000. According to at least some example embodiments of the inventive concept, RAM 112 can store data input to the memory device 2000, various parameters, and variables, as well as data output from the memory device 2000, various parameters, and variables.

[0040] Memory interface 116 serves as an interface between memory controller 1000 and memory device 2000. Memory interface 116 is connected to I / O pads 127 of memory device 2000 via the memory system bus and can exchange data with I / O pads 127 via the memory system bus. Furthermore, memory interface 116 can create commands suitable for memory device 2000 and provide the created commands to I / O pads 127 of memory device 2000. Memory interface 116 provides one or more commands to be executed by memory device 2000 and one or more addresses of memory device 2000.

[0041] According to at least one example embodiment of the inventive concept, decoder 1200 may be an error-correcting code (ECC) decoder, and encoder 1100 may be an ECC encoder. According to at least one example embodiment of the inventive concept, decoder 1200 and encoder 1100 perform error bit correction. Before data is provided to memory device 2000, encoder 1100 can generate data with one or more parity bits and / or redundant bits added by performing error-correcting encoding on the data. One or more parity bits and / or redundant bits may be stored in memory device 2000.

[0042] Decoder 1200 performs error correction decoding on the output data, determines whether the error correction decoding was successful based on the result, and outputs a command signal based on the result. Read data can be sent to decoder 1200, which can use one or more parity bits and / or redundancy bits to correct erroneous bits in the data. When the number of erroneous bits exceeds the limit of the number of erroneous bits that can be corrected, decoder 1200 cannot correct the erroneous bits, resulting in error correction failure.

[0043] Each of encoder 1100 and decoder 1200 may include error correction circuitry, a system, or a means. Encoder 1100 and decoder 1200 may perform error correction using, for example, one or more of low-density parity-check (LDPC) codes, Bosch-Joherry-Hokvenheim (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), and coded modulation (such as trellis-coded modulation (TCM) or block-coded modulation (BCM)). Furthermore, as discussed in more detail below, encoder 1100 and decoder 1200 may perform error correction using Hamming product codes (HPC).

[0044] Example coding operations based on at least some exemplary embodiments of the inventive concept will now be discussed in Part III of this disclosure below.

[0045] III. Example Encoding Operations

[0046] Typically, product codes (or iterative codes) are serial concatenated codes. The concept of product codes is relatively simple and efficient; they construct very long block codes using two or more short block codes. For example, a product code P can be defined as... Among them, C 1 and C 2 These are the first-system linear block code and the second-system linear block code, respectively. The first code is C. 1 Having parameters (n1, k1, δ1), the second code C 2 It has parameters (n2, k2, δ2), n i k i and δ i These represent the codeword length, the number of information bits, and the minimum Hamming distance, respectively. One type of product code is the Hamming product code (HPC). For example, when the first code C... 1 Second code C 2 When both are extended Hamming codes, the product code P is HPC. HPC is used to encode data to generate HPC codewords. Figure 2 An example of HPC codeword 200 is shown. The process of encoding data using HPC will now be discussed below with reference to Algorithm 1 and HPC codeword 200.

[0047] The operation of Algorithm 1 is illustrated below using pseudocode. According to at least some example embodiments of the inventive concept, each operation of Algorithm 1 may be executed by or under the control of memory controller 1000 (e.g., using microprocessor 111).

[0048]

[0049] Algorithm 1 will be discussed in the following case: First code C 1Second code C 2 All are extended Hamming codes, k1 = 183, k2 = 183, n1 = 192, n2 = 192. Therefore, the parameters of the generated product code P are n = n1 × n2, k = k1 × k2, δ = δ1 × δ2, and the code rate R is given by R = R1 × R2, where R i It is the i-th code C i The bit rate. Furthermore, in this disclosure, "redundant" data, "redundant" bits, etc., may also be referred to as "parity" data, "parity" bits, etc. Additionally, in this disclosure, "redundant" data, "redundant" bits, or "parity" data, "parity" bits, etc., may generally be referred to as (e.g., ECC codes similar to BCH codes or RS codes) "overhead".

[0050] Referring to Algorithm 1, in operation (A1), the memory controller 1000 (e.g., from an external device) receives information bits 210 and arranges the information bits 210 into k1 rows and k2 columns. Therefore, as... Figure 2 As shown in HPC codeword 200, memory controller 1000 arranges information bits 210 into 183 columns and 183 rows. In this disclosure, rows of data (e.g., rows of HPC codeword 200) may also be referred to as “frames”.

[0051] In operation (A2), the memory controller 1000 uses the second code C. 2 Encode row k1. For example, refer to... Figure 2 HPC codeword 200, memory controller 1000 uses second code C 2 Encode the 183rd row of information bits 210 to generate Figure 2 The 183 corresponding rows of redundant data shown are designated as redundant rows 230. Figure 2 In the example shown, each of the 183 redundant rows 230 includes 9 redundant bits. For example, because, as mentioned above, the second code C 2 Since it is an extended Hamming code, the 9 redundant bits can include 8 extended Hamming code parity bits and one additional parity bit, for a total of 8 + 1 = 9 redundant bits. Therefore, each row of HPC codeword 200 includes n² (i.e., 18³ + 9 = 19² = n²) bits. Therefore, HPC codeword 200 includes n² columns.

[0052] In operation (A3), the memory controller 1000 uses the first code C 1 Encode column n2. For example, refer to... Figure 2 HPC codeword 200, memory controller 1000 uses the first code C 1 Encoding the 183 columns of information bits 210 results in 183 redundant columns 220. Figure 2In the example shown, each of the 183 redundant columns 220 comprises 9 bits. Furthermore, the memory controller 1000 uses the first code C. 1 The bits in 9 columns of 183 redundant rows 230 are encoded to produce a 9×9 check-on-check block 240.

[0053] Although the example above describes Algorithm 1 where the row of reference information bit 210 is encoded first (e.g., in operation (A2)) and the columns of the subsequently encoded rows are encoded (e.g., in operation (A3)), according to at least some example embodiments of the inventive concept, operation (A3) may be performed before operation (A2) (i.e., operation (A3) may include the use of code C). 1 Encode column k2; operation (A2) may include using code C after operation (A3). 2 (Encode row n1).

[0054] According to at least some exemplary embodiments of the inventive concept, after operations (A1) to (A3), the memory controller 1000 stores the HPC codeword 200 on the memory device 2000. For example, the memory controller 1000 may send the HPC codeword 200 and one or more write commands to the memory device 2000, and the memory device 2000 may respond to one or more write commands by writing the HPC codeword 200 to the memory cell array 2100 (e.g., writing the HPC codeword 200 to a memory page of the memory cell array 2100).

[0055] As described above, the parameters of the generated product code P are n = n1 × n2, k = k1 × k2, and δ = δ1 × δ2. The code rate R is given by R = R1 × R2, where R i It is the i-th code C i The code rate. Therefore, by combining short codes with small minimum Hamming distances, relatively long block codes with relatively large minimum Hamming distances can be constructed. Given the process for constructing the product code P, the last (n²-k²) columns of the HPC codeword 200 are the first code C. 1 The codeword. By using a matrix generator, it can be shown that the last (n1-k1) rows of HPC codeword 200 are the second code C. 2 The codeword. Therefore, all rows of HPC codeword 200 are the second code C. 2 The codeword, and all columns of HPC codeword 200 are the first code C. 1 The code words.

[0056] According to at least some exemplary embodiments of the inventive concept, the operation of Algorithm 1 (A2) can be performed using projected BCH encoding, which will now be discussed in more detail in Part IV of this disclosure below.

[0057] IV. Projected BCH Encoding

[0058] According to at least some exemplary embodiments of the inventive concept, for example, according to Algorithm 2 discussed below, projection The BCH encoding algorithm is applied to, for example, lines of HPC codeword 200. For example, according to at least some exemplary embodiments of the inventive concept, in addition to the extended Hamming code encoding discussed above with reference to operation (A2) of Algorithm 1, projection The BCH encoding algorithm is used, or alternatively, projection The BCH encoding algorithm replaces the extended Hamming code encoding discussed above with reference to operation (A2) of Algorithm 1. For example, according to at least some exemplary embodiments of the inventive concept, operation (A2) of Algorithm 1 includes: performing Algorithm 2, discussed below, on line k1 of the data corresponding to HPC codeword 200. projection The BCH encoding operation (i.e., not performing extended Hamming code encoding on line k1) is performed; and parity bits are generated and stored for each line of the HPC codeword 200. The parity bits can be generated using known methods.

[0059] Furthermore, according to at least some exemplary embodiments of the inventive concept, with respect to the operation (A3) of Algorithm 1, the extended Hamming code encoding discussed above with reference to Algorithm 1 is performed on the column of codeword (e.g., HPC codeword 200), but the projected BCH encoding discussed below with respect to Algorithm 2 is not applied to the column of codeword (e.g., HPC codeword 200).

[0060] Therefore, according to at least some example embodiments of the inventive concept, in Algorithm 1: the memory controller 1000 performs projection BCH encoding according to Algorithm 2 on the rows of information bits of the codeword, and then the memory controller 1000 performs extended Hamming code encoding on the columns of bits in the rows of the projection BCH encoded information bits, thereby generating a two-dimensional HPC codeword.

[0061] Furthermore, according to at least some other example embodiments of the inventive concept, in Algorithm 1: Extended Hamming code encoding is performed on the columns of information bits of the codeword by the memory controller 1000, and then, the rows of bits in the columns of extended Hamming code encoded by the memory controller 1000 are encoded by projection BCH according to Algorithm 2, thereby generating a two-dimensional HPC codeword.

[0062] As discussed in more detail below with reference to Algorithm 2, the projective BCH encoding algorithm includes performing BCH encoding on rows of data in information bits 210, thereby generating BCH redundant data for each row. Furthermore, the projective BCH encoding algorithm includes generating incremental checksums (ds) to improve the error correction capability of the aforementioned BCH redundant data. Each incremental checksum may correspond to one of multiple stages i. The total number of error bits per row that can be appropriately corrected with the help of the corresponding incremental checksum at stage i is represented as t. i (or ti). Furthermore, as discussed in more detail below with reference to Algorithm 2, RS codes are used to concatenate and encode incremental checksums of the same level, thereby generating RS redundancy data. The error-correcting capability of the RS codes varies with the level of the encoded incremental checksums. The total number of erroneous rows in the incremental checksum data of level i that can be appropriately corrected using the RS redundancy data mentioned above for level i is denoted as F. i (or Fi).

[0063] Therefore, the parameters of the projection BCH coding algorithm can be represented by vectors F and t. For simplicity, as follows... Figures 3A to 3F As shown, Algorithm 2 will be explained below with reference only to the 8 frames of data for codeword 300 (i.e., frame 31 to frame 38). Furthermore, Algorithm 2 will be explained below with reference to the examples of vector F = [F0 F1 F2] = [8 3 1] and vector t = [t0 t1 t2] = [6 7 9].

[0064] Although Algorithm 2 is explained below with reference to 8 frames including information bits in codeword 300 for simplicity, Algorithm 2 can be executed for more than 8 frames of data. For example, the memory controller 1000 can be executed for frames including information bits in codeword 300. Figure 2 The algorithm 2 is executed using 192 frames of bits in HPC codeword 200 shown in the figure.

[0065] The operation of Algorithm 2 is illustrated below using pseudocode. According to at least some example embodiments of the inventive concept, each operation of Algorithm 2 may be executed by or under the control of memory controller 1000 (e.g., using microprocessor 111).

[0066] Algorithm 2

[0067]

[0068] According to at least some exemplary embodiments of the inventive concept, Algorithm 2 has three parts: Part 0, Part 1, and Part 2. Referring to Part 0, in operation (B1), the memory controller 1000 encodes the F0-F1 frame using the error correction capability of the t0 bit. For example, F0-F1 = 8 - 3 = 5. Therefore, as Figure 3AAs shown, the information bits (INFO) 310 of the first frame 31 to the fifth frame 35 (e.g., the first F0-F1 = 5 frames) are encoded using a BCH code capable of correcting the t0 bit, thereby generating BCH redundant data 315. Therefore, as... Figure 3A As shown in item (b), m is generated for each frame from the first frame 31 to the fifth frame 35. BCH ×t0 bits of BCH redundant data, where m BCH This represents the number of bits in the Galois field corresponding to the BCH code. Figures 3A to 3F In the example shown, m BCH =8. Therefore, for each of the first frame 31 to the fifth frame 35, the memory controller 1000 generates m BCH ×t0 = 8 × 6 = 48 bits of BCH redundant data. In this disclosure, the value m BCH It can sometimes be abbreviated as m.

[0069] Then, referring to part 1 of Algorithm 2, in operation (B2), the memory controller 1000 generates an incremental checksum for frames F0-F1. For example, as Figure 3B As shown in item (c), for each of the first F0-F1 = 5 frames (i.e., first frame 31 to fifth frame 35), the memory controller 1000 generates a level 1 incremental checksum 317A, a first level 2 incremental checksum 317B, and a second level 2 incremental checksum 317C. In this disclosure, the incremental checksum may also be referred to as "ds" or "DS". According to at least some exemplary embodiments of the inventive concept, such as... Figure 3B As shown, level 1ds 317A may include five separate incremental check subunits, F0-F1, and can be used during BCH decoding operations to increase the error correction capability of the BCH redundant data 315 from bit t0 to bit t1. According to at least some exemplary embodiments of the inventive concept, such as... Figure 3B As shown, both the first-stage 2ds 317B and the second-stage 2ds 317C can include five individual ds units (F0-F1), and can be used together with the first-stage 1ds 317A during BCH decoding operations to increase the error correction capability of the BCH redundant data 315 to t2 bits. ds 317A to ds 317C can be generated according to known methods for generating ds.

[0070] In operation (B3), the memory controller 1000 generates F1 cells of Reed-Solomon (RS) code overhead (i.e., F1 cells of RS redundancy data) for columns t1-t0 of ds. For example, according to at least some exemplary embodiments of the inventive concept, such as... Figure 3BAs shown in item (d), the memory controller 1000 can cascade individual cells of stage 1 ds 317A (i.e., the first [t1-t0=7-6=1] column ds in ds 317A to ds 317C), and encode the cascaded cells of stage 1 ds 317A using RS codes. As a result of the encoding, the memory controller 1000 generates RS overhead 320. Figure 3B As shown in item (d) of the document, RS overhead 320 includes RS overhead of F1 = 3 units (first RS overhead units to third RS overhead units 320A, 320B, and 320C). According to at least some exemplary embodiments of the inventive concept, each of the first RS overhead units 320A to the third RS overhead units 320C may have the same size (e.g., the same number of bits) as a separate ds unit included in ds 317A to ds 317C. In this disclosure, the term "RS overhead unit" is considered synonymous with "RS redundant data unit" and may also be referred to as "RS redundant data unit". According to at least some exemplary embodiments of the inventive concept, Figures 3B to 3F Each box marked "ds" in the diagram represents a single ds unit. According to at least some example embodiments of the inventive concept, a single incremental checker may include one or more ds units. For example, according to at least some example embodiments of the inventive concept, the combined first-level 2ds 317B and second-level 2ds 317C can be considered as multiple level 2 incremental checkers, each comprising 5 ds units.

[0071] In operation (B4), for frames F1-F2, the memory controller 1000 encodes the frame using a code with error correction capability of t1 bits, and sets the encoded result as vector x (where vector x may be referred to as vector X). For example, the memory controller 1000 may use a BCH code with error correction capability of t1 = 7 bits to encode frames F1-F2 = 3 - 1 = 2. According to at least some exemplary embodiments of the inventive concept, the F1-F2 frame encoded in operation (B4) may be the next F1-F2 (e.g., 2) frame after the F0-F1 (e.g., 5) frames already encoded in operation (B1). For example, in Figures 3A to 3F In the example shown, in operation (B4), the memory controller 1000 encodes the information bits 310 of the sixth frame 36 and the seventh frame 37 to generate, as shown in the example. Figure 3C The intermediate BCH redundant data 332 shown in item (e). Figure 3C As shown in item (e), for each of the sixth frame 36 and the seventh frame 37, the intermediate BCH redundant data 332 includes m BCH×t1 = 8 × 7 = 56 bits. Then, the memory controller 1000 can set the information bits 310 and intermediate redundant data 332 of each of the sixth frame 36 and the seventh frame 36 into a vector x (i.e., vectors corresponding to the sixth frame 36 and the seventh frame 37, respectively). For example, Figure 3C The sixth frame 36 of item (e) shown in the figure can correspond to vector x6. Figure 3C The seventh frame 37 of item (e) shown in the figure can correspond to vector x7.

[0072] In operation (B5), for frames F1-F2, the memory controller 1000 calculates multiple y vectors (where vector y may be referred to as vector Y). According to at least some exemplary embodiments of the inventive concept, as will be discussed in more detail in part V of this disclosure below, the y vector y calculated in operation (B5) for the r-th (r is a positive integer) frame... r It is when the corresponding x vector x is set in operation (B4) for the r-th frame. r The addition generates the combined vector v of the r-th frame. r Make the combined vector v for the r-th frame r A vector generated from one or more cells whose ds values ​​match expected (e.g., pre-fixed) values. Specifically, as will be referred to below... Figure 3C and Figure 3D As discussed in more detail, in operation (B5), the memory controller 1000 determines the y-vector of the 6th frame and the y-vector of the 7th frame (vector y6 334A and vector y7 334B) such that the y-vector y6 334A of the 6th frame and the y-vector y7 334B of the 7th frame are respectively associated with the x-vector x6 of the 6th frame and the x-vector x7 of the 7th frame (i.e., Figure 3C After adding the data of frame 36 and frame 37 of item (e), the value of the level 1ds unit generated for the sixth frame 36 (i.e., the combination vector v6) and the value of the level 1ds unit generated for the seventh frame 37 (i.e., the combination vector v7) will be equal to the value of the first RS overhead unit 320A and the value of the second RS overhead unit 320B generated in operation (B3), respectively.

[0073] Refer to step (B5) again, as follows: Figure 3C As shown in item (f), the memory controller 1000 can use the first RS overhead unit 320A to generate the 6th frame y vector y6 334A corresponding to the 6th frame 36, and the second RS overhead unit 320B to generate the 7th frame y vector y7 334B corresponding to the 7th frame 37. Then, in operation (B6), as... Figure 3CAs shown in item (g), the memory controller 1000 combines the y-vectors corresponding to the sixth frame 36 and the seventh frame 37 (i.e., the y-vector y6 334A of the sixth frame and the y-vector y7 334B of the seventh frame) and the x-vectors corresponding to the sixth frame 36 and the seventh frame 37 (x6 and x7 generated in operation (B4) of Algorithm 2 (i.e., the information bits 310 and intermediate BCH redundancy data 332 corresponding to the sixth frame 36 and the seventh frame 37)) to generate combined vectors v6 and v7 corresponding to the sixth frame 36 and the seventh frame 37, respectively. Combined vector v6 includes the information bits 310 corresponding to the sixth frame 36 and the final BCH redundancy data 333, and combined vector v7 includes the information bits 310 corresponding to the seventh frame 37 and the final BCH redundancy data 333. Figure 3C As shown in item (f), the final BCH redundancy data 333 may include a first final BCH redundancy data 336A corresponding to the sixth frame 36 and a second final BCH redundancy data 336B corresponding to the seventh frame 37. In this case, as discussed above, if the level 1ds unit is generated based on the sixth frame 36 and the seventh frame 37 (i.e., combination vector v6 and combination vector v7), the value of the level 1ds unit will be equal to the value of the first RS overhead unit 320A and the value of the second RS overhead unit 320B, respectively.

[0074] Then, referring to part 2 of Algorithm 2, in operation (B7), the memory controller 1000 generates an incremental checksum for frames F1-F2. For example, as Figure 3D As shown in item (h), for each of the 2 frames F1-F2 = 2 (i.e., the next 2 frames (sixth frame 36 to seventh frame 37) after the 5 frames F0-F1 = 5 for which incremental checksums are generated in operation (B2), the memory controller 1000 generates a first RS overhead unit 320A and a second RS overhead unit 320B as a level 1 incremental checksum, generates a first level 2 incremental checksum 337A, and generates a second level 2 incremental checksum 337B. According to at least some exemplary embodiments of the inventive concept, such as Figure 3D As shown, both the first-level 2ds 337A and the second-level 2ds 337B can include two separate ds units, F1-F2 = 2, and can be used during the BCH decoding operation to increase the error correction capability of the final BCH redundant data 333 of the sixth frame 36 and the seventh frame 37 from t1 bits to t2 bits. ds 337A to ds 337B can be generated according to known methods for generating ds.

[0075] In operation (B8), the memory controller 1000 generates F2 cells of Reed-Solomon (RS) code overhead (i.e., F2 cells of RS redundancy data) for columns t2-t1 of ds. For example, as Figure 3DAs shown in item (i), the memory controller 1000 can generate a first-level 2ds 347A comprising each of the first-level 2ds units in the first frame 31 to the seventh frame 37. Furthermore, as... Figure 3D As shown in item (i), the memory controller 1000 can generate a second-level 2ds 347B comprising a second-level 2ds unit for each of the first frames 31 to the seventh frames 37. Furthermore, according to at least some exemplary embodiments of the inventive concept, such as... Figure 3D As shown in item (i), the memory controller 1000 can encode the following [t2-t1=9-7=2] columns of ds that have not yet been encoded using RS codes. For example, the memory controller 1000 can cascade seven individual cells of the first-stage 2ds 347A and encode the cascaded cells of the first-stage 2ds 347A using RS codes to generate F2=1 fourth RS overhead cells 350A. Furthermore, the memory controller 1000 can cascade seven individual cells of the second-stage 2ds 347B and encode the cascaded cells of the second-stage 2ds 347B using RS codes to generate F2=1 fifth RS overhead cells 350B. According to at least some exemplary embodiments of the inventive concept, each of the fourth RS overhead cells 350A to the fifth RS overhead cells 350B may have the same size (e.g., the same number of bits) as the individual ds cells included in ds 347A to ds 347B.

[0076] In operation (B9), for frame F2, memory controller 1000 encodes the frame using a code with t2 bits of error correction capability and sets the encoded result as vector x. For example, memory controller 1000 can encode frame F2=1 using a BCH code with t2=9 bits of error correction capability. According to at least some exemplary embodiments of the inventive concept, the F2 frame encoded in operation (B9) can be the next unencoded F2 (e.g., 1) frame from F0=8 frames (i.e., all of the first frame 31 to the eighth frame 38). For example, in Figures 3A to 3F In the examples shown, such as Figure 3E As shown in item (j), in operation (B9), the memory controller 1000 encodes the information bits 310 of the only frame (e.g., the eighth frame 38) that has not yet been encoded according to the current iteration of Algorithm 2, thereby generating intermediate BCH redundant data 362. Figure 3E As shown in item (j), for the eighth frame 38, the intermediate BCH redundant data 362 includes m BCH ×t2 = 8 × 9 = 72 bits. Then, the memory controller 1000 can set the information bits 310 of the eighth frame 38 and the intermediate redundant data 362 to the x vector x8.

[0077] In operation (B10), for each of the F2 frames, the memory controller 1000 calculates the y vector and sets the vector yvec as the vector y. According to at least some exemplary embodiments of the inventive concept, as will be discussed in more detail in part V of this disclosure below, the y vector y calculated for the r-th frame in operation (B10) r It is when the corresponding x vector x is set for the r-th frame in operation (B9) r The addition produces a combined vector v. r This makes for vector v r A vector whose values ​​of one or more cells in the generated ds match expected (e.g., pre-fixed) values.

[0078] Specifically, as will be referred to below. Figure 3E As discussed in more detail, in operation (B10), the memory controller 1000 determines a third y vector y8 364 such that the vector y8 364 and the x vector x8 (i.e., Figure 3E After adding the data of the eighth frame 38 of item (j), the values ​​of the first level 1ds unit, the first level 2ds unit, and the second level 2ds unit generated for the eighth frame 38 (i.e., the combination vector v8) will be equal to the values ​​of the third RS overhead unit 320C generated in operation (B3), the fourth RS overhead unit 350A generated in operation (B8), and the fifth RS overhead unit 350B, respectively.

[0079] Refer to operation (B10) again, as follows: Figure 3E As shown in item (k), the memory controller 1000 can use the third RS overhead unit 320C, the fourth RS overhead unit 350A, and the fifth RS overhead unit 350B to generate the third y vector y8 364 corresponding to the eighth frame 38. Then, in operation (B11), as Figure 3E As shown in item (l), the memory controller 1000 combines the y vector corresponding to the eighth frame 38 (i.e., the third y vector y8 364) and the x vector corresponding to the eighth frame 38 (the x vector x8 generated in operation (B9) of Algorithm 2 (i.e., the information bit 310 and intermediate BCH redundancy data 362 corresponding to the eighth frame 38)) to generate a combined vector v8 corresponding to the eighth frame 38. The combined vector v8 includes the information bit 310 corresponding to the eighth frame 38 and the final BCH redundancy data 363. At this time, as discussed above, if the level 1ds unit, the first level 2ds unit, and the second level 2ds unit are generated based on the eighth frame 38 (i.e., the combined vector v8), then the values ​​of the level 1ds unit, the first level 2ds unit, and the second level 2ds unit will be equal to the values ​​of the third RS overhead unit to the fifth RS overhead unit 320C, 350A, and 350B, respectively.

[0080] Figure 3F Example codeword 300 is shown, generated by performing projection BCH encoding algorithm according to at least some example embodiments of the inventive concept on information bits of the first frame 31 to the eighth frame 38 using algorithm 2. Figure 3F As shown, according to at least some example embodiments of the inventive concept, the amount of information bits in a frame may decrease as the amount of redundant data in the frame (e.g., BCH redundant data 313 corresponding to the first frame 31 to the fifth frame 35, the final BCH redundant data 333 corresponding to the sixth frame 36 and the seventh frame 37, and the final BCH redundant data 363 corresponding to the eighth frame 38) increases.

[0081] Next, in part V of this disclosure, an example method for generating BCH codewords with desired or optionally pre-fixed incremental checksum values ​​will be discussed.

[0082] V. Example method for generating BCH codewords with pre-fixed incremental checksum values.

[0083] The problem to be solved can be viewed as determining how to create BCH codewords such that the incremental checksum of the BCH codewords is guaranteed to have a desired or optionally pre-fixed (i.e., predetermined) value.

[0084] The example solutions to the problems mentioned above will now be discussed below with reference to Expressions 1 through 7. In Expressions 1 through 7 below, symbol A [B x C] Or A B x C Let A represent a matrix (or vector) of size B×C.

[0085] A solution to the problem mentioned above can be defined by referring to the following constraints, which determine how to create BCH codewords such that the incremental checksum values ​​of the BCH codewords have desired or optionally pre-fixed values:

[0086] Let v = [u, p] be an n-bit vector, where u is the data bits and p is the parity bit (e.g., with m bits). BCH (the size of ×t1 bits); and

[0087] It satisfies the following expression 1.

[0088]

[0089] Referring to Expression 1, the value Δs represents the incremental check constraint. For example, according to at least some example embodiments of the inventive concept, the incremental check constraint Δs may be associated with the aforementioned desired or optionally predetermined incremental check value. For example, according to at least some example embodiments of the inventive concept, the incremental check constraint Δs itself may be the aforementioned desired or optionally predetermined incremental check value.

[0090] According to at least some exemplary embodiments of the inventive concept, the solution mentioned above can be achieved by breaking the problem down into two parts:

[0091] 1. The information part x should satisfy the following expression 2.

[0092]

[0093] 2. Constraints It should satisfy the following expression 3.

[0094]

[0095] This can be achieved by considering the expression 4 below for m BCH The data u with ×t1 parity bits is encoded to satisfy expression 2.

[0096]

[0097] Expression 3 can be achieved through an algebraic solution. For example, according to at least some exemplary embodiments of the inventive concept, It is full rank. Therefore, expression 5 can be determined as follows.

[0098]

[0099] Therefore, the following expression 6 can be derived.

[0100]

[0101] As a result, the y value corresponding to the incremental check constraint Δs can be determined according to the following expression 7.

[0102]

[0103] Referring to Expression 7 above, according to at least some example embodiments of the inventive concept, the memory controller 1000 may store a matrix U for each error correction capability t. According to at least some example embodiments of the inventive concept, the matrix U is a predetermined matrix. For example, the matrix U may be determined and stored in the memory controller 1000 before the operation of Algorithm 1 and / or Algorithm 2 is executed. According to at least some example embodiments of the inventive concept, the matrix U is determined by the manufacturer or user of the memory controller 1000 and / or the memory system 900 (e.g., offline), and is stored by the memory controller 1000 (e.g., in ROM 113 and / or RAM 112) before the memory controller 1000 performs the ECC decoding operation. According to at least some example embodiments of the inventive concept, the matrix U discussed in this disclosure may be determined according to known methods. For example, according to at least one example embodiment of the inventive concept, the method described in U.S. Patent Application Publication No. 2019 / 0007062 may be used to determine the matrix U discussed in this disclosure.

[0104] Therefore, according to at least some example embodiments of the inventive concept, the memory controller 1000 can determine the y vector discussed above with reference to Algorithm 2 based on the incremental check constraint Δs and an appropriate U matrix that can be stored in the memory controller 1000. For example, a discussion will now be provided below of applying the method for generating BCH codewords with pre-fixed incremental check values ​​according to at least some example embodiments to operations (B4) to (B6) and operations (B9) to (B11) of Algorithm 2.

[0105] As noted in the discussion of Algorithm 2 above, as Figure 3C As shown in item (e), in operation (B4), the x vectors x6 and x7 are generated by encoding the sixth frame 36 and the seventh frame 37 using BCH codes with error correction capability of t1 = 7 bits.

[0106] By applying expression 2 above to operation (B4), it can be seen that and (where x6 and x7 are row vectors of length n, H) t1 It is a matrix of size m·t1×n.

[0107] As noted in the discussion of Algorithm 2 above, as Figures 3B to 3DAs shown, in operation (B5), the memory controller 1000 determines the y-vector y6 334A of the 6th frame and the y-vector y7 334B of the 7th frame, such that the y-vector y6 334A of the 6th frame and the y-vector y7 334B of the 7th frame are added to the x-vector x6 of the 6th frame and the x-vector x7 of the 7th frame, respectively, to generate the combined vector v6 of the 6th frame and the combined vector v7 of the 7th frame. The value of the level 1ds unit generated for the combined vector v6 of the 6th frame is equal to the value of the first RS overhead unit 320A, and the value of the level 1ds unit generated for the combined vector v7 of the 7th frame is equal to the value of the second RS overhead unit 320B. Furthermore, in operation (B6), the memory controller 1000 generates the combined vector v6 of the 6th frame by adding the x-vector x6 and the y-vector y6 of the 6th frame, and the memory controller 1000 generates the combined vector v7 of the 7th frame by adding the x-vector x7 and the y-vector y7 of the 7th frame.

[0108] By applying expression 7 above to operation (B5), the memory controller 1000 can perform operation (B5) by determining the y-vector y6 of the 6th frame and the y-vector y7 of the 7th frame according to expression 8 below:

[0109] y6=Δs6·U t1

[0110] y7=Δs7·U t1 (Expression 8)

[0111] According to at least some exemplary embodiments of the inventive concept, in expression 8, the 6th frame incremental check constraint Δs6 is defined by the value of the first RS overhead unit 320A predetermined in operation (B3); the 7th frame incremental check constraint Δs7 is defined by the value of the second RS overhead unit 320B, also predetermined in operation (B3); matrix U t1 It can be a pre-computed matrix stored in the memory controller 1000 and having a size of m·(t1-t0)×m·t1 (i.e., m·Δt×m·t1).

[0112] Therefore, the memory controller 1000 can perform operation (B6) by determining the 6th frame combination vector v6 and the 7th frame combination vector v7 according to the following expression 9:

[0113] v6 = [0 y6] + x6

[0114] v7 = [0 y7] + x7, (Expression 9)

[0115] Among them, for example Figure 3C As shown in terms (f) and (g), the y vector y6 of frame 6 and the y vector y7 of frame 7 can both be filled with nm·t1 zeros.

[0116] As noted in the discussion of Algorithm 2 above, as Figure 3E As shown in item (j), in operation (B9), the eighth frame x vector x8 is generated by encoding the eighth frame 38 using a BCH code with error correction capability of t2 = 9 bits.

[0117] When expression 2 above is applied to operation (B9), it can be seen that... (where x8 is a row vector of length n, H) t2 It is a matrix of size m·t²×n.

[0118] As noted in the discussion of Algorithm 2 above, as Figures 3D to 3E As shown, in operation (B10), the memory controller 1000 determines the y vector y8 364 of the 8th frame, such that the vector y8 364 is added to the x vector x8 of the 8th frame to generate the combined vector v8 of the 8th frame, and the values ​​of the first-level 1ds unit, the first-level 2ds unit, and the second-level 2ds unit generated for the combined vector v8 of the 8th frame will be equal to the values ​​of the third RS overhead unit 320C generated in operation (B3), the fourth RS overhead unit 350A generated in operation (B8), and the fifth RS overhead unit 350B, respectively.

[0119] Furthermore, in operation (B11), the memory controller 1000 generates the 8th frame combined vector v8 by adding the 8th frame x vector x8 and y vector y8 together.

[0120] By applying expression 7 above to operation (B10), the y-vector y8 of frame 8 can be determined according to expression 10 below:

[0121] y8=Δs8·U t2 (Expression 10)

[0122] According to at least some exemplary embodiments of the inventive concept, in expression 10, the 8th frame incremental check constraint Δs8 is defined by the value of the third RS overhead unit 320C generated in operation (B3), the value of the fourth RS overhead unit 350A generated in operation (B8), and the value of the fifth RS overhead unit 350B; matrix U t2 It can be a pre-computed matrix stored in the memory controller 1000 and having a size of m·(t2-t0)×m·t2 (i.e., m·Δt×m·t2).

[0123] Therefore, the memory controller 1000 can perform the operation (B11) by determining the 8th frame combination vector v8 according to the following expression 11.

[0124] v8 = [0 y8] + x8, (Expression 11)

[0125] Among them, for example Figure 3E As shown in terms (k) and (l), the y vector y8 of the 8th frame can be filled with nm·t2 zeros.

[0126] Example decoding operations based on at least some exemplary embodiments of the inventive concept are discussed below in part VI of this disclosure.

[0127] VI. Example Decoding Operation

[0128] According to at least some example embodiments of the inventive concept, at some point after extended HPC encoding and projected BCH encoding have been performed on HPC codeword 200 (i.e., in the manner discussed above with reference to Algorithms 1 and 2) and memory controller 1000 has stored HPC codeword 200 in memory device 2000, memory controller 1000 may read the stored HPC codeword 200 from memory device 2000. For example, memory controller may send one or more read commands to memory device 2000. Then, memory device 2000 may respond to one or more read commands by reading bits of HPC codeword 200 from memory cells (e.g., memory pages) of memory cell array 2100 that store HPC codeword 200 and sending the read bits of HPC codeword 200 to memory controller 1000. Furthermore, according to at least some example embodiments of the inventive concept, memory controller 1000 may decode the received HPC codeword 200 by performing an external code decoding operation after performing an internal code decoding operation (e.g., using decoder 1200).

[0129] For example, the internal code decoding operation may include sequentially decoding rows and columns of HPC codeword 200 (e.g., by performing extended Hamming code decoding on rows and columns of HPC codeword 200) to reduce decoding complexity. Furthermore, improved performance can be achieved by performing maximum likelihood decoding (MLD) of component codes (e.g., soft decoding). For example, according to at least some example embodiments, decoder 1200 may be able to perform soft-input / soft-output (SISO) decoding (e.g., as part of the internal code decoding operation) that can be used to obtain improved performance when decoding rows and columns of HPC codeword 200. For example, according to at least some example embodiments, decoder 1200 may be or include a SISO decoder. Regarding CTC (convolutional Turbo codes), using a SISO decoder (e.g., decoder 1200) for decoding rows and columns of HPC codeword 200, memory controller 1000 may iterate the sequential decoding of rows and columns of HPC codeword 200, thereby reducing the bit error rate (BER) after each iteration.

[0130] For example, the memory controller 1000 can use the decoder 1200 to perform SISO decoding on rows and then on columns, and vice versa. In each such iteration, soft data can be moved from row / column to column / row, and after multiple iterations, the algorithm can (with high probability) converge to a codeword that satisfies both the row condition and the column condition used for extended Hamming codes.

[0131] Then, after the aforementioned inner code decoding is completed, the memory controller 1000 can use the decoder 1200 to perform outer code decoding in order to correct any errors still present in the HPC codeword 200 (if any). The outer code decoding operation can be used to improve the error plane of the entire decoding operation and also verify that the HPC codeword 200 is error-free. An error plane may occur when the decoder 1200 finds a codeword that satisfies both the row and column conditions for extended Hamming codes, but the remaining error patterns have too many errors for the outer code to correct. However, according to at least some example embodiments of the inventive concept, the effectiveness of the outer code decoding operation performed by the memory controller 1000 can be improved by performing projective BCH encoding on the rows of the HPC codeword 200 according to Algorithm 2 discussed above, and thus the impact of the error plane associated with the outer code decoding operation can be reduced. An example outer code decoding operation according to at least some example embodiments of the inventive concept is shown below with Algorithm 3. The operation of Algorithm 3 is illustrated below using pseudocode. According to at least some example embodiments of the inventive concept, each operation of Algorithm 3 may be executed by or under the control of memory controller 1000 (e.g., using microprocessor 111).

[0132] Algorithm 3

[0133]

[0134] For the sake of simplicity, Algorithm 3 will be described below with reference to codeword 300. The following will refer to Algorithm 1 and Algorithm 2 (i.e., using Algorithm 2 to complete operation A2 of Algorithm 1). Figure 3F Algorithm 3 describes the case of encoding codeword 300.

[0135] Although for simplicity, Algorithm 3 is explained below with reference to 8 frames of data including bits in codeword 300, Algorithm 3 can be executed for more than 8 frames of data. For example, the memory controller 1000 can be configured to execute for data including bits in codeword 300. Figure 2 The algorithm 3 is executed using 192 frames of bits in the HPC codeword 200 shown in the figure.

[0136] In operation (C1), after the memory controller 1000 completes the above-mentioned internal code decoding operation on the rows and columns of codeword 300, the memory controller 1000 performs BCH decoding operation on the frames of codeword 300 (i.e., the first frame 31 to the eighth frame 38).

[0137] In operation (C2), the memory controller 1000 determines, according to a known BCH decoding method, which frames from the first frame 31 to the eighth frame 38 have been correctly decoded (referred to as "correct frames" in this disclosure) and which frames from the first frame 31 to the eighth frame 38 contain errors (referred to as "error frames" in this disclosure).

[0138] In operation (C3), for each correct frame from the first frame 31 to the eighth frame 38, the memory controller 1000 generates a level 1 to level N incremental checksum corresponding to the correct frame. According to at least some example embodiments of the inventive concept, N represents the maximum level for generating incremental checksums. Referring above... Figures 3A to 3F In the example of codeword 300 discussed, there are two levels of incremental checksums (e.g., Figure 3B The level 1 incremental checker 317A shown in item (c) and Figure 3D The term (i) shows the first-level 2-increment checksum 347A and the second-level 2-increment checksum 347B, therefore N = 2.

[0139] Operation (C3) also includes generating embedded RS redundancy data as an incremental checksum. Specifically, as described above... Figures 3A to 3F As discussed in part V of this disclosure, for combination vectors v6 and v7 (which correspond to the sixth frame 36 and the seventh frame 37 of codeword 300, respectively), the value of the level 1ds unit generated for combination vector v6 will be equal to the value of the first RS overhead unit 320A, and the value of the level 1ds unit generated for combination vector v7 will be equal to the value of the second RS overhead unit 320B. Therefore, in operation (C3), RS redundant data is embedded into the level 1ds units generated for the sixth frame 36 and the seventh frame 37.

[0140] In addition, as mentioned above... Figures 3A to 3F As discussed in part V of this disclosure, as Figures 3D to 3E As shown, for the combination vector v8 (which corresponds to the eighth frame 38 of codeword 300), the values ​​of the level 1ds unit, the first level 2ds unit, and the second level 2ds unit generated for the combination vector v8 will be equal to the values ​​of the third RS overhead unit 320C generated in operation (B3) of Algorithm 2, the fourth RS overhead unit 350A generated in operation (B8) of Algorithm 2, and the fifth RS overhead unit 350B, respectively. Therefore, in operation (C3), RS redundant data is embedded into the level 1ds unit and the level 2ds unit generated for the eighth frame 38.

[0141] In operation (C4), the memory controller 1000 uses RS redundancy embedded in the incremental checksums of correct frames (first frames 31 to eighth frames 38) to recover the incremental checksums of erroneous frames. For example, if the first frame 31 is an erroneous frame, the memory controller 1000 may not be able to reliably generate level 1 to level N incremental checksums using data including the erroneous first frame 31. However, if the sixth frames 36 to eighth frames 38 are correct frames, the memory controller 1000 can use RS overhead unit 320 (in... Figure 3B The RS incremental check subcodeword is generated by using the Level 1ds units of the first frame 31 (shown in item (d)) and other correct frames, such that the RS incremental check subcodeword includes bits of the RS overhead unit 320 as redundant bits, and bits of the Level 1ds units of the other correct frames as information bits. Furthermore, as long as the total number of erroneous frames in the first frame 31 to the eighth frame 38 does not exceed the Level 1 error line limit F1 (which is 3 for codeword 300, as discussed in part IV of this disclosure), the memory controller 1000 can perform an RS decoding operation on the aforementioned RS incremental check subcodeword to recover the Level 1ds unit corresponding to the first frame 31.

[0142] In operation (C5), for the erroneous frame corresponding to at least one incremental checksum recovered in operation (C4), the memory controller 1000 uses the recovered incremental checksum to re-perform BCH decoding with additional error correction capability Δt provided by the at least one recovered incremental checksum corresponding to the erroneous frame. For example, because the BCH decoding operation performed in operation (C1) has an error correction capability of t0 = 6 (less than 7), if the first frame 31 includes 7 error bits, the BCH decoding operation performed for the first frame 31 in operation (C1) will fail. However, with the help of the level 1 incremental checksum recovered in operation (C4) of the first frame 31, the BCH decoding operation performed by the memory controller 1000 in operation (C5) will have an error correction capability of t1 = 7, which will be sufficient to correct the 7 error bits in the first frame 31.

[0143] Then, in operation (C6), if the memory controller 1000 determines that the termination condition has been met, the memory device may terminate the external code decoding operation. Examples of termination conditions include, but are not limited to: the memory controller 1000 determining that all error frames have been corrected; and the memory device determining that the total number of error frames exceeds the error line limit Fi of the current level i of the external code decoding operation.

[0144] Furthermore, in operation (C6), if the memory controller 1000 determines that the termination condition has not been met, the memory controller 1000 returns to operation (C2) to determine the number of erroneous frames in the first to eighth frames. If the BCH decoding operation with improved error correction capability performed in operation (C5) is successful in correcting one or more erroneous frames, the total number of erroneous frames determined in subsequent iterations of operation (C2) will be reduced compared to previous iterations of operation (C2).

[0145] As operations (C2) through (C6) are executed iteratively, more error frames can be corrected during each iteration. Furthermore, with more error frames corrected, more incremental checksums can be generated by the memory controller 1000, thus increasing the chance of recovering higher-level incremental checksums. When higher-level incremental checksums are recovered, the number of error bits that can be corrected by the BCH decoding operation performed in operation (C5) increases, so error frames that have too many error bits to be corrected during early iterations of operation (C5) can be corrected through later iterations of operation (C5). According to at least some exemplary embodiments of the inventive concept, the i-th iteration of operations (C2) through (C6) corresponds to the i-th level foreign code decoding operation.

[0146] An example implementation of the memory system 900 will now be discussed in part VII of this disclosure below.

[0147] VII. Implementation Example

[0148] Figure 4 This is a block diagram illustrating a computer system 3000 including a memory system according to at least one example embodiment of the inventive concept. The computer system 3000 (such as a mobile device, desktop computer, and server) may employ a memory system 3400 according to at least one example embodiment of the inventive concept.

[0149] Computer system 3000 may include a central processing unit (CPU) 3100, RAM 3200, user interface 3300, and memory system 3400 electrically connected to bus 3500. The host computer, as described above, may include the CPU 3100, RAM 3200, and user interface 3300 within computer system 3000. CPU 3100 can control the entire computer system 3000 and perform calculations corresponding to user commands input via user interface 3300. RAM 3200 can be used as data storage for CPU 3100, and CPU 3100 can write data to / read data from memory system 3400.

[0150] As in the example embodiments of the above-described inventive concept, the memory system 3400 may include a memory controller 3410 and a memory device 3420.

[0151] According to at least one exemplary embodiment of the inventive concept, the memory controller 3410 may be described above with reference to... Figures 1 to 2 The memory controller 1000 discussed above is used to implement this, and the memory device 3420 can be implemented as described above. Figures 1 to 2 The memory device discussed is implemented in 2000.

[0152] Figure 5 This is a block diagram illustrating a memory card 4000 according to at least one exemplary embodiment of the inventive concept. (Referring to the above reference...) Figures 1 to 3F The memory system 900 of at least some example embodiments of the inventive concept discussed may be a memory card 4000. For example, the memory card 4000 may include an embedded multimedia card (eMMC) or a secure digital card (SD). Figure 5 As shown, the memory card 4000 may include a memory controller 4100, non-volatile memory 4200, and a port area 4300. According to at least one exemplary embodiment of the inventive concept, Figure 5 The memory controller 4100 shown above can be referenced from the above. Figures 1 to 3F The memory controller 1000 discussed is used for implementation. Figure 5 The non-volatile memory 4200 shown above can be referenced from the above. Figures 1 to 3F The memory device discussed is implemented in 2000.

[0153] The memory controller 4100 can communicate with an external host via port area 4300 according to a preset protocol. This protocol can be eMMC, SD, SATA, SAS, or USB.

[0154] Figure 6 This is a block diagram illustrating an example network system 5000 including a memory system according to at least one example embodiment of the inventive concept. Figure 6 As shown, network system 5000 may include server system 5100 and multiple terminals 5300, 5400, and 5500 connected via network 5200. Server system 5100 may include server 5110 and SSD 5120, wherein server 5110 is used to process requests received from the multiple terminals 5300, 5400, and 5500 connected to network 5200, and SSD 5120 is used to store data corresponding to the requests received from terminals 5300, 5400, and 5500. Here, SSD 5120 may be a memory system according to at least one example embodiment of the inventive concept.

[0155] According to at least one exemplary embodiment of the inventive concept, the SSD 5120 can be described above with reference to... Figures 1 to 3F The memory system discussed is implemented using 900.

[0156] Furthermore, the memory system according to the exemplary embodiments of the inventive concept can be mounted via any of a variety of packages. For example, the memory system according to at least one exemplary embodiment of the inventive concept can be mounted via any of the following packages: PoP (PoS), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Chip Carrier with Leads (PLCC), Plastic Dual In-line Package (PDIP), Waffle Die Package, Die in Wafer Form, Chip on Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Package (TQFP), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer-Scale Fabrication Package (WFP), Wafer-Scale Process Stacked Package (WSP), etc.

[0157] Having described exemplary embodiments of the inventive concept, it will be apparent that these exemplary embodiments can be modified in various ways. Such modifications should not be considered as departing from the intended spirit and scope of the exemplary embodiments of the inventive concept, and it will be apparent to those skilled in the art that all such modifications are intended to be included within the scope of the claims.

Claims

1. A memory system, comprising: Memory controller; as well as Memory devices, The memory controller is configured as follows: The first error correction code is encoded on multiple first frames of data. Multiple incremental verification sub-units are generated for each of the multiple first frames of data, and each of the multiple incremental verification sub-units corresponds one-to-one with each of the multiple first frames of data. Incremental check codewords are generated by cascading multiple incremental check sub-units and performing second error correction code encoding on the cascaded incremental check sub-units. Each incremental check codeword includes one or more redundant data units. At least one second frame of the data is encoded using a third error-correcting code such that the encoded at least one second frame of the data is a first vector of bits, wherein the at least one second frame of the data follows the plurality of first frames of the data. A second vector of bits is determined such that the value of another incremental check subunit, generated based on a combination vector of bits that is the sum of the first and second vectors of bits, is pre-fixed based on at least one of the one or more redundant data units. A combined vector of bits is generated by adding the second vector of bits to the first vector of bits, and In this context, rows of data are called frames.

2. The memory system according to claim 1, wherein, The memory controller is also configured to, Hamming product codewords are generated by performing extended Hamming code encoding on columns of bits in a combination vector of multiple first frames and bits of the encoded data, and... The Hamming product codewords are stored in a memory device.

3. The memory system according to claim 2, wherein, The memory controller is also configured such that the first and third error correction codes are Bos-Joherry-Hokvenheim codes.

4. The memory system according to claim 3, wherein, The memory controller is also configured such that the second error correction code encoding is Reed-Solomon encoding.

5. The memory system according to claim 1, in, The memory controller is also configured such that, The memory controller receives multiple information bits from an external device. The memory controller arranges the plurality of information bits into a two-dimensional array of bits comprising multiple rows and multiple columns, and The memory controller performs extended Hamming code encoding on the plurality of columns of the bit array, thereby generating a plurality of columns of extended Hamming code encoded bits. Wherein, each frame of data in the plurality of first frames and the at least one second frame of data is a row of bits in a plurality of columns of extended Hamming code encoding, such that the plurality of first frames of data encoding and the bit combination vector are frames of Hamming product codewords, and The memory controller is also configured to store Hamming product codewords in the memory device.

6. The memory system according to claim 5, wherein, The memory controller is also configured such that the first and third error correction codes are Bos-Joherry-Hokvenheim codes.

7. The memory system according to claim 6, wherein, The memory controller is also configured such that the second error correction code encoding is Reed-Solomon encoding.

8. A memory system, comprising: Memory controller; as well as Memory devices, The memory controller is configured as follows: Read multiple frames of data from the memory device. By performing first error correction code decoding on the plurality of frames of data, errors in one or more frames of data are corrected. After the first error-correcting code is decoded, multiple correct frames and at least one erroneous frame are identified among the multiple frames of the data. Multiple incremental verification subunits are generated based on the multiple correct frames, and each of the multiple incremental verification subunits corresponds one-to-one with the multiple correct frames. Based on the multiple correct frames, the multiple incremental check subunits generate incremental check sub-error correction codewords including information bits and redundant bits, so that... The redundant bits of the incremental check sub-error correction code codeword are bits from at least one of the generated incremental check sub-units, and The information bits of the incremental check sub-error correction code codeword are bits from one or more incremental check sub-units among the generated plurality of incremental check sub-units, excluding the at least one incremental check sub-unit. By performing second error correction code decoding on the incremental check sub-error correction code codeword, the incremental check sub-unit corresponding to the at least one erroneous frame is recovered, and In this context, rows of data are called frames.

9. The memory system according to claim 8, wherein, The memory controller is also configured to read the plurality of frames of data from the memory device by reading Hamming product codewords from the memory device, wherein the Hamming product codewords comprise the plurality of frames of data.

10. The memory system according to claim 8, wherein, The memory controller is also configured to perform Booz-Joherry-Hokvenheim decoding on the at least one erroneous frame using a recovered incremental check subunit, wherein the recovered incremental check subunit is data that adds error correction capability to redundant data included in the at least one erroneous frame.

11. The memory system according to claim 8, wherein, The memory controller is also configured such that the first error correction code decoding is Bosch-Joherry-Hokvenheim decoding.

12. The memory system according to claim 11, wherein, The memory controller is also configured such that the second error-correcting code decoding is Reed-Solomon decoding.

13. The memory system according to claim 12, wherein, The memory controller is also configured to perform Bosch-Joherry-Hokvenheim decoding on the at least one erroneous frame using a recovered incremental check subunit, wherein the recovered incremental check subunit is data that increases the error correction capability of the Bosch-Joherry-Hokvenheim redundant data included in the at least one erroneous frame.

14. A method of operating a memory system including a memory controller and a memory device, the method comprising: Perform first error correction coding on multiple first frames of data; Multiple incremental verification sub-units are generated for the multiple first frames of data, and the multiple incremental verification sub-units correspond one-to-one with the multiple first frames of data. Incremental check codewords are generated by cascading multiple incremental check sub-units and performing second error correction code encoding on the cascaded multiple incremental check sub-units, wherein the incremental check codewords include one or more redundant data units. A third error-correcting code is performed on at least one second frame of the data such that the encoded at least one second frame of the data is a first vector of bits, and the at least one second frame of the data follows the plurality of first frames of the data; A second vector of bits is determined such that the value of the incremental check sub-unit, generated based on a combination vector of bits that is the sum of the first and second vectors of bits, is pre-fixed based on at least one of the one or more redundant data units. A combined vector of bits is generated by adding the second vector of bits to the first vector of bits, and In this context, rows of data are called frames.

15. The method of claim 14, further comprising: Hamming product codewords are generated by performing extended Hamming code encoding on columns of bits in a combination vector of multiple first frames and bits of the encoded data, and... The Hamming product codewords are stored in a memory device.

16. The method according to claim 15, wherein, The first and third error-correcting codes are Bos-Joherry-Hokvenheim codes.

17. The method according to claim 16, wherein, The second error-correcting code is the Reed-Solomon code.

18. The method of claim 14, further comprising: Receive multiple information bits from an external device; The multiple information bits are arranged into a two-dimensional array of bits comprising multiple rows and multiple columns; Extended Hamming code encoding is performed on the multiple columns of the bit array to generate multiple columns of bit extended Hamming code encoding; Each frame of data in the plurality of first frames of data and the at least one second frame of data is a row of bits in a plurality of columns of extended Hamming code encoding, such that the plurality of first frames of data encoding and the combination vector of bits are frames of Hamming product codewords. as well as The Hamming product codewords are stored in a memory device.

19. The method according to claim 18, wherein, The first and third error-correcting codes are Bos-Joherry-Hokvenheim codes.

20. The method according to claim 19, wherein, The second error-correcting code is the Reed-Solomon code.

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