Interconnect structure, semiconductor package and method of manufacturing the same

Abstract

This invention relates to an interconnect structure, a semiconductor package, and a method for manufacturing the same. An interconnect structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a first surface and a second surface, both facing the first dielectric layer. The first surface of the second dielectric layer is recessed from the second surface of the second dielectric layer, defining a notch. A portion of the first dielectric layer is disposed within the notch.

Description

Technical Field

[0001] This disclosure generally relates to an interconnect structure, and more specifically to an interconnect structure comprising one or more dielectric layers and a method for manufacturing the same. Background Technology

[0002] Interconnect structures, such as internal inserts / substrates, are often used for electrical connections / layouts between different electrical components, such as between semiconductor dies and motherboards. Different electrical components may have different input / output (I / O) terminal densities; for example, semiconductor dies may have a higher I / O terminal density than motherboards. Interconnect structures with high-density circuitry (e.g., redistribution layers) may be required, which may necessitate larger dimensions or thicknesses and could lead to defects such as solder short circuits, warping / deformation, and cracking / delamination. Summary of the Invention

[0003] In one aspect, according to some embodiments, an interconnect structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a first surface and a second surface, both facing the first dielectric layer. The first surface of the second dielectric layer is recessed from the second surface of the second dielectric layer and defines a notch. A portion of the first dielectric layer is disposed within the notch.

[0004] In another aspect, according to some embodiments, a semiconductor package includes a first interconnect layer and a second interconnect layer. The first interconnect layer has a first conductive layer and a first dielectric layer that at least partially covers the first conductive layer. The second interconnect layer has a second conductive layer and a second dielectric layer that at least partially covers the second conductive layer. The first interconnect layer is at least partially surrounded by the second interconnect layer. The material of the first dielectric layer is different from the material of the second dielectric layer.

[0005] In another aspect, according to some embodiments, a method of manufacturing an interconnect structure includes: providing a carrier; forming a patterned seed layer on the carrier; forming a patterned metal layer on the patterned seed layer; forming a first dielectric layer on the carrier to surround the patterned seed layer and the patterned metal layer; removing the carrier; removing the seed layer to form a notch defined by the surface of the patterned metal layer and the surface of the first dielectric layer; and forming a second dielectric layer in the notch and on the surface of the first dielectric layer. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale, and the dimensions of the features depicted in the drawings may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0008] Figure 1B An enlarged view of a portion of a semiconductor package according to some embodiments of the present disclosure is shown.

[0009] Figure 2 A cross-sectional view of a portion of a semiconductor package according to some embodiments of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of a portion of a semiconductor package according to some embodiments of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0013] Figure 6 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0015] Figure 8A and 8B Different types of semiconductor device packages are shown according to some embodiments of this application.

[0016] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F This is a cross-sectional view of a portion of a semiconductor package manufactured at various stages according to some embodiments of the present disclosure.

[0017] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I , Figure 10J , Figure 10K , Figure 10L , Figure 10M and Figure 10N This is a cross-sectional view of the interconnect layer manufactured at various stages according to some embodiments of the present disclosure.

[0018] Figure 11A , Figure 11B , Figure 11C, Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 11H , Figure 11I , Figure 11J , Figure 11K , Figure 11L , Figure 11M , Figure 11N , Figure 11O , Figure 11P , Figure 11Q , Figure 11R , Figure 11S , Figure 11T , Figure 11U , Figure 11V , Figure 11W , Figure 11X , Figure 11Y , Figure 11Z , Figure 11AA , Figure 11AB and Figure 11AC This is a cross-sectional view of a semiconductor package at various stages according to some embodiments of the present disclosure.

[0019] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0020] Some embodiments of this disclosure disclose an interconnect structure comprising two interconnect layers, each interconnect layer having a conductive layer and a dielectric layer. The two conductive layers may have different spacing or density. The interface between the dielectric layers of the two interconnect layers may have non-coplanar or discontinuous surfaces. The dielectric layers of the two interconnect layers may be made of different materials having different coefficients of thermal expansion (CTE) or different moduli. Through embodiments of this disclosure, cracking or delamination between the two interconnect layers due to thermal stress or warping can be prevented or reduced.

[0021] Figure 1A A cross-sectional view of a semiconductor package 100 according to some embodiments of the present disclosure is shown. The semiconductor package 100 may include, be, or be part of an interconnect structure. Figure 1B Show Figure 1A An enlarged view of part 1b of the semiconductor package 100.

[0022] Semiconductor package 100 includes interconnect layers J1, J2, J3, and J4. Interconnect layer J1 is at least partially surrounded by interconnect layer J2. Interconnect layer J3 is at least partially surrounded by interconnect layer J4. Interconnect layers J1 and J3 may have the same or similar characteristics. Interconnect layers J2 and J4 may have the same or similar characteristics and are electrically connected by conductors C1, C2, and C3, which may be conductive pillars or vias.

[0023] See Figure 1A and Figure 1B Interconnect layer J1 includes a conductive layer 50, a dielectric layer 20, a metal layer 30, and a connecting element 80. Interconnect layer J2 includes a conductive layer 60, a dielectric layer 10, a conductive via 40, an underfill adhesive 70, and a patterned insulating layer 90.

[0024] The spacing of the conductive layers 50 may be smaller than the spacing of the conductive layers 60. In some embodiments, the spacing of the conductive layers 50 is equal to or less than 7 μm. The density of the conductive layers 50 may be greater than the density of the conductive layers 60. The conductive layers 50 and 60 may comprise, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel, or mixtures, alloys, or other combinations thereof.

[0025] The dielectric layer 20 covers the conductive layer 50. In some embodiments, the dielectric layer 20 may partially cover and partially expose the conductive layer 50. The dielectric layer 20 is partially covered or surrounded by an underfill adhesive 70. The dielectric layer 10 at least partially covers the conductive layer 60.

[0026] In some embodiments, the material of the dielectric layer 10 of interconnect layer J2 is different from the material of the dielectric layer 20 of interconnect layer J1. For example, the coefficient of thermal expansion (CTE) of dielectric layer 10 may be greater than the CTE of dielectric layer 20. The modulus of dielectric layer 10 may be greater than the modulus of dielectric layer 20. In some embodiments, dielectric layer 10 comprises polypropylene (PP). In some embodiments, dielectric layer 20 comprises polyamide (PA).

[0027] like Figure 1B As shown, dielectric layer 20 is disposed on dielectric layer 10. Dielectric layer 20 includes surface 201 and surface 202, both of which face dielectric layer 10. Surface 201 is recessed from surface 202 and defines a notch R1. Surface 201 and surface 202 are discontinuous and are connected by surface 203 of dielectric layer 20.

[0028] The dielectric layer 10 includes a surface 101 and a surface 102. Surface 101 faces surface 201 of the dielectric layer 20, and surface 102 faces surface 202 of the dielectric layer 20. Surface 101 protrudes from or extends beyond surface 102. A portion of the dielectric layer 10 is disposed within a recess R1.

[0029] like Figure 1A and Figure 1BAs shown, the metal layer 30 of the interconnect layer J1 is disposed on and in contact with the surface 201 of the dielectric layer 20. The metal layer 30 is disposed within a recess R1, that is, the metal layer 30 is recessed from the surface 202 of the dielectric layer 20. The metal layer 30 can be completely accommodated in the recess R1, and the surface 301 of the metal layer 30 is not coplanar with the surface 202 of the dielectric layer 20. The surface 301 of the metal layer 30 contacts the surface 101 of the dielectric layer 10. Figure 1B As shown, the distance T1 between the surface 102 of dielectric layer 10 and the surface 201 of dielectric layer 20 is greater than the thickness T2 of metal layer 30. Metal layer 30 may contain, for example, Al, Cu, Cr, Sn, Au, Ag, Ni or stainless steel, or mixtures, alloys or other combinations thereof.

[0030] like Figure 1A and Figure 1B As shown, the conductive via 40 connects the conductive layer 60 of interconnect layer J2 and the metal layer 30 of interconnect layer J1. A portion of the conductive via 40 is disposed within or protrudes into the recess R1 and contacts the metal layer 30. The conductive via 40 is surrounded or encapsulated by the dielectric layer 10. The conductive via 40 may have a tapered shape, and the thickness / width / diameter of the portion of the conductive via 40 away from the metal layer 30 may be greater than the thickness / width / diameter of the portion of the conductive via 40 adjacent to the metal layer 30.

[0031] like Figure 1A As shown, the interface IF between interconnect layers J1 and J2 includes surface IF1 and surface IF2. Surface IF1 is defined between the metal layer 30 of interconnect layer J1 and the dielectric layer 10 of interconnect layer J2. Surface IF2 is defined between the dielectric layer 20 of interconnect layer J1 and the dielectric layer 10 of interconnect layer J2. Surfaces IF1 and IF2 are discontinuous and non-coplanar. Figure 1A In the illustrated embodiment, surface IF1 and surface IF2 are parallel to each other.

[0032] In some embodiments, the different materials between interconnect layers J1 and J2 can lead to stress (e.g., lateral stress) accumulation near the interface IF during various manufacturing processes that may include various temperature cycles. The discontinuity or non-coplanarity of the interface IF, or the material configuration (e.g., CTE or modulus) of the dielectric layers 10 and 20, can prevent stress from extending through the interface IF, thus preventing cracking or delamination between interconnect layers J1 and J2.

[0033] The connection element 80 of interconnect layer J1 is surrounded by the bottom filler 70 of interconnect layer J2 and is electrically connected to the conductor of interconnect layer J4. The connection element 80 may contain solder balls.

[0034] A patterned insulating layer 90 of interconnect layer J2 is disposed on conductive layer 60 and exposes a portion of conductive layer 60. The patterned insulating layer 90 may contain solder resist material. The exposed portion of conductive layer 60 can be used for external electrical connections.

[0035] like Figure 1A As shown, the semiconductor package 100 further includes a connection element C6, which may be part of the interconnect layer J4. The connection element C6 may contain solder and may have a square, circular, rectangular, flat, or domed shape. The connection element C6 can be used to electrically connect to another electrical device.

[0036] The underfill adhesive 70 of interconnect layer J2 or interconnect layer J4 may comprise or may be capillary underfill adhesive (CUF) or molded underfill adhesive (MUF). In some embodiments, the underfill adhesive 70 may be or may comprise an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) containing conductive particles. In some embodiments, the conductive particles within the ACF or ACP may replace the connecting element 80 for electrical connections between different interconnect layers.

[0037] Figure 2 A cross-sectional view of a portion 200 of a semiconductor package according to some embodiments of the present disclosure is shown.

[0038] like Figure 2 As shown, interconnect layers J2 and J4 are connected via connecting element 80, which is connected to conductive vias in interconnect layers J2 and J4 and surrounded by underfill adhesive 70 disposed between interconnect layers J2 and J4. The surface of the conductive via in interconnect layer J4 defines a pit or protrusion D1. The surface of the conductive via in interconnect layer J2 defines a pit or protrusion D2. The surface of the dielectric layer in interconnect layer J4 defines a pit or protrusion D3. The surface of the dielectric layer in interconnect layer J2 defines a pit or protrusion D4.

[0039] Recesses D1, D2, D3, and D4 can be created by shrinkage involved in manufacturing operations such as curing. The size or height of recess D1 or D3 can be proportional to the density of conductive vias within interconnect layer J4. The size or height of recess D2 or D4 can be proportional to the density of conductive vias within interconnect layer J2.

[0040] exist Figure 1A In the illustrated embodiment, connection element 80 is used for the connection between interconnect layer J1 and interconnect layer J4. In some embodiments, connection element 80 may be omitted. For example, see... Figure 1A and Figure 3 , Figure 1A Part 3b of the semiconductor package 100 can be Figure 3The structure shown is an alternative, in which conductor C4 is implemented to connect conductor C5 of interconnect layer J1 and conductor C3 of interconnect layer J4, which can be achieved by direct metal-to-metal bonding.

[0041] Figure 4 A cross-sectional view of a semiconductor package 400 according to some embodiments of the present disclosure is shown. The semiconductor package 400 is similar to... Figure 1A The semiconductor package 100 described below has some differences.

[0042] Interconnect layer J1 and interconnect layer J3 are directly connected. For example... Figure 4 As shown, the conductive layer 50 of interconnect layer J1 is electrically connected to the conductive layer 50 of interconnect layer J3 via a connecting element 80. That is, there may not be another conductive layer with a relatively low density or large spacing between the conductive layer 50 of interconnect layer J1 and the conductive layer 50 of interconnect layer J3.

[0043] Figure 5 A cross-sectional view of a semiconductor package 500 according to some embodiments of the present disclosure is shown. The semiconductor package 500 is similar to... Figure 1A In the semiconductor package 100, only a portion of the conductor C3 of the interconnect layer J4 is hollow, allowing a portion of the underfill adhesive 70 of the interconnect layer J2 to be disposed therein. In other words, a portion of the underfill adhesive 70 is surrounded by the conductor C3, which enhances the structural strength of the semiconductor package 500.

[0044] Figure 6 A cross-sectional view of a semiconductor package 600 according to some embodiments of the present disclosure is shown. The semiconductor package 600 is similar to... Figure 1A The semiconductor package 100 in this example simply implements conductive lines to electrically connect different interconnect layers. For instance, conductive line W1 electrically connects the metal layer 30 of interconnect layer J1 to the conductive layer 65 of interconnect layer J4, and conductive line W2 electrically connects the metal layer 30 of interconnect layer J1 to the conductive layer 67 of interconnect layer J4. Conductive lines W1 and W2 may contain Cu, Au, solder, Ag, Ni, Al, or alloys thereof.

[0045] Figure 7 A cross-sectional view of a semiconductor device package 700 according to some embodiments of the present disclosure is shown. The semiconductor device package 700 includes semiconductor packages 710 and 720, electronic components 730 and 740, and conductor 750.

[0046] Semiconductor packages 710 and 720 and Figure 1AThe semiconductor package 100 is the same as or similar to that in the semiconductor package 710. Semiconductor package 720 is disposed on semiconductor package 710 and electrically connected to semiconductor package 710 via conductor 750, which may include conductive pillars or bumps. Electronic components 730 and 740 are disposed on or bonded to semiconductor packages 720 and 710, respectively, which may involve flip-chip bonding, wire bonding, or die attach film (DAF) bonding.

[0047] Figure 8A and 8B Different types of semiconductor device packages according to some embodiments of this application are illustrated. Semiconductor device packages may be combined with each other or with external devices.

[0048] like Figure 8A As shown, a plurality of chips, dies, or semiconductor device packages 81 are placed on a square carrier 82. In some embodiments, the carrier 82 may comprise organic materials (e.g., molding compounds, BT, PI, PBO, solder resist, ABF, PP, epoxy materials, or combinations of two or more thereof), or inorganic materials (e.g., silicon, glass, ceramics, quartz, or combinations of two or more thereof), or combinations of two or more thereof.

[0049] like Figure 8B As shown, multiple chips, dies, or semiconductor device packages 81 are placed on a circular carrier 83. In some embodiments, the carrier 83 may comprise organic materials (e.g., molding compounds, BT, PI, PBO, solder resist, ABF, PP, epoxy materials, or combinations of two or more thereof), or inorganic materials (e.g., silicon, glass, ceramics, quartz, or combinations of two or more thereof), or combinations of two or more thereof.

[0050] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F This is a cross-sectional view of a portion of a semiconductor package manufactured at various stages according to some embodiments of the present disclosure.

[0051] See Figure 9A A carrier CR is provided. The carrier CR may comprise glass or epoxy resin. A seed layer S1 is formed on the carrier CR. The seed layer S1 may comprise a metallic material and can be formed by a plating operation. See also Figure 9B A photoresist (PR) layer P1 is formed on a seed layer S1, where a coating operation can be performed. A portion of the PR layer P1 and a portion of the seed layer S1 are removed, thereby patterning the seed layer S1, which may involve development and etching operations.

[0052] See Figure 9CRemove the PR layer P1. A metal layer (or patterned metal layer) 30 is formed on the seed layer S1, where a plating operation can be performed. See below. Figure 9D A dielectric layer 20 is formed on the carrier CR to cover or surround the seed layer S1 and the metal layer 30. In some embodiments, the dielectric layer 20 may comprise polyamide (PA).

[0053] See Figure 9E Remove the carrier CR. Remove the seed layer S1, where an etching operation can be performed. Form a notch R1 defined by the surface 203 of the dielectric layer 20 and the surface 301 of the metal layer 30.

[0054] See Figure 9F A dielectric layer 10 is formed on a dielectric layer 20 and a metal layer 30. A portion of the dielectric layer 10 is located in a notch R1. A conductive via 40 is formed within the dielectric layer 10 and contacts the metal layer 30. An interface IF is formed comprising surfaces IF1 and IF2. Surface IF1 is defined between the metal layer 30 and the dielectric layer 10. Surface IF2 is defined between the dielectric layer 20 and the dielectric layer 10. Surfaces IF1 and IF2 are discontinuous and not coplanar with respect to each other. In some embodiments, the CTE of the dielectric layer 10 may be greater than the CTE of the dielectric layer 20. In some embodiments, the modulus of the dielectric layer 10 may be greater than the modulus of the dielectric layer 20.

[0055] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I , Figure 10J , Figure 10K , Figure 10L , Figure 10M and Figure 10N This is a cross-sectional view of the interconnect layer 10n manufactured at various stages according to some embodiments of the present disclosure.

[0056] See Figure 10A A carrier CR is provided. The carrier CR may comprise glass or epoxy resin. A seed layer S2 is formed on the carrier CR. The seed layer S1 may comprise a metallic material and can be formed by a plating operation or a physical vapor deposition (PVD) operation. See also Figure 10B The PR layer P2 is formed on the seed layer S2, where coating or photolithography operations can be performed. Exposure operations can be performed on the PR layer P2.

[0057] See Figure 10CThe PR layer P2 is developed. A portion of the PR layer P2 is removed, where an etching operation can be performed. A portion of the seed layer S2 is exposed. A metal layer 30 is disposed on the exposed seed layer S2, where a plating operation can be performed. See below. Figure 10D The portions of PR layer P2 and seed layer S2 corresponding to PR layer P2 are removed, where etching operations can be performed.

[0058] See Figure 10E A dielectric layer (or dielectric material) 20 is formed on the carrier CR and the metal layer 30, wherein coating and photolithography operations can be performed. Exposure operations can also be performed. See below. Figure 10F A portion of the dielectric layer 20 is removed to expose the metal layer 30, where development or etching operations can be performed. A seed layer S3 is conformally formed on the dielectric layer 20 and contacts the metal layer 30.

[0059] See Figure 10G The PR layer P3 is formed on the seed layer S3, where coating and photolithography operations can be performed. Exposure operations can also be performed. See [link / reference] Figure 10H A portion of the PR layer P3 is removed to expose the seed layer S3, where an etching operation can be performed. A metal layer M1 is conformally formed on the seed layer S3, where a plating operation can be performed.

[0060] See Figure 10I The portions of PR layer P3 and seed layer S3 corresponding to PR layer P3 are removed, allowing for etching operations. See also... Figure 10J The dielectric layer (or dielectric material) 20 is formed in Figure 10I The structure within it allows for coating and photolithography operations. Exposure operations can also be performed.

[0061] See Figure 10K A portion of the dielectric layer 20 is removed to expose the metal layer M1, where development or etching operations can be performed. A seed layer S4 is conformally formed on the dielectric layer 20 and contacts the metal layer M1. See [link / reference] Figure 10L The PR layer P4 is formed on the seed layer S4, where coating and photolithography operations can be performed. Exposure operations can also be performed.

[0062] See Figure 10M The PR layer P4 is developed. A portion of the PR layer P4 is removed to expose the seed layer S4. A metal layer M2 is disposed on the exposed seed layer S4, and a connecting element 80 is disposed on the metal layer M2, wherein plating or screen printing operations can be performed. The connecting element 80 is surrounded by the PR layer P4. See [reference needed] Figure 10N The portions of PR layer P4 and seed layer S4 corresponding to PR layer P4 are removed to form interconnect layer 10n, in which etching or photolithography can be performed.

[0063] Figure 11A, Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 11H , Figure 11I , Figure 11J , Figure 11K , Figure 11L , Figure 11M , Figure 11N , Figure 11O , Figure 11P , Figure 11Q , Figure 11R , Figure 11S , Figure 11T , Figure 11U , Figure 11V , Figure 11W , Figure 11X , Figure 11Y , Figure 11Z , Figure 11AA , Figure 11AB and Figure 11AC This is a cross-sectional view of the semiconductor package 11ac at various stages according to some embodiments of the present disclosure.

[0064] See Figure 11A A carrier CR is provided. The carrier CR can be a wafer or a panel. A dielectric layer (or dielectric material) 10 is disposed on the carrier CR, wherein lamination, screen printing, or coating operations can be performed. See also Figure 11B A portion of the dielectric layer 10 is removed to expose the carrier CR, where laser drilling or etching operations can be performed. A seed layer S5 is conformally disposed on the dielectric layer 10.

[0065] See Figure 11C Metal layer M3 is disposed on seed layer S5, wherein plating (e.g., full plating) operations can be performed. See Figure 11D The PR layer P5 is formed on the metal layer M3, where coating or photolithography operations can be performed. Exposure operations can also be performed.

[0066] See Figure 11E A portion of the PR layer P5 is removed to expose the metal layer M3, where an etching operation can be performed. See [link / reference] Figure 11F Remove Figure 11E The structure includes a PR layer P5, a portion of a metal layer M3 exposed from the PR layer P5, and a portion of a seed layer S5, where etching operations can be performed.

[0067] See Figure 11G , Figure 10N The interconnect layer 10n in the middle is combined with Figure 11FThe structure includes an interconnect layer 10n with interconnecting elements 80 bonded to a metal layer M3, where a thermocompression bonding operation can be performed. See also... Figure 11H The bottom filler 70 is placed on the dielectric layer 10 to surround the interconnect element 80 of the interconnect layer 10n, wherein application and curing operations can be performed.

[0068] See Figure 11I Remove the carrier CR from interconnect layer 10n. See also Figure 11J The seed layer S2 of interconnect layer 10n is removed to form interconnect layer J1, where an etching operation can be performed. Interconnect layer J1 can be similar to... Figure 1A Interconnect layer J1 of semiconductor package 100.

[0069] See Figure 11K The dielectric layer 10 (or dielectric material) is formed in Figure 11J The structure is covered or encapsulated by an interconnect layer J1, in which coating or lamination operations can be performed. See also Figure 11L A portion of the dielectric layer 10 is removed to expose the metal layer 30 of the metal layer M3 and the interconnect layer J1, where laser drilling can be performed. A seed layer S6 is conformally formed on the dielectric layer 10.

[0070] See Figure 11M Metal layer M4 is formed on seed layer S6, where plating operations can be performed. See also Figure 11N The PR layer P6 is formed on the metal layer M4, where coating or photolithography operations can be performed. Exposure operations can also be performed. See [link / reference] Figure 11O A portion of the PR layer P6 is removed to expose the metal layer M4, where an etching operation can be performed.

[0071] See Figure 11P Remove Figure 11O The PR layer P6, a portion of the metal layer M4 exposed from the metal layer M4, and a portion of the seed layer S6, are where etching operations can be performed. See also Figure 11Q , Figure 10N Another interconnect layer 10n in the middle is combined with Figure 11P The structure in which the interconnecting element 80 of the interconnecting layer 10n is bonded to the metal layer M4, wherein a thermocompression bonding operation can be performed.

[0072] See Figure 11R The bottom filler 70 is disposed on the dielectric layer 10 to surround the connecting element 80 of the interconnect layer 10n, wherein application and curing operations can be performed. See below. Figure 11S Remove the carrier CR from interconnect layer 10n. See [link / reference] Figure 11T The seed layer S2 of interconnect layer 10n is removed to form interconnect layer J1, where an etching operation can be performed. Interconnect layer J1 can be similar to... Figure 1AInterconnect layer J1 of semiconductor package 100.

[0073] See Figure 11U The dielectric layer 10 (or dielectric material) is formed in Figure 11T The structure is covered or encapsulated by an interconnect layer J1, in which coating or lamination operations can be performed. See also Figure 11V A portion of the dielectric layer 10 is removed to expose the metal layer M4 and the metal layer 30 of the interconnect layer J1, where laser drilling can be performed. A seed layer S7 is conformally formed on the dielectric layer 10.

[0074] See Figure 11W Metal layer M5 is formed on seed layer S7, where plating operations can be performed. See also Figure 11X A portion of the metal layer M5 is removed to expose the dielectric layer 10, and an insulating layer 90 is formed on the metal layer M5, wherein coating or photolithography operations can be performed. The insulating layer 90 may contain solder resist material.

[0075] See Figure 11Y A portion of the insulating layer 90 is removed to expose the metal layer M5, where etching or development operations can be performed. See also Figure 11Z Remove the CR vector. See [link / reference] Figure 11AA Metal layer M6 and PR layer P7 are formed in Figure 11Z In terms of structure, plating, coating and photolithography operations can be performed.

[0076] See Figure 11AB A portion of the PR layer P7 is removed to expose the metal layer M6, where development or etching operations can be performed. See also Figure 11AC The portions of PR layer P7 and metal layer M6 corresponding to PR layer P7 are removed to form semiconductor package 11ac, wherein an etching operation can be performed. Semiconductor package 11ac can be similar to Figure 1A Semiconductor package 100 in the middle.

[0077] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation clearly occurs or is very close to occurring. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" or "approximately" the same. For example, "substantially" parallel might refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "generally" vertical might refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0078] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. Similarly, if the difference between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered planar or substantially planar.

[0079] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators. In the description of some embodiments, the phrase “on” or “above” one component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component), and situations where one or more intermediate components are located between the preceding and following components.

[0080] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes may be made and equivalent components may be substituted within embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. The process reproduction in this disclosure may differ from actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package comprising: A first interconnect layer having a first conductive layer and a first dielectric layer that at least partially covers the first conductive layer; as well as A second interconnect layer has a second conductive layer and a second dielectric layer that at least partially covers the second conductive layer, wherein the first interconnect layer is at least partially surrounded by the second interconnect layer, the second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer has a first surface and a second surface both facing the first dielectric layer, wherein the material of the first dielectric layer is different from the material of the second dielectric layer. The first surface of the second dielectric layer is recessed from the second surface of the second dielectric layer and defines a notch, and A portion of the first dielectric layer is disposed within the notch; as well as A metal layer disposed within the recess and having an upper surface that contacts the second dielectric layer and a lower surface that contacts the first dielectric layer.

2. The semiconductor package of claim 1, wherein the upper surface of the metal layer contacts the first surface of the second dielectric layer.

3. The semiconductor package of claim 2, wherein the upper surface of the metal layer is completely covered by the second dielectric layer.

4. The semiconductor package of claim 2, wherein the second dielectric layer has a third surface extending between the first surface and the second surface, the third surface surrounding the first surface.

5. The semiconductor package of claim 4, wherein the first surface does not perpendicularly overlap the second surface.

6. The semiconductor package of claim 2, further comprising a conductive via contacting the metal layer, wherein the conductive via is surrounded by the first dielectric layer.

7. The semiconductor package of claim 2, wherein the distance between the second surface of the first dielectric layer and the first surface of the second dielectric layer is greater than the thickness of the metal layer.

8. The semiconductor package according to claim 1, wherein the coefficient of thermal expansion of the first dielectric layer is greater than the coefficient of thermal expansion of the second dielectric layer.

9. The semiconductor package according to claim 1, wherein the modulus of the first dielectric layer is greater than the modulus of the second dielectric layer, and the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

10. The semiconductor package of claim 1, wherein the first dielectric layer comprises polypropylene and the second dielectric layer comprises polyamide.

11. The semiconductor package of claim 1, wherein the spacing of the first conductive layer is smaller than the spacing of the second conductive layer.

12. The semiconductor package of claim 1, wherein the spacing of the first conductive layer is equal to or less than 7 μm.

13. The semiconductor package of claim 1, wherein the interface between the first interconnect layer and the second interconnect layer comprises a first surface and a second surface, wherein the first surface and the second surface of the interface are discontinuous.

14. The semiconductor package of claim 13, wherein the first surface and the second surface of the interface are parallel to each other.

15. A method for manufacturing a semiconductor package, comprising: Provide a carrier; A patterned seed layer is formed on the carrier; A patterned metal layer is formed on the patterned seed layer; A first dielectric layer is formed on the carrier to surround the patterned seed layer and the patterned metal layer; Remove the carrier; Remove the seed layer to form a notch defined by the surface of the patterned metal layer and the surface of the first dielectric layer; as well as A second dielectric layer is formed in the notch and on the surface of the first dielectric layer, the patterned metal layer being in the notch and having an upper surface that contacts the first dielectric layer and a lower surface that contacts the second dielectric layer.

16. The method of claim 15, wherein the CTE of the second dielectric layer is greater than the CTE of the first dielectric layer.

17. The method of claim 15, wherein the modulus of the second dielectric layer is greater than the modulus of the first dielectric layer.

18. The method of claim 15, further comprising forming a conductive via within and in contact with the patterned metal layer of the second dielectric layer.

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