Schottky diode

Abstract

A Schottky diode includes: a first electrode; a second electrode; and a semiconductor material body that is connected to the first electrode at a first interface and to the second electrode at a second interface, wherein the first interface includes a first planar region located in a first plane, and the first electrode has a first projection on the first plane along a first direction perpendicular to the first plane, the second interface includes a second planar region located in a second plane, and the second electrode has a second projection on the first plane along the first direction, at least a part of the second projection is located outside the first projection, the second planar region is offset from the first planar region along the first direction, and one of the first interface and the second interface provides a Schottky contact.

Description

Technical Field

[0001] The present invention relates to Schottky diodes and methods of manufacturing the same. Specifically, but not exhaustively, certain embodiments of the present invention relate to Schottky diodes for integration in thin and / or flexible electronic circuits, and certain embodiments relate to thin film Schottky diodes for such applications or other applications. Background Art

[0002] Schottky diodes are well-known electronic components that typically provide very fast switching from their conducting state to their non-conducting state, and thus they are particularly useful for rectifying high-frequency signals. Schottky diodes are also well-known for use in many other electronic applications and circuit configurations.

[0003] A Schottky diode includes two conductive electrodes (a Schottky electrode and an ohmic electrode) separated laterally or longitudinally by a semiconductor. In flexible electronic devices, Schottky diodes are shown to have a variety of different material systems, including metal oxides and organic semiconductors. Vertical diodes consist of parallel plate conductors separated by a semiconductor layer, while lateral diodes typically consist of two electrodes located in the same plane and covered by a semiconductor.

[0004] Control of the Schottky barrier height is achieved by optimizing the difference between the work function of the Schottky electrode and the Fermi level of the semiconductor. This can be achieved by selecting the conductor of the Schottky electrode and / or by controlling the Fermi energy by means of modifying the semiconductor material (oxygen content in the case of metal oxides).

[0005] In a vertical diode configuration, difficulties surround achieving a stable and reproducible barrier height using a semiconductor sandwiched between metal contacts. Variability is caused by surface defects at the metal-semiconductor interface, which can have a significant impact on the threshold voltage, breakdown voltage, and RC time constant. Another key challenge for vertically stacked metal oxide semiconductors is caused by oxygen reduction. To form an ohmic contact on the top surface, for example, a conductor that locally reduces the metal oxide is typically selected. If the metal oxide semiconductor is too thin and / or the oxygen content is too low, it may result in a conduction path to the Schottky electrode, leading to early device breakdown.

[0006] The lateral diode structure provides improved control over the current path from the ohmic contact through the semiconductor to the Schottky contact. The lateral separation of the contacts becomes a key control factor, and thus has less impact on the semiconductor thickness or its oxygen content. However, for lateral diodes, the etch selectivity issue may limit the choice of two different metals for the Schottky electrode / contacts and the ohmic electrode / contacts. Summary of the Invention

[0007] Certain embodiments of the present invention are directed to overcoming at least one of the problems associated with the prior art, at least in part. Certain embodiments are directed to providing Schottky diodes suitable for thin and / or flexible electronic circuits, and certain embodiments are directed to providing thin-film Schottky diodes. Certain embodiments are directed to providing methods of manufacturing Schottky diodes that are compatible with techniques for producing thin and / or flexible electronic circuits and circuit components.

[0008] According to a first aspect of the present invention, there is provided a Schottky diode comprising: a first electrode; a second electrode; and a body of semiconductor material (e.g., a layer) that is connected to the first electrode at a first interface junction (through the first interface junction) and to the second electrode at a second interface junction (through the second interface junction), wherein the first interface includes a first planar region located in a first plane, and the first electrode has a first projection on the first plane along a first direction perpendicular to the first plane, the second interface includes a second planar region located in a second plane, and the second electrode has a second projection on the first plane along the first direction, at least a portion of the second projection being located outside the first projection, the second planar region being offset (separated, spaced apart) from the first planar region in the first direction, and one of the first interface and the second interface providing a Schottky (rectifying) contact.

[0009] In certain embodiments, the first electrode is a lower electrode and the second electrode is an upper electrode, e.g., relative to a substrate or other support. In certain alternative embodiments, the first electrode is an upper electrode and the second electrode is a lower electrode.

[0010] In certain embodiments, the diode further includes a substrate, e.g., to support the electrodes and the body of semiconductor material.

[0011] In certain embodiments, the second plane is parallel to the first plane.

[0012] In certain embodiments, the first interface consists of the first planar region.

[0013] In certain embodiments, the second interface consists of the second planar region.

[0014] In certain embodiments, the second projection is entirely (completely) located outside the first projection, whereby the projection of the second planar region on the first plane in the first direction is entirely located outside the projection of the first planar region on the first plane in the first direction.

[0015] In certain embodiments, a portion of the first projection is located inside the second projection.

[0016] In some embodiments, the first projection is entirely located inside the second projection.

[0017] In some embodiments, the projection of the second planar region onto the first plane along the first direction is entirely located outside the projection of the first planar region onto the first plane along the first direction.

[0018] In some embodiments, a part (some) of the projection of the first planar region onto the first plane along the first direction is located inside the projection of the second planar region onto the first plane along the first direction.

[0019] In some embodiments, the projection of the first planar region onto the first plane along the first direction is entirely located inside the projection of the second planar region onto the first plane along the first direction.

[0020] In some embodiments, the diode further includes a substrate, and the first electrode is disposed on a surface of the substrate.

[0021] In some embodiments, the diode further includes a dielectric material body (e.g., a layer) (e.g., a dielectric layer).

[0022] In some embodiments, the dielectric body is arranged to space (separate) the second electrode from the first electrode in the first direction.

[0023] In some embodiments, the dielectric body includes a window, and the first interface is disposed inside the window.

[0024] In some embodiments, the semiconductor material body includes a first portion that at least partially fills the window, and a second portion that extends laterally from the window (i.e., in a direction parallel to the first plane) and covers at least a portion of the surface of the dielectric body.

[0025] In some embodiments, the second electrode is arranged to cover at least a portion of the second portion of the dielectric body.

[0026] In some embodiments, the diode further includes another dielectric material body (e.g., a layer), which is arranged to cover at least a portion of the semiconductor material body and at least a portion of the second electrode.

[0027] In some embodiments, the another dielectric material body is arranged to cover the entire semiconductor material body.

[0028] In some embodiments, at least one of the first and second interfaces includes a surface-treated portion of at least one of: the first electrode; the second electrode; and the semiconductor material body.

[0029] According to another aspect of the present invention, there is provided a Schottky diode comprising: a first electrode; a second electrode; and a semiconductor material body (e.g., a layer) which is connected to the first electrode at a first interface junction (through the first interface junction) and to the second electrode at a second interface junction (through the second interface junction), wherein the first interface includes a first planar region located in a first plane, and the first interface has a first projection on the first plane along a first direction perpendicular to the first plane, the second interface includes a second planar region located in a second plane, and the second interface has a second projection on the first plane along the first direction, at least a portion of the second projection is located outside the first projection, the second planar region is offset (separated, spaced apart) from the first planar region in the first direction, and one of the first interface and the second interface provides a Schottky (rectifying) contact.

[0030] According to another aspect of the present invention, there is provided a Schottky diode comprising: a first electrode; a second electrode; and a semiconductor material body which is connected to the first electrode at a first interface junction (through the first interface junction) and to the second electrode at a second interface junction (through the second interface junction), wherein the first interface includes a first planar region located in a first plane, and the first electrode has a first projection on the first plane along a first direction perpendicular to the first plane, the second interface includes a second planar region, and the second electrode has a second projection on the first plane along the first direction, the second projection is entirely located outside the first projection, one of the first interface and the second interface provides a Schottky (rectifying) contact, the body includes a first side and a second side, the second side is spaced apart from the first side by the thickness of the body in the first direction, and the first planar region is on the first side of the body, and the second planar region is on the second side of the body.

[0031] In some embodiments, the second planar region is located in the first plane.

[0032] In some embodiments, the second planar region is located in a second plane.

[0033] In some embodiments, the second plane is parallel to the first plane.

[0034] In some embodiments, the second plane is spaced apart from the first plane along the first direction.

[0035] In some embodiments, the diode further includes a substrate arranged to support the first electrode.

[0036] In some embodiments, the semiconductive material body includes: a first portion arranged to cover at least a portion of the surface of the first electrode; and a second portion extending laterally from the first electrode, the second electrode being arranged to cover at least a portion of the second portion of the semiconductive material body.

[0037] In some embodiments, the diode further includes another dielectric material body (e.g., a layer) arranged to cover at least a portion of the semiconductive material body and at least a portion of the second electrode.

[0038] In some embodiments, the another dielectric material body is arranged to cover all of the semiconductive material body.

[0039] In some embodiments, at least one of the first interface and the second interface includes a processed (e.g., surface-treated) portion of at least one of: the first electrode; the second electrode; and the semiconductive material body.

[0040] In some embodiments, the semiconductive material body includes a first layer and a second layer, the first interface includes a portion (e.g., a surface portion) of the first layer, and the second interface includes a portion of the second layer.

[0041] Another aspect of the present invention provides a Schottky diode including: a first electrode; a second electrode; and a semiconductive material body connected to the first electrode at a first interface (junction) and connected to the second electrode at a second interface (junction), wherein the first interface is substantially planar and lies in a first plane, and the second interface is offset (separated) from the first interface in a first direction perpendicular to the first plane and in a second direction parallel to the first plane.

[0042] In some embodiments, the second interface is offset from the first interface such that the projection of the second interface onto the first plane does not overlap the first interface. In alternative embodiments, there is partial overlap, and in other embodiments, there is complete overlap.

[0043] In some embodiments, the projection of the second interface onto the first plane is separated from the first interface by a distance of at least 1 nm, but the actual separation will depend on many factors, such as the minimum feature size achievable by the manufacturing processes / lithography tools discussed in this specification and the desired device parameters.

[0044] In some embodiments, the second interface is substantially planar, lies in a second plane, and the second plane may be parallel to the first plane.

[0045] In some embodiments, the diode further includes a dielectric material layer, wherein the semiconductor material body includes a first portion extending from the first interface in a direction perpendicular to the first plane and passing through the dielectric material layer to the surface of the dielectric material layer, and a second portion extending along the surface in a direction parallel to the first plane.

[0046] In some embodiments, the second electrode overlaps one end of the second portion and a portion of the surface.

[0047] In some embodiments, the first interface includes a first portion of a substantially flat surface of the first electrode, and the dielectric material layer covers at least a second portion (overlapping therewith) of the substantially flat surface of the first electrode.

[0048] In some embodiments, the first interface is a Schottky junction, the second junction is an ohmic junction, and in alternative embodiments, the second interface is a Schottky junction and the first junction is an ohmic junction. In some embodiments, one of the first and second interfaces is a Schottky junction, and the other of the first and second interfaces is any junction that allows current to flow through the Schottky diode when the Schottky junction is conducting.

[0049] In some embodiments, the first electrode comprises or consists of a first material selected from the list comprising: metals such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, AlSi; transparent conductive oxides (such as ITO, IZO, AZO); metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, graphene; conductive polymers such as polyaniline, PEDOT:PSS; or semiconductor materials.

[0050] In some embodiments, the second electrode comprises or consists of a second material selected from the list comprising: metals such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, AlSi; transparent conductive oxides (such as ITO, IZO, AZO); metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, graphene; conductive polymers such as polyaniline, PEDOT:PSS; or semiconductor materials.

[0051] In some embodiments, the semiconductor material is selected from materials in a list including the following: compound semiconductors (such as GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb); metal oxides, such as ZnO, SnO2, NiO, SnO, Cu2O, In2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO) (sometimes referred to as GaInZnO, GIZO); metal oxynitrides, e.g., ZnxOyNz; inorganic semiconductors (such as amorphous silicon, microcrystalline silicon, or nanocrystalline silicon); organic semiconductors (such as CuPc, pentacene, PTCDA, methylene blue, orange G, rubrene); polymer semiconductors (such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, polycarbazole); 2D materials (such as graphene); chalcogenides, such as MoS2, GeSbTe; perovskites (SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, CsSnI3); any of the foregoing semiconductor materials, which are also doped or include a doping gradient, and are n-type or p-type.

[0052] Examples of suitable materials for the dielectric material and / or substrate in some embodiments are provided in the following description.

[0053] In some embodiments, at least the semiconductor material and the first and second electrodes are substantially transparent to visible light.

[0054] In some embodiments, the semiconductor material is substantially transparent to visible light, but the first and second electrodes at least partially reflect visible light.

[0055] In some embodiments, the dielectric material is substantially transparent to visible light.

[0056] In some embodiments, one of the first and second electrodes includes a titanium body (e.g., layer) and a layer formed on the surface of the titanium body and including or consisting of at least one titanium oxide or lower-valent titanium oxide, wherein the interface providing the Schottky contact includes or consists of the interface between the semiconductor material body and the layer including or consisting of at least one titanium oxide or lower-valent titanium oxide.

[0057] Another aspect of the present invention provides a circuit including at least a first diode according to any of the foregoing aspects or embodiments and a second diode according to any of the foregoing aspects or embodiments, wherein the first and second planar regions of the first diode are offset (i.e., offset from each other) by a first distance, the first and second planar regions of the second diode are offset by a second distance, and the second distance is different from the first distance.

[0058] Another aspect of the present invention provides a circuit or a circuit module, which includes a diode according to any of the foregoing aspects or embodiments. For example, the circuit or the circuit module may be a logic gate (e.g., "OR" gate, "AND" gate, etc.) or an inverter (e.g., a diode load inverter).

[0059] In some embodiments, the circuit is an integrated circuit.

[0060] Another aspect of the present invention provides an electronic device, which includes a diode according to any of the foregoing aspects or embodiments. For example, the device may be a source-gated transistor, a Schottky transistor, a gated diode, etc.

[0061] Another aspect of the present invention provides a method for manufacturing a Schottky diode, the Schottky diode including a first electrode, a second electrode, and a semiconductor material body connecting the first and second electrodes, the method including: forming a first electrode on a first region of a surface of a substrate (or support); forming a dielectric material body that at least covers a second region adjacent to the first region of the substrate surface; forming a semiconductor material body that includes a first part disposed above the first electrode and connected to the first electrode at a first interface, and a second part disposed above a part of the dielectric material body covering the second region of the substrate surface; and forming a second electrode on the second part of the semiconductor material body, the second electrode being connected to the semiconductor material body at a second interface.

[0062] In some embodiments, the first interface has a first projection on the substrate surface, the second interface has a second projection on the substrate surface, and the second projection is offset from the first projection by a certain distance.

[0063] In some embodiments, the method further includes pre-determining the distance according to at least one desired characteristic or parameter of the diode.

[0064] In some embodiments, the first interface includes a first surface portion of the first electrode, and the method further includes treating the first surface portion of the first electrode before forming the semiconductor material body.

[0065] In some embodiments, the second interface includes a surface portion of the semiconductor material body, and the method further includes treating the surface portion of the semiconductor material body before forming the second electrode.

[0066] In some embodiments, the semiconductor material body includes at least two layers.

[0067] In some embodiments, the method further includes selectively processing at least a portion of the semiconductor material body (e.g., ion implantation).

[0068] In some embodiments, the dielectric material body covers a portion of the first electrode.

[0069] In some embodiments, the dielectric material body includes a window through which at least a portion of the first electrode is visible (exposed), and the first portion of the semiconductor material body is formed inside the window.

[0070] Another aspect of the present invention provides a method of manufacturing a Schottky diode, the Schottky diode including a first electrode, a second electrode, and a semiconductor material body connecting the first and second electrodes. The method includes: forming a first electrode on a first region of a substrate (or support) surface; forming a semiconductor material body including a first portion disposed above the first electrode and connected to the first electrode at a first interface, and a second portion disposed above a second region of the substrate surface adjacent to the first region; and forming a second electrode on the second portion of the semiconductor material body, the second electrode being connected to the semiconductor material body at a second interface. The features of the above aspects and embodiments of the present invention can be utilized in this aspect, with corresponding advantages.

[0071] Another aspect of the present invention provides a method of manufacturing a Schottky diode, the Schottky diode including a first electrode, a second electrode, and a semiconductor material body connecting the first and second electrodes. The method includes: forming a first electrode on a first region of a substrate (or support) surface; forming a second electrode on a second region of the substrate surface, the second region being separated from the first region by a third region; forming a semiconductor material body including a first portion disposed above the first electrode and connected to the first electrode at a first interface, a second portion disposed above the second electrode and connected to the second electrode at a second interface, and a third portion disposed above the third region and connecting the first portion and the second portion. Again, the features of the above aspects and embodiments of the present invention can be utilized in this aspect, with corresponding advantages.

[0072] In some embodiments, the first interface includes a first surface portion of the first electrode, and the method further includes processing the first surface portion of the first electrode before forming the semiconductor material body.

[0073] In some embodiments, the second interface includes a first surface portion of the second electrode, and the method further includes processing the first surface portion of the second electrode before forming the semiconductor material body.

[0074] In some embodiments, the formation of the first electrode and the formation of the second electrode are performed simultaneously.

[0075] In some embodiments, the formation of the first electrode is performed before or after the formation of the second electrode.

[0076] In some embodiments of any of the above aspects, the method may further include implanting ions to dope at least a portion of the semiconductor material body or increasing the doping of at least a portion of the semiconductor material body.

[0077] In some embodiments of any of the above aspects, the first electrode includes a titanium body, and the treatment of the first surface portion of the first electrode includes treating the first surface portion of the first electrode to form a layer comprising at least one titanium oxide or lower-valent titanium oxide or consisting thereof.

[0078] Another aspect of the present invention provides a method of manufacturing a Schottky diode that includes a first electrode, a second electrode, and a semiconductive material body connecting the first electrode and the second electrode. The method includes: forming a first electrode having a substantially flat (upper) surface; forming a dielectric material layer having a substantially flat (upper) surface parallel to the substantially flat surface of the first electrode and having a window through which at least a portion of the flat surface of the first electrode can be seen / exposed; forming a semiconductor material body having a substantially flat (upper) surface, the semiconductor material body including a first portion that fills the window and a second portion that extends laterally from the window to cover a portion of the substantially flat (upper) surface of the dielectric material layer; and forming a second electrode on the second portion.

[0079] In some embodiments of any of the above aspects, the method may further include treating the surface / surfaces of the first electrode (e.g., performing surface engineering on the first electrode) and / or the surface of the second electrode to modify the work function and / or introduce a potential barrier. The treatment may include implantation, plasma treatment, SAM deposition, ALD, ozone UV, laser exposure, thermal annealing, etc. In some embodiments, a treatment selective only to the first electrode may be selected.

[0080] In some embodiments, the diode includes a top dielectric layer. This may allow selective deposition of the second electrode into a window in the top dielectric layer. Additionally, protection may be provided for the semiconductor during and after treatment of the second electrode.

[0081] In some embodiments, the first electrode is formed of a first conductive material and the second electrode is formed of a second conductive material different from the first material.

[0082] Another aspect of the present invention provides a Schottky diode, comprising: a first electrode; a second electrode; and a semiconductor material body, which is connected to the first electrode at a first interface and to the second electrode at a second interface, wherein the first interface provides a Schottky contact, the first electrode includes a titanium body (e.g., layer) and a layer formed on the surface of the titanium body and containing at least one titanium oxide or lower-valence titanium oxide or consisting of the same, and the first interface includes or consists of an interface between the semiconductor material body and the layer containing at least one titanium oxide or lower-valence titanium oxide or consisting of the same.

[0083] In certain embodiments, the semiconductor material is an oxide semiconductor, such as IGZO. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] Embodiments of certain aspects of the present invention will now be described with reference to the drawings, wherein:

[0085] Figure 1 A thin-film electronic device embodying the present invention and formed by a method embodying the present invention is shown;

[0086] Figure 2 A series of processing steps in a method embodying the present invention and suitable for manufacturing the Figure 1 device shown are shown;

[0087] Figure 3 Another electronic device embodying the present invention is shown;

[0088] Figure 4 Another electronic device embodying the present invention is shown;

[0089] Figure 5 Another electronic device embodying the present invention is shown;

[0090] Figure 6(a) - Figure 6(b) Another electronic device embodying the present invention is shown;

[0091] Figure 7 Another electronic device embodying the present invention is shown;

[0092] Figure 8(a) - Figure 8(b) Another electronic device embodying the present invention is shown;

[0093] Figure 9(a) - Figure 9(b) Shows the Figure 2 typical current-voltage characteristics of an electronic device embodying the present invention manufactured according to the sequence of process steps shown;

[0094] Figure 10(a) - Figure 10(d) A circuit schematic diagram embodying the present invention is shown;

[0095] Figure 11Shows a Schottky diode embodying one aspect of the present invention;

[0096] Figure 12 Shows another Schottky diode embodying one aspect of the present invention;

[0097] Figure 13 Shows another Schottky diode embodying one aspect of the present invention;

[0098] Figure 14 Shows two additional Schottky diodes embodying one aspect of the present invention;

[0099] Figure 15 Shows another Schottky diode embodying one aspect of the present invention;

[0100] Figures 16 to 19 Shows a method of manufacturing a Schottky diode embodying multiple aspects of the present invention;

[0101] Figure 20 Shows a portion of a circuit embodying one aspect of the present invention and integrating two Schottky diodes,

[0102] Figure 21 Shows a source-gated transistor (SGT) embodying the present invention;

[0103] Figure 22 Shows a diode "OR" gate embodying one aspect of the present invention and integrating a Schottky diode embodying one aspect of the present invention;

[0104] Figure 23 Shows a diode "AND" gate embodying one aspect of the present invention and integrating a Schottky diode embodying one aspect of the present invention;

[0105] Figure 24 Shows a diode load inverter embodying one aspect of the present invention and integrating a Schottky diode embodying one aspect of the present invention; and

[0106] Figure 25 Shows a Schottky diode embodying another aspect of the present invention. Detailed Description

[0107] Now refer to Figure 1 (a), which shows a side view of a multilayer device on an insulating substrate 1 that has been manufactured by a method according to the present invention.

[0108] Layer 2 represents the patterned area of the first electrode. Layer 3 represents the patterned area of the thin film dielectric material. Layer 4 represents the patterned area of the thin film semiconductor material. Layer 5 represents the patterned area of the second electrode.

[0109] Figure 1 (b) showsFigure 1 Top view of the device layer as shown in (a).

[0110] Figure 1 (c) shows a top view of the device layer, including an example of the extended contact region 21 of the first electrode 2. Such a contact region extends laterally in the plane of the electrode 2 beyond the covered semiconductor layer 4, which can facilitate the electrical connection of the first electrode 2 to other locations on the substrate 1 or to locations outside the substrate. During device fabrication, the dielectric material body 3 can protect any extended contact regions of the first electrode 2 from subsequent processing that may be performed on the second electrode 5, such as chemical or physical etching. Compared to purely vertical or lateral approaches, and compared to Figure 3 devices that omit the dielectric material body 3, the etch selectivity considerations for the two conductor layers here do not affect the choice of materials available for each of the two conductor layers.

[0111] Figure 1 (d) and 1(e) show a cross-sectional view and a top view of the device layer, respectively, to illustrate a device having a radial geometry. In this example, the first electrode 2 is radially surrounded by the second electrode 5, and the semiconductor layer 4 is connected between the two electrodes. Although a circular geometry is shown in Figure 1 (d), the device can have any geometry that provides a desired offset between the first interface 42 of the semiconductor layer 4 with the first electrode 2 and the second interface 45 of the semiconductor layer 4 with the second electrode 5.

[0112] Referring again to Figure 1 , Figure 1(a) is a schematic cross-section of a Schottky diode embodying one aspect of the present invention as defined in claim 1. The Schottky diode includes a first electrode 2, a second electrode 5, and a semiconductor material body 4 which is connected to the first electrode at (or through) a first interface (which may also be referred to as a junction or contact) 42. The body 4 is also connected to the second electrode 5 at (or equivalently through) a second interface. In this example, the first electrode is a Schottky electrode and the first interface 42 provides a Schottky (i.e., rectifying) contact. The second electrode 5 is a conductor providing an ohmic electrode such that the second interface 45 provides an ohmic contact. However, it will be understood that in alternative embodiments, the first electrode 2 may provide an ohmic electrode while the second electrode 5 may provide a Schottky electrode. Those skilled in the art will be fully aware of how Schottky and ohmic contacts are generally achieved by selecting conductor materials relative to the semiconductive material and / or by appropriately treating multiple portions of the conductive electrodes and / or the semiconductive body at the interface regions. Although the term "ohmic contact" has been used to describe one of the interface regions, it should be understood that any type of junction that enables the Schottky diode to function may actually be included, including a second Schottky junction or contact. If the potential barrier formed by this "ohmic contact" is low enough or has a low enough breakdown voltage so as not to significantly impede the current flowing through the Schottky diode when it is forward-biased, the Schottky diode may function effectively. That is, when the first Schottky contact conducts, the ohmic contact must allow current to flow through the Schottky diode.

[0113] In this first embodiment, the first interface 42 consists entirely of a first planar region 421 located in a first plane P1, and the first electrode 2 has a projection on the first plane P1 in a first direction D1 perpendicular to the first plane. In this example, the second interface 45 includes a second planar region 452 located in a second plane P2 and another region 453 that is not located in the second plane. Generally, this region 453 is part of the interface between the second conductor and the semiconductor body 4 and is located at the edge of the body 4. In this example, the second electrode 5 has a second projection on the first plane P1 in the first direction D1, and the second projection is entirely outside the first projection such that the second electrode 5 does not overlap the first electrode 2 to any extent. Thus, in this example, the second electrode 5 is laterally offset from or laterally separated from the underlying first electrode 2. In particular, in the figure, the second planar region 452 of the second interface 45 is laterally offset by a distance LO from the first planar portion or first planar region 421 (which forms all of the first interface 42 in this example).

[0114] In this example, the second electrode 5 is also vertically offset from or vertically separated from the first electrode 2, where the second planar region 452 is offset (i.e., separated or spaced apart) from the first planar region 421 in the first direction D1 by a distance S.

[0115] Figure 1 (a) The device is formed by a method in which a first electrode 2 is formed on a substrate 1. Then, a dielectric material body 3 is formed above the first electrode 2 and the substrate, and the upper part of the first electrode 2 is exposed through a window in the dielectric material layer. Then, a semiconductor material layer or body 4 is formed above the dielectric material body 3 such that the semiconductive material at least partially fills the window, and a first interface 42 is formed within the window and is located between the semiconductor material body 4 and the first electrode 2. The semiconductor material body 4 extends to cover a part of the top surface of the dielectric material body 3, so that a part of the semiconductor layer 4 extends laterally away from the window, thus laterally away from the first interface 42. Then, a second electrode 5 has been formed on top of the semiconductor material body 4 and the dielectric material body 3. In this example, the second electrode 5 includes a part that is in direct contact with a part of the top surface of the dielectric material body 3 and a part that overlaps with a region of the top surface of the semiconductor material body 4. This overlapping part contacts the top surface of the body 4 to form a second planar region 452 of the second interface 45. Advantageously, in the manufacturing technology, the lateral offset LO between the first planar region 421 and the second planar region 452 can be precisely finally controlled, thereby providing precise control of the Schottky diode characteristics.

[0116] In Figure 1 the embodiment of (a), it should be understood that the second plane P2 is parallel to the first plane P1, although in alternative embodiments the second plane P2 may not be parallel to P1.

[0117] It should also be understood that Figure 1 (b) and 1(c) show Figure 1 plan views of variants of the embodiment shown in (a), showing different arrangements of non-overlapping (i.e., laterally and vertically offset) first and second electrodes 2, 5 that can be employed in certain embodiments of the present invention.

[0118] Now refer to Figure 1 (d), which shows another embodiment closely related to the embodiment shown in Figure 1 (a). Figure 1 (e) is Figure 1 a plan view of the device shown in (d) ( Figure 1 (d) shows a cross-section). Similar to the embodiment of Figure 1 (a), the second electrode 5 is completely laterally offset from the first electrode 2 such that the projection of the second electrode 5 on the first plane P1 is completely outside the projection of the first electrode 2 on the first plane P1. In this example, the first electrode 2 is circular, while the second electrode 5 is annular (i.e., takes the shape of a circular ring). Similarly, the second planar region 452 on the second interface 45 is laterally offset (especially radially offset) from the first planar region 421 by a distance LO.

[0119] Still referring to Figure 1 (a), it will be understood that it shows a diode configuration with laterally and vertically separated electrodes, and the bottom electrode is shown only as an example as a Schottky contact.

[0120] Generally, the operating frequency of a Schottky diode is determined by the RC time constant of the diode (inversely proportional to the frequency). Compared with a conventional vertical configuration, the lateral diode configuration benefits from a minimum overlap capacitance, resulting in an overall reduction in parasitic capacitance. As for the resistance, the contact resistance can be reduced by increasing the overlap rate of the conductor-semiconductor contact while still maintaining an appropriate spacing between the two conductor contacts. However, a trade-off has to be made between the series resistance of the diode and the isolation of the Schottky - ohmic contact (the series resistance increases with the increase in isolation). This can be overcome by increasing the W / L ratio of the diode while still maintaining a low parasitic capacitance and precise control of the channel length.

[0121]

[0122] Now referring to Figure 2 , Figure 2 (a) shows the insulating substrate 1. Figure 2 (b) to 2(c) show side and top views of the substrate 1 completely covered by the conductor layer 2. This complete coverage is required in subtractive deposition techniques (e.g., conventional lithography). Another way to create the desired area of the conductor layer is to use additive or selective deposition techniques, such as one of the printing techniques described later in this specification. Figure 2(d) shows a further stage in which a layer of resist material 6 has been deposited to selectively cover a portion of the conductor layer 2, such as a photoresist that has been patterned by photolithography or a polymer that has been patterned by laser or mechanical cutting, by imprinting or embossing, and then ashed by oxygen plasma. Alternatively, in some embodiments, selective coverage of a portion of the conductor layer with the resist material is achieved by printing the resist material over the desired areas. In some embodiments, the area of the conductor layer is selectively covered by first covering the entire conductor layer and then selectively removing the resist material. A variety of techniques can be used to form at least one layer of resist material, and a variety of resist materials can be employed in different embodiments of the present invention. These methods of forming at least one layer of resist material include coating (spin coating, dip coating, knife coating, bar coating, spray coating, slot die coating) or extrusion. Suitable resist materials include polyhydroxybutyrate, polymethyl methacrylate, polyvinyl alcohol, polyvinyl acetate, polyvinylpyrrolidone, polyvinylphenol, polyvinyl chloride, polystyrene, polyamide (such as nylon), poly(hydroxy ether), polyurethane, polycarbonate, polysulfone, polyarylate, acrylonitrile butadiene styrene, polyimide, benzocyclobutene (BCB), photoresist, 1-methoxy-2-propyl acetate (SU-8), polyhydroxybenzyl silsesquioxane (HSQ), fluorinated polymers such as PTFE, liquid resins curable by ultraviolet light (such as those described in US6284072), silicone resins, siloxanes, parylene. Commercial imprint resists are available from companies such as Microchem / Microresist, Shipley, and Nanolithosolution Inc.

[0123] In an alternative embodiment, the portion is covered by selectively depositing, printing, or otherwise covering the desired area or portion of the conductor layer with the resist material. Figure 2 (e) shows a further stage in which the exposed areas 210 of the conductor layer 2 have been removed, for example, by etching (wet and / or dry etching techniques can be used), ablation, and / or grinding. Figure 2 (f) shows a subsequent stage in which the resist material 6 covering the area 610 of the conductor layer 2 has been removed, for example, by using a photoresist developer, ablation, oxygen plasma, etc. Figure 2 (g) shows a side view of the second layer after the resist material 6 has been removed.

[0124] Figure 2 (h) shows a further stage in which the dielectric material body 3 has been deposited onto the conductor layer 2. Figure 2 (i) shows that a resist layer 7 has been deposited onto the dielectric material body 3 and patterned to form a window 710 that passes through the resist and exposes an area of the underlying dielectric material body 3.Figure 2 (j) shows a further stage in which areas of the dielectric material body 3 exposed through the window 710 in the resist layer 7 are removed, for example, by etching (wet and / or dry etching techniques may be used), ablation, and / or grinding. A subsequent stage is also shown in which the resist layer 7 is removed, for example, by using a photoresist developer, ablation, oxygen plasma, etc.

[0125] Figure 2 (k) shows another stage in which the semiconductor layer 4 is deposited onto the dielectric material body 3. Figure 2 (l) shows a further stage in which a resist material layer 8 has been deposited to selectively cover a portion 810 of the semiconductor layer 4 in the manner described above with reference to Figure 2 (d). The exposed areas of the semiconductor layer 4 are then removed, for example, by etching (wet etching and / or dry etching techniques may be used), ablation, and / or grinding. In a subsequent stage, the resist material layer 8 is removed, for example, by using a photoresist developer, ablation, oxygen plasma, etc. Figure 2 (m) shows a side view of the semiconductor layer 4 after the resist material layer 8 has been removed.

[0126] Figure 2 (n) shows another stage in which the second electrode layer is deposited onto the semiconductor layer 4. Figure 2 (o) shows another stage in which a resist material layer 9 has been deposited to selectively cover a portion 910 of the second electrode layer, for example, a photoresist that has been patterned or a polymer that has been patterned by laser or mechanical cutting, by imprinting or embossing, and then ashed with oxygen plasma. Alternatively, in some embodiments, selective coverage of a portion of the conductor layer with a resist material is achieved by printing the resist material over the desired areas. Thus, in some embodiments, the areas of the conductor layer are selectively covered by first covering the entire conductor layer and then selectively removing the resist material. In alternative embodiments, the areas are covered by selectively depositing, printing, or otherwise covering the desired areas or portions of the conductor layer with a resist material. The exposed areas of the second electrode layer are then removed, for example, by etching (wet etching and / or dry etching techniques may be used), ablation, and / or grinding. In a subsequent stage, the resist material layer 9 is removed, for example, by using a photoresist developer, ablation, oxygen plasma, etc. Figure 2 (p) shows a side view of the second electrode layer after the resist material layer 9 has been removed. Thus, Figure 2 (p) shows a Schottky diode having the same general structure as that shown in Figure 1 (a) and described above.

[0127] Now refer to Figure 3, which shows a device formed by the method embodying the present invention, where there is no bulk dielectric material 3 between the first electrode 2 and the semiconductor layer 4. This method omits steps 2(h), 2(i), and 2(j). Thus, compared to the device of Figure 1 , this device has a simpler structure and requires fewer manufacturing process steps. Considering these advantages, the greater freedom in electrode material selection due to the presence of the bulk dielectric material 3 is lost.

[0128] Referring again to Figure 3 , which in some aspects shows a device (Schottky diode) similar to the embodiment shown in Figure 1 (a), but without the bulk dielectric material 3. Figure 3 's device embodies the aspects defined in claim 20. In the embodiment of Figure 3 , a first electrode 2 is formed on the surface of the substrate 1, and then a semiconductor material body 4 is formed above the first electrode 2 and the substrate 1 so as to completely cover the first electrode 2 and a part of the top surface of the substrate 1 that extends laterally from the first electrode 2. Thus, a first interface 42 is formed between the semiconductor material body 4 and the first electrode 2, and this interface includes a first planar region 421 (in this example, located on top of the first electrode 2) and a side or edge interface portion 422 (usually located at the edge of the first electrode 2). Then, a second electrode 5 has been formed on top of the semiconductor body 4 and the substrate 1 to cover a part of the body 4 and a part of the top surface of the substrate 1. By forming the second electrode 5 in this way, a second interface 45 has been formed between the second electrode 5 and the semiconductor body 4, and this second interface includes a second planar region 452 and another edge region 453. In this example, the thickness T4 of the semiconductor material body 4 is substantially the same as the thickness T2 of the first electrode 2, so the first planar region 421 and the second planar region 452 are located in the same plane, i.e., plane P1. In other examples, the thickness of the semiconductor material body 4 is not the same as the thickness of the layer of the first electrode 2, and the first planar region 421 and the second planar region 452 are not located in the same plane. Advantageously, a lateral offset LO has been provided between the first and second planar regions 421 and 452, and with the general manufacturing techniques described in the specification, precise and accurate control of this spacing LO can be achieved, enabling precise control of the Schottky diode characteristics.

[0129] Now referring to Figure 4 , which shows a device formed by the method embodying the present invention. An insulating substrate 1 completely covered by a layer of dielectric material 10 is provided. Such a dielectric material layer located below other device layers can provide a passivation or protection function for the device stack starting from the substrate 1, thereby potentially increasing the choice of materials available for the substrate 1 without adversely affecting device performance.

[0130] Referring again to Figure 4 , it will be understood that Figure 4 shows another embodiment in which the second electrode 5 is vertically and laterally offset with respect to the first electrode 2 such that the projection of the second electrode 5 on the first plane P1 of the first interface 42 is completely outside the projection of the first electrode 2 on the first plane P1. Moreover, the projection of the second planar region 452 on the first plane P1 is completely outside the projection of the first planar region 421 on P1.

[0131] Now referring to Figure 5 , which shows a device formed by another method embodying the present invention, in which an additional insulating layer 11 is provided on top of the layers 3, 4 and 5. The insulating layer 11 has the effect of improving the interface of the semiconductor layer and / or passivating the device, thereby minimizing or eliminating environmental effects.

[0132] Now referring to FIG. 6(a), which shows a device formed by a method embodying the present invention. A device is provided such that the second interface 45 is laterally offset with respect to the first interface 42 such that the projection of the second interface on the first plane overlaps the first interface partially. FIG. 6(b) shows a device formed by a method embodying the present invention. A device is provided such that the projection of the second interface on the first plane overlaps the first interface completely. Figure 6(a) and 6(b) The lateral interface overlap in the devices shown allows further control of the resistance and capacitance of the devices, and thus affects their current-voltage characteristics, operating frequency, etc.

[0133] Referring again to FIG. 6(a), it will be understood that this embodiment is one in which the projection of the second electrode 5 on the first plane P1 overlaps the projection of the first electrode 2 on the first plane P1 partially, and in fact the projection of the second planar region 452 (the projection on the first plane P1 along the first direction) overlaps the first planar region 421 partially.

[0134] Referring again to FIG. 6(b), it will be understood that in this particular embodiment, the projection of the second electrode 5 on the first plane P1 overlaps the projection of the first electrode 2 on P1 partially, but overlaps the first planar region 421 completely. In this example, the second interface includes an edge region 453, a second planar region 452, a third planar region 454 and a fourth planar region 455. The second, third and fourth planar regions 452, 454 and 455 together overlap the first planar region 421 completely. In this example, the second planar region 452 and the fourth planar region 455 are located in a second plane P2 parallel to P1, and the third planar region 454 is located in a third plane P3 also parallel to P1.

[0135] Now referring to Figure 7, which shows a device formed by the method embodying the present invention. A device is provided in which the (upper) region 21 of the first electrode 2 has been modified (e.g., by implantation, plasma treatment, self-assembled monolayer (SAM), atomic layer deposition (ALD), ozone UV, laser exposure, and / or thermal annealing). Such surface design of the first electrode 2 may modify the work function of the electrode and / or introduce a Schottky barrier. A surface modification process selective only to the substrate 1 can be selected.

[0136] For example, some embodiments include a Schottky barrier formed between a conductive electrode (e.g., layer) of titanium and a semiconductor (e.g., layer) of an oxide semiconductor (e.g., IGZO or any other oxide semiconductor mentioned elsewhere in this specification). In such embodiments, it can be modified by forming a layer of titanium oxide (e.g., TiO2 and / or TiO) on the surface (e.g., upper surface) or a portion of the surface of the titanium electrode (e.g., layer) before depositing the semiconductor (e.g., layer). More specifically, "a layer of titanium oxide" may comprise, consist of, or be composed of: a single titanium oxide or a sub-valent titanium oxide composition; a combination of some or all of titanium oxide (TiO), titanium trioxide (Ti2O3), and titanium dioxide (TiO2); and one or more sub-valent titanium oxides (TiOx, where x is between 1 and 2 or between 0 and 1, e.g., 0.7 and 1.3). In other words, "a layer of titanium oxide" or "titanium oxide layer" can be a layer comprising or consisting of at least one titanium oxide or sub-valent titanium oxide. As is well known in the art, the formation of the titanium oxide layer can be controlled by temperature, atmospheric composition, and / or pressure and / or by applying plasma or other stimuli. Thus, in some methods embodying the present invention, a conductive electrode (e.g., Schottky anode) can be formed by first depositing or otherwise forming a titanium body (e.g., layer) on a substrate or other support or structure. Then, in a surface treatment step (e.g., annealing step), a titanium oxide layer is formed on the surface of the titanium body. Then a body (e.g., layer) of a semiconductor material (e.g., oxide semiconductor, e.g., IGZO) is formed, which at least partially overlaps the titanium oxide layer such that the interface between the semiconductor material and the titanium oxide layer provides a Schottky barrier (contact). Thus, some embodiments include a Schottky anode comprising a titanium body having a titanium oxide layer formed on the surface of the body. In a diode, the titanium oxide layer abuts the semiconductor material to form a Schottky barrier.

[0137] Referring now to FIG. 8(a), which shows a device formed by the method embodying the present invention. A device is provided such that the (upper) surface of the semiconductor layer 44 has been modified (e.g., by doping, implantation, plasma treatment, self-assembled monolayers, atomic layer deposition, ozone UV, laser exposure, and / or thermal annealing), or is formed of a semiconductor material different from that forming the lower part of the semiconductor layer 43. The upper surface of the semiconductor layer 44 may be doped with donor materials deposited on that surface, which are well known to those skilled in the art. For example, the donor materials may be deposited on the semiconductor layer 44 before or after depositing the second electrode 5. FIG. 8(b) shows a device formed by the method embodying the present invention. A device is provided such that a portion of the (upper) surface of the semiconductor layer 46 in contact with the second electrode 5 has been modified (e.g., by doping, implantation, plasma treatment, self-assembled monolayers, atomic layer deposition, ozone UV, laser exposure, and / or thermal annealing) or is formed of a semiconductor material different from that forming the remaining part of the semiconductor layer 45. A portion of the upper surface of the semiconductor layer 46 may be doped with donor materials deposited on that surface, similar to the case described above with respect to FIG. 8(a). Referring Figure 8(a) and 8(b) The surface modifications described allow control of the Schottky barrier height by adjusting the Fermi level of the semiconductor, and thus control of the device characteristics.

[0138] Figure 9(a) - Figure 9(b) shows the Figure 2 typical current-voltage characteristics of an electronic device embodying the present invention formed by the method embodying the present invention after the series of processing steps shown. FIG. 9(a) shows the current-voltage characteristics of a lateral Schottky diode where the second interface is offset from the first interface such that the projection of the second interface on the first plane does not overlap the first interface, this configuration benefiting from a high reverse breakdown voltage and a low reverse leakage current (0.5 μA at 30 V reverse bias). FIG. 9(b) shows the current-voltage characteristics of a lateral Schottky diode where the second interface is offset from the first interface such that the projection of the second interface on the first plane partially overlaps the first interface, this configuration benefiting from a high forward current (1 mA at 1 V forward bias). Figure 9(a) - Figure 9(b) shows that lateral structures with different interface offsets can provide multiple devices with different characteristics on the same substrate in a manner that minimizes the number of necessary processing steps.

[0139] Figure 10(a) - Figure 10(d)Illustrated is a typical circuit configuration utilizing the lateral Schottky diode embodying the present invention. These circuits can be configured to form a rectifier to convert alternating current (full-wave (a) or half-wave (b)) into direct current, configured as an electrostatic discharge (ESD) protection element to prevent a sudden flow of current due to electrostatic discharge (c), or configured as a voltage regulator to maintain a constant voltage (d). Now referring to FIG. 10(a), which shows a schematic diagram of a typical full-wave rectifier circuit embodying the present invention. Now referring to FIG. 10(b), which shows a schematic diagram of a typical half-wave rectifier circuit embodying the present invention. Now referring to FIG. 10(c), which shows a schematic diagram of a typical ESD protection circuit embodying the present invention. Now referring to FIG. 10(d), which shows a schematic diagram of a typical voltage multiplier circuit embodying the present invention. The lateral Schottky diodes embodying the present invention can be combined in the same integrated circuit through one or more of these and / or other circuit configurations without increasing the process steps required for its manufacture.

[0140] Now referring to Figure 11 , which shows an embodiment of another aspect of the present invention, which aspect is generally defined by claim 31. The diode includes a first electrode 2 and a second electrode 5, each electrode being formed on the surface of a substrate 1. In this example, these electrodes are formed on the common upper surface of the substrate 1. Then, a body 4 of semiconductor material is formed above the underlying electrode and substrate structure such that the body 4 of semiconductor material includes a central portion covering a part of the upper surface of the substrate 1 located between the electrodes, and additional portions 420, 450 of the body 4 of semiconductor material respectively overlapping the upper portions of the first electrode 2 and the second electrode 5. Thus, a first interface 42 is formed between the body 4 of semiconductor material and the first electrode 2, which first interface includes a first planar region 421 and an edge portion 422. Similarly, a second interface 45 is formed between the semiconductor body 4 and the second electrode 5, which second interface includes a second planar region 452 and another edge region 453. In this example, the thicknesses of the first and second electrodes are substantially the same, so the first and second planar regions 421, 452 are substantially in the same first plane P1. The projections of the first and second electrodes onto the first plane P1 in a direction perpendicular to the first plane P1 do not overlap, and these projections are laterally offset by a distance LO. In this example, this lateral offset LO also corresponds respectively to the lateral spacing between the first planar region 421 of the first interface and the second planar region 452 of the second interface.

[0141] It should be understood that Figure 11 the embodiment of is a structure without a dielectric layer. The semiconductor material can be any semiconductor material disclosed in this specification or obvious to a person skilled in the art. It should also be understood that for manufacturing Figure 11For the structure, the materials selected for the first electrode 2 and the second electrode 5 should have appropriate etching selectivity. Alternatively, a method in which one or more of the electrodes are patterned not by etching but by, for example, lift-off patterning or printing can be used to provide greater freedom in selecting materials for the dielectric layer, semiconductor layer, electrode 2, and the electrode.

[0142] Now refer to Figure 12 , which shows a similar Figure 11 embodiment as shown, but here the first and second electrodes 2, 5 have different thicknesses. Thus, the first planar region 421 and the second planar region 452 are not in the same plane. Instead, they are located in the first plane P1 and the second plane P2 respectively, and these planes are separated by a distance S.

[0143] Now refer to Figure 13 , which shows a cross-sectional view of another embodiment of one aspect of the present invention generally defined by claim 20. Here, the first electrode 2 is generally formed under the semiconductor layer or the body 4 of semiconductor material, while the second electrode 5 is generally formed on top of the body 4 of semiconductor material. A portion of the body 4 of semiconductor material overlaps the upper surface of the first electrode 2, such that the interface between the body 4 of semiconductor material and the first electrode 2 includes a first planar region 421 located in the first plane P1. In this example, the thickness of the body 4 of semiconductor material (denoted by T in this figure) is less than the thickness of the first electrode 2, so the second planar region 452 (forming the entire second interface 45 between the second electrode 5 and the body 4 of semiconductor material) is located in the second plane P2, and the second plane P2 is separated from the first plane P1 in a direction perpendicular to P1. In this example, P2 is nominally below P1, but it should be understood that in alternative embodiments, the relative positions of the first plane P1 and P2 will vary depending on the relative thicknesses of the electrodes and the body 4 of semiconductor material.

[0144] Now refer to Figure 14(a), which shows a cross-sectional view of another Schottky diode embodying the present invention. This embodiment differs from some of the previously described embodiments in that the dielectric material body 3 does not cover any part of the first electrode 2. Instead, the device is fabricated using a method whereby the dielectric material body 3 is first formed on the substrate 1, and then a window W is formed that passes through the dielectric layer and extends down to the surface of the substrate 1 (the upper surface in this figure). Then, a conductive material is deposited inside the window W to form the first electrode 2. Next, a semiconductor material layer or semiconductor material body 4 is formed on this structure such that the semiconductor material fills the window W, forming a first interface 42 with the first electrode 2 and, in this example, extending laterally in two directions away from the window W. Thus, in this example, the projection of the first electrode 2 on the first plane P1 is identical to the projection of the first planar region 421. In other words, the first planar region 421 is the entire first interface 42. Then, a second electrode 5 is formed on the upper surface of the semiconductor material body 4 by a suitable technique (e.g., by deposition, masking, etching; or alternatively by selective printing). Thus, in this example, the second planar region 452 provides the entire second interface 45 between the second electrode 5 and the semiconductor material body 4, and the projection of the second electrode 5 on the first plane P1 is identical to the projection of the second planar region 452. As in some previous embodiments, the second plane P2 where the second electrode contacts the semiconductor layer is parallel to the first plane P1 of the contact or junction between the semiconductor material body 4 and the first electrode 2. The first and second planar regions 421 and 452 are vertically offset by a distance VO and laterally offset by a distance LO. Now refer to Figure 14 (b), which shows another Schottky diode embodying the present invention. Similar to Figure 14 the embodiment shown in (a), the dielectric material body 3 does not cover any part of the first electrode 2. However, in this embodiment, the first electrode 2 does not fill the entire window W in the dielectric material body 3 but rather fills a portion of the window W. The first electrode 2 can be formed by any suitable technique either before or after the dielectric material body 3 is formed. Then, a semiconductor material layer or semiconductor material body 4 is formed on this structure such that the semiconductor material fills the window W, forming a first interface 42 with the first electrode 2 and, in this example, extending laterally in two directions away from the window W. Thus, in this embodiment, the projection of the first electrode 2 on the first plane P1 is identical to the projection of the first planar region 421. However, in this embodiment, the first interface 42 includes the first planar region 421 and an edge portion 422.

[0145] Now refer to Figure 15, which shows another Schottky diode embodying one aspect of the present invention; this structure has a dielectric layer. The dielectric material body 3 is formed to surround the first electrode 2 but not to overlap with the first electrode 2. A semiconductor layer (or semiconductor material body) 4 is formed to cover the exposed upper surface of the first electrode (forming a first interface 42 consisting of a first planar region 421 in the first plane P1), and to cover a plurality of portions of the dielectric layer surrounding (i.e., adjacent to) the first electrode. A second electrode 5 is formed above a portion of the semiconductor material body 4 and a portion of the dielectric material body 3, thereby forming a second interface 45 with the semiconductor material, the second interface 45 including a second planar region 452 in the second plane P2 and another planar region 453 generally located at the edge of the semiconductor layer. In this example, the second planar region 452 partially overlaps with the first planar region 421 and thus partially overlaps with the first electrode 2.

[0146] The ability of this method to provide devices with different characteristics on the same wafer by only changing its lateral geometry is advantageous, for example, in minimizing the number of processing steps required to produce devices optimized for a large number of applications for the same integrated circuit (see Figure 6(a) - Figure 6(b) and Figure 9(a) - Figure 9(b) for the description).

[0147] Now refer to Figure 16 , which shows a method embodying one aspect of the present invention. The method includes: (a) providing a substrate 1 (or other support / support structure); (b) forming a first electrode 2 on a first region of the surface of the substrate; (c) forming a dielectric material body 3 that covers a second region of the substrate surface adjacent to the first region, and the dielectric material body 3 also has a window W through which a portion of the surface of the first electrode 2 can be seen / exposed; (d) forming a semiconductor material body 4 that includes filling the window and is disposed above the first electrode and is connected to a first portion of the first electrode at the first interface 42 (421), and a second portion disposed above a portion of the dielectric material body covering the second region of the substrate surface; and (e) forming a second electrode 5 on the second portion of the semiconductor material body, the second electrode being connected to the semiconductor material body at the second interface 452. The method includes setting a lateral offset LO between the first interface 42 and the second interface 452 to achieve the desired characteristics of the diode.

[0148] Refer to Figure 17 , which shows another method embodying one aspect of the present invention, similar to Figure 16The method shown, but different in that the dielectric material body 3 does not provide a window. Instead, the dielectric material body 3 overlaps the first electrode portion and then extends laterally to cover a second portion of the substrate surface adjacent to the first portion (covered by the first electrode). Then a semiconductor material body 4 is formed (step (c)) to overlap the uncovered portion of the upper surface of the first electrode and cover at least a portion of the dielectric material that covers the second region of the substrate surface. Then, in step (d), a second electrode 5 is formed on the surface of the second portion of the semiconductor body, with a desired lateral offset LO between the first and second interfaces.

[0149] Now refer to Figure 18 , which shows another method embodying an aspect of the present invention for manufacturing a Schottky diode that includes a first electrode, a second electrode, and a semiconductor material body connecting the first and second electrodes. The method includes: (a) forming a first electrode 2 on a first region of the surface of a substrate 1 (or support); (b) forming a semiconductor material body 4 that includes a first portion disposed above the first electrode and connected to the first electrode at a first interface 42, and a second portion disposed above a second region of the substrate surface adjacent to the first region; forming a second electrode 5 on the second portion of the semiconductor material body, the second electrode being connected to the semiconductor material body at a second interface. Again, the lateral offset LO between the first and second interfaces is selected to determine the device characteristics.

[0150] Now refer to Figure 19 , which shows another method embodying an aspect of the present invention. The method includes: (a) providing a substrate 1 (or support / support structure); (b) forming a first electrode 2 on a first region of the substrate surface and a second electrode 5 on a second region of the substrate surface, the second region being separated from the first region by a third region, and the electrodes having a desired lateral offset; (c) forming a dielectric material body 3 to cover at least the electrodes and the third region of the substrate; (d) forming a window W in the dielectric material body to expose a portion of the electrodes and the third region of the substrate surface; (e) depositing a semiconductor material body 4 at least within the window; and (f) removing the remaining dielectric body 3. Thus, the method forms a semiconductor material body 4 that includes a first portion disposed above the first electrode and connected to the first electrode at a first interface, a second portion disposed above the second electrode and connected to the second electrode at a second interface, and a third portion disposed above the third region and connecting the first and second portions. In some embodiments, the electrodes can be formed simultaneously (e.g., deposited or printed), but in alternative embodiments, one electrode is formed one after another. The upper surface can be treated before depositing the dielectric material and / or the semiconductive material to achieve the desired surface characteristics, thereby achieving a rectifying and an ohmic contact in the final diode.

[0151] Now refer to Figure 20 , which shows a part of a circuit embodying one aspect of the present invention. Two Schottky diodes are formed simultaneously on a common substrate 1. In other words, the first electrodes 2a and 2b are formed in a single corresponding processing step; as are two semiconductors 4a and 4b and two second electrodes 5a and 5b. Thus, two diodes are fabricated in a manner that requires only the same number of processing steps as for fabricating a single diode. However, the lateral offsets LO1 and LO2 are different. Thus, compared with a method of fabricating only a single diode, a method embodying one aspect of the present invention can, in an efficient manner, fabricate multiple diodes having different electrical characteristics on a single substrate without requiring additional processing steps, simply by determining the respective lateral offsets of the device electrodes. As will be understood by those skilled in the art, other and / or additional aspects of the geometric design of each device may be different from those of other devices in the same circuit. For example, the widths of the semiconductor and / or the first and / or second electrodes in a direction parallel to the surface of the substrate 1 but perpendicular to the lateral offset LO (i.e., in a direction perpendicular to the plane of the page) may be different from those of other devices in the circuit. A single device within a circuit containing multiple devices may be characterized by the elements of any of the devices disclosed in this specification. For example, a device may be different from other devices in terms of the presence, absence, or geometry of any dielectric material body 3, or in terms of the presence, absence, or geometry of any window W in any dielectric material body 3.

[0152] The Schottky diode / devices and methods according to any of the above aspects and embodiments can be incorporated or combined into the manufacturing methods of more complex devices, such as, for example, source-gated transistors, Schottky transistors, gated diodes, etc. For example, Figure 21A source-gated transistor (SGT) incorporating a Schottky diode embodying one aspect of the present invention is shown. An SGT source electrode 2 is formed / provided on a substrate 1, and a barrier contact is provided through an interface between a portion of the upper surface of the SGT source electrode and a portion of a semiconductor material body 4. This semiconductor material body 4 is formed on a first dielectric layer 31 and is in contact with the source electrode through a window in the first dielectric layer 31. Thus, the semiconductor fills the window and extends laterally above the upper surface of the first dielectric layer 31. The SGT further includes: an SGT drain electrode 5 overlapping with the upper edge of the semiconductor material body 4 and forming an ohmic contact with the semiconductor (in other words, the ohmic contact is provided by the interface between the drain electrode and the semiconductor body 4). A second dielectric layer 32 is formed above the semiconductor material body and the drain electrode, and an SGT gate electrode 500 is formed on the surface of the second dielectric layer 32. In this example, the gate electrode 500 is aligned such that the gate electrode 500 does not overlap with the drain electrode 5, but is located above the semiconductor layer and is separated from the semiconductor material by the second dielectric layer 32. A method of manufacturing the SGT may include manufacturing a Schottky diode assembly (2, 31, 4, 5) using a method according to another aspect / embodiment, forming a second dielectric layer 32 on the semiconductor layer and the drain electrode 5, and forming a gate on the surface of the second dielectric layer.

[0153] It should be understood that Schottky diodes embodying aspects of the present invention may be incorporated in various circuits, circuit modules, and electronic devices in the form of, for example, integrated circuits (ICs). Schottky diodes embodying aspects of the present invention may be incorporated in logic gates. Such logic gates may include one or more diodes, either as the sole active element (e.g., in "diode logic") or in combination with transistors ("diode-transistor logic"). In Figure 22 and Figure 23 Two diode logic examples incorporating Schottky diodes embodying aspects of the present invention are shown. Figure 22 A diode "OR" gate embodying one aspect of the present invention is shown, and the diode "OR" gate includes two diodes, each diode having a respective anode connected to a respective input terminal and a respective cathode connected to an output terminal. The output terminal is grounded through a resistor. Figure 23 A diode "AND" gate embodying one aspect of the present invention is shown, and the diode "AND" gate includes two diodes, each diode having a respective cathode connected to a respective input terminal and a respective anode connected to an output terminal. The output terminal is connected to a positive power rail 1000 through a resistor. The use of Schottky diodes in logic gates (e.g., in these embodiments) may provide advantages such as fast response and small voltage drop, as well as other advantages.

[0154] Schottky diodes embodying aspects of the present invention may also be incorporated in diode load inverters, such as inFigure 24 as shown. Conventional unipolar inverters typically place a transistor switch and a resistive load between a high voltage reference and a low voltage reference. The inverter input is connected to the transistor gate terminal, and the inverter output is connected to the junction of the transistor and the resistor. In a diode load inverter, the resistor load is replaced by a diode, such as as shown in Figure 24 as shown. Using a Schottky diode embodying one aspect of the present invention as the load in a diode load inverter, as shown in Figure 24 as shown, can provide advantages such as fast switching, low voltage drop, and low power consumption.

[0155] Referring to Figure 25 , Figure 25 shows another Schottky diode embodying one aspect of the present invention, and another Schottky diode can be fabricated by a method, and another Schottky diode can be incorporated into circuits and devices embodying other aspects of the present invention. The diode includes: a first electrode 2; a second electrode 5; and a body of semiconductor material 4 connected to the first electrode at a first interface 42 and to the second electrode at a second interface 45, wherein the first interface 42 provides a Schottky contact. The first electrode 2 includes a titanium body (e.g., layer) and a titanium oxide layer formed on the surface of the titanium body (i.e., a layer containing or including at least one titanium oxide or lower-valent titanium oxide as described above), and the first interface 42 includes the interface between the body of semiconductor material 4 and the titanium oxide layer 21. In this example, the body of semiconductor material 4 is an oxide semiconductor, more specifically IGZO, but other semiconductor materials may be employed in alternative embodiments.

[0156] It will be appreciated from the foregoing description that certain lateral diodes described in this application and embodying the present invention differ from prior art lateral diodes in that the metal contacts are spaced apart both laterally and longitudinally, and a semiconductor layer is sandwiched in between. This allows structures to be easily included in the manufacturing process, thereby minimizing additional processing steps and reducing costs. This provides several key advantages.

[0157] This configuration allows precise control of the threshold voltage and breakdown voltage of the diode by controlling the spacing between the ohmic and Schottky contacts (by increasing the spacing), without changing the material or surface properties. This means that, for example, diodes with different threshold and / or breakdown voltages can be fabricated on the same substrate using the same process, without requiring different semiconductor thicknesses, oxygen concentrations, or surface treatments. Precise control of device characteristics related to resistance and capacitance, such as contact resistance, series resistance, maximum current level, capacitance, and RC time constant, can also be provided by controlling the device geometry.

[0158] The structure is easier to fabricate because the conductor layers are separated longitudinally, allowing for more material choices by reducing issues surrounding etch selectivity. Here, two conductor layers are separated by a dielectric layer. This dielectric layer provides a longitudinal separation between the two conductor layers, thus protecting the bottom conductor layer from any processing (chemical, physical etching, etc.) performed on the top conductor layer. Compared to purely longitudinal and lateral approaches, the etch selectivity considerations for the two conductor layers here do not affect the choice of conductor layers that can be used, allowing for more material choices.

[0159] In the case of a metal-oxide semiconductor, local reduction of the semiconductor through an ohmic contact is unlikely to create a current path reaching the Schottky contact, thus providing a more robust process that is less dependent on the thickness and / or oxygen content of the metal oxide. This is because the local reduction is essentially confined to a portion of the semiconductor layer directly beneath the ohmic contact, and in some embodiments, the ohmic contact is laterally spaced from the Schottky contact. The reduction may extend slightly in the lateral direction at the edges of the ohmic contact, but if the lateral spacing between the two contacts is large enough, this will ensure that a conductive path cannot be formed extending from the ohmic contact all the way to the Schottky contact. In other words, controlling the lateral spacing between the two contacts can ensure that a conductive path extending from the ohmic contact to the Schottky contact is avoided.

[0160] Material

[0161] In some embodiments, the semiconductor material layer is a thin film, such as a thin film of a semiconductor material selected from the list including: compound semiconductors (such as GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb); metal oxides, such as ZnO, SnO2, NiO, SnO, Cu2O, In2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO); metal oxynitrides, such as ZnxOyNz; inorganic semiconductors (such as amorphous silicon, microcrystalline silicon, or nanocrystalline silicon); organic semiconductors (such as CuPc, pentacene, PTCDA, methylene blue, orange G, rubrene); polymer semiconductors (such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, polycarbazole); 2D materials (such as graphene); chalcogenides, such as MoS2, GeSbTe; and perovskites (SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, CsSnI3). These semiconductor materials can also be doped or contain doping gradients and can be n-type or p-type.

[0162] In some embodiments, the conductive material layer may include: metals such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, AlSi; transparent conductive oxides (such as ITO, IZO, AZO); metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, graphene; conductive polymers such as polyaniline, PEDOT:PSS; or semiconductor materials.

[0163] In some embodiments, the dielectric material layer includes: metal oxides such as Al2O3, ZrO2, HfO2, Y2O3, Si3N5, TiO2, Ta2O5; metal phosphates such as AI2POx; metal sulfates / sulfites such as HfSOx; metal nitrides such as AIN; metal oxynitrides such as AIOxNy; inorganic insulators such as SiO2, Si3N4, SiNx; spin-on glasses (such as polyhydroxybenzyl silsesquioxane, HSQ), polymeric dielectric materials (e.g., Cytop (an amorphous fluoropolymer available on the market), 1-methoxy-2-propyl acetate (SU-8), benzocyclobutene (BCB), polyimide, polymethyl methacrylate, polybutyl methacrylate, polyethyl methacrylate, polyvinyl acetate, polyvinyl pyrrolidone, polyvinyl phenol, polyvinyl chloride, polystyrene, polyethylene, polyvinyl alcohol, polycarbonate, parylene, silicone); ultraviolet curable resins; nanoimprint resists; or photoresists. The dielectric material may have a relatively low dielectric constant (low-k, such as Cytop, HSQ, parylene) or a relatively high dielectric constant (high-K, such as Ta2O5, HfO2).

[0164] In some embodiments, a Schottky diode may be disposed on a substrate or a substrate structure. In other words, the method may further include directly or indirectly supporting the Schottky diode on a substrate. In some embodiments, the substrate may be flexible and the substrate may include a material selected from the list consisting of: glass (rigid or flexible); polymers (such as polyethylene naphthalate or polyethylene terephthalate); polymer foils; paper; insulator-coated metals (such as coated stainless steel); cellulose, polymethyl methacrylate, polycarbonate, polyvinyl alcohol, polyvinyl acetate, polyvinyl pyrrolidone, polyvinyl phenol, polyvinyl chloride, polystyrene, polyethylene naphthalate, polyterephthalic acid, polyimide, polyamide (such as nylon), poly(hydroxy ether), polyurethane, polycarbonate, polysulfone, parylene, polyarylate, polyether ether ketone (PEEK), acrylonitrile butadiene styrene, 1-methoxy-2-propyl acetate (SU-8), polyhydroxybenzyl sesquisiloxane (HSQ), benzocyclobutene (BCB), AI203, SiOxNy, SiO2, Si3N4, UV curable resins, nanoimprint resists, photoresists.

[0165] In some embodiments, providing a layer of substrate / semiconductor / conductor / dielectric material includes forming the layer by a technique selected from the list consisting of: vapor deposition (physical such as sputtering; chemical such as PECVD); vacuum deposition (such as thermal evaporation or electron beam evaporation); coating (spin, dip coating, knife over edge, bar coating, spraying, slot die coating); printing (inkjet, gravure, offset, screen printing, flexographic printing); pulsed laser deposition (PLD); atomic layer deposition (ALD) coating.

[0166] In some embodiments, a layer of substrate / semiconductor / conductor / dielectric material may have surface modification by techniques such as thermal annealing, plasma treatment (such as O2, Cl2, Ar, CF4, BCl3, N2, SF 6, HBr), self-assembled monolayer SAM (such as HMDS) RIE, ozone UV treatment.

[0167] Throughout the specification and claims of this application, the words "comprise" and "include" and their variants mean "including but not limited to", and they are not intended to (and do not) exclude other parts, additions, components, integers or steps. Throughout the specification and claims of this application, the singular forms include the plural, unless the context otherwise requires. In particular, in the case of using an indefinite article, unless the context otherwise requires, this application should be understood to contemplate both the plural and the singular.

[0168] Features, integers, characteristics, compounds, chemical moieties or groups described in connection with a particular aspect, embodiment or example of the present invention are to be understood to be applicable to any other aspect, embodiment or example described herein, unless incompatible therewith. All features disclosed in this specification (including any accompanying claims, abstract and drawings) and / or all steps of any method or process so disclosed may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification (including any accompanying claims, abstract and drawings) or to any novel step or any novel combination of steps of any method or process so disclosed.

[0169] The reader's attention is directed to all papers and documents which are filed concurrently with or before the present application, which are relevant to this specification and which are open to public inspection in this specification, the contents of all such papers and documents being hereby incorporated by reference.

Claims

1. A Schottky diode, comprising: A substrate or other support or structure; A first electrode formed directly or indirectly on a first region of the surface of the substrate or other support or structure; A second electrode; And A semiconductor material body connected to the first electrode at a first interface and to the second electrode at a second interface, Wherein The first interface includes a first planar region located in a first plane, and the first electrode has a first projection on the first plane along a first direction perpendicular to the first plane, The second interface includes a second planar region located in a second plane, and the second electrode has a second projection on the first plane along the first direction, At least a part of the second projection is located outside the first projection, One of the first interface and the second interface provides a Schottky contact; The semiconductor material body includes a first side and a second side, the second side being spaced from the first side by the thickness of the semiconductor material body along the first direction, and The first planar region is on the first side of the semiconductor material body, and the second planar region is on the second side of the semiconductor material body; The Schottky diode further includes a dielectric body covering at least a second region adjacent to the first region of the surface of the substrate or other support or structure; Wherein the semiconductor material body includes a first part disposed above the first electrode and connected to the first electrode at the first interface, and a second part disposed above a part of the dielectric body covering the second region; Wherein the second electrode is at least partially formed on the second part of the semiconductor material body; Wherein a part but not all of the first projection is located inside the second projection; Wherein the projection of the second planar region on the first plane along the first direction is completely located outside the projection of the first planar region on the first plane along the first direction.

2. The diode according to claim 1, wherein the second plane is parallel to the first plane.

3. The diode according to claim 1, wherein the first interface consists of the first planar region.

4. The diode according to claim 1, wherein the second interface consists of the second planar region.

5. The diode according to claim 1, wherein the dielectric body is arranged to space the second electrode from the first electrode along the first direction.

6. The diode according to claim 1, wherein the dielectric body includes a window, and the first interface is arranged inside the window.

7. The diode according to claim 6, wherein the first part of the semiconductor material body at least partially fills the window, and the second part of the semiconductor material body extends laterally from the window and covers at least a part of the surface of the dielectric body.

8. The diode according to claim 7, wherein the second electrode is arranged to cover at least a part of the second part of the dielectric body.

9. The diode according to claim 1 further includes another dielectric material body arranged to cover at least a part of the semiconductor material body and at least a part of the second electrode.

10. The diode according to claim 9, wherein the another dielectric material body is arranged to cover the entire semiconductor material body.

11. The diode according to claim 1, wherein at least one of the first and second interfaces includes a treated part of at least one of the following: the first electrode; the second electrode; and the semiconductor material body.

12. The diode according to claim 1, wherein the semiconductor material body includes a first layer and a second layer, the first interface includes a part of the first layer, and the second interface includes a part of the second layer.

13. The diode according to claim 1, wherein the first electrode is a Schottky electrode and the second electrode is an ohmic electrode.

14. The diode according to claim 1, wherein the first electrode is an ohmic electrode and the second electrode is a Schottky electrode.

15. The diode according to claim 1, wherein the first electrode includes a material selected from the list consisting of: Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; MoNi, MoCr, AlSi; ITO, IZO, AZO; TiN; carbon black, carbon nanotubes, graphene; polyaniline, PEDOT:PSS; or a semiconductor material.

16. The diode according to claim 1, wherein the second electrode includes a material selected from the list consisting of: Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; MoNi, MoCr, AlSi; ITO, IZO, AZO; TiN; carbon black, carbon nanotubes, graphene; polyaniline, PEDOT:PSS; or a semiconductor material.

17. The diode according to claim 1, wherein the semiconductor material is selected from the list consisting of: GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb; ZnO, SnO2, NiO, SnO, Cu2O, In2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO); ZnxOyNz; amorphous silicon, microcrystalline silicon or nanocrystalline silicon; CuPc, pentacene, PTCDA, methylene blue, orange G, rubrene; PEDOT:PSS, POT, P3OT, P3HT, polyaniline, polycarbazole; graphene; MoS2, GeSbTe; SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, CsSnI3; any of the foregoing semiconductor materials, which is also doped or includes a doping gradient and is n-type or p-type.

18. The diode according to claim 1, wherein the diode is a thin-film Schottky diode.

19. The diode according to claim 1, wherein at least the semiconductor material and the first and second electrodes are substantially transparent to visible light.

20. The diode according to claim 18, wherein the dielectric body is substantially transparent to visible light.

21. The diode according to claim 1, wherein the semiconductor material is substantially transparent to visible light, but the first and second electrodes at least partially reflect visible light.

22. The diode according to claim 21, wherein the dielectric body is substantially transparent to visible light.

23. The diode according to claim 1, wherein one of the first and second electrodes comprises a titanium body and a layer formed on the surface of the titanium body and containing at least one titanium oxide or lower-valent titanium oxide or consisting thereof, and the interface providing the Schottky contact comprises or consists of the interface between the semiconductor material body and the layer containing at least one titanium oxide or lower-valent titanium oxide or consisting thereof.

24. The diode according to claim 1, wherein the projected portion of the second planar region on the first plane is located inside the first projection of the first electrode.

25. The diode according to claim 1, wherein the second interface comprises a plurality of planar regions, and the second planar region is one of the plurality of planar regions.

26. The diode according to claim 25, wherein the plurality of planar regions includes a third planar region, and the projection of the third planar region on the first plane in the first direction is completely located inside the projection of the first planar region on the first plane in the first direction.

27. A circuit comprising at least a first diode and a second diode, both the first diode and the second diode being the diode according to any one of the preceding claims, wherein the first and second planar regions of the first diode are offset by a first distance, the first and second planar regions of the second diode are offset by a second distance, the second distance being different from the first distance, and / or wherein the circuit is an integrated circuit.

28. A method of manufacturing a Schottky diode, the Schottky diode comprising a first electrode, a second electrode, and a semiconductor material body connecting the first and second electrodes, the method comprising: forming a first electrode on a first region of a substrate surface; forming a dielectric material body that at least covers a second region adjacent to the first region of the substrate surface; forming a semiconductor material body that includes a first portion disposed above the first electrode and connected to the first electrode at a first interface, and a second portion disposed above a portion of the dielectric material body covering the second region of the substrate surface; and forming a second electrode on the second portion of the semiconductor material body, the second electrode being connected to the semiconductor material body at a second interface, and wherein The first interface includes a first planar region in a first plane, and the first electrode has a first projection on the first plane along a first direction perpendicular to the first plane. The second interface includes a second planar region in a second plane, and the second electrode has a second projection on the first plane along the first direction. At least a part of the second projection is located outside the first projection. One of the first interface and the second interface provides a Schottky contact. The semiconductor material body includes a first side surface and a second side surface, and the second side surface is spaced from the first side surface by the thickness of the semiconductor material body along the first direction. The first planar region is on the first side surface of the semiconductor material body, and the second planar region is on the second side surface of the semiconductor material body. Wherein the second electrode is at least partially formed on the second part of the semiconductor material body. A part but not all of the first projection is located inside the second projection. And a projection of the second planar region on the first plane along the first direction is completely located outside a projection of the first planar region on the first plane along the first direction.

29. The method according to claim 28, wherein the first interface has a third projection on the substrate surface, the second interface has a fourth projection on the substrate surface, and the fourth projection is offset from the third projection by a certain distance.

30. The method according to claim 29, further comprising pre-determining the distance according to at least one desired characteristic or parameter of the diode.

31. The method according to claim 28, wherein the first interface includes a first surface portion of the first electrode, and the method further comprises treating the first surface portion of the first electrode before forming the semiconductor material body.

32. The method according to claim 31, wherein the first electrode comprises a titanium body, and the treatment comprises: Treat the first surface portion to form a layer comprising at least one titanium oxide or lower-valent titanium oxide or consisting thereof.

33. The method according to claim 28, wherein the second interface includes a surface portion of the semiconductor material body, and the method further comprises treating the surface portion of the semiconductor material body before forming the second electrode.

34. The method according to claim 28, wherein the semiconductor material body includes at least two layers.

35. The method according to claim 28, wherein the method further comprises selectively treating at least a part of the semiconductor material body.

36. The method according to claim 28, wherein the dielectric material body covers a part of the first electrode.

37. The method according to claim 28, wherein the dielectric material body includes a window through which at least a part of the first electrode is visible, and the first part of the semiconductor material body is formed inside the window.

38. The method according to claim 28, further comprising implanting ions to dope at least a part of the semiconductor material body or increase the doping of at least a part of the semiconductor material body.

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