Adder, operation circuit, chip and computing device

Abstract

The present disclosure relates to an adder, an operation circuit, a chip and a computing device. An adder is disclosed, which is used to calculate the sum of two input numbers. The adder has two inputs representing two numbers respectively, each input is divided into multiple sub-parts corresponding to each other, and the multiple sub-parts represent partial bits of the input in sequence from low to high bits. The adder includes: multiple first-level addition modules, each for summing the corresponding sub-parts of the two inputs; multiple intermediate registers, each coupled to the corresponding first-level addition module, for storing the sum of the corresponding sub-parts of the two inputs; one or more carry registers, each coupled to the corresponding first-level addition module, for storing the carry of the corresponding sub-parts of the two inputs; and a second-level addition module, coupled to the multiple intermediate registers and the one or more carry registers, for summing the sum from each intermediate register and the carry from the corresponding previous carry register.

Description

Technical Field

[0001] The present disclosure generally relates to digital circuits, and more particularly to an adder, an operation circuit including the adder, a chip, and a computing device. Background Art

[0002] Adders, used to perform addition operations, are an important component of many arithmetic circuits.

[0003] In the prior art, if the operation speed of the adder needs to be increased, a high-speed device is usually used to implement the adder. However, the high-speed device has a large area and high power consumption, which leads to a corresponding increase in the area and power consumption of the adder and the operation circuit including the adder, which significantly increases the manufacturing cost and power consumption of the chip.

[0004] Therefore, it is expected to increase the operation speed of the adder with lower manufacturing cost and power consumption, and thus an improved adder is needed. Summary of the invention

[0005] According to one aspect of the present disclosure, an adder is provided, which is used to calculate the sum of two input numbers, the adder has two inputs representing the two numbers respectively, wherein each input is divided into multiple sub-parts corresponding to each other, and the multiple sub-parts represent partial bits of the input in sequence from low bits to high bits, and the adder includes: multiple first-level addition modules, each first-level addition module is used to sum the corresponding sub-parts of the two inputs; multiple intermediate registers, each intermediate register is coupled to the corresponding first-level addition module, and is used to store the sum of the corresponding sub-parts of the two inputs; one or more carry registers, each carry register is coupled to the corresponding first-level addition module, and is used to store the carry of the corresponding sub-part of the two inputs; and a second-level addition module, coupled to the multiple intermediate registers and the one or more carry registers, and is used to sum the sum from each intermediate register and the carry from the corresponding previous carry register.

[0006] According to another aspect of the present disclosure, an adder is provided, which is used to calculate the sum of an input number and a predetermined constant, the adder having an input representing the number, the input being divided into a plurality of sub-parts, the plurality of sub-parts representing partial bits of the input in order from low bits to high bits, and the adder comprising: one or more first-stage adding modules, each first-stage adding module being used to sum a corresponding sub-part of the input and a corresponding bit of the constant; a plurality of intermediate registers, each intermediate register being coupled to a corresponding first-stage adding module, and being used to store a sum of a corresponding sub-part of the input and a corresponding bit of the constant; one or more carry registers, each carry register being coupled to a corresponding first-stage adding module, and being used to store a carry of a corresponding sub-part of the input and a corresponding bit of the constant; and a second-stage adding module, coupled to the plurality of intermediate registers and the one or more carry registers, and being used to sum a sum from each intermediate register and a carry from a corresponding previous carry register.

[0007] According to another aspect of the present disclosure, there is provided an operation circuit, which includes the adder as described above; and a pre-combinatorial logic module coupled to the input of the adder, and / or a post-combinatorial logic module coupled to the output of the adder.

[0008] According to another aspect of the present disclosure, a chip is provided, which includes the computing circuit as described above.

[0009] According to yet another aspect of the present disclosure, a computing device is provided, which includes the chip as described above.

[0010] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0012] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0013] Figure 1 A schematic diagram of an adder for calculating the sum of two input numbers according to one or more exemplary embodiments of the present disclosure is shown.

[0014] Figure 2 A schematic diagram of an adder for calculating the sum of an input number and a predetermined constant according to one or more exemplary embodiments of the present disclosure is shown.

[0015] Figure 3A portion of an arithmetic circuit including an adder according to one or more exemplary embodiments of the present disclosure is shown.

[0016] Figure 4 A part of an arithmetic circuit including an adder according to the prior art is shown.

[0017] Note that in the embodiments described below, sometimes the same reference numerals are used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In some cases, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0018] For ease of understanding, the position, size, range, etc. of each structure shown in the drawings and the like may not represent the actual position, size, range, etc. Therefore, the present disclosure is not limited to the position, size, range, etc. disclosed in the drawings and the like. DETAILED DESCRIPTION

[0019] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0020] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0021] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0022] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0023] Figure 1 FIG. 1 is a schematic diagram of an adder 100 according to one or more exemplary embodiments of the present disclosure. The adder 100 is used to calculate the sum of two input numbers.

[0024] like Figure 1As shown, the adder 100 has two inputs 111, 112 and two outputs 161, 162. The two inputs 111, 112 represent two input numbers respectively, and the outputs 161, 162 represent the sum and the carry of the sum of the two numbers respectively.

[0025] Those skilled in the art will appreciate that the configuration of the input and output of the adder 100 is not limited to Figure 1 The embodiment shown. The configuration of the input and output of the adder 100 can be appropriately adjusted according to the function of the adder and the needs of the operation circuit, and the configuration of each module of the adder 100 can be adjusted accordingly. For example, in some embodiments, the adder can also have only one output, that is, only the sum of the summation results is output without outputting the carry.

[0026] like Figure 1 As shown, each input 111, 112 is divided into N sub-parts corresponding to each other, and the N sub-parts represent partial bits of the input in order from low to high. For example, the input 111 is divided into sub-parts 111-1, 111-2, ..., 111-N from low to high, and the input 112 is divided into sub-parts 112-1, 112-2, ..., 112-N from low to high.

[0027] Specifically, the first sub-parts 111-1 and 112-1 represent the lowest bit or bits of the inputs 111 and 112, respectively, and the bits represented by 111-1 and 112-1 are the same. Correspondingly, the second sub-parts 111-2 and 112-2 represent the bits of the inputs 111 and 112 that are higher than 111-1 and 112-1, respectively, and the bits represented by 111-2 and 112-2 are the same. By analogy, the N-th sub-parts 111-N and 112-N represent the highest bit or bits of the inputs 111 and 112, respectively, and the bits represented by 111-N and 112-N are the same.

[0028] Wherein, N should be an integer greater than or equal to 2. That is, each input 111, 112 has at least two sub-parts.

[0029] In a preferred embodiment, Figure 1 As shown, the output 161 representing the sum of the inputs 111 and 112 is divided into two sub-parts 161-1 and 161-2. Among them, 161-1 corresponds to the first sub-parts 111-1 and 112-1 of the inputs 111 and 112, and represents the lowest bit or bits of the output 161; 161-2 corresponds to the other sub-parts of the inputs 111 and 112, and represents the other bits or bits of the output 161.

[0030] Those skilled in the art should understand that the division of the input and output into multiple sub-parts herein is only for the convenience of describing the different coupling relationships of the various sub-parts, and does not mean or imply that the various sub-parts must be physically separated or isolated. In particular, those skilled in the art should understand that the division of the input and output into multiple sub-parts with different coupling relationships does not require the introduction of additional components in the digital circuit or generate additional costs.

[0031] like Figure 1 As shown, the adder 100 includes a first-stage adding module group 120 , an intermediate register group 130 , a carry register group 140 , and a second-stage adding module 150 .

[0032] The first stage adding module group 120 is coupled to the inputs 111 and 112 and includes a plurality of first stage adding modules 120 - 1 , 120 - 2 , . . . , 120 -N. Each first stage adding module 120 - 1 , 120 - 2 , . . . , 120 -N is used to sum corresponding sub-parts of the two inputs 111 and 112 .

[0033] For example, the first first-stage adding module 120 - 1 is coupled to the first sub-parts 111 - 1 and 112 - 1 of the two inputs 111 , 112 for summing 111 - 1 and 112 - 1 .

[0034] The number of the first-stage adding modules is equal to the number of the sub-portions of the input, and the configuration of each first-stage adding module may be determined according to the number of bits of the corresponding sub-portion of the input.

[0035] The output of the first-stage addition module group 120 is coupled to the intermediate register group 130 and the carry register group 140 , and the sum and the carry of the summation result are output to the intermediate register group 130 and the carry register group 140 respectively.

[0036] The intermediate register group 130 includes a plurality of intermediate registers 130-1, 130-2, ..., 130-N. Each intermediate register 130-1, 130-2, ..., 130-N is coupled to a corresponding first-stage addition module 120-1, 120-2, ..., 120-N and is used to store the sum of the summation results of the corresponding sub-parts of the two inputs 111 and 112.

[0037] For example, the first intermediate register 130-1 is coupled to the first first-stage addition module 120-1, and is used to store the sum of the sum of 111-1 and 112-1. That is, the first intermediate register 130-1 corresponds to the first sub-parts 111-1 and 112-1 of the two inputs 111 and 112, and is used to store the sum of the sum of the lowest one or more bits of the two inputs 111 and 112 represented by 111-1 and 112-1.

[0038] The number of intermediate registers is equal to the number of sub-portions of the input, and the configuration of each intermediate register may be determined according to the number of bits of the corresponding sub-portion of the input.

[0039] The carry register group 140 includes a plurality of carry registers 140-1, 140-2, ..., 140-N. Each carry register 140-1, 140-2, ..., 140-N is coupled to a corresponding first-stage addition module 120-1, 120-2, ..., 120-N and is used to store the carry of the summation result of the corresponding sub-parts of the two inputs 111 and 112.

[0040] For example, the first carry register 140-1 is coupled to the first first-stage addition module 120-1 and is used to store the carry of the sum of 111-1 and 112-1. That is, the first carry register 140-1 is used to store the carry of the sum of the lowest bit or bits of the two inputs 111 and 112 represented by 111-1 and 112-1.

[0041] The number of carry registers can be determined based on the number of subdivisions of the input. Figure 1 In the preferred embodiment shown, the number of carry registers is equal to the number of sub-parts of the input. In other embodiments, the number of carry registers may be one less than the number of sub-parts of the input. That is, the Nth carry register 140-N may not exist in the carry register group 140, and the carry of the sum result of the most significant bit or bits of the two inputs 111 and 112 represented by 111-N and 112-N is not stored.

[0042] The number of carry registers can be determined as needed. In an embodiment where the adder 100 needs to output the carry of the summation result of the two inputs 111 and 112 (i.e., the adder 100 includes an output 162), the number of carry registers can be determined to be equal to the number of sub-parts of the input. In an embodiment where the adder 100 does not need to output the carry of the summation result of the two inputs 111 and 112 (i.e., the adder 100 does not include an output 162), the number of carry registers can be determined to be 1 less than the number of sub-parts of the input, thereby minimizing the additional cost of the adder 100. For example, in an embodiment where the two inputs 111 and 112 each have two sub-parts, the adder 100 may include only one carry register.

[0043] The carry register is only used to store the carry, so each carry register can be implemented by a 1-bit register.

[0044] The outputs of the intermediate register group 130 and the carry register group 140 are coupled to the second-stage addition module 150 , and the results of summing the corresponding sub-parts of the two inputs 111 , 112 (including the sum and the carry) are output to the second-stage addition module 150 .

[0045] The second-stage adding module 150 is used to sum the sum from each intermediate register and the carry from the corresponding previous carry register, so as to obtain the sum of the two inputs 111 and 112.

[0046] Specifically, the second-stage addition module 150 can output the sum of the lowest one or more bits of the sum of the two inputs 111 and 112 represented by 111-1 and 112-1 output from the first intermediate register 130-1 as the corresponding lowest one or more bits of the sum of the sum of the two inputs 111 and 112 (i.e., sub-part 161-1 of output 161).

[0047] Further, the second-stage addition module 150 can sum the sum of the one or more bits of the sum of the two inputs 111 and 112 outputted from the second intermediate register 130-2 represented by 111-2 and 112-2 and the carry of the sum of the lowest one or more bits of the two inputs 111 and 112 outputted from the first carry register 140-1, and then output the sum of the summed results as the corresponding one or more bits of the sum of the two inputs 111 and 112, and use the carry of the summed results for further operations in the second-stage addition module 150.

[0048] By analogy, the second-stage addition module 150 can sum the sum of the highest bit or bits represented by 111-N and 112-N of the two inputs 111 and 112 output from the Nth intermediate register 130-N with the carry of the sum of the highest bit or bits represented by 111-N-1 and 112-N-1 of the two inputs 111 and 112 output from the N-1th carry register 140-N-1, and then output the sum of the summed results as the corresponding highest bit or bits of the sum of the two inputs 111 and 112.

[0049] Further, the second-stage addition module 150 can sum the carry of the above-mentioned summation result with the carry of the summation result of the highest bit or bits represented by 111-N and 112-N of the two inputs 111 and 112 output from the Nth carry register 140-N, and then output the summation result as the carry of the summation result of the two inputs 111 and 112, that is, output 162.

[0050] Those skilled in the art will appreciate that the processing performed by the second-stage addition module 150 is not limited to the processing described above. The configuration of the second-stage addition module 150 may be determined according to the function of the adder 100. For example, in an embodiment where it is not necessary to output the carry of the summation result of the two inputs 111 and 112 (i.e., the adder does not include the output 162), the second-stage addition module 150 may not perform the processing for calculating and outputting the carry of the summation result of the two inputs 111 and 112.

[0051] The output of the second stage addition module 150 is coupled to outputs 161 and 162 , which represent the sum and carry of the summation results of the two inputs 111 and 112 , respectively.

[0052] In a preferred embodiment, the output 161 can be divided into two sub-parts: a first sub-part 161-1, which represents the lowest one or more bits of the sum of the two inputs 111 and 112 corresponding to 111-1 and 112-1; and a second sub-part 161-2, which represents the other one or more bits of the sum of the two inputs 111 and 112.

[0053] like Figure 1 As shown, preferably, the second-stage adding module 150 may directly couple the output of the first intermediate register 130 - 1 to the first sub-portion 161 - 1 of the output 161 .

[0054] Those skilled in the art should understand that the register mentioned in this document may be an edge-triggered register (eg, a D-type flip-flop) or a level-triggered register (eg, a latch).

[0055] The calculation speed of the adder 100 mainly depends on the calculation speed of the first-stage addition module group 120 and the second-stage addition module 150, and the calculation speed of the first-stage addition module group 120 and the second-stage addition module 150 is related to the number and the number of bits of the sub-parts of the two inputs 111 and 112. Therefore, the number and the number of bits of the sub-parts of the two inputs 111 and 112 can be appropriately determined to optimize the calculation speed of the adder 100.

[0056] The overall calculation delay of the first-stage addition module group 120 is determined by the calculation delay of the first-stage addition module with the longest calculation delay among the multiple first-stage addition modules 120-1, 120-2, ..., 120-N. Each first-stage addition module 120-1, 120-2, ..., 120-N is used to sum the corresponding sub-parts of the two inputs 111 and 112. The more bits of the sub-part, the longer the calculation delay of the corresponding first-stage addition module.

[0057] Therefore, the overall calculation delay of the first-stage addition module group 120 depends on the maximum number of bits of the multiple sub-parts of the inputs 111 and 112. The larger the maximum number of bits, the longer the overall calculation delay of the first-stage addition module group 120.

[0058] The second-stage addition module 150 is used to sum the sums from multiple intermediate registers and the carries from the corresponding previous carry register. The output of the first intermediate register 130-1 represents the corresponding lowest bit or bits of the sum of the sum result. Therefore, the second-stage addition module 150 may not perform additional processing on the output of the first intermediate register 130-1. In particular, in some embodiments, the second-stage addition module 150 may also perform certain processing on the output of the first intermediate register 130-1 as needed, but the time consumption of such processing will be much less than the summation processing that the second-stage addition module 150 needs to perform on the outputs of other intermediate registers and the carry register as described above. In other words, the calculation delay of the second-stage addition module 150 is determined by the calculation delay of the summation processing as described above.

[0059] Therefore, the calculation delay of the second-stage addition module 150 may depend on the number of other sub-parts of the multiple sub-parts of the input 111, 112 except the first sub-part 111-1, 112-1 and the sum of their bit numbers. The more the number of the other sub-parts is, or the larger the sum of their bit numbers is, the longer the calculation delay of the second-stage addition module 150 is. In other words, the fewer the number of sub-parts of the input 111, 112 is, or the larger the number of bits of the first sub-part 111-1, 112-1 is, the shorter the calculation delay of the second-stage addition module 150 is.

[0060] Therefore, it is desirable to reduce the maximum number of bits among the number of bits of the multiple sub-parts of the two inputs 111, 112. At the same time, it is desirable to reduce the number of sub-parts of the inputs 111, 112, and it is desirable to increase the number of bits of the first sub-part.

[0061] In a preferred embodiment, the number of bits of the first sub-parts 111-1, 112-1 of the inputs 111, 112 is greater than or equal to the number of bits of the other sub-parts. In a further preferred embodiment, the number of bits of the multiple sub-parts of the inputs 111, 112 is substantially equal. This is conducive to reducing the calculation delay of the first-stage addition module group 120 and the second-stage addition module 150, thereby improving the calculation speed of the adder 100, and further reducing the power consumption and computing power ratio of the chip.

[0062] In a preferred embodiment, the input 111, 112 has two sub-parts, and the number of bits of the first sub-part 111-1, 112-1 is greater than or equal to half of the number of bits of the input 111, 112. This is beneficial for minimizing the additional cost while increasing the calculation speed of the adder 100.

[0063] It should be noted that the expression "substantially equal" herein means that the two are roughly equal, but not necessarily strictly and precisely equal. Those skilled in the art should understand that this is in line with technical principles and engineering practices. For example, the two may differ by about 5% or 10%. In some contexts, the two may differ by about 15% or 20%.

[0064] Figure 2 FIG. 2 is a schematic diagram of an adder 200 according to one or more exemplary embodiments of the present disclosure. The adder 200 is used to calculate the sum of an input number and a predetermined constant.

[0065] like Figure 2 As shown, the adder 200 has an input 210 and two outputs 261, 262. The input 210 represents an input number, and the outputs 261, 262 represent the sum and carry of the sum of the number and a predetermined constant, respectively.

[0066] Similarly, in some embodiments, the adder 200 may also have only one output 261, that is, only the sum of the summation results is output without outputting the carry.

[0067] The configuration of the adder 200 is similar to that of the adder 100 and can be appropriately adjusted according to the predetermined constant.

[0068] like Figure 2 As shown, the input 210 is divided into N sub-parts, and the N sub-parts represent the partial bits of the input in order from low to high. That is, the input 210 is divided into sub-parts 210-1, 210-2, ..., 210-N from low to high. Among them, N should be an integer greater than or equal to 2. That is, the input 210 has at least two sub-parts.

[0069] In a preferred embodiment, Figure 2 As shown, the output 261 representing the sum of the input 210 and the constant is divided into two sub-parts 261-1 and 261-2. Among them, 261-1 corresponds to the first sub-part 210-1 of the input 210, representing the lowest bit or bits of the output 261; 261-2 corresponds to the other sub-parts 210-2, ..., 210-N of the input 210, representing the other bits or bits of the output 261.

[0070] like Figure 2 As shown, the adder 200 includes a first-stage adding module group 220 , an intermediate register group 230 , a carry register group 240 , and a second-stage adding module 250 .

[0071] The first stage addition module group 220 is coupled to the input 210 and includes a plurality of first stage addition modules 220-1, 220-2, ..., 220-N. Each first stage addition module 220-1, 220-2, ..., 220-N is used to sum a corresponding sub-portion of the input 210 and a corresponding bit of the constant.

[0072] The configuration of each first-stage addition module 220-1, 220-2, ..., 220-N may be related to the corresponding bit of the constant. In a preferred embodiment, the number and configuration of the first-stage addition modules 220-1, 220-2, ..., 220-N may be determined or adjusted at least in part based on the constant. For example, for any sub-portion of the input 210, if it is known that the corresponding bits of the predetermined constant are all zero, then the sub-portion and the corresponding bits of the constant may not be summed, and thus the first-stage addition module group 220 may not include the corresponding first-stage addition module. This is conducive to reducing the manufacturing cost of the adder 200.

[0073] For example, in a preferred embodiment, if the constant is small (i.e., all higher bits are zero), the first-stage addition module group 220 may include only one first-stage addition module, i.e., only the first first-stage addition module 220-1 corresponding to the first sub-portion 210-1 of the input 210. In particular, when the constant is 1, the adder 200 is a self-incrementing 1 adder and may include only one first-stage addition module.

[0074] The output of the first-stage addition module group 220 is coupled to the intermediate register group 230 and the carry register group 240 , and the summation result (including the sum and the carry) is output to the intermediate register group 230 and the carry register group 240 respectively.

[0075] The intermediate register group 230 includes a plurality of intermediate registers 230-1, 230-2, ..., 230-N. Figure 2 As shown, each intermediate register 230-1, 230-2, ..., 230-N is coupled to the corresponding first-stage addition module 220-1, 220-2, ..., 220-N for storing the sum of the corresponding sub-portion of the input 210 and the corresponding bit of the constant.

[0076] The carry register group 240 includes a plurality of carry registers 240-1, 240-2, ..., 240-N. Each carry register 240-1, 240-2, ..., 240-N is coupled to a corresponding first-stage addition module 220-1, 220-2, ..., 220-N for storing a carry of a summation result of a corresponding sub-portion of the input 210 and a corresponding bit of the constant.

[0077] The configurations of the intermediate register group 230 and the carry register group 240 may be appropriately adjusted according to the configuration of the first-stage addition module group 220. For example, when the first-stage addition module group 220 does not include a first-stage addition module corresponding to any sub-portion of the input 210, the corresponding intermediate register in the intermediate register group 230 may be directly coupled to the sub-portion of the input 210, and the carry register group 240 may not include a corresponding carry register.

[0078] exist Figure 2 In the preferred embodiment shown, the number of carry registers is equal to the number of sub-divisions of the input. In other embodiments, the number of carry registers may be one less than the number of sub-divisions of the input, ie, there is no Nth carry register 240-N.

[0079] The outputs of the intermediate register group 230 and the carry register group 240 are coupled to the second-stage addition module 250 , and the results of summing the sub-parts of the input 210 and the corresponding bits of the constant (including the sum and the carry) are output to the second-stage addition module 250 .

[0080] The second-stage addition module 250 is used to sum the sum from each intermediate register and the carry from the corresponding previous carry register, that is, to sum the results of summing each sub-part of the input 210 and the corresponding bits of the constant (including the sum and the carry), so as to obtain the sum of the input 210 and the constant.

[0081] Specifically, the second-stage addition module 250 can output the sum of the lowest bit or bits represented by 210-1 of the input 210 output from the first intermediate register 230-1 and the corresponding lowest bit or bits of the constant as the corresponding lowest bit or bits of the sum of the input 210 and the constant (i.e., sub-portion 261-1 of output 261).

[0082] Further, the second-stage addition module 250 can sum the sum of one or more bits represented by 210-2 of the input 210 output from the second intermediate register 230-2 and the corresponding one or more bits of the constant with the carry output from the first carry register 240-1, and then output the sum of the summation results as the corresponding one or more bits of the sum of the input 210 and the constant, and use the carry of the summation result for further operations in the second-stage addition module 250.

[0083] By analogy, the second-stage addition module 250 can sum the sum of the highest bit or bits represented by 210-N of the input 210 output from the Nth intermediate register 230-N and the corresponding highest bit or bits of the constant with the carry output from the N-1th carry register 240-N-1, and then output the sum of the summation results as the corresponding highest bit or bits of the sum of the input 210 and the constant.

[0084] Furthermore, the second-stage addition module 250 may sum the carry of the above summation result with the carry output from the Nth carry register 240-N, and then output the summation result as the carry of the summation result of the input 210 and the constant (ie, output 262).

[0085] Those skilled in the art will appreciate that the processing performed by the second-stage adding module 250 is not limited to the above. The configuration of the second-stage adding module 250 may be determined according to the function of the adder. For example, in an embodiment where the adder 200 does not include the output 262, the configuration of the second-stage adding module 250 and the processing performed by it may be adjusted accordingly.

[0086] The output of the second stage addition module 250 is coupled to outputs 261 and 262, which respectively represent the sum and carry of the sum of the input 210 and the constant.

[0087] In a preferred embodiment, the output 261 can be divided into two sub-parts: a first sub-part 261-1, which represents the lowest one or more bits of the sum of the input 210 and the constant corresponding to 210-1; and a second sub-part 261-2, which represents the other one or more bits of the sum of the input 210 and the constant. Figure 2 As shown, preferably, the second-stage adding module 250 may directly couple the output of the first intermediate register 230 - 1 to the first sub-portion 261 - 1 of the output 261 .

[0088] The calculation speed of the adder 200 mainly depends on the calculation speeds of the first-stage adding module group 220 and the second-stage adding module 250 .

[0089] Regarding the second-stage addition module 250, similarly, the smaller the number of sub-divisions of the input 210, or the larger the number of bits of the first sub-division 210-1, the shorter the computational delay of the second-stage addition module 250. Therefore, it is desirable to reduce the number of sub-divisions of the input 210 and increase the number of bits of the first sub-division 210-1.

[0090] On the other hand, unlike the adder 100, in the adder 200, the configuration of the first-stage addition modules 220-1, 220-2, ..., 220-N can be related to the constant. As described above, if the corresponding bits of the constant are all zero for a certain sub-portion of the input 210, the corresponding first-stage addition module may not be included in the first-stage addition module group 220. Therefore, the calculation delay of the first-stage addition module group 220 is independent of the number of bits of such a sub-portion, but only depends on the number of bits of other sub-portions of the input 210 (i.e., for these sub-portions, the corresponding bits of the constant are not all zero). Specifically, it is expected to appropriately increase the number of bits of the sub-portion corresponding to the all-zero bits of the constant, and it is expected to reduce the maximum number of bits among the number of bits of other sub-portions.

[0091] In a preferred embodiment, the number of sub-portions of input 210 and the number of bits in each sub-portion are determined at least in part based on the constant. For example, if the constant is small (i.e., the higher bits of the constant are all zero, such as the constant is 1), input 210 can have two sub-portions, such that the bits of the constant corresponding to the second sub-portion are all zero. For example, if the constant includes a plurality of consecutive bits that are all zero, a sub-portion of input 210 can be divided corresponding to at least a portion of the consecutive bits.

[0092] Figure 3 A portion of an operation circuit 3000 including an adder 300 according to one or more exemplary embodiments of the present disclosure is shown.

[0093] As an example only, Figure 3 In FIG. 1 , adder 300 is shown as Figure 1 However, those skilled in the art will appreciate that the adder 300 may be replaced by an adder 310 as shown in FIG. Figure 2 The adder shown for calculating the sum of an input number and a predetermined constant only requires appropriate adjustments to the operation circuit 3000.

[0094] The operation circuit 3000 includes the previous stage registers 3101 and 3102, the adder 300, and the next stage register 3200. In addition, the operation circuit 3000 may further include a pre-combinatorial logic module 3110 and a post-combinatorial logic module 3120.

[0095] The previous stage registers 3101 and 3102 are directly coupled to the adder 300 or are optionally coupled to the adder 300 via the pre-combinatorial logic module 3110. The adder 300 is directly coupled to the next stage register 3200 or are optionally coupled to the post-combinatorial logic module 3120.

[0096] Those skilled in the art should understand that the number and configuration of the previous registers 3101, 3102 and the next register 3200 are not limited to Figure 3 For example, in some embodiments, the operation circuit 3000 may include only one previous-stage register 3101 , and the previous-stage register 3101 provides two inputs 311 and 312 to the adder 300 via a pre-combinatorial logic module 3110 .

[0097] Just as an example, Figure 3 The embodiment in which the operation circuit 3000 includes a pre-combinatorial logic module 3110 and a post-combinatorial logic module 3120 is shown. Those skilled in the art should understand that the following description can also be applied to the embodiment in which the operation circuit 3000 does not include the pre-combinatorial logic module 3110 or the post-combinatorial logic module 3120, and only needs to be appropriately adjusted.

[0098] Adder 300 and Figure 1 The illustrated adder 100 is similarly configured.

[0099] The adder 300 has two inputs 311 and 312 respectively representing two numbers input, and two outputs 361 and 362 respectively representing the sum and carry of the sum of the two numbers. The output 361 has two sub-parts 361-1 and 361-2.

[0100] The adder 300 includes: a first-stage adding module group 320, an intermediate register group 330 including a plurality of intermediate registers 330-1, 330-2, ..., 330-N, a carry register group 340, and a second-stage adding module 350. Preferably, the second-stage adding module 350 directly couples the output of the first intermediate register 330-1 to the first sub-portion 361-1 of the output 361.

[0101] In the operation circuit 3000, the frequencies of the clocks used for the previous-stage registers 3101 and 3102, the intermediate register group 330, and the next-stage register 3200 are the same. Therefore, it is expected that the operation of the front-stage combinational logic module 3110 and the first-stage addition module group 320 can be completed within one clock cycle, and the operation of the second-stage addition module 350 and the post-stage combinational logic module 3120 can be completed within one clock cycle.

[0102] Therefore, it is expected that the calculation delay of the first-level addition module group 320 is smaller than the difference between the clock cycle and the calculation delay of the front-end combinational logic module 3110, and the calculation delay of the second-level addition module 350 is smaller than the difference between the clock cycle and the calculation delay of the post-combinatorial logic module 3120.

[0103] As for the first-stage addition module group 320, as described above, in the adder 300, the larger the maximum number of bits among the multiple sub-parts of the inputs 311 and 312, the longer the calculation delay of the first-stage addition module group 320. Therefore, the upper limit of the maximum number of bits among the multiple sub-parts of the inputs 311 and 312 can be determined at least in part based on the difference between the clock cycle and the calculation delay of the front-end combinational logic module 3110.

[0104] In a preferred embodiment, the maximum number of bits of the multiple sub-parts of the inputs 311 and 312 of the adder 300 may be determined at least in part based on the difference between the clock cycle and the calculation delay of the front combinatorial logic module 3110. Specifically, the maximum number of bits may be determined such that the calculation delay of the first-stage addition module group 320 is less than the difference between the clock cycle and the calculation delay of the front combinatorial logic module 3110. Further preferably, the maximum number of bits may be determined such that the calculation delay of the first-stage addition module group 320 is substantially equal to the difference between the clock cycle and the calculation delay of the front combinatorial logic module 3110.

[0105] Furthermore, in an embodiment where the operation circuit 3000 does not include the preceding combinational logic module 3110 , the maximum number of bits among the plurality of sub-parts of the inputs 311 , 312 of the adder 300 is preferably determined at least in part based on the clock cycle.

[0106] On the other hand, in the adder 300 Figure 2 In the case of the adder for calculating the sum of an input number and a predetermined constant, the calculation delay of the first-stage addition module group 320 is also related to the constant. As described above, the number of bits of the multiple sub-parts can be adjusted according to the constant.

[0107] Therefore, in a preferred embodiment, the maximum number of bits in the multiple sub-parts of the input of the adder 300 can be determined first according to the difference between the clock cycle and the calculation delay of the front combinational logic module 3110, and then the number of bits of the multiple sub-parts can be adjusted according to the constant. For example, if the constant includes a plurality of continuous bits that are all zero, a sub-part of the input can be divided corresponding to the continuous bits, regardless of whether the number of bits of the sub-part is greater than the determined maximum number of bits. Further preferably, the number of bits of the multiple sub-parts of the input can be adjusted so that the maximum number of bits in the sub-part that does not correspond to the all-zero bits of the constant is substantially equal to the determined maximum number of bits.

[0108] As for the second-stage adding module 350, as described above, in the adder 300, the more the number of sub-parts of the inputs 311 and 312 is, or the smaller the number of bits of the first sub-part is, the longer the calculation delay of the second-stage adding module 350 is. Therefore, the lower limit of the number of bits of the first sub-part of the inputs 311 and 312 of the adder 300 can be determined at least in part based on the difference between the clock cycle and the calculation delay of the post-combinatorial logic module 3120.

[0109] In a preferred embodiment, the number of bits of the first sub-portion of the inputs 311, 312 of the adder 300 is determined at least in part based on the difference between the clock cycle and the computational delay of the post-combinatorial logic module 3120. Specifically, the number of bits of the first sub-portion can be determined such that the computational delay of the second-stage addition module 350 is less than the difference between the clock cycle and the computational delay of the post-combinatorial logic module 3120. Further preferably, the number of bits of the first sub-portion can be determined such that the computational delay of the second-stage addition module 350 is substantially equal to the difference between the clock cycle and the computational delay of the post-combinatorial logic module 3120.

[0110] Furthermore, in embodiments where the operation circuit 3000 does not include a post-combinatorial logic module 3120, the number of bits of the first sub-portion of the inputs 311, 312 of the adder 300 is preferably determined at least in part based on a clock cycle.

[0111] On the other hand, as mentioned above, the number of bits of the first sub-part of the input 311, 312 is preferably determined to be greater than or equal to the number of bits of other sub-parts. Further preferably, the number of bits of multiple sub-parts of the input 311, 312 is determined to be substantially equal.

[0112] Further preferably, the strategies described above may be combined to determine the number and the number of bits of the sub-parts of the inputs 311 , 312 of the adder 300 .

[0113] For example, in a preferred embodiment, the number of bits of the first sub-part of the inputs 311 and 312 of the adder 300 can be determined first according to the difference between the clock cycle and the calculation delay of the front-end combinational logic module 3110 and the difference between the clock cycle and the calculation delay of the post-combinatorial logic module 3120. For example, the upper limit of the number of bits of the first sub-part can be determined according to the difference between the clock cycle and the calculation delay of the front-end combinational logic module 3110, and the lower limit of the number of bits of the first sub-part can be determined according to the difference between the clock cycle and the calculation delay of the post-combinatorial logic module 3120.

[0114] Then, if the number of bits of the determined first sub-part is greater than or equal to half of the number of bits of the input 311, 312, the other bits of the input 311, 312 can be divided into the second sub-part. In this way, the input 311, 312 is divided into two sub-parts, wherein the number of bits of the first sub-part is greater than or equal to the number of bits of the second sub-part.

[0115] If the number of bits of the determined first sub-portion is less than half of the number of bits of the inputs 311 and 312, the other bits of the inputs 311 and 312 may be divided into a number of sub-portions, such that the number of these sub-portions is as small as possible and the number of bits of each sub-portion is less than or equal to the number of bits of the determined first sub-portion. For example, the number of bits of these sub-portions may be determined to be substantially equal to the number of bits of the first sub-portion.

[0116] In the adder 300 Figure 2 In the case of the adder 200 shown for calculating the sum of an input number and a predetermined constant, the number and the number of bits of the sub-parts can be adjusted according to the constant. For example, if the constant includes a continuous plurality of bits that are all zero, a sub-part of the input can be divided corresponding to the continuous plurality of bits, regardless of whether the number of bits of the sub-part is greater than the number of bits of the first sub-part determined.

[0117] Those skilled in the art should understand that the manner of determining the number and the number of bits of the sub-parts of the input of the adder is not limited to the specific embodiments described above. The various strategies described herein may be used independently or in combination to determine the number and the number of bits of the sub-parts of the input of the adder by comprehensively considering various factors such as the function, configuration, area, cost, speed, power consumption, etc. of the adder and the arithmetic circuit.

[0118] Compared with the prior art that requires the use of high-speed devices, the present invention achieves an increase in the operating speed of the adder at a lower cost and lower power consumption.

[0119] As a comparison, Figure 4 A portion of an operational circuit 4000 including an adder 4120 according to the prior art is shown.

[0120] The operation circuit 4000 includes first-stage registers 4101 and 4102 , a front-stage combinational logic module 4110 , an adder 4120 , a second-stage register 4200 , a post-stage combinational logic module 4210 , and a third-stage register 4300 .

[0121] The first-stage registers 4101 and 4102 are coupled to the second-stage register 4200 via the pre-combinatorial logic module 4110 and the adder 4120 . The second-stage register 4200 is coupled to the third-stage register 4300 via the post-combinatorial logic module 4210 .

[0122] It can be seen that Figure 4 The first-stage registers 4101 and 4102, the second-stage register 4200 and the third-stage register 4300 in the operation circuit 4000 respectively correspond to Figure 3 The preceding registers 3101 and 3102, the intermediate register group 330 and the following register 3200 in the operation circuit 3000 are shown. Accordingly, the preceding combinational logic module 4110 and the following combinational logic module 4210 in the operation circuit 4000 correspond to the preceding combinational logic module 3110 and the following combinational logic module 3120 in the operation circuit 3000, respectively.

[0123] The important difference between the present invention and the prior art is that Figure 4 The adder 4120 in the prior art operation circuit 4000 is coupled between the first-stage registers 4101, 4102 and the second-stage register 4200. Figure 3 The adder 300 in the operation circuit 3000 of the present invention is coupled between the previous-stage registers 3101 and 3102 and the next-stage register 3200 across the intermediate register group 330 .

[0124] exist Figure 4 In the prior art shown in FIG. 4 , the adder 4120 can only operate together with the pre-combinatorial logic module 4110 using the clock cycle between the first-stage registers 4101 and 4102 and the second-stage register 4200. Figure 3 In the technical solution of the present invention shown, the adder 300 can perform operations together with the pre-combinatorial logic module 3110 and the post-combinatorial logic module 3120 using two clock cycles between the previous-stage registers 3101, 3102 and the intermediate register group 330 and between the intermediate register group 330 and the next-stage register 3200. In the technical solution of the present invention, the configuration of the adder 300 can be appropriately adjusted according to the configuration of the pre-combinatorial logic module 3110 and the post-combinatorial logic module 3120, so as to more fully and flexibly use the time of two clock cycles to complete the addition operation.

[0125] In addition, those skilled in the art should understand that Figure 3 The operations performed by the first-stage adding module group 320 and the second-stage adding module 350 in the adder 300 are as follows: Figure 4 The operations performed by the adder 4120 shown are substantially the same. In other words, the adder 4120 also has modules or units that are the same or corresponding to the first-stage adding module group 320 and the second-stage adding module 350 in the adder 300. Therefore, compared with the prior art, the configuration of the first-stage adding module group 320 and the second-stage adding module 350 in the adder 300 does not introduce additional costs.

[0126] That is to say, Figure 4 Compared with the prior art shown in Figure 3 The only additional module or unit required by the adder 300 in the operation circuit 3000 shown is the carry register group 340. As mentioned above, each carry register in the carry register group 340 is implemented by a 1-bit register, which has a low manufacturing cost. Figure 4 Compared with the prior art shown, the additional cost of implementing the adder of the present invention is basically only the manufacturing cost of several 1-bit registers.

[0127] Therefore, compared with the prior art, the adder proposed in the present invention creatively utilizes the clock cycle of an adjacent stage to complete part of the operation, thereby effectively improving the operation speed of the adder and the operation circuit including the adder at a lower cost.

[0128] The adder and the operation circuit according to the present disclosure may be implemented in various appropriate ways such as software, hardware, a combination of software and hardware, etc. In one implementation, a chip may include the operation circuit as described above, and the chip may also be included in a computing device.

[0129] The words "front", "rear", "top", "bottom", "above", "below", etc., if present, in the specification and claims are used for descriptive purposes and are not necessarily used to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances, such that the embodiments of the disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0130] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not limited by any expressed or implied theory given in the above technical field, background technology, summary of the invention, or detailed description.

[0131] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0132] In addition, the foregoing description may have referred to elements or nodes or features that are "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature electrically, mechanically, logically or otherwise. Similarly, unless otherwise expressly stated, "coupling" means that one element / node / feature can be mechanically, electrically, logically or otherwise connected to another element / node / feature in a direct or indirect manner to allow interaction, even if the two features may not be directly connected. In other words, "coupling" is intended to include direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0133] In addition, the terms "first", "second" and the like may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first", "second" and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0134] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0135] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0136] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0137] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An adder for calculating the sum of two input numbers, characterized in that: The adder has two inputs representing the two numbers respectively, wherein each input is divided into a plurality of sub-parts corresponding to each other, and the plurality of sub-parts represent partial bits of the input in sequence from low bits to high bits, and the adder comprises: a plurality of first stage adding modules, each first stage adding module being configured to sum corresponding sub-portions of the two inputs; a plurality of intermediate registers, each intermediate register being coupled to a corresponding first-stage addition module and configured to store a sum of corresponding sub-portions of the two inputs; one or more carry registers, each carry register coupled to a corresponding first stage addition module, for storing a carry of a corresponding sub-portion of the two inputs; and a second stage addition module, coupled to the plurality of intermediate registers and the one or more carry registers, for summing the sum from each intermediate register and the carry from the corresponding previous carry register, The overall computation delay of the plurality of first-stage addition modules depends on the maximum number of bits among the plurality of sub-parts of the two inputs.

2. The adder according to claim 1, characterized in that The second stage adding module couples the output of a first intermediate register of the plurality of intermediate registers corresponding to a first sub-portion of the input directly to the output of the adder, wherein the first sub-portion represents the least significant bit or bits of the input.

3. The adder according to claim 1 or 2, characterized in that: The number of bits of the first sub-part of the two inputs is greater than or equal to the number of bits of the other sub-parts.

4. The adder according to claim 1 or 2, characterized in that: Each input has two sub-parts.

5. An adder for calculating the sum of an input number and a predetermined constant, characterized in that: The adder has an input representing the number, the input is divided into a plurality of sub-parts, the plurality of sub-parts sequentially representing partial bits of the input from low bits to high bits, and the adder comprises: one or more first stage addition modules, each first stage addition module being configured to sum a corresponding sub-portion of the input and a corresponding bit of the constant; a plurality of intermediate registers, each intermediate register being coupled to a corresponding first-stage addition module and configured to store a sum of a corresponding sub-portion of the input and a corresponding bit of the constant; one or more carry registers, each carry register being coupled to a corresponding first-stage addition module and configured to store a carry of a corresponding sub-portion of the input and a corresponding bit of the constant; and a second stage addition module, coupled to the plurality of intermediate registers and the one or more carry registers, for summing the sum from each intermediate register and the carry from the corresponding previous carry register, The calculation delay of the one or more first-stage adding modules is related to the constant.

6. The adder according to claim 5, characterized in that The second stage adding module couples the output of a first intermediate register of the plurality of intermediate registers corresponding to a first sub-portion of the input directly to the output of the adder, wherein the first sub-portion represents the least significant bit or bits of the input.

7. The adder according to claim 5 or 6, characterized in that: The number of sub-portions of the input and the number of bits per sub-portion are determined at least in part by the constant.

8. The adder according to claim 5 or 6, characterized in that: The number and configuration of the first stage addition modules are determined at least in part based on the constant.

9. The adder according to claim 8, characterized in that The constant is 1.

10. The adder according to claim 5 or 6, characterized in that: The input has two sub-parts.

11. A computing circuit, characterized in that: The operation circuit comprises: An adder according to any one of claims 1 to 10; and A pre-combinatorial logic module coupled to the input of the adder, and / or a post-combinatorial logic module coupled to the output of the adder.

12. The operation circuit according to claim 11, characterized in that: The number of sub-portions of the input of the adder and the number of bits of each sub-portion are determined at least in part according to the period of the clock for the operation circuit, the calculation delay of the preceding combinatorial logic module and / or the following combinatorial logic module.

13. The operation circuit according to claim 12, characterized in that: If the operation circuit includes a pre-combinatorial logic module, the maximum number of bits of the plurality of sub-parts of the input of the adder is determined at least in part based on a difference between a period of a clock for the operation circuit and a calculation delay of the pre-combinatorial logic module, If the arithmetic circuit does not include a preceding combinatorial logic module, a maximum number of bits of the plurality of sub-portions of the input to the adder is determined based at least in part on a period of a clock for the arithmetic circuit.

14. The operation circuit according to claim 12, characterized in that: If the arithmetic circuit includes a post-combinatorial logic module, the number of bits of the first sub-portion of the input of the adder is determined at least in part based on the difference between the period of the clock for the arithmetic circuit and the calculation delay of the post-combinatorial logic module, If the arithmetic circuit does not include a post-combinatorial logic module, the number of bits of the first sub-portion of the input to the adder is determined at least in part based on the period of the clock for the arithmetic circuit.

15. A chip, characterized in that: The chip comprises the operation circuit according to any one of claims 11-14.

16. A computing device, characterized in that: The computing device comprises the chip according to claim 15.

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