A packaging structure and packaging method for high voltage power semiconductor chip

Abstract

A packaging structure and packaging method for a high-voltage power semiconductor chip, the packaging structure for the high-voltage power semiconductor chip comprising: a substrate; a high-voltage power semiconductor chip located on the substrate, the high-voltage power semiconductor chip having a gate on a side opposite to the substrate; a first packaging frame cover covering the high-voltage power semiconductor chip, the first packaging frame cover having a first top plate, the first top plate having a gate reserved opening; a gate lead-out portion, one end of the gate lead-out portion being located in the gate reserved opening and electrically connected to the gate. The parasitic inductance of the packaging structure for the high-voltage power semiconductor chip is reduced.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor device packaging, and in particular to a packaging structure and a packaging method for a high-voltage power semiconductor chip. Background Art

[0002] In order to meet the large-scale development and utilization of renewable energy, the traditional power grid is developing towards the direction of smart grid represented by the widespread application of power electronics technology. Power electronic devices play an irreplaceable role in various fields such as the construction of strong smart grid of State Grid Corporation of China, FACTS high-voltage transmission, and access to new energy. This undoubtedly puts forward higher requirements for high-voltage, large-capacity, high-frequency, and high-temperature resistant power electronic devices. At present, most of the high-power power electronic devices in the power system use silicon-based power electronic devices to achieve the control and conversion of electric energy. Since silicon-based power electronic devices are subject to the limitations of the physical properties of the material itself, such as voltage resistance and operating temperature, in order to fundamentally improve the reliability and stability of high-power power electronic equipment, reduce the overall loss of the system, and improve the control and conversion efficiency of energy, it is necessary to research and develop new power electronic devices with higher voltage resistance, lower power consumption, and high temperature resistance. Silicon Carbide (SiC)-based devices are one of the most mature and widely used third-generation semiconductor power electronic devices so far. They can break the physical limits of traditional silicon-based devices and have the advantages of high voltage level, large current capacity, low loss, and fast heat dissipation. They can be widely used in new power electronic equipment such as solid-state transformers and solid-state circuit breakers, as well as traditional FACTS and DC transmission equipment. They will have an important impact on the economic and safe operation of power systems and realize the innovation of power grid technology.

[0003] The gate of a conventional silicon-based power electronic device is usually led out to another conductive layer by a bonding wire, and the gate test electrode and the conductive layer are sintered or welded together.

[0004] Currently, there are few packaging structures for high-voltage SiC-based devices. High-voltage SiC-based devices require low parasitic inductance. However, if high-voltage SiC-based devices use the same packaging form as silicon-based power electronic devices, it is difficult to meet the performance requirements of high-voltage SiC-based devices due to the large number of bonding wires and the resulting parasitic inductance. Summary of the invention

[0005] The technical problem to be solved by the present invention is to overcome the defect of high parasitic inductance of high-voltage power semiconductor chips in the prior art.

[0006] In order to solve the above technical problems, the present invention provides a packaging structure of a high-voltage power semiconductor chip, comprising: a substrate; a high-voltage power semiconductor chip located on the substrate, the high-voltage power semiconductor chip having a gate on a side opposite to the substrate; a first packaging frame cover covering the high-voltage power semiconductor chip, the first packaging frame cover having a first top plate, the first top plate having a gate reserved opening; a gate lead-out portion, one end of the gate lead-out portion being located in the gate reserved opening and electrically connected to the gate.

[0007] Optionally, the top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate.

[0008] Optionally, the opening area of ​​the gate reserved opening is smaller than the top surface area of ​​the gate.

[0009] Optionally, the opening area of ​​the gate reserved opening is 0.8 to 0.9 times the top surface area of ​​the gate.

[0010] Optionally, the top surface of the gate lead-out portion includes a test connection region, and the area of ​​the test connection region is 2 to 8 times the area of ​​the top surface of the gate.

[0011] Optionally, the gate reserved opening passes through the first top plate; the first top plate also has an additional groove located in the partial thickness of the first top plate, the opening of the additional groove faces away from the high-voltage power semiconductor chip, the additional groove is located on the side of the gate reserved opening and is connected to the gate reserved opening; the gate lead-out portion is also located in the additional groove.

[0012] Optionally, the gate lead-out portion includes a first lead-out portion and a second lead-out portion, one end of the second lead-out portion is connected to one end of the first lead-out portion, the first lead-out portion and the second lead-out portion form an "L" shape, the first lead-out portion is located in the gate reserved opening and is electrically connected to the gate, and the second lead-out portion is located in the additional groove.

[0013] Optionally, it also includes: a first test electrode assembly, the first test electrode assembly includes a first electrode connector and a first main test electrode connected to the first electrode connector, the first electrode connector is located on the first packaging frame cover and is electrically connected to the gate lead-out parts respectively.

[0014] Optionally, the first electrode connector covers the entire top surface of the gate lead-out portion.

[0015] Optionally, the gate reserved opening is located in the first top plate of partial thickness, and the opening of the gate reserved opening faces the high-voltage power semiconductor chip; the gate lead-out portion includes a spring probe and a conductive sheet connected to the spring probe, the spring probe is located in the gate reserved opening and is electrically connected to the gate, and the conductive sheet is embedded in the first top plate; the first top plate also has a gate connection groove located on a partial area of ​​the conductive sheet.

[0016] Optionally, it also includes: a first test electrode assembly, the first test electrode assembly includes a first electrode connector, a plurality of second electrode connectors, and a first main test electrode, the second electrode connector is located in the gate connection groove and is electrically connected to the conductive sheet, the first electrode connector is located on the first packaging frame cover and is respectively connected to the second electrode connector, and the first main test electrode is connected to the first electrode connector.

[0017] Optionally, the first electrode connector is in a rectangular ring structure, and the first main test electrode is connected to a portion of the inner ring side wall of the first electrode connector.

[0018] Optionally, it also includes: a gate sintering plating layer located between one end of the gate lead-out portion and the gate.

[0019] Optionally, the high-voltage power semiconductor chip also has a first emitter on the side opposite to the substrate; a discrete first coating layer located on the top surface of the first emitter portion; and the first top plate also has a plurality of discrete first electrode grooves passing through the first top plate, the first electrode grooves being located above the first coating layer and separate from the gate reserved opening.

[0020] Optionally, the first coating is in the shape of a long strip.

[0021] Optionally, it also includes: a second test electrode assembly, the second test electrode assembly including: third electrode connectors respectively located in the first electrode grooves; fourth electrode connectors respectively connected to the third electrode connectors and located on the first packaging frame cover; and a second test main electrode, the second test main electrode being connected to the fourth electrode connector.

[0022] Optionally, the material of the first packaging frame cover includes polyimide or ceramic.

[0023] Optionally, the substrate includes a ceramic main substrate and a conductive adhesion layer located on the surface of the ceramic main substrate; the high-voltage power semiconductor chip is electrically connected to the conductive adhesion layer.

[0024] Optionally, the thickness of the ceramic main substrate is 2 mm to 3 mm.

[0025] Optionally, it also includes: a packaging outer frame, which is located on the side of the substrate, as well as the substrate, the high-voltage power semiconductor chip and the first packaging frame cover; a silicone gel layer located between the packaging outer frame and the first packaging frame cover, and between the packaging outer frame and the substrate.

[0026] The present invention also provides a packaging method for preparing a packaging structure of a high-voltage power semiconductor chip as described in any one of the above items, comprising: providing a substrate, a high-voltage power semiconductor chip, a first packaging frame cover and a gate lead-out portion, wherein one side of the high-voltage power semiconductor chip has a gate, and the first packaging frame cover has a first top plate, wherein the first top plate has a gate reserved opening; fixing the high-voltage power semiconductor chip on the substrate, with the gate facing away from the substrate; placing the first packaging frame cover and the gate lead-out portion on the high-voltage power semiconductor chip, with the gate reserved opening facing the gate, and one end of the gate lead-out portion being located in the gate reserved opening; after placing the first packaging frame cover and the gate lead-out portion on the high-voltage power semiconductor chip, sintering one end of the gate lead-out portion and the gate together.

[0027] Optionally, the top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate; the gate reserved opening passes through the first top plate; the first top plate also has an additional groove located in the partial thickness of the first top plate, and the additional groove is located on the side of the gate reserved opening and is connected to the gate reserved opening; placing the first packaging frame cover and the gate lead-out portion on the high-voltage power semiconductor chip, including: placing the first packaging frame cover on the high-voltage power semiconductor chip, with the opening of the additional groove facing away from the high-voltage power semiconductor chip; placing the gate lead-out portion in the gate reserved opening and the additional groove.

[0028] Optionally, it also includes: providing a first test electrode assembly, the first test electrode assembly including a first electrode connector and a first main test electrode connected to the first electrode connector; after sintering one end of the gate lead-out portion with the gate, placing the first electrode connector on the first packaging frame cover and covering the gate lead-out portion; sintering or welding the first electrode connector and the gate lead-out portion together.

[0029] Optionally, the top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate; the gate reserved opening is located in the first top plate of partial thickness, the gate lead-out portion includes a spring probe and a conductive sheet connected to the spring probe, the spring probe is located in the gate reserved opening, the conductive sheet is embedded in the first top plate, and the first top plate also has a gate connection groove located on a partial area of ​​the conductive sheet; placing the first packaging frame cover and the gate lead-out portion on the high-voltage power semiconductor chip, including: placing the first packaging frame cover embedded with the gate lead-out portion on the high-voltage power semiconductor chip, the gate connection groove facing away from the high-voltage power semiconductor chip; sintering one end of the gate lead-out portion to the gate, including: sintering the spring probe and the gate together.

[0030] Optionally, it also includes: providing a first test electrode assembly, the first test electrode assembly including a first electrode connector, a plurality of second electrode connectors, and a first main test electrode, the first electrode connector being connected to the second electrode connectors respectively, and the first main test electrode being connected to the first electrode connector; after sintering one end of the gate lead-out portion with the gate, placing the second electrode connector in the gate connection groove, and the first electrode connector being located on the first packaging frame cover; after placing the second electrode connector in the gate connection groove, sintering or welding the second electrode connector to the conductive sheet at the bottom of the gate connection groove.

[0031] Correspondingly, the present invention also provides a packaging method for preparing the packaging structure of the above-mentioned high-voltage power semiconductor chip, comprising: providing a substrate, a high-voltage power semiconductor chip and a first packaging frame cover, wherein one side of the high-voltage power semiconductor chip has a gate, the first packaging frame cover has a first top plate, the first top plate has a gate reservation opening, the gate reservation opening penetrates the first top plate, the first top plate also has an additional groove located in the thickness of the first top plate portion, the additional groove is located on the side of the gate reservation opening and is connected to the gate reservation opening; the high-voltage power semiconductor chip is fixedly connected to the substrate, and the gate is opposite to the substrate; the first packaging frame cover is placed on the high-voltage power semiconductor chip, the gate reservation opening faces the gate, and the opening of the additional groove faces away from the high-voltage power semiconductor chip; after placing the first packaging frame cover on the high-voltage power semiconductor chip, a deposition process or an electroplating process is used to form a gate lead-out portion in the gate reservation opening and the additional groove, and the gate lead-out portion contacts the gate.

[0032] The technical solution of the present invention has the following advantages:

[0033] 1. In the packaging structure of the high-voltage power semiconductor chip provided by the technical solution of the present invention, by providing a first packaging frame cover and a gate lead-out portion, one end of the gate lead-out portion is electrically connected to the gate, and the first packaging frame cover is used to position the gate lead-out portion, so that the position between one end of the gate lead-out portion and the gate can be better controlled. The present invention uses the gate lead-out portion to lead out from the gate, avoiding the use of bonding wires to lead out from the gate, thereby reducing parasitic inductance.

[0034] 2. In the packaging structure of the high-voltage power semiconductor chip provided by the technical solution of the present invention, the top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate, the extension portion (second lead-out portion) of the gate lead-out portion is isolated from the high-voltage power semiconductor chip by the first packaging frame cover, and the gate lead-out portion is not easily connected to the high-voltage power semiconductor chip outside the gate. Since the top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate, and the gate lead-out portion is used to electrically connect with the first test electrode assembly, it is easier to sinter or weld the first test electrode assembly and the gate lead-out portion together, avoiding the problem of difficulty in sintering when directly sintering the larger first test electrode and the gate.

[0035] 3. The packaging structure of the high-voltage power semiconductor chip provided by the technical solution of the present invention also includes a packaging outer frame. Since the packaging outer frame is combined with the first packaging frame cover and the second packaging frame cover, the insulation strength inside the packaging structure is improved.

[0036] 4. In the packaging structure of the high-voltage power semiconductor chip provided by the technical solution of the present invention, the substrate includes a ceramic main substrate and a conductive adhesion layer located on the surface of the ceramic main substrate, and the conductive adhesion layer is used to be electrically connected to the collector of the high-voltage power semiconductor chip. The substrate adopts a ceramic aluminum-coated plate, which increases the heat dissipation capacity of the packaging structure. In addition, the thickness of the ceramic main substrate is 2mm to 3mm, and the thickness of the ceramic main substrate is relatively thick, which can improve the insulation ability of the ceramic main substrate, improve the voltage resistance, and better meet the packaging requirements of high-voltage power semiconductor chips.

[0037] 5. In the packaging method provided by the technical solution of the present invention, the first packaging frame cover and the gate lead-out portion are placed on the high-voltage power semiconductor chip, the gate reserved opening faces the gate, and one end of the gate lead-out portion is located in the gate reserved opening, and then one end of the gate lead-out portion is sintered together with the gate. By setting the first packaging frame cover and the gate lead-out portion, one end of the gate lead-out portion is electrically connected to the gate, and the first packaging frame cover is used to position the gate lead-out portion, so that the position between one end of the gate lead-out portion and the gate can be better controlled. The present invention uses the gate lead-out portion to lead out from the gate, avoiding the use of bonding wires to lead out from the gate, thereby reducing parasitic inductance.

[0038] 6. In the packaging method provided by the technical solution of the present invention, since the top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate, and the gate lead-out portion is used to be electrically connected to the first test electrode assembly, the first test electrode assembly and the gate lead-out portion are easier to sinter or weld together, avoiding the problem of difficulty in sintering the larger first test electrode and the gate.

[0039] 7. In the packaging method provided by the technical solution of the present invention, after placing the first packaging frame cover on the high-voltage power semiconductor chip, a deposition process or an electroplating process is used to form a gate lead-out portion in the gate reserved opening and the additional groove. The present invention uses a gate lead-out portion to lead out from the gate, avoiding the use of bonding wires to lead out from the gate, thereby reducing parasitic inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 It is a three-dimensional schematic diagram of a packaging structure of a high-voltage power semiconductor chip in one embodiment of the present invention;

[0042] Figure 2 For the corresponding Figure 1 Exploded diagram of

[0043] Figure 3 A schematic diagram of packaging a high-voltage power semiconductor chip, an additional power semiconductor chip, and a substrate together in one embodiment of the present invention;

[0044] Figure 4 is a schematic diagram of a first packaging frame cover in an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of a gate lead-out portion in one embodiment of the present invention;

[0046] Figure 6 A flowchart of a packaging method provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0047] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0048] An embodiment of the present invention provides a packaging structure of a high voltage power semiconductor chip, please refer to Figure 1 ,include:

[0049] substrate 10;

[0050] A high-voltage power semiconductor chip 20 is located on the substrate 10, and a gate 201 is provided on a surface of the high-voltage power semiconductor chip 20 opposite to the substrate 10;

[0051] A first packaging frame cover 30 covering the high-voltage power semiconductor chip 20 , wherein the first packaging frame cover 30 has a first top plate 301 , and the first top plate 301 has a gate reserved opening 302 ;

[0052] The gate lead-out portion 40 has one end located in the gate reserved opening 302 and electrically connected to the gate 201 .

[0053] It should be noted that in order to more clearly describe the internal structure of the package structure, Figure 2 , Figure 2 For the corresponding Figure 1 Exploded diagram. Figure 3 It is a schematic diagram of packaging a high-voltage power semiconductor chip 20 , an additional power semiconductor chip 50 and a substrate 10 together. Figure 4 is a schematic diagram of the first packaging frame cover 30 . Figure 5 is a schematic diagram of the gate lead-out portion 40 .

[0054] In this embodiment, the substrate 10 includes a ceramic main substrate and a conductive adhesion layer located on the surface of the ceramic main substrate, and the conductive adhesion layer is used to be electrically connected to the collector of the high-voltage power semiconductor chip. The material of the ceramic main substrate can be AlN, Si3N4 or AlSiC. The material of the conductive adhesion layer can be aluminum. In this embodiment, the substrate adopts a ceramic aluminum-coated plate, which increases the heat dissipation capacity of the packaging structure. The thickness of the ceramic main substrate is 2mm to 3mm, and the thickness of the ceramic main substrate is more than twice the thickness of the usual substrate. The advantage is that the thickness of the ceramic main substrate is relatively thick, which can improve the insulation ability of the ceramic main substrate, improve the voltage resistance, and better meet the packaging requirements of high-voltage power semiconductor chips.

[0055] The high-voltage power semiconductor chip 20 includes a SiC-based semiconductor chip. The high-voltage power semiconductor chip 20 is a triode power semiconductor chip. One side of the high-voltage power semiconductor chip 20 has a gate 201 and a first emitter, and the first emitter is separate from the gate 201. The other side of the high-voltage power semiconductor chip 20 has a first collector. Specifically, the high-voltage power semiconductor chip 20 can be a SiC-based IGBT chip or a MOSFET-based IGBT chip.

[0056] In the packaging structure, the first collector faces the substrate 10 , and the first collector and the conductive adhesive layer are welded or sintered together.

[0057] The packaging structure further includes: a separate first plating layer 203 located on the top surface of the first emitter portion. The first plating layer 203 is used to: during the process of sintering or welding the second test electrode assembly and the first emitter together, it is beneficial to release stress during the compression process and to ensure uniform compression, thereby avoiding damage to the high-voltage power semiconductor chip caused by the compression.

[0058] The first plating layer 203 is in the shape of a long strip.

[0059] Specifically, for any high-voltage power semiconductor chip 20, the spacing between each first plating layer 203 is equal. In the process of sintering or welding the second test electrode assembly and the first emitter together, the first emitter is pressed uniformly.

[0060] In this embodiment, the material of the first plating layer 203 is a conductive material, such as Ag.

[0061] The total top surface area of ​​the first coating layer 203 on the first emitter occupies 40% to 60% of the top surface area of ​​the first emitter; the thickness of the first coating layer 203 is 10 micrometers to 12 micrometers.

[0062] The SiC-based high-voltage power semiconductor chip 20 has the advantages of high voltage resistance, low power consumption, large current capacity, fast heat dissipation, and high temperature resistance. It can be widely used in new power electronic equipment such as solid-state transformers and solid-state circuit breakers, as well as traditional flexible AC transmission systems (FACTS) and DC transmission equipment. It will have an important impact on the economic and safe operation of the power system and realize the innovation of power grid technology.

[0063] The SiC-based high-voltage power semiconductor chip 20 has the advantage of a high junction temperature.

[0064] In the high-voltage power semiconductor chip 20, the top surface area of ​​the gate 201 is relatively small, and the top surface area of ​​the gate 201 is generally designed to be 0.4 mm*0.6 mm, so that the gate 201 occupies a relatively small area on the surface of the high-voltage power semiconductor chip 20, thereby improving the integration of the high-voltage power semiconductor chip 20. In the high-voltage power semiconductor chip 20, the top surface area of ​​the gate 201 is smaller than the top surface area of ​​the first emitter and smaller than the top surface area of ​​the first collector.

[0065] In this embodiment, the packaging structure further includes: an additional power semiconductor chip 50, which is a diode power semiconductor chip, such as a SiC-based FRD chip. The additional power semiconductor chip 50 is separate from the high-voltage power semiconductor chip 20.

[0066] One side of the additional power semiconductor chip 50 has a second emitter, and the other side of the additional power semiconductor chip has a second collector.

[0067] In the packaging structure, the second collector faces the substrate 10 , and the second collector and the conductive adhesive layer are welded or sintered together.

[0068] The number of the high-voltage power semiconductor chips 20 is one or more. In this embodiment, the number of the high-voltage power semiconductor chips 20 is multiple, and the multiple high-voltage power semiconductor chips 20 are separate from each other. The number of the additional power semiconductor chips 50 is one or more. In this embodiment, the number of the additional power semiconductor chips 50 is multiple.

[0069] In this embodiment, the packaging structure further includes: a separate second plating layer 502 located on the top surface of the second emitter portion. The second plating layer 502 is used to facilitate pressure diffusion during sintering or welding the second test electrode assembly and the second emitter to avoid damage to the additional power semiconductor chip caused by pressure.

[0070] The second plating layer 502 is in the shape of a long strip. In this embodiment, the material of the second plating layer 502 is a conductive material, such as Ag.

[0071] The total top surface area of ​​the second coating layer 502 on the second emitter occupies 40% to 60% of the top surface area of ​​the second emitter; the thickness of the second coating layer 502 is 10 micrometers to 12 micrometers.

[0072] For any additional power semiconductor chip 50, the spacing between each second plating layer 502 is equal. In the process of sintering or welding the second test electrode assembly and the second emitter together, the second emitter is pressed uniformly.

[0073] The material of the first packaging frame cover 30 includes polyimide or ceramic, so that the first packaging frame 30 cover has a high insulation performance. The first packaging frame cover 30 has a first top plate 301 and a first side plate 303, and the first side plate 303 is connected to the edge area of ​​the first top plate 301. In the packaging structure, the first side plate 303 surrounds the side wall of the high-voltage power semiconductor chip 20, and the first top plate 301 is located on the top of the high-voltage power semiconductor chip 20. One high-voltage power semiconductor chip 20 is covered by one first packaging frame cover 30.

[0074] In this embodiment, the opening area of ​​the gate reserved opening 302 is smaller than the top surface area of ​​the gate 201. This has the advantage that in the process of sintering one end of the gate lead-out portion 40 and the gate 201 together, even if there is a certain deviation in the alignment of the gate reserved opening 302 and the gate 201, the gate lead-out portion 40 will not be sintered on the electrical terminals around the gate 201 that are closer to the gate 201, thereby avoiding a short circuit between the gate lead-out portion 40 and the electrical terminals that are closer to the gate 201, and reducing the alignment accuracy requirements of the gate reserved opening 302 and the gate 201.

[0075] If the opening area of ​​the gate reserved opening 302 is less than 0.8 times the top surface area of ​​the gate 201, the area of ​​the gate 201 exposed by the gate reserved opening 302 will be too small, increasing the difficulty of sintering one end of the gate lead-out portion 40 and the gate 201; if the opening area of ​​the gate reserved opening 302 is greater than 0.9 times the top surface area of ​​the gate 201, then it is not very obvious to avoid short circuits between the gate lead-out portion 40 and the electrical terminals near the gate 201 and reduce the alignment accuracy requirements of the gate reserved opening 302 and the gate 201. Therefore, in a specific embodiment, the opening area of ​​the gate reserved opening 302 is 0.8 to 0.9 times the top surface area of ​​the gate 201.

[0076] In this embodiment, the gate reserved opening 302 passes through the first top plate 301; the first top plate 301 also has an additional groove 304 located in a partial thickness of the first top plate 301, the opening of the additional groove 304 faces away from the high-voltage power semiconductor chip 20, and the additional groove 304 is located on the side of the gate reserved opening 302 and is connected to the gate reserved opening 302; the gate lead-out portion 40 is also located in the additional groove 304.

[0077] In this embodiment, the first top plate 301 further has a plurality of separate first electrode grooves 305 penetrating the first top plate, the first electrode grooves 305 are located above the first plating layer 203 and separate from the grid reserved opening 302. The first electrode grooves 305 are also separate from the additional grooves 304.

[0078] In this embodiment, the top surface area of ​​the gate lead-out portion 40 is larger than the top surface area of ​​the gate 201 .

[0079] In this embodiment, the gate lead-out portion 40 includes a first lead-out portion 401 and a second lead-out portion 402, one end of the second lead-out portion 402 is connected to one end of the first lead-out portion 401, the first lead-out portion 401 and the second lead-out portion 402 form an "L" shape, the first lead-out portion 401 is located in the gate reserved opening 302 and is electrically connected to the gate 201, and the second lead-out portion 402 is located in the additional groove 304.

[0080] In this embodiment, the material of the first lead-out portion 401 and the second lead-out portion 402 is a conductive material, such as metal, specifically copper, aluminum or silver.

[0081] In this embodiment, one end of the gate lead-out portion 40 is located in the gate reserved opening 302 and is electrically connected to the gate 201, and the top surface area of ​​the gate lead-out portion 40 is larger than the top surface area of ​​the gate 201. In this embodiment, the top surface area of ​​the second lead-out portion 402 is larger than the top surface area of ​​the gate 201.

[0082] The top surface of the gate lead-out portion 40 includes a test connection region, and the test connection region is used to be electrically connected to the first test electrode assembly.

[0083] In this embodiment, the entire top surface of the gate lead-out portion 40 is used as the test connection area. In this embodiment, the area of ​​the test connection area is 2 to 8 times the area of ​​the top surface of the gate. In this way, the area of ​​the test connection area is larger, the contact area between the first test electrode assembly and the test connection area is larger, and the first test electrode assembly is easy to sinter or weld with the gate lead-out portion 40.

[0084] In this embodiment, the packaging structure further includes: a first test electrode assembly 60, the first test electrode assembly 60 includes a first electrode connector 601 and a first main test electrode 602 connected to the first electrode connector 601, the first electrode connector 601 is located on the first packaging frame cover 30 and is respectively electrically connected to the gate lead-out portion 40. When there are multiple high-voltage power semiconductor chips 20, the first electrode connector 601 is electrically connected to the gate lead-out portions 40 of the multiple high-voltage power semiconductor chips 20.

[0085] In this embodiment, the first electrode connector 601 is in a rectangular ring structure, and the first main test electrode 602 is connected to a portion of the inner ring side wall of the first electrode connector 601 .

[0086] In this embodiment, the first electrode connector 601 covers the entire top surface of the gate lead-out portion 40 .

[0087] In this embodiment, the first electrode connector 601 and the gate lead-out portion 40 are sintered or welded together.

[0088] In this embodiment, the packaging structure further includes: a gate sintered plating layer 204 located between one end of the gate lead-out portion 40 and the gate 201. Specifically, the gate sintered plating layer 204 is located between the first lead-out portion 401 and the gate 201.

[0089] The gate sintering layer 204 is made of Ag.

[0090] In this embodiment, the packaging structure further includes: a second packaging frame cover 70 covering the additional power semiconductor chip 50, the second packaging frame cover 70 having a second top plate 701 and a second side plate 702, the second side plate 702 being connected to the edge area of ​​the second top plate 701. In the packaging structure, the second side plate 702 surrounds the side wall of the additional power semiconductor chip 50, and the second top plate 701 is located on the top of the additional power semiconductor chip 50. One additional power semiconductor chip 50 is covered by one second packaging frame cover 70.

[0091] The material of the second packaging frame cover 70 includes polyimide or ceramic, so that the second packaging frame cover 70 has a high insulation performance.

[0092] The second top plate 701 has a plurality of separate second electrode grooves 703 penetrating the second top plate 701 , and the second electrode grooves 703 are located above the second plating layer.

[0093] In this embodiment, the packaging structure also includes: a second test electrode assembly 80, the second test electrode assembly 80 includes: third electrode connectors 801 respectively located in the first electrode grooves 305; fourth electrode connectors 802 respectively connected to the third electrode connectors 801 and located on the first packaging frame cover 30; a second test main electrode 803, the second test main electrode 803 is connected to the fourth electrode connector 802.

[0094] When there are multiple high-voltage power semiconductor chips 20 , the fourth electrode connector 802 is connected to the third electrode connector 801 on each high-voltage power semiconductor chip 20 .

[0095] In this embodiment, when there is an additional power semiconductor chip 50, the second test electrode assembly 80 is also electrically connected to the second emitter. Specifically, the second test electrode assembly 50 also includes: a third additional electrode connector 804, which is located in the second electrode groove 703; the fourth electrode connector 802 is also connected to the third additional electrode connector 804 respectively.

[0096] In this embodiment, the packaging structure further includes: a packaging outer frame (not shown), the packaging outer frame is located on the side of the substrate 10, the substrate 10, the high-voltage power semiconductor chip 20 and the first packaging frame cover 30, and the packaging outer frame is also located on the additional power semiconductor chip 50 and the second packaging frame cover 70; a silicone gel layer is located between the packaging outer frame and the first packaging frame cover 30, between the packaging outer frame and the second packaging frame cover 70, and between the packaging outer frame and the substrate 10. The packaging outer frame also covers the first electrode connector 601 and exposes the first main test electrode 602; the packaging outer frame also covers the third electrode connector 801, the fourth electrode connector 802 and the third additional electrode connector 804, and exposes the second test main electrode 803. In this embodiment, in the packaging structure, the packaging outer frame is combined with the first packaging frame cover 30 and the second packaging frame cover 70 to improve the insulation strength inside the packaging structure.

[0097] In this embodiment, a gate lead-out portion 40 is provided, and one end of the gate lead-out portion 40 is sintered together with the gate 201, so that the contact resistance between the one end of the gate lead-out portion 40 and the gate 201 is reduced; secondly, the area of ​​the test connection region for electrical connection with the first test electrode assembly is larger than the top surface area of ​​the gate 201, so that the first test electrode assembly and the gate lead-out portion 40 are easier to sinter or weld together, avoiding the problem of difficulty in sintering the larger first test electrode directly with the gate 201; and avoiding the use of bonding wires on the gate 201, thereby reducing parasitic inductance.

[0098] In this embodiment, the first packaging frame cover 30 is used to position the gate lead-out portion 40, so that the position between one end of the gate lead-out portion 40 and the gate 201 can be better controlled. During the sintering process of the gate lead-out portion 40 and the gate 201, the extended portion (the second lead-out portion) of the gate lead-out portion 40 is isolated from the high-voltage power semiconductor chip 20 by the first packaging frame cover 30, and the gate lead-out portion 40 is not easily connected to the high-voltage power semiconductor chip 20 outside the gate 201.

[0099] Correspondingly, this embodiment also provides a packaging method for preparing the packaging structure of the above-mentioned high-voltage power semiconductor chip, please refer to Figure 6 , including the following steps:

[0100] S1: providing a substrate 10, a high-voltage power semiconductor chip 20, a first packaging frame cover 30 and a gate lead-out portion 40, wherein one side of the high-voltage power semiconductor chip 20 has a gate 201, the first packaging frame cover 30 has a first top plate 301, the first top plate 301 has a gate reserved opening 302, and the top surface area of ​​the gate lead-out portion 40 is larger than the top surface area of ​​the gate 201;

[0101] S2: The high-voltage power semiconductor chip 20 is fixedly connected to the substrate 10, with the gate 201 facing away from the substrate 10;

[0102] S3: placing the first packaging frame cover 30 and the gate lead-out portion 40 on the high-voltage power semiconductor chip 20, with the gate reserved opening 302 facing the gate 201, and one end of the gate lead-out portion 40 located in the gate reserved opening 302;

[0103] S4: After placing the first packaging frame cover 30 and the gate lead-out portion 40 on the high-voltage power semiconductor chip 20 , one end of the gate lead-out portion 40 is sintered together with the gate 201 .

[0104] In this embodiment, specifically, a vacuum ion sputtering process is used to form an Ag coating on the surface of the conductive adhesion layer of the substrate 10, and then the high-voltage power semiconductor chip 20 is welded or sintered on the substrate 10 through the Ag coating, and the additional power semiconductor chip 50 is welded or sintered on the substrate 10 through the Ag coating. Specifically, the first collector of the high-voltage power semiconductor chip 20 and the second collector of the additional power semiconductor chip 50 are electrically connected to the conductive adhesion layer.

[0105] In this embodiment, placing the first packaging frame cover 30 and the gate lead-out portion 40 on the high-voltage power semiconductor chip 20 includes: placing the first packaging frame cover 30 on the high-voltage power semiconductor chip 20, with the gate reserved opening 302 facing the gate 201, and the opening of the additional groove 304 facing away from the high-voltage power semiconductor chip 20; placing the gate lead-out portion 40 in the gate reserved opening 302 and the additional groove 304. In this embodiment, the first lead-out portion 401 is located in the gate reserved opening 302 and is electrically connected to the gate 201, and the second lead-out portion 402 is located in the additional groove 304.

[0106] In this embodiment, the method further includes: providing a second packaging frame cover, and placing the second packaging frame cover on the additional power semiconductor chip.

[0107] In this embodiment, one end of the gate lead-out portion 40 is sintered with the gate 201, specifically, the first lead-out portion 401 is sintered with the gate 201. Specifically, before the first packaging frame cover 30 is placed on the high-voltage power semiconductor chip 20, a gate sintering coating 204 is formed on the surface of the gate 201, and the process of forming the gate sintering coating 204 can be a vacuum ion sputtering process; the first lead-out portion 401 is sintered with the gate 201 through the gate sintering coating 204.

[0108] In this embodiment, it also includes: providing a first test electrode assembly 60; after sintering one end of the gate lead-out portion 40 and the gate 201 together, placing a first electrode connector 601 on the first packaging frame cover 30 and covering the gate lead-out portion 40; sintering or welding the first electrode connector 601 and the gate lead-out portion 40 together.

[0109] In this embodiment, it also includes: providing a second test electrode assembly 80; after sintering one end of the gate lead-out portion 40 with the gate 201, placing the third electrode connector 801 in the first electrode groove 305, and placing the third additional electrode connector 804 in the second electrode groove 703; sintering or welding the third electrode connector 801 and the first emitter together through the first coating 203, and sintering or welding the third additional electrode connector 804 and the second emitter together through the second coating.

[0110] In this embodiment, it also includes: providing an outer packaging frame; placing the outer packaging frame on the side of the substrate 10, as well as the substrate 10, the high-voltage power semiconductor chip 20 and the first packaging frame cover 30, and the outer packaging frame is also located on the additional power semiconductor chip 50 and the second packaging frame cover 70; injecting a silicone gel layer between the outer packaging frame and the first packaging frame cover 30, between the outer packaging frame and the second packaging frame cover 70, and between the outer packaging frame and the substrate 10; and then vacuum-curing the silicone gel layer at high temperature.

[0111] The package outer frame also covers the first electrode connector 601 and exposes the first main test electrode 602; the package outer frame also covers the third electrode connector 801, the fourth electrode connector 802 and the third additional electrode connector 804, and exposes the second test main electrode 803. In this embodiment, in the package structure, the package outer frame is combined with the first package frame cover 30 and the second package frame cover 70 to improve the insulation strength inside the package structure.

[0112] Another embodiment of the present invention further provides a packaging structure, and the difference between this embodiment and the packaging structure in the previous embodiment is that the structure of the first packaging frame cover in this embodiment is different from the structure of the first packaging frame cover in the previous embodiment, the gate lead-out portion in this embodiment is different from the gate lead-out portion in the previous embodiment, and the first test electrode assembly in this embodiment is different from the first test electrode assembly in the previous embodiment. The same contents between this embodiment and the previous embodiment are not described in detail.

[0113] In this embodiment, the first packaging frame cover includes a first top plate, wherein the first top plate has a gate reserved opening, wherein the gate reserved opening is located in a portion of the thickness of the first top plate, and the opening of the gate reserved opening faces the high-voltage power semiconductor chip.

[0114] In this embodiment, the gate lead-out portion includes a spring probe and a conductive sheet connected to the spring probe, the spring probe is located in the gate reserved opening and is electrically connected to the gate, and the conductive sheet is embedded in the first top plate.

[0115] The first top plate also has a gate connection groove located on a partial area of ​​the conductive sheet. The conductive sheet exposed by the gate connection groove is used to form a test connection area.

[0116] In this embodiment, the gate sintering coating is located between the spring probe and the gate.

[0117] The first test electrode assembly includes a first electrode connector, a plurality of second electrode connectors, and a first main test electrode, wherein the second electrode connector is located in the gate connection groove and is electrically connected to the conductive sheet, the first electrode connector is located on the first packaging frame cover and is respectively connected to the second electrode connectors, and the first main test electrode is connected to the first electrode connector.

[0118] The first electrode connector is in a rectangular ring structure, and the first main test electrode is connected to a portion of the inner ring side wall of the first electrode connector.

[0119] Correspondingly, another embodiment of the present invention further provides a packaging method. Placing the first packaging frame cover and the gate lead portion on the high-voltage power semiconductor chip includes: placing the first packaging frame cover embedded with the gate lead portion on the high-voltage power semiconductor chip, with the gate connection groove facing away from the high-voltage power semiconductor chip.

[0120] Sintering one end of the gate lead-out portion with the gate includes: sintering the spring probe with the gate. Specifically, sintering the spring probe with the gate through a gate sintering coating.

[0121] After sintering one end of the gate lead-out portion and the gate together, the second electrode connector is placed in the gate connection groove, and the first electrode connector is located on the first packaging frame cover; after placing the second electrode connector in the gate connection groove, the second electrode connector and the conductive sheet at the bottom of the gate connection groove are sintered or welded together.

[0122] The parts of the packaging method of this embodiment that are the same as those in the previous embodiment will not be described in detail.

[0123] Correspondingly, the present invention also provides a packaging method, including: providing a substrate, a high-voltage power semiconductor chip and a first packaging frame cover, wherein one side of the high-voltage power semiconductor chip has a gate, the first packaging frame cover has a first top plate, the first top plate has a gate reservation opening, the gate reservation opening penetrates the first top plate, the first top plate also has an additional groove located in the thickness of the first top plate portion, the additional groove is located on the side of the gate reservation opening and is connected to the gate reservation opening; the high-voltage power semiconductor chip is fixedly connected to the substrate, and the gate is opposite to the substrate; the first packaging frame cover is placed on the high-voltage power semiconductor chip, the gate reservation opening faces the gate, and the opening of the additional groove faces away from the high-voltage power semiconductor chip; after placing the first packaging frame cover on the high-voltage power semiconductor chip, a deposition process or an electroplating process is used to form a gate lead-out portion in the gate reservation opening and the additional groove, and the gate lead-out portion contacts the gate.

[0124] The parts of the present packaging method that are the same as the above packaging method will not be described in detail. It should be noted that the present packaging method is not suitable for the case where the gate lead-out portion includes a spring probe and a conductive sheet connected to the spring probe.

[0125] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A packaging structure of a high-voltage power semiconductor chip, characterized in that: include: substrate; A high-voltage power semiconductor chip is located on the substrate, wherein the high-voltage power semiconductor chip has a gate on a side opposite to the substrate; A first packaging frame cover covering the high-voltage power semiconductor chip, wherein the first packaging frame cover has a first top plate, wherein the first top plate has a gate reserved opening; wherein the gate reserved opening penetrates the first top plate; wherein the first top plate also has an additional groove located in a thickness of the first top plate, wherein the opening of the additional groove faces away from the high-voltage power semiconductor chip, wherein the additional groove is located at a side of the gate reserved opening and is in communication with the gate reserved opening; wherein the gate lead-out portion is also located in the additional groove; A gate lead-out portion, one end of which is located in the gate reserved opening and electrically connected to the gate; the gate lead-out portion includes a first lead-out portion and a second lead-out portion, one end of the second lead-out portion is connected to one end of the first lead-out portion, the first lead-out portion and the second lead-out portion form an "L" shape, the first lead-out portion is located in the gate reserved opening and electrically connected to the gate, and the second lead-out portion is located in the additional groove; The top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate; The packaging structure of the high-voltage power semiconductor chip further includes: a first test electrode assembly, the first test electrode assembly including a first electrode connector and a first main test electrode connected to the first electrode connector, the first electrode connector being located on the first packaging frame cover and electrically connected to the gate lead-out portions respectively; The top surface of the gate lead-out portion includes a test connection area, and the test connection area is used to be electrically connected to the first test electrode assembly; the area of ​​the test connection area is 2 to 8 times the area of ​​the top surface of the gate.

2. The packaging structure of the high-voltage power semiconductor chip according to claim 1, characterized in that: The opening area of ​​the gate reserved opening is smaller than the top surface area of ​​the gate.

3. The packaging structure of the high-voltage power semiconductor chip according to claim 2, characterized in that: The opening area of ​​the gate reserved opening is 0.8 to 0.9 times the top surface area of ​​the gate.

4. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: The first electrode connector covers the entire top surface of the gate lead-out portion.

5. The packaging structure of the high-voltage power semiconductor chip according to claim 1, characterized in that: The gate reserved opening is located in the first top plate of a partial thickness, and the opening of the gate reserved opening faces the high-voltage power semiconductor chip; The gate lead-out portion includes a spring probe and a conductive sheet connected to the spring probe, the spring probe is located in the gate reserved opening and is electrically connected to the gate, and the conductive sheet is embedded in the first top plate; The first top plate also has a gate connection groove located on a partial area of ​​the conductive sheet.

6. The packaging structure of the high-voltage power semiconductor chip according to claim 5, characterized in that: Also includes: A first test electrode assembly, the first test electrode assembly includes a first electrode connector, a plurality of second electrode connectors, and a first main test electrode, the second electrode connector is located in the gate connection groove and is electrically connected to the conductive sheet, the first electrode connector is located on the first packaging frame cover and is respectively connected to the second electrode connector, and the first main test electrode is connected to the first electrode connector.

7. The packaging structure of a high-voltage power semiconductor chip according to claim 1 or 6, characterized in that: The first electrode connector is in a rectangular ring structure, and the first main test electrode is connected to a portion of the inner ring side wall of the first electrode connector.

8. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: Also includes: A gate sintering plating layer is located between one end of the gate lead-out portion and the gate.

9. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: The high-voltage power semiconductor chip further has a first emitter on a side opposite to the substrate; a separate first plating layer located on a top surface of the first emitter portion; The first top plate also has a plurality of separate first electrode grooves penetrating the first top plate, wherein the first electrode grooves are located above the first plating layer and separate from the grid reserved opening.

10. The packaging structure of a high-voltage power semiconductor chip according to claim 9, characterized in that: The first plating layer is in the shape of a long strip.

11. The packaging structure of a high-voltage power semiconductor chip according to claim 9, characterized in that: Also includes: A second test electrode assembly, the second test electrode assembly includes: third electrode connectors respectively located in the first electrode grooves; fourth electrode connectors respectively connected to the third electrode connectors and located on the first packaging frame cover; a second test main electrode, the second test main electrode is connected to the fourth electrode connector.

12. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: The material of the first packaging frame cover includes polyimide or ceramic.

13. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: The substrate comprises a ceramic main substrate and a conductive adhesion layer located on the surface of the ceramic main substrate; the high-voltage power semiconductor chip is electrically connected to the conductive adhesion layer.

14. The packaging structure of a high-voltage power semiconductor chip according to claim 13, characterized in that: The thickness of the ceramic main substrate is 2 mm to 3 mm.

15. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: Also includes: A package outer frame, the package outer frame is located on the side of the substrate, the substrate, the high-voltage power semiconductor chip and the first package frame cover; A silicone gel layer is located between the packaging outer frame and the first packaging frame cover, and between the packaging outer frame and the substrate.

16. A packaging method for preparing a packaging structure of a high-voltage power semiconductor chip according to any one of claims 1 to 15, characterized in that: include: Providing a substrate, a high-voltage power semiconductor chip, a first packaging frame cover and a gate lead-out portion, wherein one side of the high-voltage power semiconductor chip has a gate, the first packaging frame cover has a first top plate, and the first top plate has a gate reserved opening; The high-voltage power semiconductor chip is fixedly connected to the substrate, with the gate facing away from the substrate; The first packaging frame cover and the gate lead-out portion are placed on the high-voltage power semiconductor chip, the gate reserved opening faces the gate, and one end of the gate lead-out portion is located in the gate reserved opening; the top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate; the gate reserved opening passes through the first top plate; the first top plate also has an additional groove located in the thickness of the first top plate, the additional groove is located at the side of the gate reserved opening and is connected to the gate reserved opening; Placing the first packaging frame cover and the gate lead-out portion on the high-voltage power semiconductor chip, including: placing the first packaging frame cover on the high-voltage power semiconductor chip, with the opening of the additional groove facing away from the high-voltage power semiconductor chip; placing the gate lead-out portion in the gate reserved opening and the additional groove; After placing the first packaging frame cover and the gate lead-out portion on the high-voltage power semiconductor chip, sintering one end of the gate lead-out portion and the gate together; A first test electrode assembly is provided, the first test electrode assembly comprising a first electrode connector and a first main test electrode connected to the first electrode connector; after sintering one end of the gate lead-out portion with the gate, the first electrode connector is placed on the first packaging frame cover and covers the gate lead-out portion; the first electrode connector and the gate lead-out portion are sintered or welded together.

17. The packaging method according to claim 16, characterized in that: The top surface area of ​​the gate lead-out portion is larger than the top surface area of ​​the gate; the gate reserved opening is located in the first top plate of a partial thickness, the gate lead-out portion comprises a spring probe and a conductive sheet connected to the spring probe, the spring probe is located in the gate reserved opening, the conductive sheet is embedded in the first top plate, and the first top plate also has a gate connection groove located on a partial area of ​​the conductive sheet; Placing the first packaging frame cover and the gate lead-out portion on the high-voltage power semiconductor chip, including: placing the first packaging frame cover embedded with the gate lead-out portion on the high-voltage power semiconductor chip, with the gate connection groove facing away from the high-voltage power semiconductor chip; Sintering one end of the gate lead-out portion with the gate includes: sintering the spring probe with the gate.

18. The packaging method according to claim 17, characterized in that: The method further includes: providing a first test electrode assembly, the first test electrode assembly including a first electrode connector, a plurality of second electrode connectors, and a first main test electrode, the first electrode connector being connected to the second electrode connectors respectively, and the first main test electrode being connected to the first electrode connector; after sintering one end of the gate lead-out portion and the gate together, placing the second electrode connector in the gate connection groove, and the first electrode connector being located on the first packaging frame cover; After the second electrode connector is placed in the gate connection groove, the second electrode connector and the conductive sheet at the bottom of the gate connection groove are sintered or welded together.

19. A packaging method for preparing a packaging structure of a high-voltage power semiconductor chip according to any one of claims 1 to 4 and 9 to 15, characterized in that: include: A substrate, a high-voltage power semiconductor chip and a first packaging frame cover are provided, wherein one side of the high-voltage power semiconductor chip has a gate, the first packaging frame cover has a first top plate, the first top plate has a gate reserved opening, the gate reserved opening penetrates the first top plate, the first top plate also has an additional groove located in a thickness of the first top plate, the additional groove is located at a side of the gate reserved opening and is connected to the gate reserved opening; The high-voltage power semiconductor chip is fixedly connected to the substrate, with the gate facing away from the substrate; Placing the first packaging frame cover on the high-voltage power semiconductor chip, with the gate reserved opening facing the gate and the opening of the additional groove facing away from the high-voltage power semiconductor chip; After placing the first packaging frame cover on the high-voltage power semiconductor chip, a gate lead-out portion is formed in the gate reserved opening and the additional groove by using a deposition process or an electroplating process, and the gate lead-out portion contacts the gate.

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