Semiconductor devices

Abstract

The semiconductor device includes: a plurality of first signal output circuits, which have a first transistor (MN101, MN105) and a second transistor (MN102, MN106), which output the voltage of the connection point of the two transistors, the first transistor and the second transistor are connected in series between a signal line providing a power supply voltage and a signal line providing a reference voltage, and a predetermined voltage is provided to each gate; and a plurality of second signal output circuits, which have a third transistor (MN103, MN107) and a fourth transistor (MN104, MN108), which output the voltage of the connection point of the two transistors, the third transistor and the fourth transistor are connected in series between a signal line providing a power supply voltage and a signal line providing a reference voltage, and a predetermined voltage is provided to each gate, the third transistor has the same layout as the first transistor but has different characteristics, and the fourth transistor has the same layout as the second transistor but has different characteristics.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a technology for protecting a semiconductor device from reverse engineering. Background Art

[0002] In recent years, improper reverse engineering of semiconductor devices has increased. As a reverse engineering method, not only optical analysis is performed on the surface of the chip on which the semiconductor device is mounted, but also the following technology is used: the wiring layers are peeled off layer by layer and photographed, the obtained images are superimposed, and the wiring information is extracted using software tools to reproduce the circuit diagram.

[0003] Various methods for preventing reverse engineering have been proposed (for example, see Patent Documents 1 to 9). In order to prevent reverse engineering, the following methods have been proposed: for example, by working on the wiring layer, or using a diffusion layer or bulk below the wiring layer to change the characteristics or connection information of the transistor, so that the function cannot be reproduced by reading the wiring layer alone. In addition, for example, Patent Document 1 proposes the following technology: using a transistor with the gate set to a floating state, and generating a signal using the difference in output voltage caused by the characteristic deviation of the transistor, thereby making it difficult to reproduce the semiconductor device through reverse engineering.

[0004] However, the technology described in the above-mentioned patent document 1 has the following problems. Since the gate is in a floating state, useless consumption current will flow from the power supply voltage to the ground terminal, and if noise enters due to crosstalk, etc., it will cause voltage fluctuations, resulting in unstable operation or consumption current. In addition, the output voltage generated by multiple transistors is not a binary voltage, but a continuous analog quantity, so the comparator that receives the output voltage is required to have high-precision analog characteristics, and the consumption current and size become larger. Due to such constraints on consumption current and size, there are restrictions on the number that can be mounted on a chip. In addition, in other methods of preventing reverse engineering, there are the following problems: special processes are required, and the process development period and cost increase.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: U.S. Patent No. 9437555

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 6-163539

[0009] Patent Document 3: Japanese Patent Application Laid-Open No. 9-92727

[0010] Patent Document 4: U.S. Patent No. 6117762

[0011] Patent Document 5: U.S. Patent No. 6979606

[0012] Patent Document 6: U.S. Patent No. 7128271

[0013] Patent Document 7: U.S. Patent No. 9337156

[0014] Patent Document 8: Japanese Patent Application No. 2004-518273

[0015] Patent Document 9: Japanese Patent Application Publication No. 2014-135386 Summary of the invention

[0016] Problems to be solved by the invention

[0017] An object of the present invention is to provide a semiconductor device that is difficult to reproduce by reverse engineering.

[0018] Means for solving problems

[0019] The semiconductor device of the present invention is characterized in that the semiconductor device includes: a plurality of first signal output circuits, which have a first transistor and a second transistor, which output a voltage at a connection point between the first transistor and the second transistor, the first transistor and the second transistor are connected in series between a signal line providing a first voltage and a signal line providing a second voltage lower than the first voltage, and a prescribed voltage is provided to each gate; and a plurality of second signal output circuits, which have a third transistor and a fourth transistor, which output a voltage at a connection point between the third transistor and the fourth transistor, the third transistor and the fourth transistor are connected in series between a signal line providing the first voltage and a signal line providing the second voltage, and a prescribed voltage is provided to each gate, the third transistor has the same layout as the first transistor but has different characteristics, and the fourth transistor has the same layout as the second transistor but has different characteristics.

[0020] Effects of the Invention

[0021] According to the present invention, it is possible to provide a semiconductor device that is difficult to reproduce by reverse engineering. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A It is a diagram showing an example of the semiconductor device according to the first embodiment.

[0023] Figure 1B It is a diagram showing an example of the semiconductor device according to the first embodiment.

[0024] Figure 2AIt is a diagram showing an example of a semiconductor device according to the second embodiment.

[0025] Figure 2B It is a diagram showing an example of a semiconductor device according to the second embodiment.

[0026] Figure 3A It is a diagram showing an example of a semiconductor device according to a third embodiment.

[0027] Figure 3B It is a diagram showing an example of a semiconductor device according to a third embodiment.

[0028] Figure 4A It is a diagram showing an example of a semiconductor device according to a fourth embodiment.

[0029] Figure 4B It is a diagram showing an example of a semiconductor device according to a fourth embodiment.

[0030] Figure 5A It is a diagram showing an example of a semiconductor device according to a fifth embodiment.

[0031] Figure 5B It is a diagram showing an example of a semiconductor device according to a fifth embodiment.

[0032] Fig. 6A It is a diagram showing an example of a semiconductor device according to a sixth embodiment.

[0033] Figure 6B It is a diagram showing an example of a semiconductor device according to a sixth embodiment.

[0034] Fig. 7A This is a diagram showing an example of a semiconductor device according to a seventh embodiment.

[0035] Figure 7B This is a diagram showing an example of a semiconductor device according to a seventh embodiment.

[0036] Figure 8 A diagram showing an application example of the semiconductor device according to the present embodiment. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0038] (First embodiment)

[0039] A first embodiment of the present invention will be described. A semiconductor device according to the first embodiment includes a plurality of Figure 1A and Figure 1B The signal output circuit shown. Figure 1A and 1B This is a diagram showing an example of a signal output circuit included in the semiconductor device according to the first embodiment. Figure 1A The first signal output circuit shown includes N-type MOS transistors MN101 , MN102 , MN103 , and MN104 and an amplifier 11 .

[0040] Between the signal line providing the power supply voltage VDD and the signal line providing the reference voltage GND, two N-type MOS transistors MN101 and MN102 are connected in series in order from the signal line providing the power supply voltage VDD, and the voltage at the connection point of the two N-type MOS transistors MN101 and MN102 is output as a signal SINA. In the N-type MOS transistors MN101 and MN102, the gate is connected to the signal line providing the power supply voltage VDD, and the back gate is connected to the signal line providing the reference voltage GND.

[0041] In addition, between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage GND, two N-type MOS transistors MN103 and MN104 are connected in series in order from the signal line for supplying the power supply voltage VDD, and the voltage at the connection point of the two N-type MOS transistors MN103 and MN104 is output as the signal SINB. In the N-type MOS transistors MN103 and MN104, the gate is connected to the signal line for supplying the power supply voltage VDD, and the back gate is connected to the signal line for supplying the reference voltage GND.

[0042] The amplifier 11 receives a signal SINA at an input terminal INA and receives a signal SINB at an input terminal INB. The amplifier 11 outputs a '1' signal of a power supply voltage VDD level or a '0' signal of a reference voltage GND level from an output terminal OUT as an output signal SOUT, according to the voltages of the input signals SINA and SINB. In the present embodiment, as an example, the function of the amplifier 11 is realized by a level converter (level shifter, level conversion circuit) having P-type MOS transistors MP11, MP12 and N-type MOS transistors MN11, MN12. By using a level converter (level conversion circuit) as the amplifier 11, it is possible to prevent an unnecessary through current from flowing, and to reduce current consumption.

[0043] Between the signal line that supplies the power supply voltage VDD and the signal line that supplies the reference voltage GND, a P-type MOS transistor MP11 and an N-type MOS transistor MN11 are connected in series in order from the signal line side that supplies the power supply voltage VDD. Also, between the signal line that supplies the power supply voltage VDD and the signal line that supplies the reference voltage GND, a P-type MOS transistor MP12 and an N-type MOS transistor MN12 are connected in series in order from the signal line side that supplies the power supply voltage VDD.

[0044] The signal SINA is input to the gate of the N-type MOS transistor MN11, and the signal SINB is input to the gate of the N-type MOS transistor MN12. In addition, the gate of the P-type MOS transistor MP11 is connected to the connection point between the P-type MOS transistor MP12 and the N-type MOS transistor MN12, and the gate of the P-type MOS transistor MP12 is connected to the connection point between the P-type MOS transistor MP11 and the N-type MOS transistor MN11. The voltage at the connection point between the P-type MOS transistor MP12 and the N-type MOS transistor MN12 is output as the output signal SOUT.

[0045] Here, the threshold voltages of the N-type MOS transistors MN101 and MN104 are the same voltage, which is a value higher than the power supply voltage VDD. In addition, the threshold voltages of the N-type MOS transistors MN102 and MN103 are the same voltage, which is a normal (standard) threshold voltage (for example, about +0.5V). The control of the threshold voltage of the transistor can be achieved by changing the channel injection doping control of the doping amount of the channel, changing the gate oxide film thickness control of the gate oxide film thickness, and back gate voltage control for utilizing the back gate effect. In addition, in the figure, the component with the annotation (HVT) indicates that it is a transistor with a high threshold voltage (the same is true in the following embodiments).

[0046] In addition, the layout of the two N-type MOS transistors MN101 and MN102 and the layout of the two N-type MOS transistors MN103 and MN104, including the wiring related thereto, are of the same shape. That is, the layout and wiring shapes of the N-type MOS transistors MN101 and MN103 are the same, and the layout and wiring shapes of the N-type MOS transistors MN102 and MN104 are the same. For example, the gate length and gate width of the N-type MOS transistors MN101 and MN103 are the same, and the gate length and gate width of the N-type MOS transistors MN102 and MN104 are the same.

[0047] In this way, since the layout and wiring shapes of the N-type MOS transistors MN101 and MN103 are the same, it is impossible to distinguish which transistor has a higher threshold value than the power supply voltage VDD in appearance. Similarly, since the layout and wiring shapes of the N-type MOS transistors MN102 and MN104 are the same, it is impossible to distinguish which transistor has a higher threshold value than the power supply voltage VDD in appearance.

[0048] In the image Figure 1AIn the circuit connected as shown, N-type MOS transistors MN101 and MN104 having a threshold voltage higher than the power supply voltage VDD are in an off state, and N-type MOS transistors MN102 and MN103 having a normal (standard) threshold voltage are in an on state. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN101 and MN102 is substantially the reference voltage GND, and the voltage (signal SINB) at the connection point of the N-type MOS transistors MN103 and MN104 is (VDD-VTH) lower than the power supply voltage VDD by the threshold value VTH of the N-type MOS transistor MN103.

[0049] At this time, in the amplifier (level converter) 11, the P-type MOS transistor MP11 and the N-type MOS transistor MN12 are in the on state, and the P-type MOS transistor MP12 and the N-type MOS transistor MN11 are in the off state. Figure 1A The circuit shown outputs a '0' signal of the reference voltage GND level as the output signal SOUT.

[0050] Next, Figure 1B The second signal output circuit shown in FIG. 1 includes N-type MOS transistors MN105, MN106, MN107, MN108 and an amplifier 11. Figure 1B In, with Figure 1A The same components as those shown are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0051] Between the signal line for supplying power supply voltage VDD and the signal line for supplying reference voltage GND, two N-type MOS transistors MN105 and MN106 are connected in series in order from the signal line for supplying power supply voltage VDD, and the voltage at the connection point of the two N-type MOS transistors MN105 and MN106 is output as a signal SINA. In the N-type MOS transistors MN105 and MN106, the gate is connected to the signal line for supplying power supply voltage VDD, and the back gate is connected to the signal line for supplying reference voltage GND.

[0052] In addition, between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage GND, two N-type MOS transistors MN107 and MN108 are connected in series in order from the signal line for supplying the power supply voltage VDD, and the voltage at the connection point of the two N-type MOS transistors MN107 and MN108 is output as the signal SINB. In the N-type MOS transistors MN107 and MN108, the gate is connected to the signal line for supplying the power supply voltage VDD, and the back gate is connected to the signal line for supplying the reference voltage GND.

[0053] Here, the threshold voltages of the N-type MOS transistors MN106 and MN107 are the same voltage, which is a value higher than the power supply voltage VDD. In addition, the threshold voltages of the N-type MOS transistors MN105 and MN108 are the same voltage, which is a normal (standard) threshold voltage. That is, the two N-type MOS transistors for outputting the signal SINA and the two N-type MOS transistors for outputting the signal SINB are replaced with each other, and the circuit structure of the output signals SINA and SINB is the same as that of the output signal SINA. Figure 1A The circuit structure shown is the opposite.

[0054] In addition, the layout of the two N-type MOS transistors MN105 and MN106 and the layout of the two N-type MOS transistors MN107 and MN108, including the wiring related thereto, are of the same shape. The layout and wiring shapes of the N-type MOS transistors MN105 and MN107 are the same, and the layout and wiring shapes of the N-type MOS transistors MN106 and MN108 are the same. Therefore, it is impossible to distinguish which of the N-type MOS transistors MN105 and MN107 has a higher threshold than the power supply voltage VDD, and it is impossible to distinguish which of the N-type MOS transistors MN106 and MN108 has a higher threshold than the power supply voltage VDD.

[0055] In the image Figure 1B In the circuit connected as shown, N-type MOS transistors MN106 and MN107 having a threshold voltage higher than the power supply voltage VDD are in an off state, and N-type MOS transistors MN105 and MN108 having a normal (standard) threshold voltage are in an on state. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN105 and MN106 is (VDD-VTH) lower than the power supply voltage VDD by the threshold value VTH of the N-type MOS transistor MN105, and the voltage (signal SINB) at the connection point of the N-type MOS transistors MN107 and MN108 is approximately the reference voltage GND.

[0056] At this time, in the amplifier (level converter) 11, the P-type MOS transistor MP11 and the N-type MOS transistor MN12 are in the off state, and the P-type MOS transistor MP12 and the N-type MOS transistor MN11 are in the on state. Figure 1B The circuit shown outputs a '1' signal of the power supply voltage VDD level as the output signal SOUT.

[0057] As described above, transistors with different characteristics are used, and two signal output circuits are used that have the same layout and wiring shapes but implement different functions, and the level of the output signal is determined based on the signals from the two signal output circuits. As a result, the operation cannot be reproduced by simply reading the circuit diagram from the layout, making it difficult to reproduce the semiconductor device by reverse engineering.

[0058] In addition, if Figure 1A and Figure 1B As shown, the size can be achieved by eight transistors equivalent to a four-input NAND, and multiple signal output circuits can be mounted in the automatic configuration wiring area on the semiconductor chip. When multiple signal output circuits of this embodiment are mounted on a semiconductor chip, it is necessary to determine all functions (output states) of these signal output circuits during reverse engineering. However, it is very difficult and unrealistic to analyze all the mounted signal output circuits using the FIB or probe method.

[0059] Even if the transistor-level circuit diagram in the automatic configuration wiring area is identified by peeling off the layers one by one and photographing, the output state of each signal output circuit is still unclear. As a method for identifying the output state of each signal output circuit, it is considered to assign outputs of '0' or '1' to all signal output circuits and perform simulation and inference, but it is necessary to perform 2 times the number of signal output circuits. For example, in the case of 100 signal output circuits of this embodiment, it becomes 2 100 =1.26×10 30 Such astronomical figures are extremely difficult to infer through simulation and can make it difficult to reproduce semiconductor devices through reverse engineering.

[0060] (Second embodiment)

[0061] In the semiconductor device of the second embodiment, the two N-type MOS transistors connected in series between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND in the first embodiment are replaced with two P-type MOS transistors.

[0062] The semiconductor device of the second embodiment has a plurality of Figure 2A and Figure 2B The signal output circuit shown. Figure 2A and Figure 2B This is a diagram showing an example of a signal output circuit included in the semiconductor device according to the second embodiment. Figure 2A The first signal output circuit shown includes P-type MOS transistors MP201 , MP202 , MP203 , and MP204 , and an amplifier 21 .

[0063] Between the signal line for supplying power supply voltage VDD and the signal line for supplying reference voltage GND, two P-type MOS transistors MP201 and MP202 are connected in series in order from the signal line for supplying power supply voltage VDD, and the voltage at the connection point of the two P-type MOS transistors MP201 and MP202 is output as a signal SINA. In the P-type MOS transistors MP201 and MP202, the gate is connected to the signal line for supplying reference voltage GND, and the back gate is connected to the signal line for supplying power supply voltage VDD.

[0064] In addition, between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage GND, two P-type MOS transistors MP203 and MP204 are connected in series in order from the signal line for supplying the power supply voltage VDD, and the voltage at the connection point of the two P-type MOS transistors MP203 and MP204 is output as the signal SINB. In the P-type MOS transistors MP203 and MP204, the gate is connected to the signal line for supplying the reference voltage GND, and the back gate is connected to the signal line for supplying the power supply voltage VDD.

[0065] The amplifier 21 receives a signal SINA at an input terminal INA and receives a signal SINB at an input terminal INB. The amplifier 21 outputs a '1' signal at a power supply voltage VDD level or a '0' signal at a reference voltage GND level from an output terminal OUT as an output signal SOUT according to the voltages of the input signals SINA and SINB. In the present embodiment, as an example, the function of the amplifier 21 is realized by a level converter (level conversion circuit) having P-type MOS transistors MP21 and MP22 and N-type MOS transistors MN21 and MN22.

[0066] Between the signal line that supplies the power supply voltage VDD and the signal line that supplies the reference voltage GND, a P-type MOS transistor MP21 and an N-type MOS transistor MN21 are connected in series in order from the signal line side that supplies the power supply voltage VDD. Also, between the signal line that supplies the power supply voltage VDD and the signal line that supplies the reference voltage GND, a P-type MOS transistor MP22 and an N-type MOS transistor MN22 are connected in series in order from the signal line side that supplies the power supply voltage VDD.

[0067] The signal SINA is input to the gate of the P-type MOS transistor MP21, and the signal SINB is input to the gate of the P-type MOS transistor MP22. In addition, the gate of the N-type MOS transistor MN21 is connected to the connection point between the P-type MOS transistor MP22 and the N-type MOS transistor MN22, and the gate of the N-type MOS transistor MN22 is connected to the connection point between the P-type MOS transistor MP21 and the N-type MOS transistor MN21. The voltage at the connection point between the P-type MOS transistor MP22 and the N-type MOS transistor MN22 is output as the output signal SOUT.

[0068] Here, the threshold voltages of the P-type MOS transistors MP201 and MP204 are the same voltage, which is a value lower than the value of (reference voltage GND-power supply voltage VDD). In addition, the threshold voltages of the P-type MOS transistors MP202 and MP203 are the same voltage, which is a normal (standard) threshold voltage. The control of the threshold voltage of the transistor can be achieved by channel implantation doping control, gate oxide film thickness control, back gate voltage control, etc., as in the first embodiment.

[0069] In addition, the layout of the two P-type MOS transistors MP201 and MP202 and the layout of the two P-type MOS transistors MP203 and MP204, including the wiring related thereto, are of the same shape. That is, the layout and wiring shapes of the P-type MOS transistors MP201 and MP203 are the same, and the layout and wiring shapes of the P-type MOS transistors MP202 and MP204 are the same. For example, the gate length and gate width of the P-type MOS transistors MP201 and MP203 are the same, and the gate length and gate width of the P-type MOS transistors MP202 and MP204 are the same.

[0070] In this way, since the layout and wiring shapes of the P-type MOS transistors MP201 and MP203 are made the same, it is difficult to distinguish which transistor has a lower threshold value than (reference voltage GND-power supply voltage VDD) in appearance. Similarly, since the layout and wiring shapes of the P-type MOS transistors MP202 and MP204 are made the same, it is difficult to distinguish which transistor has a lower threshold value than (reference voltage GND-power supply voltage VDD) in appearance.

[0071] In the image Figure 2AIn the circuit connected as shown, the P-type MOS transistors MP201 and MP204 whose threshold voltage is lower than the value of (reference voltage GND-power supply voltage VDD) are in the off state, and the P-type MOS transistors MP202 and MP203 whose threshold voltage is normal (standard) are in the on state. Therefore, the voltage (signal SINA) at the connection point of the P-type MOS transistors MP201 and MP202 is (GND+|VTH|) higher than the reference voltage GND by the absolute value of the threshold value VTH of the P-type MOS transistor MP202, and the voltage (signal SINB) at the connection point of the P-type MOS transistors MP203 and MP204 is approximately the power supply voltage VDD.

[0072] At this time, in the amplifier (level converter) 21, the P-type MOS transistor MP21 and the N-type MOS transistor MN22 are in the on state, and the P-type MOS transistor MP22 and the N-type MOS transistor MN21 are in the off state. Figure 2A The circuit shown outputs a '0' signal of the reference voltage GND level as the output signal SOUT.

[0073] Next, Figure 2B The second signal output circuit shown in FIG. 1 includes P-type MOS transistors MP205, MP206, MP207, MP208 and an amplifier 21. Figure 2B In, with Figure 2A The same components as those shown are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0074] Between the signal line for supplying power voltage VDD and the signal line for supplying reference voltage GND, two P-type MOS transistors MP205 and MP206 are connected in series in order from the signal line for supplying power voltage VDD, and the voltage at the connection point of the two P-type MOS transistors MP205 and MP206 is output as a signal SINA. In the P-type MOS transistors MP205 and MP206, the gate is connected to the signal line for supplying reference voltage GND, and the back gate is connected to the signal line for supplying power voltage VDD.

[0075] In addition, between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage GND, two P-type MOS transistors MP207 and MP208 are connected in series in order from the signal line for supplying the power supply voltage VDD, and the voltage at the connection point of the two P-type MOS transistors MP207 and MP208 is output as the signal SINB. In the P-type MOS transistors MP207 and MP208, the gate is connected to the signal line for supplying the reference voltage GND, and the back gate is connected to the signal line for supplying the power supply voltage VDD.

[0076] Here, the threshold voltages of the P-type MOS transistors MP206 and MP207 are the same voltage, which is a value lower than the value of (reference voltage GND-power supply voltage VDD). In addition, the threshold voltages of the P-type MOS transistors MP205 and MP208 are the same voltage, which is a normal (standard) threshold voltage. That is, the two P-type MOS transistors for outputting the signal SINA and the two P-type MOS transistors for outputting the signal SINB are arranged in a manner that is different from the circuit structure of the output signals SINA and SINB. Figure 2A The circuit structure shown is the opposite.

[0077] In addition, the layout of the two P-type MOS transistors MP205 and MP206 and the layout of the two P-type MOS transistors MP207 and MP208, including the wiring related thereto, are of the same shape. The layout and wiring shapes of the P-type MOS transistors MP205 and MP207 are the same, and the layout and wiring shapes of the P-type MOS transistors MP206 and MP208 are the same. Therefore, it is not possible to distinguish which of the P-type MOS transistors MP205 and MP207 has a lower threshold value than the value of (reference voltage GND-power supply voltage VDD), and it is not possible to distinguish which of the P-type MOS transistors MP206 and MP208 has a lower threshold value than the value of (reference voltage GND-power supply voltage VDD).

[0078] In the image Figure 2B In the circuit connected as shown, the P-type MOS transistors MP206 and MP207 whose threshold voltage is lower than the value of (reference voltage GND-power supply voltage VDD) are in the off state, and the P-type MOS transistors MP205 and MP208 whose threshold voltage is normal (standard) are in the on state. Therefore, the voltage (signal SINA) at the connection point of the P-type MOS transistors MP205 and MP206 is approximately the power supply voltage VDD, and the voltage (signal SINB) at the connection point of the P-type MOS transistors MP207 and MP208 is (GND+|VTH|) which is higher than the reference voltage GND by the absolute value of the threshold value VTH of the P-type MOS transistor MP208.

[0079] At this time, in the amplifier (level converter) 21, the P-type MOS transistor MP21 and the N-type MOS transistor MN22 are in the off state, and the P-type MOS transistor MP22 and the N-type MOS transistor MN21 are in the on state. Figure 2B The circuit shown outputs a '1' signal of the power supply voltage VDD level as the output signal SOUT.

[0080] As described above, also in the second embodiment using a P-type MOS transistor instead of an N-type MOS transistor, the same effect as in the first embodiment can be obtained, and the semiconductor device can be made difficult to reproduce by reverse engineering.

[0081] (Third embodiment)

[0082] Next, a third embodiment of the present invention is described. In the third embodiment, the two N-type MOS transistors connected in series between the signal line providing the power supply voltage VDD and the signal line providing the reference voltage GND in the first embodiment are connected in series between the signal line providing a voltage lower than the power supply voltage VDD and the signal line providing the reference voltage GND.

[0083] The semiconductor device of the third embodiment has a plurality of Figure 3A and Figure 3B The signal output circuit shown. Figure 3A and Figure 3B FIG. 1 is a diagram showing an example of a signal output circuit included in the semiconductor device according to the third embodiment. Figure 3A The first signal output circuit shown includes N-type MOS transistors MN301 , MN302 , MN303 , MN304 , and MN305 , and an amplifier 11 .

[0084] The N-type transistor MN305 is a transistor having a normal (standard) threshold voltage, and is connected between a signal line providing a power supply voltage VDD and a signal line providing a voltage lower than the power supply voltage VDD, and the gate of the N-type transistor MN305 is connected to the signal line providing the power supply voltage VDD. That is, the N-type transistor MN305 is connected to the signal line providing the power supply voltage VDD in a diode manner. Therefore, the voltage of the signal line providing a voltage lower than the power supply voltage VDD is (VDD-VTH) lower than the power supply voltage VDD by the threshold voltage VTH of the N-type transistor MN305.

[0085] The N-type MOS transistors MN301, MN302, MN303, MN304 and the amplifier 11 are respectively Figure 1A The N-type MOS transistors MN101, MN102, MN103, MN104 and the amplifier 11 shown are the same.

[0086] However, in this embodiment, two N-type MOS transistors MN301 and MN302 are connected in series between a signal line for providing a voltage (VDD-VTH) and a signal line for providing a reference voltage GND. Similarly, two N-type MOS transistors MN303 and MN304 are connected in series between a signal line for providing a voltage (VDD-VTH) and a signal line for providing a reference voltage GND. In addition, the gates of the N-type MOS transistors MN301, MN302, MN303, and MN304 are connected to a signal line for providing a voltage (VDD-VTH).

[0087] In the image Figure 3A In the circuit connected as shown, N-type MOS transistors MN301 and MN304 are in the off state, and N-type MOS transistors MN302 and MN303 are in the on state. Therefore, the voltage (signal SINA) at the connection point of N-type MOS transistors MN301 and MN302 is approximately the reference voltage GND, and the voltage (signal SINB) at the connection point of N-type MOS transistors MN303 and MN304 is (VDD-2VTH) which is lower than the voltage (VDD-VTH) by the threshold value VTH of N-type MOS transistor MN303. Therefore, Figure 3A The circuit shown outputs a '0' signal of the reference voltage GND level as the output signal SOUT.

[0088] Next, Figure 3B The second signal output circuit shown includes N-type MOS transistors MN306 , MN307 , MN308 , MN309 , and MN310 and an amplifier 11 .

[0089] The N-type transistor MN310 is a transistor having a normal (standard) threshold voltage, and is connected between a signal line providing a power supply voltage VDD and a signal line providing a voltage lower than the power supply voltage VDD, and the gate of the N-type transistor MN310 is connected to the signal line providing the power supply voltage VDD. That is, the N-type transistor MN310 is connected to the signal line providing the power supply voltage VDD in a diode manner. Therefore, the voltage of the signal line providing a voltage lower than the power supply voltage VDD is (VDD-VTH) lower than the power supply voltage VDD by the threshold voltage VTH of the N-type transistor MN310.

[0090] N-type MOS transistors MN306, MN307, MN308, MN309 and amplifier 11 are respectively Figure 1B The N-type MOS transistors MN105, MN106, MN107, MN108 and the amplifier 11 shown are the same.

[0091] However, in this embodiment, two N-type MOS transistors MN306 and MN307 are connected in series between a signal line for providing a voltage (VDD-VTH) and a signal line for providing a reference voltage GND. Similarly, two N-type MOS transistors MN308 and MN309 are connected in series between a signal line for providing a voltage (VDD-VTH) and a signal line for providing a reference voltage GND. In addition, the gates of the N-type MOS transistors MN306, MN307, MN308, and MN309 are connected to the signal line for providing a voltage (VDD-VTH).

[0092] In the image Figure 3B In the circuit connected as shown, N-type MOS transistors MN307 and MN308 are in the off state, and N-type MOS transistors MN306 and MN309 are in the on state. Therefore, the voltage (signal SINA) at the connection point of N-type MOS transistors MN306 and MN307 is (VDD-2VTH) lower than the voltage (VDD-VTH) by the threshold value VTH of N-type MOS transistor MN306, and the voltage (signal SINB) at the connection point of N-type MOS transistors MN308 and MN309 is approximately the reference voltage GND. Therefore, Figure 3B The circuit shown outputs a '1' signal of the power supply voltage VDD level as the output signal SOUT.

[0093] As described above, an N-type MOS transistor connected to the power supply voltage VDD side in a diode manner is provided, and two N-type MOS transistors are connected in series between a signal line providing a voltage lower than the power supply voltage VDD obtained by the N-type MOS transistor and a signal line providing a reference voltage GND. In such a third embodiment, the same effect as the first embodiment can be obtained, and it can be difficult to reproduce the semiconductor device by reverse engineering. In addition, the third embodiment is equivalent to the case of lowering the power supply voltage in the first embodiment, so that power consumption can be reduced.

[0094] (Fourth embodiment)

[0095] Next, a fourth embodiment of the present invention will be described.

[0096] The semiconductor device of the fourth embodiment has a plurality of Figure 4A and Figure 4B The signal output circuit shown. Figure 4A and Figure 4B This is a diagram showing an example of a signal output circuit included in the semiconductor device according to the fourth embodiment. Figure 4AThe first signal output circuit shown in FIG. 1 includes N-type MOS transistors MN401, MN402, MN403, MN404 and an amplifier 11. The N-type MOS transistors MN401, MN402, MN403, MN404 and the amplifier 11 are respectively connected to Figure 1A The N-type MOS transistors MN101 , MN102 , MN103 , MN104 and the amplifier 11 shown are the same.

[0097] However, in this embodiment, the gate of the N-type MOS transistor MN401 is connected to the signal line for providing the voltage VDD, and the gate of the N-type MOS transistor MN402 is connected to the connection point of the two N-type MOS transistors MN401 and MN402. In addition, the gate of the N-type MOS transistor MN403 is connected to the signal line for providing the voltage VDD, and the gate of the N-type MOS transistor MN404 is connected to the connection point of the two N-type MOS transistors MN403 and MN404. That is, the N-type MOS transistors MN401, MN402, MN403, and MN404 are connected in the form of diodes.

[0098] In the image Figure 4A In the circuit connected as shown, N-type MOS transistors MN401 and MN404 are in the off state, and N-type MOS transistors MN402 and MN403 are in the on state. Therefore, the voltage (signal SINA) at the connection point of N-type MOS transistors MN401 and MN402 is higher than the reference voltage GND by the threshold value VTH of N-type MOS transistor MN402 (GND+VTH), and the voltage (signal SINB) at the connection point of N-type MOS transistors MN403 and MN404 is lower than the power supply voltage VDD by the threshold value VTH of N-type MOS transistor MN403 (VDD-VTH). Therefore, Figure 4A The circuit shown outputs a '0' signal of the reference voltage GND level as the output signal SOUT.

[0099] Next, Figure 4B The second signal output circuit shown in FIG. 1 includes N-type MOS transistors MN405, MN406, MN407, MN408 and an amplifier 11. The N-type MOS transistors MN405, MN406, MN407, MN408 and the amplifier 11 are respectively connected to Figure 1B The N-type MOS transistors MN105, MN106, MN107, MN108 and the amplifier 11 shown are the same.

[0100] However, in this embodiment, the gate of the N-type MOS transistor MN405 is connected to the signal line for providing the voltage VDD, and the gate of the N-type MOS transistor MN406 is connected to the connection point of the two N-type MOS transistors MN405 and MN406. In addition, the gate of the N-type MOS transistor MN407 is connected to the signal line for providing the voltage VDD, and the gate of the N-type MOS transistor MN408 is connected to the connection point of the two N-type MOS transistors MN407 and MN408. That is, the N-type MOS transistors MN405, MN406, MN407, and MN408 are connected in the form of diodes.

[0101] In the image Figure 4B In the circuit connected as shown, N-type MOS transistors MN406 and MN407 are in the off state, and N-type MOS transistors MN405 and MN408 are in the on state. Therefore, the voltage (signal SINA) at the connection point of N-type MOS transistors MN405 and MN406 is (VDD-VTH) lower than the power supply voltage VDD by the threshold value VTH of N-type MOS transistor MN405, and the voltage (signal SINB) at the connection point of N-type MOS transistors MN407 and MN408 is (GND+VTH) higher than the reference voltage GND by the threshold value VTH of N-type MOS transistor MN408. Therefore, Figure 4B The circuit shown outputs a '1' signal of the power supply voltage VDD level as the output signal SOUT.

[0102] According to the fourth embodiment described above, the same effects as those of the first embodiment can be obtained, and the semiconductor device can be made difficult to reproduce by reverse engineering, and power consumption can be reduced.

[0103] In addition, in the third and fourth embodiments described above, examples using N-type MOS transistors are shown, but P-type MOS transistors can also be used to implement. In this case, as long as the connection is changed based on the second embodiment, the following same effects can be obtained: it is difficult to reproduce the semiconductor device by reverse engineering, and power consumption can be reduced.

[0104] (Fifth embodiment)

[0105] Next, a fifth embodiment of the present invention will be described.

[0106] The semiconductor device of the fifth embodiment has a plurality of Figure 5A and Figure 5B The signal output circuit shown. Figure 5A and 5B This is a diagram showing an example of a signal output circuit included in the semiconductor device according to the fifth embodiment. Figure 5AThe first signal output circuit shown includes a depletion-type N-type MOS transistor MN501 and an enhancement-type N-type MOS transistor MN502.

[0107] Between the signal line providing the power supply voltage VDD and the signal line providing the reference voltage GND, N-type MOS transistors MN501 and MN502 are connected in series in sequence from the signal line side providing the power supply voltage VDD, and the voltage at the connection point of the N-type MOS transistors MN501 and MN502 is output as the output signal SOUT. The gate of the N-type MOS transistor MN501 is connected to the connection point of the N-type MOS transistors MN501 and MN502, and the gate of the N-type MOS transistor MN502 is connected to the signal line providing the reference voltage GND. That is, the N-type MOS transistors MN501 and MN502 are connected in the form of diodes. In addition, the back gates of the N-type MOS transistors MN501 and MN502 are connected to the signal line providing the reference voltage GND.

[0108] In the image Figure 5A In the circuit connected as shown, the depletion-type N-type MOS transistor MN501 is in the on state, and the enhancement-type N-type MOS transistor MN502 is in the off state. Figure 5A The circuit shown outputs a '1' signal of the power supply voltage VDD level as the output signal SOUT.

[0109] Next, Figure 5B The second signal output circuit shown has an enhancement type N-type MOS transistor MN503 and a depletion type N-type MOS transistor MN504. Here, the layout and wiring shape of the N-type MOS transistor MN503 are the same as the layout and wiring shape of the N-type MOS transistor MN501, and the layout and wiring shape of the N-type MOS transistor MN504 are the same as the layout and wiring shape of the N-type MOS transistor MN502.

[0110] Between the signal line providing the power supply voltage VDD and the signal line providing the reference voltage GND, N-type MOS transistors MN503 and MN504 are connected in series in sequence from the signal line side providing the power supply voltage VDD, and the voltage at the connection point of the N-type MOS transistors MN503 and MN504 is output as the output signal SOUT. The gate of the N-type MOS transistor MN503 is connected to the connection point of the N-type MOS transistors MN503 and MN504, and the gate of the N-type MOS transistor MN504 is connected to the signal line providing the reference voltage GND. That is, the N-type MOS transistors MN503 and MN504 are connected in the form of diodes. In addition, the back gates of the N-type MOS transistors MN503 and MN504 are connected to the signal line providing the reference voltage GND.

[0111] exist Figure 5B In the circuit shown, the depletion-type N-type MOS transistor MN504 is in the on state, and the enhancement-type N-type MOS transistor MN503 is in the off state. Figure 5B The circuit shown outputs a '0' signal of the reference voltage GND level as the output signal SOUT. In addition, in the signal output circuit of the semiconductor device of the fifth embodiment, since the voltage of the connection point of the N-type MOS transistors MN501 and MN502 and the voltage of the connection point of the N-type MOS transistors MN503 and MN504 are at the power supply voltage VDD level or the reference voltage GND level, an amplifier is not required.

[0112] As described above, by using transistors with the same layout and wiring shapes but different characteristics, the operation cannot be reproduced by simply reading the circuit diagram from the layout, making it difficult to reproduce the semiconductor device by reverse engineering. Figure 1A and Figure 1B Compared with the signal output circuit shown in the figure, the number of transistors to be constructed is small, and an amplifier is not required, so the area required for installation can be reduced, and more signal output circuits can be mounted in the automatic configuration wiring area on the semiconductor chip. Therefore, it is difficult to reproduce the semiconductor device by reverse engineering. In addition, since there is almost no current flow, power consumption can also be reduced.

[0113] (Sixth embodiment)

[0114] Next, a sixth embodiment of the present invention will be described. In the sixth embodiment, a P-type MOS transistor is used instead of the N-type MOS transistor of the fifth embodiment.

[0115] The semiconductor device of the sixth embodiment has a plurality of Fig. 6A and Figure 6B The signal output circuit shown. Fig. 6A and Figure 6B This is a diagram showing an example of a signal output circuit included in the semiconductor device according to the sixth embodiment. Fig. 6A The first signal output circuit shown includes a depletion-type P-type MOS transistor MP601 and an enhancement-type P-type MOS transistor MP602 .

[0116] Between the signal line providing the power supply voltage VDD and the signal line providing the reference voltage GND, P-type MOS transistors MP601 and MP602 are connected in series in order from the signal line side providing the power supply voltage VDD, and the voltage at the connection point of the P-type MOS transistors MP601 and MP602 is output as the output signal SOUT. The gate of the P-type MOS transistor MP601 is connected to the signal line providing the power supply voltage VDD, and the gate of the P-type MOS transistor MP602 is connected to the connection point of the P-type MOS transistors MP601 and MP602. That is, the P-type MOS transistors MP601 and MP602 are connected in the form of diodes. In addition, the back gates of the P-type MOS transistors MP601 and MP602 are connected to the signal line providing the power supply voltage VDD.

[0117] In the image Fig. 6A In the circuit connected as shown, the depletion-type P-type MOS transistor MP601 is in the on state, and the enhancement-type P-type MOS transistor MP602 is in the off state. Fig. 6A The circuit shown outputs a '1' signal of the power supply voltage VDD level as the output signal SOUT.

[0118] Next, Figure 6B The second signal output circuit shown has an enhancement type P-type MOS transistor MP603 and a depletion type P-type MOS transistor MP604. Here, the layout and wiring shape of the P-type MOS transistor MP603 are the same as the layout and wiring shape of the P-type MOS transistor MP601, and the layout and wiring shape of the P-type MOS transistor MP604 are the same as the layout and wiring shape of the P-type MOS transistor MP602.

[0119] Between the signal line providing the power supply voltage VDD and the signal line providing the reference voltage GND, P-type MOS transistors MP603 and MP604 are connected in series in order from the signal line side providing the power supply voltage VDD, and the voltage at the connection point of the P-type MOS transistors MP603 and MP604 is output as the output signal SOUT. The gate of the P-type MOS transistor MP603 is connected to the signal line providing the power supply voltage VDD, and the gate of the P-type MOS transistor MP604 is connected to the connection point of the P-type MOS transistors MP603 and MP604. That is, the P-type MOS transistors MP603 and MP604 are connected in the form of diodes. In addition, the back gates of the P-type MOS transistors MP603 and MP604 are connected to the signal line providing the power supply voltage VDD.

[0120] In the image Figure 6B In the circuit connected as shown, the depletion-type P-type MOS transistor MP604 is in the on state, and the enhancement-type P-type MOS transistor MP603 is in the off state. Figure 6B The circuit shown outputs a '0' signal of the reference voltage GND level as the output signal SOUT. In the sixth embodiment, since the voltage at the connection point of PMOS transistors MP601 and MP602 and the voltage at the connection point of PMOS transistors MP603 and MP604 are at the power supply voltage VDD level or the reference voltage GND level, an amplifier is not required.

[0121] As described above, in the sixth embodiment using P-type MOS transistors instead of N-type MOS transistors, the same effects as those of the fifth embodiment can be obtained, making it difficult to reproduce the semiconductor device by reverse engineering and reducing power consumption.

[0122] (Seventh Implementation Method)

[0123] Next, a seventh embodiment of the present invention will be described.

[0124] The semiconductor device of the seventh embodiment has a plurality of Fig. 7A and 7B The signal output circuit shown. Fig. 7A and 7B This is a diagram showing an example of a signal output circuit included in the semiconductor device according to the seventh embodiment. Fig. 7A The first signal output circuit shown in FIG. 1 includes a P-type MOS transistor MP701 and an N-type MOS transistor MN701. Here, the withstand voltage of the P-type MOS transistor MP701 is different from that of the N-type MOS transistor MN701. Fig. 7A In the example shown, the N-type MOS transistor MN701 is a high withstand voltage transistor.

[0125] Between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage GND, a P-type MOS transistor MP701 and an N-type MOS transistor MN701 are connected in series in order from the signal line side for supplying the power supply voltage VDD, and the voltage at the connection point between the P-type MOS transistor MP701 and the N-type MOS transistor MN701 is output as the output signal SOUT. In the P-type MOS transistor MP701, the gate is connected to the signal line for supplying the reference voltage GND, and the back gate is connected to the signal line for supplying the power supply voltage VDD. In addition, in the N-type MOS transistor MN701, the gate is connected to the signal line for supplying the power supply voltage VDD, and the back gate is connected to the signal line for supplying the reference voltage GND. Fig. 7A The circuit shown outputs a signal of a voltage VH which is a high voltage close to a power supply voltage VDD as an output signal SOUT.

[0126] Next, Figure 7BThe second signal output circuit shown in FIG. 1 includes a P-type MOS transistor MP702 and an N-type MOS transistor MN702. The withstand voltage of the P-type MOS transistor MP702 is different from that of the N-type MOS transistor MN702. Fig. 7A In contrast to the example shown, Figure 7B In the example shown, the P-type MOS transistor MP702 is a high withstand voltage transistor. Here, the layout and wiring shape of the P-type MOS transistor MP702 are the same as the layout and wiring shape of the P-type MOS transistor MP701, and the layout and wiring shape of the N-type MOS transistor MN702 are the same as the layout and wiring shape of the N-type MOS transistor MN701.

[0127] Between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage GND, a P-type MOS transistor MP702 and an N-type MOS transistor MN702 are connected in series in order from the signal line side for supplying the power supply voltage VDD, and the voltage at the connection point between the P-type MOS transistor MP702 and the N-type MOS transistor MN702 is output as the output signal SOUT. In the P-type MOS transistor MP702, the gate is connected to the signal line for supplying the reference voltage GND, and the back gate is connected to the signal line for supplying the power supply voltage VDD. In addition, in the N-type MOS transistor MN702, the gate is connected to the signal line for supplying the power supply voltage VDD, and the back gate is connected to the signal line for supplying the reference voltage GND. Figure 7B The circuit shown outputs a signal of a voltage VL which is a low voltage close to a reference voltage GND as an output signal SOUT.

[0128] As described above, by using transistors with the same layout and wiring shapes but different withstand voltages, the operation cannot be reproduced by simply reading the circuit diagram from the layout, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering. In addition, in the signal output circuit of the seventh embodiment, the number of transistors to be constructed is small, and more signal output circuits can be mounted in the automatic configuration wiring area on the semiconductor chip. Therefore, it is possible to make it difficult to reproduce the semiconductor device by reverse engineering.

[0129] Furthermore, embodiments in which the above-described first to seventh embodiments are appropriately combined may be possible, and these embodiments are also included in the embodiments of the present invention.

[0130] (Other embodiments)

[0131] Figure 8 FIG. 1 is a diagram showing an application example of the semiconductor device of this embodiment. Figure 8In the figure, 100 is a semiconductor chip including the semiconductor device of the present embodiment. In the semiconductor chip 100, the outputs of a plurality of signal output circuits 120 are connected to a logic processing circuit unit 110 that performs various logic processing. Since the logic processing circuit unit 110 uses the outputs of the signal output circuits 120 to perform a part or all of the logic processing, the relationship between the input and output in the logic processing circuit unit 110 also depends on the output state of the signal output circuit 120. As described above, it is difficult to determine the output state of the signal output circuit 120 of the present embodiment by reverse engineering, and it is also difficult to analyze the relationship between the input and output in the logic processing circuit unit 110, which can prevent illegal copying of semiconductor chips, etc.

[0132] In addition, the above-mentioned embodiments are merely examples of specific implementations of the present invention, and the technical scope of the present invention is not to be interpreted in a limitative manner by them. That is, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0133] Industrial Applicability

[0134] According to these semiconductor devices, it is possible to make it difficult to reproduce the semiconductor device by reverse engineering.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a plurality of first signal output circuits, each having a first transistor and a second transistor, and outputting a voltage at a connection point between the first transistor and the second transistor, wherein the first transistor and the second transistor are connected in series between a signal line that supplies a first voltage and a signal line that supplies a second voltage that is lower than the first voltage, and a predetermined voltage is supplied to each gate; as well as a plurality of second signal output circuits, each having a third transistor and a fourth transistor, outputting a voltage at a connection point between the third transistor and the fourth transistor, the third transistor and the fourth transistor being connected in series between a signal line providing the first voltage and a signal line providing the second voltage, and having respective gates provided with a predetermined voltage, the third transistor having the same layout as the first transistor but different characteristics, and the fourth transistor having the same layout as the second transistor but different characteristics, The first voltage is a power supply voltage, The second voltage is a reference voltage, The first transistor and the third transistor are connected to a signal line that provides the first voltage, a threshold voltage of the first transistor is different from a threshold voltage of the third transistor, and a threshold voltage of the second transistor is different from a threshold voltage of the fourth transistor. The plurality of first signal output circuits include a first signal output circuit in which a threshold voltage of the first transistor is higher than the power supply voltage, the first transistor and the second transistor are N-type transistors whose gates are connected to a signal line that supplies the first voltage, The plurality of second signal output circuits include a second signal output circuit in which a threshold voltage of the fourth transistor is higher than the power supply voltage, and the third transistor and the fourth transistor are N-type transistors whose gates are connected to a signal line providing the first voltage.

2. The semiconductor device according to claim 1, wherein: The semiconductor device includes an N-type transistor connected in a diode-like manner between a signal line providing the first voltage and a signal line providing a third voltage. The first transistor and the second transistor are connected in series between a signal line that provides the third voltage and a signal line that provides the second voltage. The third transistor and the fourth transistor are connected in series between a signal line that supplies the third voltage and a signal line that supplies the second voltage.

3. The semiconductor device according to claim 1, wherein: The plurality of first signal output circuits further include a first signal output circuit in which a threshold voltage of the first transistor is lower than a value obtained by subtracting the first voltage from the second voltage, and the first transistor and the second transistor are P-type transistors whose gates are connected to a signal line that supplies the second voltage. The multiple second signal output circuits also include the following second signal output circuit: in this second signal output circuit, the threshold voltage of the fourth transistor is lower than the value obtained by subtracting the first voltage from the second voltage, and the third transistor and the fourth transistor are P-type transistors whose gates are connected to the signal line providing the second voltage.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor and the second transistor are connected in the form of diodes, respectively. The plurality of second signal output circuits further include a second signal output circuit in which the third transistor and the fourth transistor are respectively connected in a diode manner.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor is a depletion type transistor and the second transistor is an enhancement type transistor. The plurality of second signal output circuits further include a second signal output circuit in which the third transistor is an enhancement type and the fourth transistor is a depletion type.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor is a high withstand voltage transistor, the second transistor is a low withstand voltage transistor having a withstand voltage lower than that of the first transistor, The plurality of second signal output circuits further include a second signal output circuit in which the third transistor is the low withstand voltage transistor and the fourth transistor is the high withstand voltage transistor.

7. A semiconductor device, characterized in that: The semiconductor device comprises: a plurality of first signal output circuits, each having a first transistor and a second transistor, and outputting a voltage at a connection point between the first transistor and the second transistor, wherein the first transistor and the second transistor are connected in series between a signal line that supplies a first voltage and a signal line that supplies a second voltage that is lower than the first voltage, and a predetermined voltage is supplied to each gate; as well as a plurality of second signal output circuits, each having a third transistor and a fourth transistor, outputting a voltage at a connection point between the third transistor and the fourth transistor, the third transistor and the fourth transistor being connected in series between a signal line providing the first voltage and a signal line providing the second voltage, and having respective gates provided with a predetermined voltage, the third transistor having the same layout as the first transistor but different characteristics, and the fourth transistor having the same layout as the second transistor but different characteristics, The first voltage is a power supply voltage, The second voltage is a reference voltage, The first transistor and the third transistor are connected to a signal line that provides the first voltage, a threshold voltage of the first transistor is different from a threshold voltage of the third transistor, and a threshold voltage of the second transistor is different from a threshold voltage of the fourth transistor. The plurality of first signal output circuits include a first signal output circuit in which a threshold voltage of the first transistor is lower than a value obtained by subtracting the first voltage from the second voltage, and the first transistor and the second transistor are P-type transistors whose gates are connected to a signal line that supplies the second voltage. The multiple second signal output circuits include the following second signal output circuit: in this second signal output circuit, the threshold voltage of the fourth transistor is lower than the value obtained by subtracting the first voltage from the second voltage, and the third transistor and the fourth transistor are P-type transistors whose gates are connected to the signal line providing the second voltage.

8. The semiconductor device according to claim 7, wherein: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor and the second transistor are connected in a diode manner; and The plurality of second signal output circuits further include a second signal output circuit in which the third transistor and the fourth transistor are respectively connected in a diode manner.

9. The semiconductor device according to claim 7 or 8, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor is a depletion type transistor and the second transistor is an enhancement type transistor. The plurality of second signal output circuits further include a second signal output circuit in which the third transistor is an enhancement type and the fourth transistor is a depletion type.

10. The semiconductor device according to claim 7 or 8, characterized in that The plurality of first signal output circuits further include a first signal output circuit in which the first transistor is a high withstand voltage transistor, the second transistor is a low withstand voltage transistor having a withstand voltage lower than that of the first transistor, The plurality of second signal output circuits further include a second signal output circuit in which the third transistor is the low withstand voltage transistor and the fourth transistor is the high withstand voltage transistor.

11. A semiconductor device, characterized in that: The semiconductor device has: a plurality of first signal output circuits, each having a first transistor and a second transistor, and outputting a voltage at a connection point between the first transistor and the second transistor, wherein the first transistor and the second transistor are connected in series between a signal line that supplies a first voltage and a signal line that supplies a second voltage that is lower than the first voltage, and a predetermined voltage is supplied to each gate; a plurality of second signal output circuits, comprising a third transistor and a fourth transistor, which output a voltage at a connection point between the third transistor and the fourth transistor, the third transistor and the fourth transistor being connected in series between a signal line providing the first voltage and a signal line providing the second voltage, and having respective gates provided with a predetermined voltage, the third transistor having the same layout as the first transistor but different characteristics, and the fourth transistor having the same layout as the second transistor but different characteristics; and A logic processing circuit that performs logic processing, The logic processing circuit is connected to the output of the first signal output circuit and the output of the second signal output circuit, and uses the output of the connected signal output circuit to perform a part or all of the logic processing. The first voltage is a power supply voltage, The second voltage is a reference voltage, The first transistor and the third transistor are connected to a signal line that provides the first voltage, a threshold voltage of the first transistor is different from a threshold voltage of the third transistor, and a threshold voltage of the second transistor is different from a threshold voltage of the fourth transistor. The plurality of first signal output circuits include a first signal output circuit in which a threshold voltage of the first transistor is higher than the power supply voltage, the first transistor and the second transistor are N-type transistors whose gates are connected to a signal line that supplies the first voltage, The plurality of second signal output circuits include a second signal output circuit in which a threshold voltage of the fourth transistor is higher than the power supply voltage, and the third transistor and the fourth transistor are N-type transistors whose gates are connected to a signal line providing the first voltage.

12. The semiconductor device according to claim 11, characterized in that The semiconductor device includes an N-type transistor connected in a diode manner between a signal line providing the first voltage and a signal line providing a third voltage. The first transistor and the second transistor are connected in series between a signal line that provides the third voltage and a signal line that provides the second voltage. The third transistor and the fourth transistor are connected in series between a signal line that supplies the third voltage and a signal line that supplies the second voltage.

13. The semiconductor device according to claim 11, characterized in that The plurality of first signal output circuits further include a first signal output circuit in which a threshold voltage of the first transistor is lower than a value obtained by subtracting the first voltage from the second voltage, and the first transistor and the second transistor are P-type transistors whose gates are connected to a signal line that supplies the second voltage. The multiple second signal output circuits also include the following second signal output circuit: in this second signal output circuit, the threshold voltage of the fourth transistor is lower than the value obtained by subtracting the first voltage from the second voltage, and the third transistor and the fourth transistor are P-type transistors whose gates are connected to the signal line providing the second voltage.

14. The semiconductor device according to any one of claims 11 to 13, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor and the second transistor are connected in the form of diodes, respectively. The plurality of second signal output circuits further include a second signal output circuit in which the third transistor and the fourth transistor are respectively connected in a diode manner.

15. The semiconductor device according to any one of claims 11 to 13, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor is a depletion type transistor and the second transistor is an enhancement type transistor. The plurality of second signal output circuits further include a second signal output circuit in which the third transistor is an enhancement type and the fourth transistor is a depletion type.

16. The semiconductor device according to any one of claims 11 to 13, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor is a high withstand voltage transistor, the second transistor is a low withstand voltage transistor having a withstand voltage lower than that of the first transistor, The plurality of second signal output circuits further include a second signal output circuit in which the third transistor is the low withstand voltage transistor and the fourth transistor is the high withstand voltage transistor.

17. A semiconductor device, characterized in that: The semiconductor device has: a plurality of first signal output circuits, each having a first transistor and a second transistor, and outputting a voltage at a connection point between the first transistor and the second transistor, wherein the first transistor and the second transistor are connected in series between a signal line that supplies a first voltage and a signal line that supplies a second voltage that is lower than the first voltage, and a predetermined voltage is supplied to each gate; a plurality of second signal output circuits, comprising a third transistor and a fourth transistor, which output a voltage at a connection point between the third transistor and the fourth transistor, the third transistor and the fourth transistor being connected in series between a signal line providing the first voltage and a signal line providing the second voltage, and having respective gates provided with a predetermined voltage, the third transistor having the same layout as the first transistor but different characteristics, and the fourth transistor having the same layout as the second transistor but different characteristics; and A logic processing circuit that performs logic processing, The logic processing circuit is connected to the output of the first signal output circuit and the output of the second signal output circuit, and uses the output of the connected signal output circuit to perform a part or all of the logic processing. The first voltage is a power supply voltage, The second voltage is a reference voltage, The first transistor and the third transistor are connected to a signal line that provides the first voltage, a threshold voltage of the first transistor is different from a threshold voltage of the third transistor, and a threshold voltage of the second transistor is different from a threshold voltage of the fourth transistor. The plurality of first signal output circuits include a first signal output circuit in which a threshold voltage of the first transistor is lower than a value obtained by subtracting the first voltage from the second voltage, and the first transistor and the second transistor are P-type transistors whose gates are connected to a signal line that supplies the second voltage. The multiple second signal output circuits include the following second signal output circuit: in this second signal output circuit, the threshold voltage of the fourth transistor is lower than the value obtained by subtracting the first voltage from the second voltage, and the third transistor and the fourth transistor are P-type transistors whose gates are connected to the signal line providing the second voltage.

18. The semiconductor device according to claim 17, wherein: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor and the second transistor are connected in the form of diodes, respectively. The plurality of second signal output circuits further include a second signal output circuit in which the third transistor and the fourth transistor are respectively connected in a diode manner.

19. The semiconductor device according to claim 17 or 18, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor is a depletion type transistor and the second transistor is an enhancement type transistor. The plurality of second signal output circuits further include a second signal output circuit in which the third transistor is an enhancement type and the fourth transistor is a depletion type.

20. The semiconductor device according to claim 17 or 18, characterized in that: The plurality of first signal output circuits further include a first signal output circuit in which the first transistor is a high withstand voltage transistor, the second transistor is a low withstand voltage transistor having a withstand voltage lower than that of the first transistor, The plurality of second signal output circuits further include a second signal output circuit in which the third transistor is the low withstand voltage transistor and the fourth transistor is the high withstand voltage transistor.

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