Computer system and error detection method thereof

Abstract

The present invention provides a computer system and a debugging method thereof. The computer system includes a circuit board, a memory, a circuit board image, and a processor. The circuit board includes a plurality of connection interfaces for electrically coupling a plurality of hardware devices. The memory stores a basic input / output system program. The basic input / output system program includes a power-on self-detection program. When the computer system is turned on, the processor loads the basic input / output system to perform the power-on program, and reads and executes the power-on self-detection program to detect the plurality of hardware devices electrically coupled to the plurality of connection interfaces. When any hardware device is detected to be abnormal, the processor displays the circuit board image through a display and displays a marking pattern on the circuit board image at a position corresponding to the connection interface image of the abnormal hardware device.

Description

Technical Field

[0001] The present invention relates to a computer error detection technology, and in particular to a computer system and an error detection method thereof for displaying the hardware detection result of the computer system. Background Art

[0002] Whether it is a client computer system or a server computer system, when the computer system is started, the basic input and output system generally executes a boot self-test program to self-diagnose the status of each connection interface and whether the hardware components connected to each connection interface are functioning normally, or starts a debugging program under the intervention of a technician or remote monitoring (for example, through the RAS function in the BMC Web interface) to perform the above diagnostic operations. Traditionally, the debugging results will be displayed on the screen or the debugging code will be presented in a setting or through a display or light-emitting element, so that the technician can visually determine or look up a table to determine which connection interface or hardware device has an error and what kind of error problem may occur. However, for ordinary users who are not familiar with the computer hardware architecture and do not understand the meaning of the debugging code, they cannot easily understand which connection interface or hardware device has an error problem. Therefore, they cannot solve the problem by themselves, and they cannot communicate smoothly with the technicians and report which connection interface or hardware device has an error problem. Therefore, the debugging display method of the traditional computer system makes the entire diagnosis and repair work more time-consuming and cannot be handled and solved in time. In view of this, the present invention proposes a solution to solve the above problems. Summary of the invention

[0003] The invention provides a computer system and an error detection method thereof, which can provide real-time device abnormality information through graphical error detection results.

[0004] The computer system of the present invention includes a circuit board, a memory, a circuit board image and a processor. The circuit board includes a plurality of connection interfaces for electrically coupling a plurality of hardware devices. The memory is mounted on the circuit board. The memory stores a basic input / output system program for executing a boot program. The basic input / output system program includes a boot self-detection program. The circuit board image is stored in the memory or in any memory on the circuit board. The circuit layout of the circuit board image corresponds to the circuit layout of the circuit board. The processor is used to load the basic input / output system to perform the boot program when the computer system is turned on, and to read and execute the boot self-detection program to detect the plurality of hardware devices electrically coupled to the plurality of connection interfaces. When any hardware device is detected to be abnormal, the processor displays the circuit board image through the display and displays a marking pattern at the position of the connection interface image of the abnormal hardware device on the circuit board image.

[0005] The computer system debugging method of the present invention includes the following steps: booting up and executing a basic input / output system program to perform a booting procedure; executing a booting self-detection program to detect multiple hardware devices electrically coupled to multiple connection interfaces; when any hardware device is detected to be abnormal, displaying a circuit board image corresponding to the circuit layout of the circuit board on a display; and displaying a marking pattern at a position on the circuit board image corresponding to the connection interface image of the abnormal hardware device.

[0006] Based on the above, the computer system and the debugging method thereof of the present invention can automatically detect whether a plurality of hardware devices electrically coupled to a plurality of connection interfaces have device anomalies when the computer system executes a booting procedure, so that the booting procedure is terminated. In addition, the computer system and the hardware device debugging method of the present invention can display a circuit board image marked with the position of the connection interface image corresponding to the hardware device detected to have an abnormality, so as to provide real-time hardware device debugging information.

[0007] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention.

[0009] Figure 2 is a schematic diagram of a circuit board image according to an embodiment of the present invention.

[0010] Figure 3 According to the present invention Figure 2 A schematic diagram of an image of a circuit board with locations of hardware devices detected to be abnormal marked according to an embodiment.

[0011] Figure 4 is an operation flow chart of a computer system according to an embodiment of the present invention.

[0012] Figure 5 It is a flowchart of the basic steps of a hardware device debugging method according to an embodiment of the present invention.

[0013] Description of reference numerals:

[0014] 100: Computer Systems

[0015] 110: Circuit board

[0016] 120: Processor

[0017] 130: Memory

[0018] 131: Basic Input and Output System Programs

[0019] 1311: Power-on self-test procedure

[0020] 132, 200: Circuit board image

[0021] 140_1, 140_2 to 140_N: Connection interface

[0022] 150: Display

[0023] 241_1, 241_2, 241_3, 241_4: PCIe connection interface image

[0024] 242_1, 242_2, 242_3, 242_4, 242_5, 242_6, 242_7, 242_8, 243_1, 243_2, 243_3, 243_4, 243_5, 243_6, 243_7, 243_8: DIMM connection interface image

[0025] 244_1, 244_2: CPU socket images

[0026] 245_1, 245_2: USB connection interface image

[0027] 246: LAN connection interface image

[0028] 247: VGA connection interface image

[0029] 301, 302, 303: Box Icon

[0030] S410, S420, S430, S435, S440, S450, S460, S470, S480, S490, S510, S520, S530, S540: Steps DETAILED DESCRIPTION

[0031] In order to make the content of the present invention more understandable, multiple embodiments are provided below to illustrate the present invention, but the present invention is not limited to the multiple embodiments illustrated. Appropriate combinations are also allowed between the embodiments. In addition, wherever possible, the elements / components / steps with the same reference numerals in the drawings and embodiments represent the same or similar parts.

[0032] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention. Figure 1The computer system 100 includes a circuit board 110, a processor 120 and a display 150, and the circuit board 110 is electrically coupled to the processor 120 and the display 150. The circuit board 110, for example, may be a motherboard, and includes a memory 130 and a plurality of connection interfaces 140_1, 140_2 to 140_N. N is an integer greater than zero. The memory 130 may be a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (Flash ROM), etc. The memory 130 may be used to store a basic input / output system (BIOS) program 131 and a circuit board image 132. In the present embodiment, the circuit layout of the circuit board image 132 corresponds to the circuit layout of the circuit board 110. However, in one embodiment, the circuit board image 132 may also be stored in any memory on the circuit board 110, not limited to the memory 130.

[0033] In the present embodiment, the BIOS program 131 includes a Power-On Self-Test (POST) program 1331. It should be noted that the BIOS program 131 is only a general term here, and it can generally refer to any firmware that is first loaded and initialized and tests hardware devices and components before the operating system is started when the computer is started, such as the Unified Extensible Firmware Interface (UEFI). In the present embodiment, the circuit board 110 connection interfaces 140_1, 140_2~140_N can refer to various input and output ports (I / O Ports) or buses (Bus), which can be used to couple hardware devices or hardware components (hereinafter referred to as hardware devices) respectively. For example, the connection interface 140_1 is electrically coupled to the display 150.

[0034] In this embodiment, when the computer system 100 is booted, the BIOS program 131 will be loaded by the processor 120 and the boot program will be executed. The processor 120 will read and execute the boot self-test program 1311 in the BIOS program 131 to detect whether the connection interfaces 140_1, 140_2 to 140_N and the multiple hardware devices electrically coupled to the connection interfaces 140_1, 140_2 to 140_N are abnormal. The abnormality may refer to a hardware device that cannot operate normally due to some reason. In this embodiment, the connection interfaces 140_1, 140_2~140_N may include, for example, a Peripheral Component Interconnect Express (PCIe) connection interface, a Dual In-line Memory Module (DIMM) connection interface, a Video Graphics Array (VGA) connection interface, a Local Area Network (LAN) connection interface, a Universal Serial Bus (USB) connection interface, and a CPU socket, etc., but the present invention is not limited thereto.

[0035] In this embodiment, when at least one of the various types of multiple hardware devices electrically coupled to the connection interfaces 140_1, 140_2 to 140_N is abnormal and causes the boot process to hang out, the display 150 may display a debugging result interface having a circuit board image 132, and the processor 120 will mark the position of the connection interface image corresponding to the hardware device that has been detected to have an abnormality on the circuit board image 132. In other words, during the process of executing the POST program (or any debugging instruction) of the computer system 100 of this embodiment, if a hardware device is abnormal and causes the boot process to hang out, the computer system 100 will display a graphical debugging result through the display 150 to visually inform the user of the relevant information about which hardware device cannot run normally. In other words, the user can view the marking result of the connection interface image corresponding to the hardware device that has been detected to have an abnormality on the circuit board image 132 through the display 150, so that the user can quickly eliminate the abnormality of the device.

[0036] However, in one embodiment, if a hardware device has an abnormality but does not cause the boot process to be terminated, the computer system 100 can continue to execute the boot process, and the graphical debugging results can be not automatically displayed during the boot self-test process. In another embodiment, the graphical debugging results can also be automatically displayed during the boot self-test process. Or in another embodiment, during the boot self-test process, the computer system 100 can display the graphical debugging results based on the user's specific operation (such as pressing a specific function key to enter the basic input and output setting interface). In this regard, since the boot self-test program 1311 will record the information of the device abnormality, the user can also obtain the information of the device abnormality on other operation interfaces in the subsequent boot process. For example, in some server-type computer systems 100, regardless of whether a hardware device has an abnormality that causes the boot process to be terminated, the user can also remotely view the graphical debugging results by entering a specific management web page interface (such as the baseboard management controller web page (Baseboard Management Controller Web, BMCWeb)).

[0037] Figure 2 is a schematic diagram of a circuit board image according to an embodiment of the present invention. Figure 3 According to the present invention Figure 2 A schematic diagram of a circuit board image with a location of a hardware device detected to have an abnormality marked in an embodiment. Figure 1 as well as Figure 2 During the above-mentioned debugging process or detection operation, the display 150 may display the following Figure 2 . In the present embodiment, the circuit board image 200 includes PCIe connection interface images 241_1 to 241_4, DIMM connection interface images 242_1 to 242_8, 243_1 to 243_8, CPU socket images 244_1, 244_2, USB connection interface images 245_1, 245_2, LAN connection interface image 246, and VGA connection interface image 247. In the present embodiment, the circuit board image 200 may be pre-stored in the memory 130 or in any form of memory on the circuit board 110 (e.g., flash memory, solid state drive, hard disk, etc.), and may be matched with the circuit board 110 actually installed in the computer system 100. The matching may be that the circuit layout of the circuit board image 200 is exactly the same or similar to that of the circuit board 110, or that the circuit board image 200 is only a schematic diagram of the circuit layout of the circuit board 110. In the present embodiment, when the power-on self-test program 200 detects that a hardware device is abnormal, the display 150 may display a display having the following characteristics: Figure 2 The debugging interface of the circuit board image 200 is shown.

[0038] Next, refer to Figure 1 as well as Figure 3 , the processor 120 may mark the position of the connection interface image corresponding to the hardware device detected to be abnormal on the circuit board image 200. Specifically, assuming that the hardware devices corresponding to the PCIe connection interface image 241_2, the USB connection interface image 245_1, and the DIMM connection interface image 243_5 are detected to be abnormal, the basic input and output system program 131 may obtain the status code (Status code) and the connection interface number corresponding to the hardware device detected to be abnormal, and the basic input and output system program 131 may read the lookup table to obtain the corresponding multiple coordinate parameters (coordinate X and coordinate Y) as shown in the following Table 1. In this regard, the processor 120 may mark the position of the PCIe connection interface image 241_2, the USB connection interface image 245_1, and the DIMM connection interface image 243_5 corresponding to the hardware device detected to be abnormal on the circuit board image 200 according to the multiple coordinate parameters. Among them, the number of the status code, the number of the connection interface number, and the correspondence between the status code and the connection interface number in Table 1 are only hypothetical examples.

[0039] Status Code Connection interface number Coordinate X Coordinate Y 0x15 DIMM2-5 300 0 0x92 PCIe Slot2 50 50 0x9A USB2 250 200

[0040] Table 1

[0041] Specifically, the processor 120 can execute the C language code (or algorithm) recorded in the basic input and output system program 131 to display multiple marking patterns on the circuit board image 200 according to the multiple coordinate parameters such as the above Table 1. The multiple coordinate parameters are, for example, (300, 0), (50, 50) and (250, 200), and the multiple coordinate parameters respectively represent the image starting points of the corresponding connection interface images, so that the processor 120 can deduce the relevant coordinate data corresponding to the entirety or image frame of each connection interface image based on the multiple coordinate parameters to draw the marking pattern. For those skilled in the art, one of the specific methods of displaying the marking pattern according to the coordinate parameters using the above C language code can refer to the method of displaying a frame text on the display 150 during the boot operation of a general computer system to guide the user whether to press the corresponding keyboard key, such as displaying the ESC frame text (if the user presses the ESC key accordingly, the "Setup Menu" can be entered) or the F12 frame text (if the user presses the F12 key accordingly, the "Boot Option" can be entered). However, in other embodiments of the present invention, the memory 130 may also pre-store marking patterns of various shapes and sizes, and the position where each marking pattern is to be displayed is determined according to the aforementioned coordinate parameters.

[0042] In this embodiment, the plurality of marking patterns may be as follows: Figure 3 The multiple frame icons 301-303 are shown, and the frame icons 301-303 are located on the PCIe connection interface image 241_2, the USB connection interface image 245_1, and the DIMM connection interface image 243_5 corresponding to the PCIe device, USB device, and memory module detected to be abnormal in the circuit board image 200. Therefore, the user can easily recognize the hardware device detected to be abnormal corresponding to each of the PCIe connection interface image 241_2, the USB connection interface image 245_1, and the DIMM connection interface image 243_5 in real time through the display 150, so that the user can quickly eliminate the abnormalities of these devices.

[0043] It should be noted that, in one embodiment, the above-mentioned status code can be formulated by the manufacturer of the basic input and output system program 131, so the present invention is not limited thereto. In addition, the above-mentioned connection interface number can be determined by the circuit designer of the circuit board 110 according to the socket and the root port to determine the device name, and the connection interface number is assigned to the corresponding bus number according to the corresponding configuration PCIe channel (Lane), so the present invention is not limited thereto.

[0044] Regarding how the power-on self-test program 1311 detects device abnormalities, for example, multiple hardware devices electrically coupled to the circuit board 110 include multiple memory modules, and the multiple memory modules can be connected to multiple DIMM connection interfaces (for example, corresponding to DIMM connection interface images 242_1 to 242_8, 243_1 to 243_8). In one embodiment, the processor 120 can activate the reliability, availability and serviceability (RAS) function through the integrated memory controller (IMC) to scan the multiple memory modules and determine whether at least one of the multiple memory modules has error information or error log. In this regard, the processor 120 can determine whether at least one of the multiple memory modules has an abnormality based on the memory location corresponding to the error information or error log, so that the processor 120 can obtain the connection interface number and status code corresponding to the abnormal memory module. The memory connection interface location can refer to a socket, a channel or a DIMM connection interface.

[0045] For another example, the plurality of hardware devices electrically coupled to the circuit board 110 include a plurality of PCIe devices, and the plurality of PCIe devices may be connected to the PCIe connection interface image (e.g., corresponding to the PCIe connection interface images 241_1 to 241_4). In one embodiment, since each PCIe device may have an Advanced Error Reporting Extended Capability function, the processor 120 may read the Advanced Error Reporting (AER) of each of the plurality of PCIe devices to determine whether an abnormal PCIe device is detected by determining whether an error status is included in each of the Advanced Error Reports.

[0046] Figure 4 is an operation flow chart of a computer system according to an embodiment of the present invention. Figure 1 as well as Figure 4 The operation process of this embodiment can be applied to at least Figure 1 The computer system 100. In step S410, the computer system 100 is turned on. In step S420, the computer system 100 executes the basic input and output system program 131 to perform the booting procedure. In step S430, the processor 120 reads and executes the power-on self-test program 1311 recorded in the basic input and output system program 131 to perform the power-on self-test program. In step S435, the processor 120 reads the memory 130 so that the display 150 displays the circuit board image 132. In step S440, the power-on self-test program 1311 detects whether any hardware device electrically coupled to the connection interface 140_1, 140_2 ~ 140_N has an abnormality. If no abnormality occurs, the process proceeds to step S460. In step S460, the computer system 100 continues the booting procedure and enters the operating system. If an abnormality occurs, the process proceeds to step S450. In step S450, the processor 120 further determines whether a specific operation occurs. If a specific operation occurs, the process proceeds to step S470. In step S470, the display 150 displays the circuit board image 132 with an abnormality mark pattern (such as the frame icon described above), and after the specific operation is completed, the process proceeds to step S460. In step S460, the computer system 100 continues the boot process and enters the operating system.

[0047] In one embodiment, if the circuit board 110 of this embodiment is a circuit board type of a personal computer, the above-mentioned specific operation may be that the basic input and output system program 131 displays a setup menu (Setup Menu) on the display 150 during the power-on self-test process and is selected and started by the user. In another embodiment, if the circuit board 110 is a server circuit board, the above-mentioned specific operation may be to enter the management web page interface of the baseboard management controller (Baseboard Management Controller, BMC). In other words, the user can enter the management web page interface of the server through a browser to execute the hardware management and monitoring functions of the baseboard management controller to obtain relevant hardware device abnormality information found during the power-on self-test process.

[0048] In step S450, when the processor 120 determines that there is no specific operation, the process proceeds to step S480. In step S480, the processor 120 further determines whether the boot process is terminated due to an abnormality in the hardware device. If not, the process proceeds to step S470, and the display 150 displays the circuit board image 132 with an abnormal mark pattern, and after the specific operation is completed, the process proceeds to step S460 so that the computer system 100 continues the boot process and enters the operating system. If yes, the process proceeds to step S490. In step S490, the display 150 only displays the circuit board image with an abnormal mark pattern but cannot enter the operating system because the boot process has been forced to terminate.

[0049] In other embodiments of the present invention, the above step S435 may not be displayed first, but may only appear together with the abnormal mark pattern in step S470 and step S490.

[0050] In another embodiment of the present invention, it is also possible not to perform the determination of step S450 and step S480, but to enter step S470 or step S490 to display the circuit board image with the abnormal marking pattern only when it is determined in step S440 that the hardware device is abnormal. In other embodiments of the present invention, step S450 and step S480 can only be selectively selected. In other embodiments of the invention, the order of step S450 and step S480 is not limited, and can be as follows Figure 4 Generally, step S450 is performed first and then step S480, but the steps can be reversed and step S480 is performed first and then step S450.

[0051] In addition, for the details of the relevant equipment, implementation methods and technical features of the computer system 100 of this embodiment, please refer to the above Figures 1 to 3 The description of the embodiments provides sufficient inspiration, suggestions and implementation instructions, so they are not repeated here.

[0052] Figure 5 is a flowchart of the basic steps of a hardware device debugging method according to an embodiment of the present invention. Figure 1 as well as Figure 5 The operation process of this embodiment can be applied to at least Figure 1 The computer system 100 is configured to enable the computer system 100 to execute steps S510 to S540. In step S510, the computer system 100 is turned on, and the processor 120 executes the basic input and output system program 131 to perform the boot procedure. In step S520, the processor 120 reads and executes the power-on self-test program 1311 to detect multiple hardware devices electrically coupled to the multiple connection interfaces 140_1, 140_2 to 140_N. In step S530, when the processor 120 detects that any hardware device is abnormal, the processor 120 reads the circuit board image 132, and the display 150 displays the circuit board image 132 corresponding to the circuit layout of the circuit board 110. In step S540, the display 150 displays a marking pattern at a position on the circuit board image 132 corresponding to the connection interface image of the abnormal hardware device. Therefore, the operation process of this embodiment enables the computer system 100 to display information about hardware device abnormalities in a graphical manner.

[0053] In addition, for the details of the relevant equipment, implementation methods and technical features of the computer system 100 of this embodiment, please refer to the above Figures 1 to 4 The description of the embodiments provides sufficient inspiration, suggestions and implementation instructions, so they are not repeated here.

[0054] In summary, the computer system and hardware device debugging method of the present invention can automatically detect whether multiple hardware devices electrically coupled to multiple connection interfaces have device anomalies, and can display in real time during the self-detection program of the computer system executing the boot program a circuit board image marked with the position of the connection interface image corresponding to the hardware device detected to have an abnormality, so as to provide real-time and visual hardware device debugging information. In addition, the computer system and hardware device debugging method of the present invention can also display the above-mentioned graphical debugging information through the user's selection on the basic input and output system setting menu or the web page interface of the baseboard management controller. Therefore, the computer system and hardware device debugging method of the present invention can provide real-time and user-friendly graphical device anomaly information, so as to help users quickly eliminate device anomaly problems.

[0055] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A computer system comprising: A circuit board comprising a plurality of connection interfaces for electrically coupling a plurality of hardware devices; A memory, mounted on the circuit board, storing a basic input / output system program for executing a booting program, wherein the basic input / output system program includes a booting self-test program; a circuit board image, stored in the memory or any memory on the circuit board, wherein the circuit layout of the circuit board image corresponds to the circuit layout of the circuit board, and the circuit board image includes a plurality of interface images corresponding to a plurality of connection interfaces of the circuit board, wherein each interface image corresponds to a connection interface, and each connection interface is associated with a coordinate parameter of the circuit board image; as well as A processor is used to load the basic input and output system to perform a boot program when the computer system is turned on, and read and execute the boot self-test program to detect the hardware devices electrically coupled to the connection interfaces. When any hardware device is detected to be abnormal, the circuit board image is displayed through a display, and a mark pattern is displayed on an interface image of the connection interface corresponding to the abnormal hardware device on the circuit board image according to the coordinate parameter position associated with the connection interface. The marking pattern is a frame-shaped icon.

2. The computer system of claim 1, wherein when any of the hardware devices is detected to be abnormal, the basic input and output system obtains a status code, a connection interface number and the coordinate parameter corresponding to the abnormal hardware device, The processor displays the marking pattern at a position on the circuit board image corresponding to the interface image of the abnormal hardware device according to the coordinate parameter.

3. The computer system as claimed in claim 2, wherein the processor executes a C language code recorded in the basic input and output system to display the marking pattern on the circuit board image according to the coordinate parameter.

4. The computer system as claimed in claim 1, wherein the hardware devices include a plurality of IPS devices, and the processor reads an advanced error report of each of the IPS devices to determine the hardware device that has an abnormality according to an error status code of the advanced error report.

5. The computer system as claimed in claim 1, wherein the hardware devices include a plurality of memory modules, and the processor scans the memory modules via a memory controller to determine the abnormal hardware device according to at least one of the memory modules having an error message or an error record.

6. The computer system as claimed in claim 1, wherein when a specific operation is executed, the display displays the circuit board image, and the processor displays the marking pattern at a position on the circuit board image corresponding to the interface image of the abnormal hardware device based on a detection result of the power-on self-test program.

7. The computer system as claimed in claim 6, wherein the specific operation is entering a setting menu of the basic input and output system program.

8. The computer system as claimed in claim 6, wherein the circuit board is a server circuit board, and the specific operation is entering a management web page interface of a baseboard management controller.

9. A computer system as described in claim 1, wherein when the computer system is terminated during the boot process, the display displays the circuit board image, and the processor displays the marking pattern at a position on the circuit board image corresponding to the interface image of the abnormal hardware device based on a detection result of the boot self-test program.

10. A computer system debugging method, the computer system having a circuit board including a plurality of connection interfaces, the debugging method comprising: Booting up and executing a basic input and output system program to perform a booting procedure; Reading and executing a power-on self-test program to detect a plurality of hardware devices electrically coupled to the plurality of connection interfaces; When any hardware device is detected to be abnormal, a circuit board image corresponding to a circuit layout of the circuit board is displayed on a display, and the circuit board image includes a plurality of interface images corresponding to a plurality of connection interfaces of the circuit board, wherein each interface image corresponds to a connection interface, and a coordinate parameter corresponding to the hardware device detected to be abnormal is obtained; as well as A marking pattern is displayed on an interface image corresponding to the connection interface to which the abnormal hardware device is connected on the circuit board image according to the position of the coordinate parameter, The marking pattern is a frame-shaped icon.

11. The debugging method of claim 10, when any hardware device is detected to be abnormal, the debugging method further comprises: Obtaining a status code and a connection interface number corresponding to the hardware device that has been detected to be abnormal; The coordinate parameter is obtained according to the status code and the connection interface number.

12. The debugging method as claimed in claim 11, wherein the step of marking a position corresponding to the interface image of the abnormal hardware device on the circuit board image and displaying the marking pattern comprises: A C language code recorded in the basic input and output system is executed to display the marking pattern on the circuit board image according to the coordinate parameter.

13. The debugging method of claim 10, wherein the hardware devices include a plurality of quick peripheral interconnect standard devices, and the step of executing the power-on self-test program to detect the hardware devices of the circuit board comprises: An advanced error report of each of the quick peripheral interconnect standard devices is read to determine the hardware device that has detected an abnormality according to an error status code of the advanced error report.

14. The debugging method of claim 10, wherein the hardware devices include a plurality of memory modules, and the step of executing the power-on self-test program to detect the hardware devices of the circuit board comprises: The memory modules are scanned by a memory controller to determine the abnormal hardware device according to an error message or an error record of at least one of the memory modules.

15. The error detection method according to claim 10, further comprising: Determine whether a specific operation is performed; as well as When it is determined that the specific operation is executed, the circuit board image is displayed, and according to a detection result of the power-on self-test program, the marking pattern is displayed at a position corresponding to the abnormal hardware device on the circuit board image.

16. The debugging method of claim 15, wherein the specific operation is entering a setting menu of the basic input and output system program.

17. The debugging method of claim 15, wherein the circuit board is a server circuit board, and the specific operation interface is a management web page interface for entering a baseboard management controller.

18. The debugging method of claim 10, wherein when the boot process is terminated, the display displays the circuit board image, and a processor displays the marking pattern at a position on the circuit board image corresponding to the interface image of the abnormal hardware device based on a detection result of the boot self-test process.

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