Semiconductor device and equipment for manufacturing semiconductor device

Abstract

A semiconductor device and an apparatus for manufacturing the semiconductor device are provided. The semiconductor device comprises: gate electrodes and interlayer insulating layers alternately stacked on a substrate; a channel structure, the channel structures being spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate; and a first separation region, the first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode comprises a first conductive layer and a second conductive layer, the first conductive layer being arranged between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region of each gate electrode located between the outermost channel structure adjacent to the first separation region and the first separation region, the thickness of the first conductive layer decreases toward the first separation region, and the thickness of the second conductive layer increases toward the first separation region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0032477 filed on March 21, 2019, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2019-0085709 filed on July 16, 2019, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device and an apparatus for manufacturing the semiconductor device. Background Art

[0004] Semiconductor devices have been reduced in size and are designed to store large amounts of data. Therefore, it is necessary to increase the integration density of transistors included in semiconductor devices. For higher integration density of semiconductor devices, vertical transistor structures have been developed to replace planar transistor structures. Summary of the invention

[0005] Example embodiments provide a semiconductor device having improved reliability and an apparatus for manufacturing the semiconductor device.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes: a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked on a substrate; a plurality of channel structures, the plurality of channel structures being spaced apart from each other in a first direction and extending vertically through the plurality of gate electrodes and the plurality of interlayer insulating layers to the substrate; and a first separation region, the first separation region extending vertically through the plurality of gate electrodes and the plurality of interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer being disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region of each gate electrode located between the outermost channel structure adjacent to the first separation region and the first separation region, the thickness of the first conductive layer decreases toward the first separation region, and the thickness of the second conductive layer increases toward the first separation region.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes: a plurality of gate electrodes vertically stacked to be spaced apart from each other on a substrate; a plurality of channel structures vertically extending through the plurality of gate electrodes to the substrate; and a separation region extending through the plurality of gate electrodes. Each gate electrode includes a first conductive layer having a lateral recessed region adjacent to an outermost channel structure and a second conductive layer disposed in the lateral recessed region, the outermost channel structure being adjacent to the separation region. The width of the lateral recessed region decreases toward the outermost channel structure.

[0008] According to an exemplary embodiment of the present invention, an apparatus for manufacturing a semiconductor device includes: a gas supply unit, the gas supply unit including a first deposition gas source, a second deposition gas source and an etching gas source; a process chamber, the process chamber being connected to the gas supply unit; a gas injection unit, the gas injection unit being arranged in the process chamber and including a gas supply channel connected to the first deposition gas source, the second deposition gas source and the etching gas source; and a controller, the controller being configured to control the gas supply unit so that a first deposition process, an etching process and a second deposition process are sequentially performed, in which in the first deposition process, a first process gas of the first deposition gas source and a second process gas of the second deposition gas source are alternately supplied to the process chamber via the gas injection unit, in which in the etching process, a third process gas of the etching gas source is supplied to the process chamber via the gas injection unit, and in the third deposition process, the first process gas of the first deposition gas source and the second process gas of the second deposition gas source are alternately supplied to the process chamber via the gas injection unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic block diagram of a semiconductor device according to an example embodiment;

[0011] Figure 2 is an equivalent circuit diagram of a cell array of a semiconductor device according to example embodiments;

[0012] Figure 3 is a schematic top view of a semiconductor device according to an example embodiment;

[0013] Figure 4 is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0014] FIG. 5A to FIG. 5CAccording to an example embodiment Figure 4 A partial enlarged cross-sectional view of regions A, B and C;

[0015] Fig. 6A and Figure 6B is a partially enlarged cross-sectional view of a semiconductor device according to an example embodiment;

[0016] Figure 7 and Figure 8 is a partially enlarged cross-sectional view of a semiconductor device according to an example embodiment;

[0017] Fig. 9 is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0018] Fig.10 is a flowchart illustrating a method of manufacturing a semiconductor device according to an example embodiment;

[0019] FIG. 11A to FIG. 11I are cross-sectional views illustrating steps of a method of manufacturing a semiconductor device according to an example embodiment;

[0020] Fig.12 is a process flow chart illustrating a method of manufacturing a semiconductor device according to an example embodiment;

[0021] Fig.13 is a schematic diagram of a manufacturing apparatus for manufacturing a semiconductor device according to an example embodiment; and

[0022] Fig.14A and Fig. 14B is a schematic diagram of a manufacturing apparatus for manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, the inventive concept will be described with reference to the accompanying drawings.

[0024] Figure 1 is a schematic block diagram of a semiconductor device according to example embodiments.

[0025] Reference Figure 1 , the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30. The peripheral circuit 30 may include a row decoder 32, a page buffer 34, an input and output buffer 35, a control logic 36, and a voltage generator 37.

[0026] The memory cell array 20 may include a plurality of memory blocks, and each memory block may include a plurality of memory cells. The plurality of memory cells may be connected to the row decoder 32 through the string selection line SSL, the word line WL, and the ground selection line GSL, and may be connected to the page buffer 34 through the bit line BL. In an example embodiment, a plurality of memory cells arranged in the same row may be connected to the same word line WL, and a plurality of memory cells arranged in the same column may be connected to the same bit line BL.

[0027] The row decoder 32 may decode the input address ADDR and may generate and transmit a driving signal of the word line WL. The row decoder 32 may provide the word line voltage generated from the voltage generator 37 to the selected word line WL and the unselected word line WL in response to the control of the control logic 36.

[0028] The page buffer 34 may be connected to the memory cell array 20 through the bit line BL, and may read information stored in the memory cell. The page buffer 34 may temporarily store data to be stored in the memory cell according to the operation mode, or may sense data stored in the memory cell. The page buffer 34 may include a column decoder and a sense amplifier. The column decoder may selectively activate the bit line BL of the memory cell array 20, the sense amplifier may sense the voltage of the bit line BL selected by the column decoder, and may read the data stored in the selected memory cell during a read operation.

[0029] When performing a program operation (which may be referred to as a write operation), the input and output buffer 35 may receive data DATA and may transmit the data to the page buffer 34, and in a read operation, the input and output buffer 35 may output the data DATA received from the page buffer 34 to an external entity. The input and output buffer 35 may transmit an input address or an input command to the control logic 36.

[0030] The control logic 36 may control the operation of the row decoder 32 and the operation of the page buffer 34. The control logic 36 may receive a control signal and an external voltage transmitted from an external entity and may operate according to the received control signal. The control logic 36 may control a read operation, a write operation, and / or an erase operation in response to the control signal.

[0031] The voltage generator 37 may use an external voltage to generate voltages required for internal operations, such as a program voltage, a read operation voltage, an erase operation voltage, etc. The voltage generated by the voltage generator 37 may be transmitted to the memory cell array 20 through the row decoder 32 .

[0032] Figure 2 is an equivalent circuit diagram of a cell array of a semiconductor device according to example embodiments.

[0033] Reference Figure 2 , the memory cell array 20 may include: a plurality of memory cell strings S, including memory cells MC connected in series to each other; a ground selection transistor GST connected in series to both ends of the memory cell MC; and string selection transistors SST1 and SST2. The plurality of memory cell strings S may be connected in parallel to the bit lines BL0 to BL2. The plurality of memory cell strings S may be connected in common to a common source line CSL. For example, the plurality of memory cell strings S may be arranged between the bit lines BL0 to BL2 and a common source line CSL. In an example embodiment, the plurality of common source lines CSL may be arranged two-dimensionally.

[0034] The memory cells MC connected in series to each other may be controlled by word lines WL0 to WLn for selecting the memory cells MC. Each memory cell MC may include a data storage element. The gate electrodes of the memory cells MC arranged at substantially the same distance from the common source line CSL may be commonly connected to one of the word lines WL0 to WLn to be in an equipotential state. Alternatively, even when the gate electrodes of the memory cells MC are arranged at substantially the same distance from the common source line CSL, the gate electrodes arranged in different rows or columns may be independently controlled.

[0035] The ground selection transistor GST may be controlled by a ground selection line GSL and may be connected to a common source line CSL. The string selection transistors SST1 and SST2 may be controlled by string selection lines SSL1 and SSL2 and may be connected to the bit lines BL0 to BL2. Figure 2 , one ground selection transistor GST and two string selection transistors SST1 and SST2 are shown as being connected to a plurality of memory cells MC connected in series. However, one of the transistors SST1 and SST2 may be respectively connected to a plurality of memory cells MC connected in series, or a plurality of ground selection transistors GST may be respectively connected to a plurality of memory cells MC connected in series. One or more dummy lines DWL or buffer lines may be further provided between the topmost word line WLn among the word lines WL0 to WLn and the string selection lines SSL1 and SSL2. In example embodiments, one or more dummy lines DWL may be provided between the bottommost word line WL0 and the ground selection line GSL.

[0036] When a signal is applied to the string selection transistors SST1 and SST2 via the string selection lines SSL1 and SSL2, the signal applied through the bit lines BL0 to BL2 may be transmitted to the memory cells MC connected in series to perform a read operation and a write operation. In addition, an erase operation may be performed by applying a predetermined erase voltage via the substrate to erase the data recorded in the memory cells MC. In example embodiments, the memory cell array 20 may include at least one of the dummy memory cell strings electrically isolated from the bit lines BL0 to BL2.

[0037] Figure 3 is a schematic top view of a semiconductor device according to example embodiments.

[0038] Figure 4 Shown along Figure 3 A cross-sectional view of a semiconductor device taken along line II' in FIG. Figure 3 and Figure 4 Only the main components of the semiconductor device are shown.

[0039] FIG. 5A to FIG. 5C They are Figure 4 A partial enlarged view of areas A, B and C in FIG.

[0040] Reference Figure 3 and Figure 4 , the semiconductor device 100 may include: a substrate 101; a channel structure CH extending in a direction perpendicular to the upper surface of the substrate 101, wherein a channel layer 140 is disposed in the channel structure CH; a plurality of interlayer insulating layers 120 stacked along the outer sidewalls of the channel structure CH; a plurality of gate electrodes 130 alternately stacked with the interlayer insulating layers 120, wherein each gate electrode 130 includes a first conductive layer 130A and a second conductive layer 130B; and a separation region SR extending through the stacked structure of the interlayer insulating layers 120 and the gate electrodes 130 alternately stacked on the substrate 101. The semiconductor device 100 may further include a gate dielectric layer 145 disposed between the channel layer 140 and the gate electrode 130, an epitaxial layer 107 disposed under the channel layer 140, a channel pad 155 located at the upper end of the channel structure CH, and a source conductive layer 180 and a source insulating layer 185 disposed in each separation region SR.

[0041] In the semiconductor device 100 , a single memory cell string may be configured around each channel layer 140 , and a plurality of memory cell strings may be arranged in rows and columns in an X direction and a Y direction different from the X direction.

[0042] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, etc.

[0043] The channel structures CH may be disposed on the substrate 101 so as to be spaced apart from each other in rows and columns. The channel structures CH may be arranged in the form of a lattice, or may be arranged in a zigzag shape in one direction. The channel structures CH may have a side surface perpendicular to the substrate 101, or may have an inclined side surface that narrows in a direction toward the substrate 101 according to an aspect ratio. Each channel structure CH may include a channel layer 140, a gate dielectric layer 145, a channel pad 155, and an epitaxial layer 107. Each channel structure CH may also include a channel insulating layer 150.

[0044] In the channel structure CH, the channel layer 140 may be arranged in a ring shape to surround the channel insulating layer 150 therein. In some embodiments, the channel layer 140 may be a columnar shape such as a cylindrical shape or a prism shape without the channel insulating layer 150. The channel layer 140 may be connected to the epitaxial layer 107. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material including p-type or n-type impurities. The channel structure CH arranged on a straight line along the X direction may be connected to different bit lines by arranging an upper interconnect structure connected to the channel pad 155. Part of the channel structure CH may be a dummy channel that is not connected to a bit line.

[0045] The gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. The gate dielectric layer 145 may include a tunneling layer 142, a charge storage layer 143, and a blocking layer 144 sequentially stacked from the channel layer 140. The channel layer 140, the tunneling layer 142, and the charge storage layer 143 may extend in the Z direction perpendicular to the substrate 101. The blocking layer 144 may be disposed to surround at least a portion of the gate electrode 130. In this case, the blocking layer 144 may extend between the first conductive layer 130A and each of the two adjacent interlayer insulating layers 120. In some embodiments, the channel layer 140 and the tunneling layer 142 may extend in the Z direction, and the charge storage layer 143 may also be disposed to surround the gate electrode 130 together with the blocking layer 144. In this case, the charge storage layer 143 and the blocking layer 144 may extend between the first conductive layer 130A and each of the two adjacent interlayer insulating layers 120. The relative thicknesses of the layers constituting the gate dielectric layer 145 are not limited to the thicknesses shown in the drawings, but may vary according to example embodiments. Figure 5A , the side surface of the barrier layer 144 is shown to be coplanar with the side surface of the gate electrode 130. However, the shape of the barrier layer 144 is not limited thereto, and may further extend along the interlayer insulating layer 120 toward, for example, the side surface of the interlayer insulating layer 120.

[0046] Electrons in the channel layer 140 may tunnel through the tunnel layer 142 through a Fowler-Nordheim (FN) tunneling mechanism to be stored in the charge storage layer 143. The tunnel layer 142 may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer 143 may be a charge trapping layer and may be formed of silicon nitride. The blocking layer 144 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), high-k dielectrics, or combinations thereof. The term "high-k dielectric" refers to a dielectric having a higher dielectric strength than silicon oxide (SiO 2 ) dielectric material with a high dielectric constant. High-k dielectrics may include, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ), praseodymium oxide (Pr 2 O 3 ) or a combination thereof.

[0047] The epitaxial layer 107 may be disposed on the substrate 101 at the lower portion of the channel structure CH, and may be disposed on the side surface of at least one gate electrode 130. The epitaxial layer 107 may be disposed in a recessed region of the substrate 101. The height of the upper surface of the epitaxial layer 107 may be greater than the height of the upper surface of the lowest gate electrode 130 and less than the height of the lower surface of the upper gate electrode 130 adjacent to the lowest gate electrode 130, but the height of the upper surface of the epitaxial layer 107 is not limited thereto. Even when the aspect ratio of the channel structure CH increases, the channel layer 140 may be stably electrically connected to the substrate 101 through the epitaxial layer 107, and the characteristics of the ground selection transistors GST between the memory cell strings may be consistent. In some embodiments, the epitaxial layer 107 may be omitted. In this case, the channel layer 140 may be directly connected to the substrate 101.

[0048] The channel pad 155 may be disposed over the channel layer 140 in the channel structure CH. The channel pad 155 may be disposed to cover an upper surface of the channel insulating layer 150 and be electrically connected to the channel layer 140. The channel pad 155 may include, for example, doped polysilicon.

[0049] The gate electrode 130 may be arranged to be spaced apart from each other in a direction perpendicular to the substrate 101 along the side surface of each channel structure CH. The gate electrode 130 may include a ground selection electrode 130G, a cell electrode 130M, and a string selection electrode 130S, which respectively constitute the gate electrode of the ground selection transistor, the gate electrode of a plurality of memory cells, and the gate electrode of the string selection transistor. The gate electrode 130 may extend when forming a ground selection line, a word line, and a string selection line. The word line may be connected together in adjacent memory cell strings of predetermined cells arranged in the X and Y directions. The string selection electrodes 130S constituting the string selection line may be spaced apart from each other at regular intervals in the X direction by the upper insulating layer 103. However, the number of string selection electrodes 130S separated by the upper insulating layer 103 is not limited to the number shown in the figure.

[0050] In some embodiments, one or more string selection electrodes 130S and one or more ground selection electrodes 130G may be provided, and they may have the same or different structures as the cell electrodes 130M. Some gate electrodes 130 (e.g., a plurality of gate electrodes 130) adjacent to the string selection electrode 130S or the ground selection electrode 130G may be dummy gate electrodes.

[0051] Reference FIG. 5A to FIG. 5C , each gate electrode 130 may include a first conductive layer 130A adjacent to the interlayer insulating layer 120 and the channel structure CH, and a second conductive layer 130B located on the first conductive layer 130A.

[0052] The first conductive layer 130A may be disposed on the upper and lower surfaces of the interlayer insulating layer 120, and may be disposed on the sidewalls of the channel structure CH. Therefore, the first conductive layer 130A may be disposed to have a lateral recessed region LR toward the channel structure CH. The first conductive layer 130A may be disposed between a portion of the gate dielectric layer 145 and the second conductive layer 130B. For example, the first conductive layer 130A may be disposed between the barrier layer 144 of the gate dielectric layer 145 and the second conductive layer 130B. In this case, the barrier layer 144 may be disposed between the channel layer 140 and the first conductive layer 130 and between each of the two adjacent interlayer insulating layers 120 and the first conductive layer 130.

[0053] The thickness of the first conductive layer 130A on the upper and lower surfaces of the interlayer insulating layer 120 may decrease from the outermost channel structure CH adjacent to the separation region SR to the separation region SR in the X direction. For example, when the region of the gate electrode 130 adjacent to the separation region SR is referred to as the edge region GE, the thickness of the first conductive layer 130A in at least the edge region GE may decrease in the direction toward the separation region SR, as shown in FIG. Figure 5A As shown. Therefore, the width of the lateral recessed region LR in the region adjacent to the separation region SR in the Z direction may be greater than the width in the region adjacent to the channel structure CH in the Z direction. In example embodiments, the width of the lateral recessed region LR may decrease toward the channel structure CH in the x direction. In particular, the edge region GE may include a region between the channel structure CH adjacent to the separation region SR in the x direction and the separation region SR.

[0054] The second conductive layer 130B may be provided to fill the inner side of the first conductive layer 130A between two interlayer insulating layers 120 vertically adjacent to each other (i.e., the lateral recessed region LR). According to the shape of the first conductive layer 130A, the second conductive layer 130B may have a first thickness T1 in a region away from the separation region SR, a second thickness T2 greater than the first thickness T1 in a region adjacent to the separation region SR, and may have a thickness increasing toward the separation region SR. The height of the upper surface of the second conductive layer 130B may increase toward the separation region SR. The increase in thickness of the second conductive layer 130B may be continuous. However, the inventive concept is not limited thereto. In some embodiments, the second conductive layer 130B may have a shape in which the height increases stepwise or gradually stepwise in a stepwise manner in the direction toward the separation region SR.

[0055] For example, the thickness of the first conductive layer 130A may be in the range of about 0.1 nm to about 3 nm, and the thickness of the second conductive layer 130B may be in the range of about 10 nm to about 30 nm on the inner side of the first conductive layer 130A. In an example embodiment, the first conductive layer 130A and the second conductive layer 130B may be substantially symmetrical between two adjacent separation regions SR in the X direction. For example, the topmost gate electrode 130 (e.g., the string selection electrode 130S) may be symmetrical about the upper insulating layer 103, and the gate electrode 130 (e.g., the unit electrode 130M) below the topmost gate electrode 130 may be symmetrical about the extension area of ​​the upper insulating layer 103 in the z direction. In an exemplary embodiment, the upper insulating layer 103 and its extension area in the z direction may be located in the central area between the two adjacent separation regions SR. In this case, the gate electrode 130 including the first conductive layer 130A and the second conductive layer 130B may be symmetrical about the central area of ​​the two adjacent separation regions SR.

[0056] The first conductive layer 130A and the second conductive layer 130B may include the same material or different materials. The first conductive layer 130A and the second conductive layer 130B may include metal materials such as tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), etc. In some embodiments, the first conductive layer 130A and the second conductive layer 130B may include polysilicon or metal silicide materials. In some embodiments, the gate electrode 130 may also include a diffusion barrier layer to protect the channel structure CH during the formation of the gate electrode 130. In this case, the diffusion barrier layer may be provided between the first conductive layer 130A and each of the channel structures CH and between the first conductive layer 130A and each of the two adjacent interlayer insulating layers 120.

[0057] There may be an interface IF between the first conductive layer 130A and the second conductive layer 130B, which can be identified by, for example, a transmission electron microscope (TEM). For example, even when the materials of the first conductive layer 130A and the second conductive layer 130B are the same as each other, the interface IF can be identified due to the discontinuity of the crystal structure (e.g., grain boundary). In example embodiments, the grain boundary between the first conductive layer 130A and the second conductive layer 130B may be continuous or discontinuous. The interface IF between the first conductive layer 130A and the second conductive layer 130B may form an inclined surface. For example, the interface IF between the first conductive layer 130A and the second conductive layer 130B may be inclined relative to the X direction in the edge region GE. The first conductive layer 130A and the second conductive layer 130B are shown as being recessed a predetermined distance from the side surface of the interlayer insulating layer 120 in contact with the separation region SR toward the channel layer 140, and the shapes of the first conductive layer 130A and the second conductive layer 130B are not limited thereto. For example, the first and second conductive layers 130A and 130B may have sidewalls coplanar with the interlayer insulating layer 120 adjacent to the separation region SR.

[0058] like Figure 5B As shown, the first conductive layer 130A and the second conductive layer 130B have substantially the same thickness in the first region farthest from the separation region SR. Therefore, the interface IF may also be a substantially flat surface. For example, the interface IF may be substantially parallel to the X direction. The second conductive layer 130B may have a third thickness T3, and the third thickness T3 may be less than or equal to the first thickness T1. This is because the thickness of the first conductive layer 130A is greater than or equal to the maximum thickness in the edge region GE.

[0059] like Figure 5C As shown, in the second region between the first region and the edge region GE, the first conductive layer 130A and the second conductive layer 130B may have a substantially uniform thickness, or may have a thickness that decreases and increases in the direction toward the edge region GE, respectively. Therefore, the interface IF may also be substantially parallel to the X direction or inclined relative to the X direction. The second conductive layer 130B may have a fourth thickness T4 and a fifth thickness T5 at the opposite end adjacent to the channel structure CH. In some embodiments, the fourth thickness T4 may be substantially the same as or less than the fifth thickness T5. The fourth thickness T4 may be greater than or equal to the third thickness T3, and the fifth thickness T5 may be less than or equal to the first thickness T1. This is because the thickness of the first conductive layer 130A in the second region may be greater than or equal to the maximum thickness in the edge region GE.

[0060] In example embodiments, the thickness of the first conductive layer 130A may gradually decrease from the first region to the edge region GE via the second region along the X direction. Alternatively, the thickness of the first conductive layer 130A in the first region and the second region may be substantially the same as the maximum thickness in the edge region GE, and may have a reduced thickness only in the edge region GE.

[0061] The interlayer insulating layer 120 may be disposed between the gate electrodes 130. Similar to the gate electrode 130, the interlayer insulating layer 120 may be disposed to be spaced apart from each other in the z direction perpendicular to the upper surface of the substrate 101, and may extend in the x direction. The interlayer insulating layer 120 may include an insulating material such as silicon oxide or silicon nitride. The side surface of the interlayer insulating layer 120 may have a structure protruding from the side surface of the gate electrode 130 toward the separation region SR. However, in example embodiments, the side surface of the interlayer insulating layer 120 may be coplanar with the side surface of the gate electrode 130.

[0062] The separation region SR may extend through the gate electrode 130 and the interlayer insulating layer 120 between the channel structures CH in the z direction and may be connected to the substrate 101. A source conductive layer 180 and a source insulating layer 185 may be disposed in the separation region SR. The source conductive layer 180 may have a shape whose width decreases in a direction toward the substrate 101 due to a high aspect ratio, but the shape of the source conductive layer 180 is not limited thereto. The source conductive layer 180 may have a side surface perpendicular to the upper surface of the substrate 101.

[0063] The source conductive layer 180 may be electrically insulated from the gate electrode 130 by the source insulating layer 185. Therefore, the stacked structure of the gate electrode 130 may be separated from each other in the X direction by the source conductive layer 180 arranged therebetween. The source conductive layer 180 may be arranged in a linear shape extending in the Y direction, and may correspond to a common source line of the semiconductor device 100. The source conductive layer 180 may be repeatedly arranged at predetermined intervals (e.g., every four to eight columns of channel structures CH) in the X direction, but the arrangement of the source conductive layer 180 is not limited thereto. The source insulating layer 185 may partially extend between the interlayer insulating layers 120 and protrude to contact the side surface of the gate electrode 130. For example, the source insulating layer 185 may include a plurality of protrusions, each of which contacts the corresponding gate electrode 130 and is arranged between two adjacent interlayer insulating layers 120. The source conductive layer 180 may include a conductive material such as polysilicon, metal, etc., and the source insulating layer 185 may include an insulating material such as silicon oxide, silicon nitride, etc. In some embodiments, the separation region SR may be filled with only an insulating material without the source conductive layer 180. In this case, a region corresponding to a common source line may be disposed in or on the substrate 101.

[0064] The cell region insulating layer 190 may be disposed on the stack structure of the gate electrodes 130 , and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0065] Fig. 6A and Figure 6B is a partially enlarged cross-sectional view of a semiconductor device according to example embodiments. Fig. 6A and Figure 6B Shows the corresponding Figure 4 An enlarged view of the area of ​​region A.

[0066] Reference Fig. 6A In the semiconductor device 100 a , the first conductive layer 130A may include a first nucleation layer 130As and a first bulk layer 130Ab, and the second conductive layer 130B may include a second nucleation layer 130Bs and a second bulk layer 130Bb.

[0067] The first nucleation layer 130As and the second nucleation layer 130Bs may be formed first to provide nucleation sites, thereby assisting nucleation, to grow the subsequent first and second bulk layers 130Ab and 130Bb. The first and second bulk layers 130Ab and 130Bb may be grown based on the first and second nucleation layers 130As and 130Bs, respectively, to have desired thicknesses.

[0068] The first nucleation layer 130As and the second nucleation layer 130Bs and the first body layer 130Ab and the second body layer 130Bb may be formed under different process conditions and may have different thicknesses. In an example embodiment, the first nucleation layer 130As and the second nucleation layer 130Bs have an amorphous structure, while the first body layer 130Ab and the second body layer 130Bb have a crystalline structure. For example, the first nucleation layer 130As and the second nucleation layer 130Bs and the first body layer 130Ab and the second body layer 130Bb may be formed using different reactant gases and may be formed at different deposition rates. The first nucleation layer 130As and the second nucleation layer 130Bs may each have a thickness of about 3nm or less (e.g., a thickness in the range of about 10 angstroms to about 20 angstroms), and may have a substantially uniform thickness. The thickness of the first body layer 130Ab on one surface of the interlayer insulating layer 120 may decrease in a direction toward the separation region SR, while the thickness of the second body layer 130Bb may increase in a direction toward the separation region SR. In some embodiments, the first and second nucleation layers 130As and 130Bs and the first and second bulk layers 130Ab and 130Bb may include different impurities.

[0069] For example, when the gate electrode 130 is formed of tungsten (W) and WF is used 6When used as source gas, the first nucleation layer 130As and the second nucleation layer 130Bs can be used to prevent the residual fluorine (F) from diffusing. Therefore, the first nucleation layer 130As and the second nucleation layer 130Bs can prevent the fluorine (F) in the gate electrode 130 from diffusing to the gate dielectric layer 145, thereby preventing the electrical characteristics of the semiconductor device 100a from being degraded.

[0070] Reference Figure 6B , in the semiconductor device 100b, the first conductive layer 130A may include a first nucleation layer 130As and a first bulk layer 130Ab, and the second conductive layer 130B may substantially include only a single layer as a bulk layer without a nucleation layer.

[0071] In this embodiment, the second conductive layer 130B is disposed on the first conductive layer 130A without forming a nucleation layer on the first conductive layer 130A. Fig. 6A Compared with the example embodiments of the present invention, process efficiency can be improved.

[0072] Figure 7 and Figure 8 yes Figure 4 A partially enlarged cross-sectional view of area A in FIG.

[0073] Reference Figure 7 , in the semiconductor device 100c, the first conductive layer 130A may extend toward the separation region SR to be shorter than the barrier layer 144 of the gate dielectric layer 145. Therefore, the first conductive layer 130A may not be disposed in at least one region on the barrier layer 144, and the second conductive layer 130B may be in contact with the barrier layer 144. The term "contact" as used herein refers to direct connection (i.e., touch) unless the context otherwise indicates. More specifically, the second conductive layer 130B may fill the space between the barrier layer 144 on the upper interlayer insulating layer 120 and the barrier layer 144 on the lower interlayer insulating layer 120 in the region adjacent to the separation region SR. In example embodiments, the length of the region in which the first conductive layer 130A is not disposed on the barrier layer 144 may be changed differently.

[0074] Reference Figure 8 In the semiconductor device 100d, the barrier layer 144a of the gate dielectric layer 145a may be arranged to extend in a direction perpendicular to the upper surface of the substrate 101, similar to the channel structure CH, without extending in a horizontal direction along the gate electrode 130. Therefore, the first conductive layer 130A of the gate electrode 130 may contact the interlayer insulating layer 120.

[0075] Fig. 9 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

[0076] Reference Fig. 9, the semiconductor device 200 may include a vertically stacked memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL may be disposed on an upper surface of the peripheral circuit region PERI. For example, Figure 4 The semiconductor device 100 of the embodiment may include a peripheral circuit region PERI disposed on a substrate 101 in an unillustrated region, and the semiconductor device 200 according to the present embodiment may include a memory cell region CELL and a peripheral circuit region PERI stacked vertically. In example embodiments, the cell region CELL may be disposed below the peripheral circuit region PERI. Figure 3 and Figure 4 The description made can be similarly applied to the description of the memory cell region CELL.

[0077] The peripheral circuit region PERI may include a base substrate 201 , circuit elements 220 disposed on the base substrate 201 , circuit contact plugs 270 , and circuit interconnection lines 280 .

[0078] The base substrate 201 may have an upper surface extending in the X direction and the Y direction. In the base substrate 201, an isolation layer may be formed to define an active region. A source / drain region 205 including impurities may be disposed in a portion of the active region. The base substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0079] The circuit elements 220 may include planar transistors. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The source / drain region 205 may be disposed in the base substrate 201 on opposite sides adjacent to the circuit gate electrode 225.

[0080] The peripheral region insulating layer 290 may be disposed on the circuit element 220 on the base substrate 201. The circuit contact plug 270 may be connected to the source / drain region 205 through the peripheral region insulating layer 290. An electrical signal may be applied to the circuit element 220 through the circuit contact plug 270. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit interconnection line 280 may be connected to the circuit contact plug 270, and may be arranged in a plurality of layers.

[0081] In the semiconductor device 200, after the peripheral circuit region PERI is formed, the substrate 101 in the memory cell region CELL may be formed on the peripheral circuit region PERI to form the memory cell region CELL. The substrate 101 may be formed to have the same size as the base substrate 201 or to have a size smaller than the base substrate 201. The memory cell region CELL and the peripheral circuit region PERI may be connected to each other in an area not shown. For example, one end of the gate electrode 130 in the Y direction may be electrically connected to the circuit element 220.

[0082] Fig.10 is a flowchart illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0083] FIG. 11A to FIG. 11I is a diagram showing the manufacturing process according to an example embodiment Figure 4 A cross-sectional view of steps of a method of manufacturing a semiconductor device.

[0084] Reference Fig.10 and Fig.11A , sacrificial layers 110 and interlayer insulating layers 120 may be alternately stacked on the substrate 101 to form a stack structure ( S110 ).

[0085] In a subsequent process, the sacrificial layer 110 may be replaced with the gate electrode 130. The sacrificial layer 110 may be formed of a material different from that of the interlayer insulating layer 120. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial layer 110 may be formed of a material selected from silicon, silicon oxide, silicon carbide, and silicon nitride, which is different from the material of the interlayer insulating layer 120. In an example embodiment, the thicknesses of the interlayer insulating layers 120 may not all be equal to each other. For example, the lowermost interlayer insulating layer 120 may be formed to have a relatively large thickness, and the uppermost interlayer insulating layer 120 may be formed to have a relatively small thickness. The thickness of the interlayer insulating layer 120 and the thickness of the sacrificial layer 110 and the number of layers constituting them may be changed differently from those shown in the figure. A cell region insulating layer 190 may be formed on the uppermost portion.

[0086] Reference Fig.10 and Fig. 11B , an upper insulating layer 103 may be formed, and a channel structure CH may be formed to penetrate the stack structure ( S120 ).

[0087] The upper insulating layer 103 may be formed by removing a predetermined number of sacrificial layers 110 and interlayer insulating layers 120 from the uppermost portion of the stacked structure using an additional mask layer. The upper insulating layer 103 may be formed by depositing an insulating material on a region where the sacrificial layers 110 and interlayer insulating layers 120 are removed. The upper insulating layer 103 and interlayer insulating layers 120 may be formed of a material having an etching selectivity with respect to the sacrificial layers 110. In example embodiments, the upper insulating layer 103 may be formed of the same material as the interlayer insulating layer 120.

[0088] Next, in order to form the channel structure CH, a channel hole may be formed. The channel hole may be formed by anisotropically etching the stacked structure, and the channel hole may be formed in a hole shape, for example. Due to the height of the stacked structure, the sidewall of the channel hole may not be perpendicular to the upper surface of the substrate 101. The channel hole may be formed in a portion of the substrate 101. For example, the portion of the substrate 101 where the channel hole is formed may be recessed from the upper surface of the substrate 101.

[0089] Next, an epitaxial layer 107, a gate dielectric layer 145, a channel layer 140, a channel insulating layer 150, and a channel pad 155 may be formed in the channel hole to form a channel structure CH. A selective epitaxial growth (SEG) process may be used to form the epitaxial layer 107. The epitaxial layer 107 may be formed as a single layer or multiple layers, and may include doped or undoped polysilicon, single crystal silicon, polycrystalline germanium, or single crystal germanium.

[0090] The gate dielectric layer 145 may be formed to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this process step, all or a portion of the gate dielectric layer 145 may be formed, and a portion extending in a direction perpendicular to the substrate 101 along the channel structure CH may be formed, for example, Figure 4 The tunneling layer 142 and the charge storage layer 143 are shown in FIG.

[0091] The channel layer 140 may be formed on the gate dielectric layer 145 in the channel hole. The channel insulating layer 150 may be formed to fill the channel hole and may be an insulating material. However, in some embodiments, the channel hole may be filled with a conductive material instead of the channel insulating layer 150. The channel pad 155 may be formed of a conductive material (e.g., polysilicon).

[0092] Reference Fig.10 and Fig. 11C , separation regions SR may be formed to separate and penetrate the stack structure at predetermined intervals ( S130 ).

[0093] In example embodiments, before forming the separation region SR, an additional layer may be formed on the cell region insulating layer 190 and the channel pad 155 to prevent damage to the channel pad 155, the channel layer 140 below, etc. In example embodiments, the additional layer and the cell region insulating layer 190 may be formed of the same material. The separation region SR may be formed by forming a mask layer using a photolithography process and anisotropically etching the stacked structure of the sacrificial layer 110 and the interlayer insulating layer 120. The separation region SR may be formed in the shape of a trench extending in the Y direction. Figure 4 A source conductive layer 180 and a source insulating layer 185 may be disposed in each of the separation regions SR.

[0094] Reference Fig.10 and Fig.11D , the lateral opening LT may be formed by removing the sacrificial layer 110 exposed through the separation region SR ( S140 ).

[0095] The sacrificial layer 110 may be removed selectively with respect to the interlayer insulating layer 120 using, for example, wet etching. Thus, a lateral opening LT may be formed between the interlayer insulating layers 120, and a sidewall of the channel structure CH may be partially exposed through the lateral opening LT.

[0096] Reference Fig.10 and Fig.11E , a preliminary first conductive layer 130AP of the gate electrode 130 may be formed in the lateral opening LT ( S150 ).

[0097] Before forming the preliminary first conductive layer 130AP, a portion of the gate dielectric layer 145 may be formed in the lateral opening LT, for example, Figure 4 In some embodiments, when the barrier layer 144 is formed on the inner sidewall of the channel structure CH, the barrier layer 144 may not be formed in this process step, but may be preformed together with the channel layer 140 .

[0098] The preliminary first conductive layer 130AP may be formed by, for example, a CVD process or an ALD process. The preliminary first conductive layer 130AP may be formed to have a substantially uniform thickness along the upper and lower surfaces of the interlayer insulating layer 120 and the sidewalls of the channel structure CH, and may have a thickness insufficient to fill the lateral opening LT. Therefore, the preliminary first conductive layer 130AP may have a lateral recessed region LR formed concavely toward the channel structure CH.

[0099] When the preliminary first conductive layer 130AP is formed of tungsten (W), WF 6 、WCl 6 、WCl 5 、W(CO) 6 、W(C6 H 6 ) 2 、W(PF 3 ) 6 、W(allyl) 4 and (1,5-COD)W(CO) 4 , (C 5 H 5 ) 2 WH 2 At least one of the following can be used as the source gas, and B 2 H 6 、SiH 4 and H 2 At least one of the following is used as a reactant gas. Fig. 6A and Figure 6B Similar to the embodiment of , the preliminary first conductive layer 130AP may include a nucleation layer and a bulk layer. In this case, the reactant gas used to form the nucleation layer may have a higher source gas decomposition rate than the reactant gas used to form the bulk layer.

[0100] Reference Fig.10 and Fig.11F , a portion of the preliminary first conductive layer 130AP may be removed to reduce a thickness thereof in a direction toward the separation region SR ( S160 ).

[0101] The process of removing a portion of the preliminary first conductive layer 130AP may be a dry etching process using plasma or a dry etching process not using plasma. The dry etching process using plasma may use, for example, NF 3 , Cl 2 and F 2 The dry etching process without using plasma may use the source gas used when depositing the preliminary first conductive layer 130AP. For example, when the preliminary first conductive layer 130AP is formed of tungsten (W), WF 6 、WCl 6 、WCl 5 、W(CO) 6 、W(C 6 H 6 ) 2 、W(PF 3 ) 6 、W(allyl) 4 、(1,5-COD)W(CO) 4 and (C 5 H 5 ) 2 WH 2For example, the etching may be performed by a chemical reaction by introducing only the source gas without introducing the reactant gas, thereby using the source gas used for deposition as the etching gas.

[0102] During the etching process, the preliminary first conductive layer 130AP adjacent to the separation region SR and relatively more exposed to the etchant may be removed relatively more, and the preliminary first conductive layer 130AP spaced apart from the separation region SR and relatively less exposed to the etchant may be removed relatively less. Therefore, the thickness of the first conductive layer 130A in the direction from the outer side adjacent to the separation region SR to the channel structure CH may gradually increase, and may have a surface profile inclined on the upper and lower surfaces of the interlayer insulating layer 120. The first conductive layer 130A may not be etched or rarely etched between the channel structures CH not disposed adjacent to the separation region SR to have a substantially flat upper surface, but the shape of the upper surface of the first conductive layer 130A is not limited thereto. In some embodiments, the first conductive layer 130A may have, for example, an inclined upper surface even between the internal channel structures CH not disposed adjacent to the separation region SR.

[0103] In this process step, the etching conditions may be controlled so that the interlayer insulating layer 120 is not removed while removing a portion of the preliminary first conductive layer 130AP. In some embodiments, a portion of the interlayer insulating layer 120 adjacent to the separation region SR may be removed while removing a portion of the preliminary first conductive layer 130AP. In the case of the barrier layer 144, at least a portion of the barrier layer 144 on the sidewall of the interlayer insulating layer 120 may be removed together with the preliminary first conductive layer 130AP.

[0104] Reference Fig.10 and Fig.11G , a preliminary second conductive layer 130BP may be formed on the first conductive layer 130A to form the gate electrode 130 ( S170 ).

[0105] The preliminary second conductive layer 130BP may be formed by, for example, a CVD or ALD process. The preliminary second conductive layer 130BP may be formed to completely fill the lateral openings LT between the interlayer insulating layers 120 .

[0106] When the preliminary second conductive layer 130BP is formed of tungsten (W), WF 6 、WCl 6 、WCl 5 、W(CO) 6 、W(C 6 H 6 ) 2 、W(PF 3 ) 6 、W(allyl)4 、(1,5-COD)W(CO) 4 and (C 5 H 5 ) 2 WH 2 At least one of the following can be used as the source gas, and B 2 H 6 、SiH 4 and H 2 In some embodiments, the preliminary second conductive layer 130BP may include a nucleation layer and a bulk layer, or may include only a bulk layer.

[0107] Since the lateral recessed region LR has a profile in which the opening width increases in a direction toward the separation region SR depending on the shape of the first conductive layer 130A, the step coverage of the preliminary second conductive layer 130BP can be increased and its gap filling capability can be increased. Therefore, in the semiconductor device, in the process of forming the semiconductor device, even if the number of stacked gate electrodes is increased in order to improve the integration density and the distance between adjacent separation regions SR is increased in order to prevent the inclination of the stacked structure, the gate electrode 130 without a gap can be formed.

[0108] Reference Fig.11H , materials of the gate electrode 130 formed on the sidewalls of the interlayer insulating layer 120 in the separation region SR and on the substrate 101 may be removed.

[0109] The preliminary second conductive layer 130BP formed in the separation region SR may be removed by an etching process so that the gate electrode 130 is disposed only in the lateral opening LT. The etching process may be, for example, a wet etching process. In the etching process, the preliminary second conductive layer 130BP may be partially removed and recessed to form the second conductive layer 130B, and as the preliminary second conductive layer 130BP is partially removed, the gate electrode 130 may be partially removed. Fig.11G The gate electrode 130 may include the first conductive layer 130A that is partially removed and the second conductive layer 130B. As a result, the side surface of the gate electrode 130 may be defined. In order to electrically isolate between the gate electrodes 130 vertically adjacent to each other, the side surface of the gate electrode 130 may be more recessed inwardly toward the channel structure CH than the side surface of the interlayer insulating layer 120. In this process step, the barrier layer 144 formed in the separation region SR may also be removed to form the side surface of the barrier layer 144 at the same or similar position as the side surface of the gate electrode 130.

[0110] Reference Fig.11I , a source insulating layer 185 may be formed in the separation region SR.

[0111] The source insulating layer 185 may be formed by forming an insulating material to cover side surfaces of the gate electrode 130 and the interlayer insulating layer 120 , and removing the insulating material on the substrate 101 to expose an upper surface of the substrate 101 .

[0112] Reference Figure 4 A conductive material may be deposited between the source insulating layers 185 on opposite sides of the separation region SR to form a source conductive layer 180. Then, an interconnection structure such as a contact plug and a bit line may be further formed on the channel pad 155 to manufacture the semiconductor device 100.

[0113] Fig.12 is a process flow chart illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0114] Reference Fig.12 , shows that in reference FIG. 11E to FIG. 11G The gate electrode 130 may be formed by sequentially performing a first deposition process to form a preliminary first conductive layer 130AP, an etching process to remove a portion of the preliminary first conductive layer 130AP, and a second deposition process to form a second conductive layer 130B.

[0115] In the first deposition process, source gas and reactant gas may be alternately supplied to form the preliminary first conductive layer 130AP. After each of the source gas and the reactant gas is supplied, a purge gas may be supplied. One deposition cycle may be repeatedly performed two or more times to form the preliminary first conductive layer 130AP.

[0116] The source gas may include a precursor containing a material forming the preliminary first conductive layer 130AP. The precursor may be supplied in a gaseous state or an inert gas may be supplied as a carrier gas. A reactant gas may be supplied to assist nucleation of the precursor, and the reactant gas may be a gas for oxidizing or reducing the precursor. Argon (Ar), helium (He), or nitrogen (N 2 ) as a purge gas. The remaining byproducts and the unadsorbed source gas and reactant gas may be removed by the purge gas. For example, when the preliminary first conductive layer 130AP is formed of tungsten (W), the source gas may be WF 6 、WCl 6 、WCl 5 、W(CO) 6 、W(C 6 H 6 ) 2 、W(PF 3 ) 6 、W(allyl) 4 、(1,5-COD)W(CO)4 and (C 5 H 5 ) 2 WH 2 The reactant gas may be B 2 H 6 、SiH 4 and H 2 At least one of .

[0117] In the etching process, an etching gas may be supplied to remove a portion of the preliminary first conductive layer 130AP. After the etching gas is supplied, a purge gas may be supplied. The etching gas may be supplied for a predetermined time ΔT2, which may be longer than or equal to a supply time ΔT1 of the source gas in the first deposition process.

[0118] The etching gas may include a precursor containing a material forming the preliminary first conductive layer 130AP. When the preliminary first conductive layer 130AP is formed of tungsten (W), the etching gas may include WF 6 、WCl 6 、WCl 5 、W(CO) 6 、W(C 6 H 6 ) 2 、W(PF 3 ) 6 、W(allyl) 4 、(1,5-COD)W(CO) 4 and (C 5 H 5 ) 2 WH 2 In example embodiments, the source gas may be WF 6 , the etching gas can be WCl which has a relatively large etching characteristic 6 Alternatively, in an example embodiment, the source gas and the etching gas may be the same gas. In the etching process, one cycle may also be repeatedly performed two or more times. In this embodiment, the preliminary first conductive layer 130AP may be removed using a precursor that may be used as a source gas without using plasma. Therefore, the process may be simplified and may be performed using a single manufacturing device.

[0119] In the second deposition process, source gas and reactant gas may be alternately supplied to form the second conductive layer 130B. After each of the source gas and the reactant gas is supplied, a purge gas may be supplied. One deposition cycle may be repeated two or more times to form the second conductive layer 130B. The description of the first deposition process may be similarly applied to the above-mentioned gases.

[0120] The first deposition process, the etching process, and the second deposition process may be performed in a single chamber or multiple chambers of a manufacturing apparatus, which will be referred to below. Figures 13 to 14B Described in further detail.

[0121] Fig.13 is a schematic diagram of a manufacturing apparatus for manufacturing a semiconductor device according to example embodiments.

[0122] Reference Fig.13 , an apparatus 1 for manufacturing a semiconductor device may include a process chamber 1100, a substrate supporting unit 1110 disposed in the process chamber 1100, a gas injection unit 1200 disposed in the process chamber 1100, a gas supply unit 1300 connected to the gas injection unit 1200, a power supply unit 1400 connected to the substrate supporting unit 1110, a power supply unit 1450 connected to the gas injection unit 1200, an exhaust unit 1500 connected to the inside of the process chamber 1100, and a control unit 1600.

[0123] The apparatus 1 may be an apparatus for depositing and etching a thin film on a substrate SUB, and may perform not only a CVD process or an ALD process but also a dry etching process. In particular, the apparatus 1 may be used to form Figures 1 to 9 The gate electrode 130 of the semiconductor device may be formed by placing the substrate SUB processed by the apparatus 1 on the substrate supporting unit 1110 .

[0124] The process chamber 1100 may provide a space for performing a deposition process. The process chamber 1100 may include an upper wall, a side wall, and a lower wall. Although not shown, a channel through which the substrate SUB is fed in or out may be provided at one side of the process chamber 1100.

[0125] The substrate support unit 1110 may be disposed in the lower region of the process chamber 1100. The substrate support unit 1110 may include a support portion having an upper surface and an electrode 1150 located in the support portion, on which the substrate SUB is placed. For example, radio frequency (RF) power may be supplied from the power supply unit 1400 to the electrode 1150.

[0126] The gas injection unit 1200 may be disposed above the substrate support unit 1110 to face the substrate support unit 1110 in the process chamber 1100. The gas injection unit 1200 may be connected to the gas supply unit 1300 to distribute process gases, such as source gas, reactant gas, and etching gas, supplied from the gas supply unit 1300, and provide the distributed gas to the upper surface of the substrate SUB. The gas injection unit 1200 may be, for example, a shower head, and may include a first gas source 1310, a second gas source 1320, a third gas source 1330, and a fourth gas source 1340 connected to the gas supply unit 1300. In addition, the gas injection unit 1200 may include a plate 1220 having a plurality of injection holes PH for injecting process gas. The injection holes PH may be radially arranged from the central area of ​​the gas injection unit 1200. The gas injection unit 1200 may also include an electrode 1250 located on the plate 1220, and RF power, for example, may be supplied to the electrode 1250 from the power supply unit 1450. In example embodiments, a diffusion plate may be further provided in the gas injection unit 1200 to disperse the process gas.

[0127] The gas supply unit 1300 may include a first gas source 1310, a second gas source 1320, a third gas source 1330, and a fourth gas source 1340, and the first gas source 1310, the second gas source 1320, the third gas source 1330, and the fourth gas source 1340 may be configured to supply different gases. Fig.12 The source gas described above can be supplied through the second gas source 1320, and the reactant gas can be supplied through the second gas source 1320. In addition, the etching gas can be supplied through the third gas source 1330, and the purge gas can be supplied through the fourth gas source 1340. In some embodiments, the gas supply unit 1300 may include only three gas sources. For example, when the etching process is performed using the source gas used during the deposition process, in other words, when the deposition gas and the etching gas are the same, the third gas source 1330 can be omitted in the gas supply unit 1300. In addition to the first gas source 1310, the second gas source 1320, the third gas source 1330, and the fourth gas source 1340, the gas supply unit 1300 may further include a mass flow controller (MFC) configured to control the supply flow rate, a valve configured to supply gas to the process chamber 1100 or cut off the supplied gas, etc.

[0128] The power supply units 1400 and 1450 may supply RF power, and may generate an electric field in the lower and upper portions of the substrate SUB by a voltage difference. Therefore, plasma may be generated in a process region where a deposition process is performed on the substrate SUB. The gas injection unit 1200 may be connected to a ground voltage by the power supply unit 1450. The process region may correspond to a region between the substrate support unit 1110 and the gas injection unit 1200. In an example embodiment, since at least a portion of the source gas may be in a plasma state, deposition on the substrate SUB may be facilitated. However, plasma may be controlled not to be generated in an etching process.

[0129] The exhaust unit 1500 may be configured to exhaust byproducts and residual gases in the process chamber 1100 to the outside of the process chamber 100. The exhaust unit 1500 may include a vacuum pump. The material in the process chamber 1100 may be exhausted to the outside of the process chamber 1100 by vacuum suction generated by the vacuum pump. In example embodiments, the position, number, etc. of the exhaust unit 1500 may be variously changed.

[0130] The controller 1600 may control the gas supply sequence, time, flow rate, etc. of the gas supplied by the gas supply unit 1300. Fig.12As described, the first gas source 1310 and the second gas source 1320 may be controlled to alternately supply source gas and reactant gas in the first deposition process and the second deposition process, and the third gas source 1330 may be controlled to supply etching gas in the etching process. In addition, the gas supply unit 1300 may be controlled to sequentially perform the first deposition process, the etching process, and the second deposition process. As a result, the first deposition process, the etching process, and the second deposition process may be performed on-site in a single process chamber 1100. In this case, the movement of the substrate SUB between chambers may be omitted to shorten the process time and improve productivity. In addition, the controller 1600 may also control the supply of RF power supplied by the power supply units 1400 and 1450. Although not shown, the controller may include one or more of the following components: at least one central processing unit (CPU) configured to execute computer program instructions to perform various processes and methods; random access memory (RAM) and read-only memory (ROM) configured to access and store data and information and computer program instructions; input / output (I / O) devices (e.g., keyboard, mouse, display, speaker, printer, modem, network card, etc.) configured to provide input and / or output to the processing controller 1020, and storage media or other appropriate types of memory that can store data and / or instructions (e.g., such as RAM, ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic disks, optical disks, floppy disks, hard disks, removable cassettes, flash drives, any type of tangible and non-temporary storage media). In addition, the controller may include an antenna, a network interface to provide a wireless and / or wired digital and / or analog interface to one or more networks via one or more network connections (not shown), a power source to provide appropriate alternating current (AC) or direct current (DC) to one or more components of the controller, and a bus to allow communication between the various disclosed components of the controller.

[0131] However, Fig.13 The configuration, structure, and arrangement of the process chamber 1100 , the gas injection unit 1200 , the substrate support unit 1110 , the gas supply unit 1300 , and the power supply units 1400 , 1450 of the illustrated apparatus 1 are merely exemplary and may vary according to example embodiments.

[0132] Fig.14A and Fig. 14B is a schematic diagram of a manufacturing apparatus for manufacturing a semiconductor device according to example embodiments.

[0133] Reference Fig.14AThe manufacturing equipment 2A may include two chambers (including a first process chamber 1620 and a second process chamber 1640 that perform different processes), and may also include a rotation driver 1700 connected to the first process chamber 1620 and the second process chamber 1640 and a load interlock vacuum chamber 1800 disposed on one side of the rotation driver 1700.

[0134] The first process chamber 1620 may be a chamber for deposition, and the second process chamber 1640 may be a chamber for performing an etching process. Fig.12 The first deposition process for forming the preliminary first conductive layer 130AP and the second deposition process for forming the preliminary second conductive layer 130BP described above may be performed in the first process chamber 1620. Fig.12 The etching process of etching the preliminary first conductive layer 130AP and the preliminary second conductive layer 130BP described above may be performed in the second process chamber 1640. The first process chamber 1620 and the second process chamber 1640 may both have the same structure as described above with reference to FIG. Fig.13 The process chambers described herein have the same or similar structures.

[0135] The rotation driver 1700 may be connected to the first process chamber 1620 and the second process chamber 1640. The rotation driver 1700 may drive the arm portion 1750 to raise the substrate SUB (see Fig.13 ), and the arm portion 1750 may be rotated to move the substrate SUB between the first process chamber 1620 and the second process chamber 1640.

[0136] The load lock chamber 1800 may be provided to protect the first process chamber 1620 and the second process chamber 1640 from the external environment and may include a loading portion and an unloading portion. For example, the load lock chamber 1800 may allow a new wafer to be introduced into the spin drive 1700 without substantially breaking the vacuum therein.

[0137] Reference Fig. 14B The manufacturing equipment 2B may include three process chambers (including a first process chamber 1620, a second process chamber 1640, and a third process chamber 1660 for performing different processes), and may also include a rotation driver 1700 connected to the process chambers 1620, 1640, and 1660, and a load interlock vacuum chamber 1800 disposed on one side of the rotation driver 1700.

[0138] The first process chamber 1620 and the third process chamber 1660 may be chambers for deposition, and the second process chamber 1640 may be a chamber for performing an etching process. Fig.12The first deposition process for forming the preliminary first conductive layer 130AP described above may be performed in the first process chamber 1620. Fig.12 The etching process described above for etching the preliminary first conductive layer 130AP may be performed in the second process chamber 1640. Fig.12 The second deposition process for forming the preliminary second conductive layer 130BP described above may be performed in the third process chamber 1660. The first process chamber 1620, the second process chamber 1640, and the third process chamber 1660 may all have the same structure as described above with reference to FIG. Fig.13 The process chambers described herein have the same or similar structures.

[0139] When using a Fig.14A and Fig. 14B The system in-situ apparatus of manufacturing apparatus 2A and 2B is manufactured as described above with reference to Figures 1 to 9 When describing the semiconductor device, the above reference Fig.12 The described first deposition process for forming the preliminary first conductive layer 130AP, the etching process for etching the preliminary first conductive layer 130AP, and the second deposition process for forming the preliminary second conductive layer 130BP may be performed in the same apparatus, and at least part of the processes may be performed in different process chambers 1620, 1640, and 1660. In this case, the chamber for performing the deposition process and the chamber for performing the etching process may be separated to facilitate process control such as control of each etching rate thereof.

[0140] As described above, the gate electrode can be formed to include a first conductive layer and a second conductive layer having an interface and an inclined surface in an edge region. Therefore, a semiconductor device with improved reliability can be provided. In addition, an apparatus for efficiently manufacturing such a semiconductor device can be provided.

[0141] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A plurality of gate electrodes and a plurality of interlayer insulating layers are alternately stacked on a substrate; a plurality of channel structures spaced apart from each other in a first direction and extending vertically through the plurality of gate electrodes and the plurality of interlayer insulating layers to the substrate; as well as a first separation region vertically extending through the plurality of gate electrodes and the plurality of interlayer insulating layers, Each of the plurality of gate electrodes comprises a first conductive layer and a second conductive layer, the first conductive layer being disposed between the second conductive layer and each of two adjacent interlayer insulating layers in the plurality of interlayer insulating layers, In a first region of each of the plurality of gate electrodes located between an outermost channel structure of the plurality of channel structures adjacent to the first separation region and the first separation region, a thickness of the first conductive layer decreases toward the first separation region, and a thickness of the second conductive layer increases toward the first separation region, and The first conductive layer includes a first nucleation layer located on each of the two adjacent interlayer insulating layers and a first main layer stacked on the first nucleation layer.

2. The semiconductor device according to claim 1, in, An interface between the first conductive layer and the second conductive layer is inclined with respect to the first direction in the first region.

3. The semiconductor device according to claim 2, in, The interface between the first conductive layer and the second conductive layer is substantially parallel to the first direction in a second region of each of the plurality of gate electrodes located between two adjacent channel structures of the plurality of channel structures.

4. The semiconductor device according to claim 1, in, The first conductive layer is also disposed between the second conductive layer and a sidewall of each of the plurality of channel structures.

5. The semiconductor device according to claim 1, in, The second conductive layer includes a second nucleation layer contacting the first conductive layer and a second bulk layer stacked on the second nucleation layer.

6. The semiconductor device according to claim 5, in, The first nucleation layer and the second nucleation layer each have an amorphous structure, and the first bulk layer and the second bulk layer each have a crystalline structure.

7. The semiconductor device according to claim 1, further comprising: a gate dielectric layer, the gate dielectric layer being disposed between the channel structure and the gate electrode, The gate dielectric layer extends between the interlayer insulating layer and the first conductive layer.

8. The semiconductor device according to claim 7, in, The second conductive layer contacts the gate dielectric layer in a region adjacent to an edge portion of the first conductive layer.

9. The semiconductor device according to claim 1, in, The thickness of the first conductive layer in the first region is in the range of 0.1 nm to 3 nm, and the thickness of the second conductive layer in the first region is in the range of 10 nm to 30 nm.

10. The semiconductor device according to claim 1, in, The first separation region includes a source conductive layer connected to the substrate and a source insulating layer disposed between the source conductive layer and each of the plurality of gate electrodes.

11. The semiconductor device according to claim 10, in, The source insulating layer includes a plurality of protrusions, each of which is disposed between two adjacent interlayer insulating layers among the plurality of interlayer insulating layers.

12. The semiconductor device according to claim 1, further comprising: a second separation region, the second separation region being spaced apart from the first separation region in the first direction, Wherein, between the first separation region and the second separation region, a shape of the first conductive layer and a shape of the second conductive layer are substantially symmetrical in a first direction.

13. A semiconductor device, comprising: a plurality of gate electrodes vertically stacked on the substrate to be spaced apart from each other; a plurality of channel structures extending vertically through the plurality of gate electrodes to the substrate; as well as a separation region extending through the plurality of gate electrodes, Each of the plurality of gate electrodes comprises a first conductive layer having a lateral recessed region adjacent to an outermost channel structure of the plurality of channel structures and a second conductive layer disposed in the lateral recessed region, wherein the outermost channel structure is adjacent to the separation region. The laterally recessed region has a first width in a first direction perpendicular to the upper surface of the substrate in a first region adjacent to the outermost channel structure, and has a second width greater than the first width in the first direction in a second region adjacent to the separation region, and The second conductive layer includes a nucleation layer in contact with the first conductive layer and a main body layer stacked on the nucleation layer.

14. The semiconductor device according to claim 13, in, An interface between the laterally recessed region of the first conductive layer and the second conductive layer disposed in the laterally recessed region is inclined, and The lateral recessed region is disposed between the separation region and the outermost channel structure.

15. The semiconductor device according to claim 13, in, An interface between the laterally recessed region of the first conductive layer and the second conductive layer disposed in the laterally recessed region includes a discontinuous crystal structure.

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