Three-dimensional semiconductor memory device and method of operating the same

Abstract

A three-dimensional semiconductor memory device and a method for operating the same are provided. A three-dimensional semiconductor memory device includes a plurality of wordline blocks, each of which includes a plurality of cell strings connected in parallel between a bit line and a common source line. Each of the plurality of cell strings includes: a plurality of memory cell transistors stacked vertically on a substrate; a plurality of ground selection transistors connected in series between the plurality of memory cell transistors and the substrate; and a string selection transistor located between the plurality of memory cell transistors and the bit line. In each of the plurality of cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and the remaining ground selection transistors have a second threshold voltage different from the first threshold voltage.

Description

[0001] This patent application claims priority from Korean Patent Application No. 10-2019-0031961, filed on March 20, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor memory device and a method of operating the same. Background Art

[0003] Higher integration levels in semiconductor devices can be used to meet consumer demand for superior performance and low prices. In the case of semiconductor devices, increased integration can be particularly beneficial, as their integration is a significant factor in determining product price. To meet these technological demands, three-dimensional semiconductor memory devices comprising three-dimensionally arranged memory cells have recently been proposed. Summary of the Invention

[0004] Some embodiments of the inventive concepts provide three-dimensional semiconductor memory devices with increased integration density.

[0005] Some embodiments of the inventive concept provide a three-dimensional semiconductor memory device with improved reliability.

[0006] According to some embodiments of the inventive concept, a three-dimensional (3D) semiconductor memory device may include a plurality of word line blocks, the plurality of word line blocks including a plurality of cell strings connected in parallel between a bit line and a common source line. Each of the plurality of cell strings may include: a plurality of memory cell transistors stacked on a substrate in a vertical direction; a plurality of ground selection transistors connected in series between the plurality of memory cell transistors and the substrate; and a string selection transistor located between the plurality of memory cell transistors and the bit line. In each of the plurality of word line blocks, the string selection transistors of the plurality of cell strings may be electrically isolated from each other, and the ground selection transistors located at the same vertical level among the plurality of ground selection transistors may be controlled in common. In addition, in each of the plurality of cell strings, at least one of the plurality of ground selection transistors may have a first threshold voltage, and the remaining ground selection transistors may have a second threshold voltage different from the first threshold voltage.

[0007] According to some embodiments of the inventive concept, a 3D semiconductor memory device may include a substrate. The 3D semiconductor memory device may include a first cell string and a second cell string commonly connected to a bit line. Each of the first cell string and the second cell string may include: a plurality of memory cell transistors stacked vertically on the substrate; a first ground selection transistor and a second ground selection transistor connected in series between the plurality of memory cell transistors and the substrate; and a string selection transistor located between the plurality of memory cell transistors and the bit line. The 3D semiconductor memory device may include a first string selection line connected to the string selection transistors of the first cell string. The 3D semiconductor memory device may include a second string selection line connected to the string selection transistors of the second cell string. The 3D semiconductor memory device may include a first ground selection line commonly connected to the first ground selection transistors of the first and second cell strings. The 3D semiconductor memory device may include a second ground selection line commonly connected to the second ground selection transistors of the first and second cell strings. Furthermore, in each of the first and second cell strings, the first and second ground selection transistors may have respective threshold voltages different from each other.

[0008] According to some embodiments of the inventive concept, a 3D semiconductor memory device may include a substrate. The 3D semiconductor memory device may include a cell electrode structure, the cell electrode structure including word lines vertically stacked on the substrate. The cell electrode structure may include a plurality of word line blocks, each word line block including: a plurality of ground selection electrodes vertically stacked between the cell electrode structure and the substrate; and a plurality of string selection electrodes located on the cell electrode structure and horizontally spaced apart from each other. The 3D semiconductor memory device may include a plurality of vertical semiconductor patterns passing through the cell electrode structure, the ground selection electrodes, and the string selection electrodes. In addition, the 3D semiconductor memory device may include a data storage pattern located between the ground selection electrodes and the vertical semiconductor patterns.

[0009] According to some embodiments of the inventive concept, a method for operating a three-dimensional semiconductor memory device is provided, the three-dimensional semiconductor memory device including a first ground selection transistor, a second ground selection transistor, and a third ground selection transistor. The method may include: in a first cell string of the three-dimensional semiconductor memory device, increasing the threshold voltage of the third ground selection transistor to be higher than the threshold voltages of the first and second ground selection transistors. The method may include: in a second cell string of the three-dimensional semiconductor memory device, increasing the threshold voltage of the second ground selection transistor to be higher than the threshold voltages of the first and third ground selection transistors. The method may include: then, in a third cell string of the three-dimensional semiconductor memory device, increasing the threshold voltage of the first ground selection transistor to be higher than the threshold voltages of the second and third ground selection transistors. The first cell string, the second cell string, and the third cell string may be connected in parallel between a bit line and a common source line of the three-dimensional semiconductor memory device. In addition, each of the first cell string, the second cell string and the third cell string may include: a plurality of memory cell transistors stacked on a substrate in a vertical direction; a first ground selection transistor, a second ground selection transistor and a third ground selection transistor connected in series between the plurality of memory cell transistors and the substrate; and a string selection transistor located between the plurality of memory cell transistors and a bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0011] Figure 1 is a diagram schematically illustrating a structure of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0012] Figure 2 is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0013] Figure 3 It shows Figure 2 Circuit diagram of a cell string of a three-dimensional semiconductor memory device.

[0014] Figure 4 It shows Figure 2 A plan view of a cell array of a three-dimensional semiconductor memory device.

[0015] Figure 5A and Figure 5B Along Figure 4 Cross-sectional views taken along line 1-I' and line II-II'.

[0016] Figure 6is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0017] Figure 7 It shows Figure 6 Circuit diagram of a cell string of a three-dimensional semiconductor memory device.

[0018] Figure 8 It shows Figure 6 A plan view of a cell array of a three-dimensional semiconductor memory device.

[0019] Figure 9 It is along Figure 8 A cross-sectional view taken along line III-III'.

[0020] Figure 10 is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0021] Figures 11 to 13 It shows Figure 10 Circuit diagram of a cell string of a three-dimensional semiconductor memory device.

[0022] Figure 14 It shows Figure 10 A plan view of a cell array of a three-dimensional semiconductor memory device.

[0023] Figure 15 It is along Figure 14 A sectional view taken along line IV-IV'.

[0024] Figure 16 is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0025] Figure 17 Is to show the operation reference Figure 10 and Figure 11 A flow chart of a method for producing a three-dimensional semiconductor memory device is described.

[0026] Figure 18 is a circuit diagram illustrating a method of determining a threshold voltage of a ground selection transistor in a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0027] Figure 19 is a diagram illustrating a method of determining a threshold voltage of a ground selection transistor in a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0028] Figure 20 It shows Figure 10 Table of threshold voltages of ground selection transistors in a three-dimensional semiconductor memory device.

[0029] Figure 21 It is shown for Figure 10 A table showing voltage conditions for program operations and read operations of a three-dimensional semiconductor memory device.

[0030] It should be noted that these figures are intended to illustrate the general characteristics of methods, structures, and / or materials used in specific example embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and do not accurately reflect the precise structure or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of properties or values ​​encompassed by the example embodiments. For example, the relative thicknesses and positions of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0031] A three-dimensional semiconductor memory device and a method of operating the same according to example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings in which example embodiments are shown.

[0032] Figure 1 is a diagram schematically illustrating a structure of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0033] Reference Figure 1 , a three-dimensional semiconductor memory device may include a memory cell array 1 and a peripheral circuit 2 that controls the memory cell array 1. The peripheral circuit 2 may include a row decoder 3, a page buffer 4, a column decoder 5, a voltage generator 6, and a control (eg, control logic) circuit 7.

[0034] The memory cell array 1 may include a plurality of memory blocks BLK0-BLKn, each of which includes a plurality of memory cells arranged in a three-dimensional manner. In some embodiments, the memory blocks BLK0-BLKn may include a plurality of cell strings constituting a NAND cell array. The memory blocks BLK0-BLKn may be connected to a row decoder 3 via word lines and select lines.

[0035] The row decoder 3 can decode the address ADD input from outside the peripheral circuit 2 and / or from outside the memory device to select one of the memory blocks BLK0-BLKn and select one of the multiple word lines of the selected memory block. The page buffer 4 can be connected to the memory cell array 1 through the bit line BL and can read out the data stored in the memory cell. The column decoder 5 can decode the address input from outside the peripheral circuit 2 and / or from outside the memory device to select one of the multiple bit lines BL. The column decoder 5 can provide a data transmission path (for example, a data transmission path for input / output (I / O) data) between the page buffer 4 and an external device (for example, a memory controller). The voltage generator 6 can generate voltages for internal operations of the memory cell array 1 (for example, programming voltage, read voltage, erase voltage, etc.) according to the control of the control circuit 7.

[0036] Figure 2 is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0037] Reference Figure 2 A cell array of a three-dimensional semiconductor memory device may include a plurality of memory blocks, each memory block including a plurality of word line blocks WLBLK1 and WLBLK2. As an example, each memory block may include a first word line block WLBLK1 and a second word line block WLBLK2. In some embodiments, each memory block is shown as including two word line blocks WLBLK1 and WLBLK2, but the inventive concept is not limited to this example.

[0038] In each of the plurality of word line blocks, the plurality of cell strings may include n cell strings, and each of the plurality of cell strings may include m ground selection transistors, where m is equal to or less than n, and both m and n are natural numbers greater than 0. As an example, each of the first word line block WLBLK1 and the second word line block WLBLK2 may include cell strings CS1 and CS2, which are arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect each other and extend along a third direction D3. The cell strings CS1 and CS2 may be connected in parallel to each of the bit lines BL1-BL3. The two-dimensionally arranged cell strings CS1 and CS2 may be commonly connected to a common source line CSL.

[0039] In each of the first and second word line blocks WLBLK1 and WLBLK2 , the first and second cell strings CS1 and CS2 may be connected in parallel to each of the bit lines BL1 - BL3 .

[0040] Each of the first cell string CS1 and the second cell string CS2 may include a plurality of memory cell transistors MCT, a plurality of ground selection transistors GST1 and GST2, and a string selection transistor SST, wherein the plurality of memory cell transistors MCT are connected in series with each other along a third direction D3, the plurality of ground selection transistors GST1 and GST2 are connected in series with each other between a common source line CSL and the memory cell transistor MCT, and the string selection transistor SST is arranged between the memory cell transistor MCT and one of the bit lines BL1-BL3.

[0041] In some embodiments, each of the first word line block WLBLK1 and the second word line block WLBLK2 may include two string selection lines (e.g., a first string selection line SSL1 and a second string selection line SSL2) electrically isolated from each other. The first string selection line SSL1 may control the string selection transistors SST of the first cell string CS1 arranged along the first direction D1. The second string selection line SSL2 may control the string selection transistors SST of the second cell string CS2 arranged along the first direction D1. In some embodiments, the first string selection line SSL1 and the second string selection line SSL2 may be a first string selection electrode and a second string selection electrode, respectively.

[0042] The bit lines BL1-BL3, word lines WL1-WLn, and common source line CSL may be collectively arranged in the first word line block WLBLK1 and the second word line block WLBLK2. The first lower ground selection line GSL1a and the first upper ground selection line GSL1b may be arranged in the first word line block WLBLK1, and the second lower ground selection line GSL2a and the second upper ground selection line GSL2b may be arranged in the second word line block WLBLK2. In some embodiments, the first lower ground selection line GSL1a and the first upper ground selection line GSL1b may be the first ground selection electrode and the second ground selection electrode, respectively. Similarly, the second lower ground selection line GSL2a and the second upper ground selection line GSL2b may be the first ground selection electrode and the second ground selection electrode (or the third ground selection electrode and the fourth ground selection electrode), respectively.

[0043] Memory cell transistors MCT can be controlled by word lines WL1-WLn. In a first word line block WLBLK1 and a second word line block WLBLK2, gate electrodes of a plurality of memory cell transistors MCT located at the same level (or height) from a common source line CSL can be commonly connected to one of the word lines WL1-WLn. Each memory cell transistor MCT may include a data storage element. The "cell electrode structure" may include a stack of word lines WL1-WLn on a substrate and / or may include the first word line block WLBLK1 and the second word line WLBLK2.

[0044] In some embodiments, when each of the first and second word line blocks WLBLK1 and WLBLK2 includes a pair of first and second string selection lines SSL1 and SSL2 electrically isolated from each other, each of the cell strings CS1 and CS2 may include a pair of ground selection transistors GST1 and GST2. In other words, each of the cell strings CS1 and CS2 may include a first and second ground selection transistors GST1 and GST2 connected in series. In each of the cell strings CS1 and CS2, the first and second ground selection transistors GST1 and GST2 may have different threshold voltages.

[0045] The first and second ground selection transistors GST1 and GST2 of the first word line block WLBLK1 may be controlled by a first lower ground selection line GSL1a and a first upper ground selection line GSL1b. The first and second ground selection transistors GST1 and GST2 of the second word line block WLBLK2 may be controlled by a second lower ground selection line GSL2a and a second upper ground selection line GSL2b. The first lower and first upper ground selection lines GSL1a and GSL1b may be electrically isolated from the second lower and second upper ground selection lines GSL2a and GSL2b.

[0046] The first lower ground selection lines GSL1a may be electrically connected in common to the first ground selection transistors GST1 of the first word line block WLBLK1. The first upper ground selection lines GSL1b may be electrically connected in common to the second ground selection transistors GST2 of the first word line block WLBLK1.

[0047] The second lower ground selection lines GSL2a may be electrically connected in common to the first ground selection transistors GST1 of the second word line block WLBLK2. The second upper ground selection lines GSL2b may be electrically connected in common to the second ground selection transistors GST2 of the second word line block WLBLK2.

[0048] Figure 3 It shows Figure 2 Circuit diagram of a cell string of a three-dimensional semiconductor memory device.

[0049] Reference Figure 3 , the first cell string CS1 and the second cell string CS2 may be connected in parallel to one of the bit lines (eg, BL1 ) and a common source line CSL.

[0050] The string selection transistor SST of the first cell string CS1 may be controlled by a first string selection line SSL1 , and the string selection transistor SST of the second cell string CS2 may be controlled by a second string selection line SSL2 .

[0051] In each of the first cell string CS1 and the second cell string CS2, the first ground selection transistor GST1 and the second ground selection transistor GST2 may be programmed to have different threshold voltages. Figure 3 , reference letter “P” indicates that the ground selection transistors GST1 and GST2 are programmed to have the second threshold voltage.

[0052] In the first cell string CS1, the first ground selection transistor GST1 may have a first threshold voltage, and the second ground selection transistor GST2 may have a second threshold voltage higher than the first threshold voltage. In the second cell string CS2, the first ground selection transistor GST1 may have a second threshold voltage, and the second ground selection transistor GST2 may have a first threshold voltage. In other words, the first ground selection transistors GST1 of the first cell string CS1 and the second cell string CS2 may have different threshold voltages, and the second ground selection transistors GST2 of the first cell string CS1 and the second cell string CS2 may have different threshold voltages.

[0053] The first ground selection transistor GST1 of the first cell string CS1 and the second ground selection transistor GST2 of the second cell string CS2 may be turned on by a first operating voltage that is higher than the first threshold voltage and lower than the second threshold voltage. The second ground selection transistor GST2 of the first cell string CS1 and the first ground selection transistor GST1 of the second cell string CS2 may be turned on by a second operating voltage that is higher than the second threshold voltage.

[0054] In some embodiments, the first ground selection transistors GST1 of the first cell string CS1 and the second cell string CS2, which are commonly connected to the first lower ground selection line GSL1a, may operate in a complementary manner according to a voltage applied to the first lower ground selection line GSL1a. In addition, the second ground selection transistors GST2 of the first cell string CS1 and the second cell string CS2, which are commonly connected to the first upper ground selection line GSL1b, may operate in a complementary manner according to a voltage applied to the first upper ground selection line GSL1b.

[0055] The electrical connection between the first bit line BL1 and the first and second cell strings CS1 and CS2 can be controlled by voltages applied to the first and second string selection lines SSL1 and SSL2. The electrical connection between the first and second cell strings CS1 and CS2 and the common source line CSL can be controlled by voltages applied to the first lower and first upper ground selection lines GSL1a and GSL1b.

[0056] In some embodiments, for the first cell string CS1 and the second cell string CS2 connected to the first bit line BL1, the first lower ground selection line GSL1a and the first upper ground selection line GSL1b are physically connected to the first cell string CS1 and the second cell string CS2 in common, but the first ground selection transistors GST1 and the second ground selection transistors GST2 of the first cell string CS1 and the second cell string CS2 may be electrically isolated from each other.

[0057] Specifically, a power supply voltage Vcc ( Figure 18 ), a ground voltage may be applied to the second string selection line SSL2, a second operating voltage may be applied to the first upper ground selection line GSL1b, and a first operating voltage may be applied to the first lower ground selection line GSL1a. In this case, the first bit line BL1 and the common source line CSL may be electrically connected to each other through the first cell string CS1, but the second cell string CS2 may be electrically isolated from the first bit line BL1 and the common source line CSL and may be in a floating state. In other words, the unselected second cell string CS2 may be electrically isolated from the first bit line BL1 and the common source line CSL. Therefore, during a read operation on the cell array, a read disturbance phenomenon may be suppressed / prevented from occurring in an unselected cell string (e.g., CS2) of the cell strings CS1 and CS2 connected to a selected bit line (e.g., BL1) among the bit lines.

[0058] Figure 4 It shows Figure 2 A plan view of a cell array of a three-dimensional semiconductor memory device. Figure 5A and Figure 5B Along Figure 4 Cross-sectional views taken along line 1-I' and line II-II'.

[0059] Reference Figure 4 、 Figure 5A and Figure 5B The electrode structure ST may be provided on a substrate 100. The substrate 100 may include at least one of a semiconductor material (e.g., silicon), an insulating material (e.g., glass), and a semiconductor material or a conductive material covered by an insulating material. For example, the substrate 100 may be a silicon wafer of a first conductivity type.

[0060] The electrode structures ST may extend in a first direction D1 parallel to the top surface of the substrate 100. The electrode structures ST may be spaced apart from each other in a second direction D2 intersecting the first direction D1 by an electrode separation structure ESS disposed therebetween.

[0061] In each electrode structure ST, the string selection lines SSL1 and SSL2, the word lines WL1-WLn, and the ground selection lines GSL1a, GSL1b, GSL2a, and GSL2b may be stacked along a third direction D3 with the insulating layer 110 interposed therebetween. The third direction D3 may be perpendicular to the top surface of the substrate 100 and may be perpendicular to the first direction D1 and the second direction D2. In each electrode structure ST, the ground selection lines GSL1a and GSL1b / GSL2a and GSL2b and the word lines WL1-WLn may have a first width along the second direction D2, and the string selection lines SSL1 and SSL2 may have a second width along the second direction D2 that is smaller than the first width.

[0062] Each electrode structure ST may include a ground selection structure GS1 or GS2 , a memory cell structure MCS on the ground selection structure GS1 or GS2 , and a string selection structure SS1 or SS2 on the memory cell structure MCS.

[0063] The ground selection structure GS1 or GS2 may include ground selection lines GSL1a and GSL1b / GSL2a and GSL2b stacked along a third direction D3, and the string selection structure SS1 or SS2 may include string selection lines SSL1 and SSL2 extending along a first direction D1 and spaced apart from each other along a second direction D2. As an example, each electrode structure ST may include first and second ground selection lines GSL1a, GSL1b, GSL2a, GSL2b, and first and second string selection lines SSL1 and SSL2. The first and second string selection lines SSL1 and SSL2 may be spaced apart from each other by an insulating separation pattern 150 disposed between the first and second string selection lines SSL1 and SSL2 and extending along the first direction D1.

[0064] The memory cell structure MCS may include word lines WL1-WLn stacked along a third direction D3. The memory cell structure MCS may be provided in common in a plurality of electrode structures ST. That is, in the plurality of electrode structures ST, the word lines WL1-WLn located at the same level (or height) from the substrate 100 may be in an equipotential state. In the plurality of electrode structures ST, the word lines WL1-WLn located at the same level from the substrate 100 may be formed from a physically single layer.

[0065] The bit lines BL may be commonly connected to the plurality of electrode structures ST. The bit lines BL may be spaced apart from each other along the first direction D1 and may extend along the second direction D2.

[0066] A common source line / common source region CSL may be disposed in the substrate 100 between the electrode structures ST. By way of example, the common source line / common source region CSL may be formed by doping the substrate 100 of a first conductivity type with impurities of a second conductivity type, and may include, for example, n-type impurities (e.g., arsenic (As) or phosphorus (P)). The common source line / common source region CSL may extend parallel to the electrode structures ST (e.g., along the first direction D1) and may be spaced apart from each other along the second direction D2. In other words, each electrode structure ST may be disposed between each pair of adjacent common source lines / common source regions CSL.

[0067] The electrode separation structure ESS may extend parallel to the electrode structures ST (e.g., along the first direction D1) and may be disposed between each pair of adjacent electrode structures ST. The electrode separation structure ESS may include a common source contact plug CSP coupled to each common source line / common source region CSL and an insulating spacer SS disposed between the common source contact plug CSP and side surfaces of the ground selection lines GSL1a, GSL1b, GSL2a, and GSL2b, the word lines WL1-WLn, and the string selection lines SSL1 and SSL2.

[0068] In some embodiments, the first to eighth vertical structures VS1 to VS8 may be arranged to penetrate each electrode structure ST and may be connected to the substrate 100. In other words, the first to eighth vertical structures VS1 to VS8 may extend along a third direction D3 perpendicular to the top surface of the substrate 100. The first to eighth vertical structures VS1 to VS8 may be arranged in respective columns, each column including a plurality of vertical structures and extending along the first direction D1. The columns of the first to eighth vertical structures VS1 to VS8 may be sequentially arranged along the second direction D2. Furthermore, when viewed in a plan view, the first to eighth vertical structures VS1 to VS8 may be arranged along the first direction D1 and the second direction D2 to form a zigzag pattern.

[0069] The first to fourth vertical structures VS1 to VS4 can penetrate the first string selection line SSL1 and word lines WL1-WLn of each electrode structure ST. In the first word line block WLBLK1, the first to fourth vertical structures VS1 to VS4 can also penetrate the first ground selection lines GSL1a and GSL1b. In the second word line block WLBLK2, the first to fourth vertical structures VS1 to VS4 can also penetrate the second ground selection lines GSL2a and GSL2b. The fifth to eighth vertical structures VS5 to VS8 can penetrate the second string selection line SSL2 and word lines WL1-WLn of each electrode structure ST. In the first word line block WLBLK1, the fifth to eighth vertical structures VS5 to VS8 can also penetrate the first ground selection lines GSL1a and GSL1b. In the second word line block WLBLK2, the fifth to eighth vertical structures VS5 to VS8 can also penetrate the second ground selection lines GSL2a and GSL2b.

[0070] In addition, a dummy vertical structure DVS may be provided to penetrate each electrode structure ST between the first and second string selection lines SSL1 and SSL2 . The dummy vertical structure DVS may be configured to have substantially the same structural features as the first to eighth vertical structures VS1 to VS8 .

[0071] Each of the first to eighth vertical structures VS1 to VS8 may include a conductive pad disposed on a top thereof, and the conductive pad may be an impurity region doped with impurities, or may be formed of a conductive material.

[0072] Each of the first to eighth vertical structures VS1 to VS8 and the dummy vertical structure DVS may include a vertical semiconductor pattern VP connected to the substrate 100 (eg, see Figure 19 ) and a data storage pattern DS surrounding the vertical semiconductor pattern VP. In other words, the data storage pattern DS may be disposed on an outer sidewall of the vertical semiconductor pattern VP.

[0073] The vertical semiconductor pattern VP (see, for example, Figure 19 ) may include semiconductor materials and may be used as a reference Figure 3 Channel regions of the first and second ground selection transistors GST1 and GST2 , the string selection transistor SST, and the memory cell transistor MCT are described.

[0074] The data storage pattern DS may include a charge storage layer used as a data storage element of a NAND flash memory device. As an example, Figure 19As shown in FIG, the data storage pattern DS may include a tunnel insulating layer TIL, a charge storage layer CIL, and a blocking insulating layer BIL. The charge storage layer CIL may be one or more insulating layers having a large number of trap sites and / or one or more insulating layers having nanoparticles. For example, the charge storage layer CIL may include one of an insulating layer having conductive nanodots, a trap insulating layer, and a floating gate electrode.

[0075] In some embodiments, the data storage pattern DS may extend along the third direction D3 to cross side surfaces of the first and second ground selection lines GSL1a and GSL1b, GSL2a and GSL2b, the word lines WL1-WLn, the first and second string selection lines SSL1, and SSL2. Figure 3 The first ground selection transistor GST1 and the second ground selection transistor GST2 described may be composed of first ground selection lines GSL1a, GSL1b and second ground selection lines GSL2a, GSL2b and a data storage pattern DS and a vertical semiconductor pattern VP adjacent thereto. Since each of the first ground selection transistor GST1 and the second ground selection transistor GST2 includes a data storage pattern DS, they can be programmed by a voltage applied to the first ground selection lines GSL1a, GSL1b and second ground selection lines GSL2a, GSL2b. Specifically, charges can be stored in the data storage pattern DS of the first ground selection transistor GST1 and the second ground selection transistor GST2 by the first ground selection lines GSL1a, GSL1b and second ground selection lines GSL2a, GSL2b and the vertical semiconductor pattern VP (for example, see Figure 19 ). The first and second ground selection transistors GST1 and GST2 are trapped by Fowler-Nordheim (FN) tunneling caused by the voltage difference between the two transistors. This can cause the first and second ground selection transistors GST1 and GST2 to have different threshold voltages. A method for programming the first and second ground selection transistors GST1 and GST2 to different threshold voltages will be described in more detail below.

[0076] In addition, refer to Figure 5A 、 Figure 5B and Figure 19The horizontal insulating pattern HL may extend horizontally from an area between the vertical semiconductor pattern VP and side surfaces of the string select lines SSL1 and SSL2, the word lines WL1-WLn, and the ground select lines GSL1a, GSL1b, GSL2a, and GSL2b to cover the top and bottom surfaces of each of the lines SSL1, SSL2, WL1-WLn, GSL1a, GSL1b, GSL2a, and GSL2b. The horizontal insulating pattern HL may serve as part of a data storage layer of the NAND flash memory device. The horizontal insulating pattern HL may be formed of or include at least one high-k dielectric material (e.g., aluminum oxide and / or hafnium oxide) having a lower dielectric constant than the blocking insulating layer BIL.

[0077] A capping insulating pattern 210 may be disposed on the electrode structure ST to cover top surfaces of the first to eighth vertical structures VS1 to VS8 , and an interlayer insulating layer 220 may be disposed on the capping insulating pattern 210 and may cover top surfaces of the common source plug CSP.

[0078] Bit lines BL may be disposed on the interlayer insulating layer 220. The bit lines BL may extend along the second direction D2 to intersect the electrode structures ST and may be alternately disposed along the first direction D1. In some embodiments, when viewed in plan, a pair of bit lines BL may span each of the vertical structures VS1-VS8. In other words, the bit lines BL may have a line width that is less than half the width of the upper portions of the vertical structures VS1-VS8. The bit lines BL may be selectively connected to the first through eighth vertical structures VS1 through VS8 via contact plugs PLG.

[0079] In some embodiments, a three-dimensional semiconductor memory device may be a reference Figure 3 In other words, the word lines WL1-WLn, the first string selection line SSL1, the second string selection line SSL2, the first ground selection lines GSL1a, GSL1b, and the second ground selection lines GSL2a, GSL2b of the electrode structure ST can control the vertical semiconductor patterns VP of the first vertical structure VS1 to the eighth vertical structure VS8 (for example, see Figure 19 ) potential, and can control the electrical connection between the bit line BL and the common source line / common source region CSL.

[0080] For the sake of simplicity, the same reference numerals may be used to identify and refer to Figures 2 to 5B Elements of the three-dimensional semiconductor memory device described are identical to the elements, and their overlapping descriptions will not be repeated.

[0081] Figure 6is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Figure 7 It shows Figure 6 Circuit diagram of a cell string of a three-dimensional semiconductor memory device.

[0082] Reference Figure 6 and Figure 7 , the cell array may include a first word line block WLBLK1 and a second word line block WLBLK2.

[0083] In each of the first word line block WLBLK1 and the second word line block WLBLK2, the first cell string CS1, the second cell string CS2, the third cell string CS3, and the fourth cell string CS4 may be connected in parallel to each of the bit lines BL. Each of the first to fourth cell strings CS1 to CS4 may include a string selection transistor SST, a memory cell transistor MCT connected in series, and a plurality of ground selection transistors GST1 and GST2 connected in series. As an example, each of the first to fourth cell strings CS1 to CS4 may include two or four ground selection transistors GST1 and GST2. In addition, in at least one of the cell strings CS1-CS4, the ground selection transistors GST1 and GST2 may have two different threshold voltages.

[0084] In some embodiments, each of the first to fourth cell strings CS1 to CS4 may include a first ground selection transistor GST1 and a second ground selection transistor GST2 connected in series with each other. In each of the first to fourth cell strings CS1 to CS4, the first and second ground selection transistors GST1 and GST2 may be programmed to have different threshold voltages from each other.

[0085] A first lower ground selection line GSL1a and a first upper ground selection line GSL1b may be provided in the first word line block WLBLK1, and a second lower ground selection line GSL2a and a second upper ground selection line GSL2b may be provided in the second word line block WLBLK2. In the first word line block WLBLK1, the first ground selection transistors GST1 may be electrically connected in common to the first lower ground selection line GSL1a, and the second ground selection transistors GST2 may be electrically connected in common to the first upper ground selection line GSL1b. In the second word line block WLBLK2, the first ground selection transistors GST1 may be electrically connected in common to the second lower ground selection line GSL2a, and the second ground selection transistors GST2 may be electrically connected in common to the second upper ground selection line GSL2b.

[0086] In some embodiments, the first ground selection transistors GST1 of the first and second cell strings CS1 and CS2 may have a first threshold voltage, and the second ground selection transistors GST2 of the first and second cell strings CS1 and CS2 may have a second threshold voltage higher than the first threshold voltage. The first ground selection transistors GST1 of the third and fourth cell strings CS3 and CS4 may have a second threshold voltage, and the second ground selection transistors GST2 of the third and fourth cell strings CS3 and CS4 may have a first threshold voltage. In this case, when the first bit line BL1 is selected and the first cell string CS1 is electrically connected to the first bit line BL1 and the common source line CSL, the string selection transistors SST and the first and second ground selection transistors GST1 and GST2 of the unselected third and fourth cell strings CS3 and CS4 may be turned off, thereby electrically disconnecting the unselected third and fourth cell strings CS3 and CS4 from the common source line CSL and the first bit line BL1.

[0087] In some embodiments, the first ground selection transistor GST1 of the first cell string CS1 and the third cell string CS3 may have a first threshold voltage, and the second ground selection transistor GST2 of the first cell string CS1 and the third cell string CS3 may have a second threshold voltage higher than the first threshold voltage. The first ground selection transistor GST1 of the second cell string CS2 and the fourth cell string CS4 may have a second threshold voltage, and the second ground selection transistor GST2 of the second cell string CS2 and the fourth cell string CS4 may have a first threshold voltage. In this case, when the first bit line BL1 is selected and the first cell string CS1 is electrically connected to the first bit line BL1 and the common source line CSL, the unselected second cell string CS2 and the fourth cell string CS4 may be electrically disconnected from the common source line CSL and the first bit line BL1. In other words, the unselected second cell string CS2 and the fourth cell string CS4 may be in an electrically floating state.

[0088] Figure 8 It shows Figure 6 A plan view of a cell array of a three-dimensional semiconductor memory device. Figure 9 It is along Figure 8 A cross-sectional view taken along line III-III'.

[0089] For the sake of simplicity, the same reference numerals may be used to identify and refer to Figure 4 、 Figure 5A and Figure 5B Elements of the three-dimensional semiconductor memory device described are the same elements, and overlapping descriptions thereof will not be repeated.

[0090] Reference Figure 8 and Figure 9The electrode structures ST disposed on the substrate 100 may be spaced apart from each other along a second direction D2 intersecting the first direction D1 by the electrode separation structure ESS. Each electrode structure ST may include a ground selection structure GS1 or GS2, a memory cell structure MCS on the ground selection structure GS1 or GS2, and a string selection structure SS1 or SS2 on the memory cell structure MCS.

[0091] The ground selection structure GS1 or GS2 may include a plurality of ground selection lines GSL1a and GSL1b or GSL2a and GSL2b stacked along a third direction D3, and the string selection structure SS1 or SS2 may include a plurality of string selection lines SSL1, SSL2, SSL3, and SSL4 extending along a first direction D1 and spaced apart from one another along a second direction D2. By way of example, each electrode structure ST may include first ground selection lines GSL1a and GSL1b or second ground selection lines GSL2a and GSL2b and first, second, third, and fourth string selection lines SSL1, SSL2, and SSL3. The first to fourth string selection lines SSL1 to SSL4 may be spaced apart from one another by insulating separation patterns 150, each of which is disposed between the first to fourth string selection lines SSL1 to SSL4 and extends along the first direction D1.

[0092] In each of the word line blocks WLBLK1 and WLBLK2, first to eighth vertical structures VS1 to VS8 may be provided to penetrate each electrode structure ST and may be connected to the substrate 100. Specifically, the first and second vertical structures VS1 to VS2 may penetrate the first string selection line SSL1, word lines WL1-WLn, and first ground selection lines GSL1a and GSL1b or second ground selection lines GSL2a and GSL2b of each electrode structure ST. The third and fourth vertical structures VS3 to VS4 may penetrate the second string selection line SSL2, word lines WL1-WLn, and first ground selection lines GSL1a and GSL1b or second ground selection lines GSL2a and GSL2b of each electrode structure ST. The fifth and sixth vertical structures VS5 to VS6 may penetrate the third string selection line SSL3, word lines WL1-WLn, and first ground selection lines GSL1a and GSL1b or second ground selection lines GSL2a and GSL2b of each electrode structure ST. The seventh and eighth vertical structures VS7 and VS8 may penetrate the fourth string selection line SSL4 , the word lines WL1 -WLn, and the first and second ground selection lines GSL1 a and GSL1 b or GSL2 a and GSL2 b of each electrode structure ST.

[0093] As described above, the data storage pattern DS may extend along the third direction D3 to cross side surfaces of the first to fourth ground selection lines GSL1a and GSL1b, GSL2a and GSL2b, word lines WL1-WLn, and first to fourth string selection lines SSL1 to SSL4.

[0094] Reference Figure 6 The described first and second ground selection transistors GST1 and GST2 may be connected by first and second ground selection lines GSL1a and GSL1b or second ground selection lines GSL2a and GSL2b and data storage patterns DS and vertical semiconductor patterns VP adjacent thereto (eg, see Figure 19 ). Since each of the first and second ground selection transistors GST1 and GST2 includes a data storage pattern DS, the first and second ground selection transistors GST1 and GST2 can be programmed by a voltage applied to the first ground selection lines GSL1a and GSL1b or the second ground selection lines GSL2a and GSL2b. A method of programming the first and second ground selection transistors GST1 and GST2 to different threshold voltages will be described in more detail below.

[0095] Figure 10 is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Figures 11 to 13 It shows Figure 10 Circuit diagram of a cell string of a three-dimensional semiconductor memory device.

[0096] Reference Figure 10 and Figure 11 , the cell array may include a first word line block WLBLK1 and a second word line block WLBLK2, and in each of the first word line block WLBLK1 and the second word line block WLBLK2, a first cell string CS1, a second cell string CS2, a third cell string CS3, a fourth cell string CS4, a fifth cell string CS5, and a sixth cell string CS6 may be connected in parallel to each of the bit lines BL1-BL3.

[0097] Each of the first to sixth cell strings CS1 to CS6 may include a string selection transistor SST, a memory cell transistor MCT connected in series, and a plurality of ground selection transistors GST1, GST2, and GST3 connected in series. As an example, each of the first to sixth cell strings CS1 to CS6 may include two, three, or six ground selection transistors. In addition, in each cell string, at least one of the ground selection transistors GST1, GST2, and GST3 may have a threshold voltage different from that of the other transistors.

[0098] As an example, each of the first to sixth cell strings CS1 to CS6 may include a first ground selection transistor GST1, a second ground selection transistor GST2, and a third ground selection transistor GST3. In each of the first to sixth cell strings CS1 to CS6, one of the first to third ground selection transistors GST1, GST2, and GST3 may be programmed to have a second threshold voltage, while the other ground selection transistors may be programmed to have a first threshold voltage lower than the second threshold voltage.

[0099] In each of the first and second word line blocks WLBLK1 and WLBLK2 , string selection transistors SST of first to sixth cell strings CS1 to CS6 may be controlled by first to sixth string selection lines SSL1 to SSL6 , respectively.

[0100] First, second, and third ground selection transistors GST1, GST2, and GST3 of first to sixth cell strings CS1 to CS6 of the first word line block WLBLK1 may be connected to first lower, middle, and upper ground selection lines GSL1a, GSL1b, and GSL1c, respectively.

[0101] The first, second, and third ground selection transistors GST1, GST2, and GST3 of the first to sixth cell strings CS1 to CS6 of the second word line block WLBLK2 may be connected to the second lower, second middle, and second upper ground selection lines GSL2a, GSL2b, and GSL2c, respectively.

[0102] In some embodiments, the first and second ground selection transistors GST1 and GST2 of the first and second cell strings CS1 and CS2 may have a first threshold voltage, and the third ground selection transistors GST3 of the first and second cell strings CS1 and CS2 may have a second threshold voltage higher than the first threshold voltage.

[0103] The first and third ground selection transistors GST1 and GST3 of the third and fourth cell strings CS3 and CS4 may have a first threshold voltage, and the second ground selection transistors GST2 of the third and fourth cell strings CS3 and CS4 may have a second threshold voltage higher than the first threshold voltage.

[0104] The second and third ground selection transistors GST2 and GST3 of the fifth and sixth cell strings CS5 and CS6 may have a first threshold voltage, and the first ground selection transistors GST1 of the fifth and sixth cell strings CS5 and CS6 may have a second threshold voltage higher than the first threshold voltage.

[0105] according to Figure 11 In the embodiment shown in , when the first bit line BL1 is selected and the first cell string CS1 is electrically connected to the first bit line BL1 and the common source line CSL, the unselected third cell string CS3, fourth cell string CS4, fifth cell string CS5 and sixth cell string CS6 can be electrically disconnected from the common source line CSL and the first bit line BL1 by the second ground selection transistor GST2 and the third ground selection transistor GST3.

[0106] according to Figure 12 In the embodiment shown in , each of the first to sixth cell strings CS1 to CS6 connected in parallel between the first bit line BL1 and the common source line CSL may include a first ground selection transistor GST1 and a second ground selection transistor GST2. Here, the first ground selection transistor GST1 of the first, second, and third cell strings CS1, CS2, and CS3 may have a first threshold voltage, while the second ground selection transistor GST2 of the first, second, and third cell strings CS1, CS2, and CS3 may have a second threshold voltage higher than the first threshold voltage. The second ground selection transistor GST2 of the fourth, fifth, and sixth cell strings CS4, CS5, and CS6 may have a first threshold voltage, while the first ground selection transistor GST1 of the fourth, fifth, and sixth cell strings CS4, CS5, and CS6 may have a second threshold voltage higher than the first threshold voltage.

[0107] In this case, when the first bit line BL1 is selected and the first cell string CS1 is electrically connected to the first bit line BL1 and the common source line CSL, the unselected fourth cell string CS4, fifth cell string CS5 and sixth cell string CS6 can be electrically disconnected from the common source line CSL and the first bit line BL1 through the second ground selection transistor GST2.

[0108] Reference Figure 13 Each of the first to sixth cell strings CS1 to CS6 connected in parallel between the first bit line BL1 and the common source line CSL may include first to sixth ground selection transistors GST1, GST2, GST3, GST4, GST5, and GST6. In each of the first to sixth cell strings CS1 to CS6, one of the first to sixth ground selection transistors GST1 to GST6 may be programmed to have a second threshold voltage, and the other ground selection transistors may be programmed to have a first threshold voltage less than the second threshold voltage.

[0109] As an example, the sixth ground selection transistor GST6 of the first cell string CS1, the fifth ground selection transistor GST5 of the second cell string CS2, the fourth ground selection transistor GST4 of the third cell string CS3, the third ground selection transistor GST3 of the fourth cell string CS4, the second ground selection transistor GST2 of the fifth cell string CS5, and the first ground selection transistor GST1 of the sixth cell string CS6 can be programmed to have a second threshold voltage higher than the first threshold voltage.

[0110] In each of the word line blocks WLBLK1 and WLBLK2, first to sixth ground selection lines GSL1a to GSL1f may be connected to first to sixth ground selection transistors GST1 to GST6 of each cell string CS1 to CS6, respectively. In each of the word line blocks WLBLK1 and WLBLK2, the first ground selection transistors GST1 of the first to sixth cell strings CS1 to CS6 may be electrically connected in common to the first ground selection line GSL1a. Except for the first ground selection transistor GST1 of the sixth cell string CS6, all first ground selection transistors GST1 of the first to sixth cell strings CS1 to CS6 connected to the first ground selection line GSL1a may have a first threshold voltage. The second to sixth ground selection transistors GST2 to GST6 of the first to sixth cell strings CS1 to CS6 may be configured to have similar or identical characteristics to the first ground selection transistor GST1.

[0111] according to Figure 13 In the embodiment shown in , when the first bit line BL1 is selected and the first cell string CS1 is electrically connected to the first bit line BL1 and the common source line CSL, the unselected second to sixth cell strings CS2 to CS6 may be electrically disconnected from the common source line CSL and the first bit line BL1 by the first to fifth ground selection transistors GST1 to GST5 of the second to sixth cell strings CS2 to CS6. In other words, the unselected second to sixth cell strings CS2 to CS6 may be in an electrically floating state.

[0112] Figure 14 It shows Figure 10 A plan view of a cell array of a three-dimensional semiconductor memory device. Figure 15 It is along Figure 14 A cross-sectional view taken along line IV-IV′.

[0113] Reference Figure 14 and Figure 15The electrode structures ST disposed on the substrate 100 may be spaced apart from each other along a second direction D2 intersecting the first direction D1 by the electrode separation structure ESS. Each electrode structure ST may include a ground selection structure GS1 or GS2, a memory cell structure MCT on the ground selection structure GS1 or GS2, and a string selection structure SS1 or SS2 on the memory cell structure MCT.

[0114] As an example, each electrode structure ST may include a first ground selection line GSL1a or GSL2a, a second ground selection line GSL1b or GSL2b, and a third ground selection line GSL1c or GSL2c, and first to sixth string selection lines SSL1, SSL2, SSL3, SSL4, SSL5, and SSL6. The first to sixth string selection lines SSL1, SSL2, SSL3, SSL4, SSL5, and SSL6 may be spaced apart from each other by insulating separation patterns 150, each of which is disposed between the first to sixth string selection lines SSL1, SSL2, SSL3, SSL4, SSL5, and SSL6 and extends in the first direction D1.

[0115] The first to twelfth vertical structures VS1 to VS12 may be provided to penetrate each electrode structure ST and may be connected to the substrate 100. Specifically, the first and second vertical structures VS1 and VS2 may penetrate the first string selection line SSL1, the word lines WL1-WLn, the first ground selection line GSL1a or GSL2a, the second ground selection line GSL1b or GSL2b, and the third ground selection line GSL1c or GSL2c of each electrode structure ST. The third and fourth vertical structures VS3 and VS4 may penetrate the second string selection line SSL2, the word lines WL1-WLn, the first ground selection line GSL1a or GSL2a, the second ground selection line GSL1b or GSL2b, and the third ground selection line GSL1c or GSL2c of each electrode structure ST. The fifth and sixth vertical structures VS5 and VS6 may penetrate the third string selection line SSL3, word lines WL1-WLn, first ground selection line GSL1a or GSL2a, second ground selection line GSL1b or GSL2b, and third ground selection line GSL1c or GSL2c of each electrode structure ST. The seventh and eighth vertical structures VS7 and VS8 may penetrate the fourth string selection line SSL4, word lines WL1-WLn, first ground selection line GSL1a or GSL2a, second ground selection line GSL1b or GSL2b, and third ground selection line GSL1c or GSL2c of each electrode structure ST. The ninth and tenth vertical structures VS9 and VS10 may penetrate the fifth string selection line SSL5, word lines WL1-WLn, first ground selection line GSL1a or GSL2a, second ground selection line GSL1b or GSL2b, and third ground selection line GSL1c or GSL2c of each electrode structure ST. The eleventh and twelfth vertical structures VS11 and VS12 may penetrate the sixth string selection line SSL6 , the word lines WL1 -WLn, the first, second, and third ground selection lines GSL1 a or GSL2 a , GSL1 b or GSL2 b , and GSL1 c or GSL2 c of each electrode structure ST.

[0116] The data storage pattern DS may extend along a third direction D3 to cross side surfaces of first to sixth ground selection lines GSL1a and GSL2a, GSL1b and GSL2b, GSL1c and GSL2c, word lines WL1-WLn, and SSL1 to SSL6.

[0117] Reference Figure 10 and Figure 11The first to third ground selection transistors GST1 to GST3 described above may be connected to first, second, and third ground selection lines GSL1a and GSL2a, GSL1b and GSL2b, and GSL1c and GSL2c, and data storage patterns DS and vertical semiconductor patterns VP adjacent thereto (eg, see FIG. Figure 19 ). Since each of the first to third ground selection transistors GST1 to GST3 includes a data storage pattern DS, the first to third ground selection transistors GST1 to GST3 can be programmed by voltages applied to the first ground selection lines GSL1a and GSL2a, the second ground selection lines GSL1b and GSL2b, and the third ground selection lines GSL1c and GSL2c. A method of programming the first to third ground selection transistors GS1 to GST3 to different threshold voltages will be described in more detail below.

[0118] Figure 16 is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0119] Reference Figure 16 , each of the cell strings CS1 - CS6 may be composed of a string selection transistor SST, a memory cell transistor MCT connected in series, a plurality of ground selection transistors GST1 , GST2 , and GST3 connected in series, and an erase control transistor ECT.

[0120] The erase control transistor ECT may be controlled by an erase control line ECL. A common source line CSL may be commonly connected to the source of the erase control transistor ECT. The erase control transistors ECT of the first word line block WLBLK1 and the second word line block WLBLK2 may be commonly connected to the erase control line ECL and may be in an equipotential state.

[0121] During an erase operation of the memory cell array, the erase control transistor ECT may cause a gate-induced drain leakage (GIDL) current. In some embodiments, during an erase operation of the memory cell array, an erase voltage may be applied to the bit lines BL1-BL3 and / or the common source line CSL, and the GIDL current may appear in the string select transistor SST and / or the erase control transistor ECT.

[0122] Figure 17 Is to show the operation reference Figure 10 and Figure 11 A flow chart of a method for producing a three-dimensional semiconductor memory device is described. Figure 18 is a circuit diagram illustrating a method of determining a threshold voltage of a ground selection transistor in a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Figure 19is a diagram illustrating a method of determining a threshold voltage of a ground selection transistor in a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Figure 20 It shows Figure 10 and Figure 11 Table of threshold voltages of ground selection transistors in a three-dimensional semiconductor memory device.

[0123] Reference Figure 10 、 Figure 11 、 Figure 17 and Figure 18 , all memory blocks in the cell array may be initialized (in block S10 ). In other words, the string selection transistors SST and the ground selection transistors GST1 , GST2 , and GST3 and the memory cell transistors MCT of each memory block may be erased simultaneously.

[0124] Specifically, the string selection lines SSL1-SSL6, the ground selection lines GSL1a, GSL1b, GSL1c, GSL2a, GSL2b, and GSL2c, and the word lines WL1-WLn may be applied with a ground voltage Vss (which may be 0V). Figure 18 ), and the substrate 100 and the vertical semiconductor pattern VP may be applied with an erase voltage. Here, the bit lines BL1-BL3 and the common source line CSL may be in an electrically floating state. As a result of the erase operation, the string selection transistor SST and the ground selection transistors GST1, GST2, and GST3 may have a first threshold voltage lower than 0V.

[0125] Thereafter, a program operation may be sequentially performed to program the first to third ground selection transistors GST1 , GST2 , and GST3 of the first to sixth cell strings CS1 to CS6 to a predetermined threshold voltage (in blocks S20 , S30 , and S40 ).

[0126] Specifically, refer to Figure 18 and Figure 19 , a first Vth adjustment (ie, threshold voltage adjustment) operation may be performed (in block S20) to program the third ground selection transistors GST3 of the first and second cell strings CS1 and CS2 of each word line block to have a second threshold voltage.

[0127] In the first Vth adjustment operation (block S20), the bit line BL may be applied with a ground voltage Vss (e.g., 0V), the first and second string selection lines SSL1 and SSL2 may be applied with a pass voltage Vcc+Vth, and the word lines WL1-WLn and the first lower and first middle ground selection lines GSL1a and GSL1b may be applied with a pass voltage Vpass. The first upper ground selection line GSL1c may be applied with a program voltage Vpgm. Here, the program voltage Vpgm may be a voltage high enough to cause FN tunneling from the vertical semiconductor pattern VP. The pass voltage Vpass may be selected within a range from the threshold voltage of the memory cell transistor to the program voltage Vpgm.

[0128] Under such voltage conditions, the ground voltage Vss applied to the bit line BL may be transferred to the vertical semiconductor patterns VP of the first and second cell strings CS1 and CS2 to cause a large potential difference between the first upper ground selection line GSL1c to which the programming voltage Vpgm is applied and the vertical semiconductor patterns VP of the first and second cell strings CS1 and CS2 adjacent to the first upper ground selection line GSL1c, and thus, charges may be captured in the charge storage layer CIL adjacent to the first upper ground selection line GSL1c. Therefore, as Figure 20 As shown in FIG, the threshold voltage of the third ground selection transistor GST3 of the first and second cell strings CS1 and CS2 may increase from the first threshold voltage to the second threshold voltage.

[0129] Thereafter, a second Vth adjustment operation may be performed (in block S30 ) to program the second ground selection transistors GST2 of the third and fourth cell strings CS3 and CS4 of each word line block to a second threshold voltage.

[0130] In the second Vth adjustment operation (block S30), the bit line BL may be applied with a ground voltage Vss (e.g., 0V), the third and fourth string selection lines SSL3 and SSL4 may be applied with a pass voltage Vcc+Vth, the word lines WL1-WLn and the first lower and first upper ground selection lines GSL1a and GSL1c may be applied with a pass voltage Vpass, and the first middle ground selection line GSL1b may be applied with a program voltage Vpgm.

[0131] Under such voltage conditions, a large potential difference may occur between the first middle ground selection line GSL1b and the vertical semiconductor pattern VP of the third and fourth cell strings CS3 and CS4 adjacent to the first middle ground selection line GSL1b. Therefore, charges may be trapped in the charge storage layer CIL adjacent to the first middle ground selection line GSL1b. Figure 20As shown in FIG, the threshold voltage of the second ground selection transistors GST2 of the third and fourth cell strings CS3 and CS4 may increase from the first threshold voltage to the second threshold voltage.

[0132] Thereafter, a third Vth adjustment operation may be performed (in block S40 ) to program the first ground selection transistors GST1 of the fifth and sixth cell strings CS5 and CS6 of each word line block to the second threshold voltage.

[0133] In the third Vth adjustment operation (in block S40), the bit line BL may be applied with a ground voltage Vss (e.g., 0V), the fifth and sixth string selection lines SSL5 and SSL6 may be applied with a pass voltage Vcc+Vth, the word lines WL1-WLn, the first middle ground selection line GSL1b, and the first upper ground selection line GSL1c may be applied with a pass voltage Vpass, and the first lower ground selection line GSL1a may be applied with a program voltage Vpgm.

[0134] Under such voltage conditions, a large potential difference may occur between the first lower ground selection line GSL1a and the vertical semiconductor pattern VP of the fifth and sixth cell strings CS5 and CS6 adjacent to the first lower ground selection line GSL1a. Therefore, charges may be trapped in the charge storage layer adjacent to the first lower ground selection line GSL1a. Figure 20 As shown in FIG, the threshold voltage of the first ground selection transistor GST1 of the fifth and sixth cell strings CS5 and CS6 may increase from the first threshold voltage to the second threshold voltage.

[0135] If the threshold voltages of the first to third ground selection transistors GST1 to GST3 of the first to sixth cell strings CS1 to CS6 are set as follows in each word line block: Figure 20 As shown in , one of a program operation, a read operation, and an erase operation may be performed on the memory cell transistors MCT of the memory cell array (in block S50 ).

[0136] Figure 21 is shown for the Figure 10 A table showing voltage conditions for selecting a cell string during program and read operations of a three-dimensional semiconductor memory device.

[0137] Reference Figure 10 and Figure 21 , one of the first to sixth cell strings CS1 to CS6 may be selected to program data in or read data from the selected memory cell.

[0138] When the first cell string CS1 or the second cell string CS2 is selected, a ground voltage may be applied to the selected bit line, and the first string selection line SSL1 or the second string selection line SSL2 may be applied to the power supply voltage Vcc. Unselected bit lines may be applied to a predetermined bit line voltage, and unselected string selection lines SSL3-SSL6 may be applied to a ground voltage Vss (e.g., 0V). The first upper ground selection line GSL1c may be applied to a second operating voltage Vgsl2 higher than the second threshold voltage, and the first lower ground selection line GSL1a and the first middle ground selection line GSL1b may be applied to a first operating voltage Vgsl1 higher than the first threshold voltage and lower than the second threshold voltage.

[0139] Under such voltage conditions, the third ground selection transistor GST3 of the first cell string CS1 or the second cell string CS2 may be turned on, and the first ground selection transistor GST1 and the second ground selection transistor GST2 may be turned on. Therefore, a current may be formed between the selected bit line and the common source line CSL through the first cell string CS1 or the second cell string CS2.

[0140] At this time, the first to third ground selection transistors GST1 to GST3 of the unselected third to sixth cell strings CS3 to CS6 may be turned off. In other words, during a read operation or a program operation on the memory cell array, the unselected cell strings CS3-CS6 among the first to sixth cell strings CS1 to CS6 connected to the selected bit line may be electrically disconnected from the selected bit line and the common source line CSL and may become in a floating state.

[0141] At the same time, when the third cell string CS3 or the fourth cell string CS4 is selected, the first middle ground selection line GSL1b may be applied with a second operating voltage Vgsl2 higher than the second threshold voltage, and the first lower ground selection line GSL1a and the first upper ground selection line GSL1c may be applied with a first operating voltage Vgsl1 higher than the first threshold voltage and lower than the second threshold voltage.

[0142] When the fifth cell string CS5 or the sixth cell string CS6 is selected, the first lower ground selection line GSL1a may be applied with a second operating voltage Vgsl2 higher than the second threshold voltage, and the first middle ground selection line GSL1b and the first upper ground selection line GSL1c may be applied with a first operating voltage Vgsl1 higher than the first threshold voltage and lower than the second threshold voltage.

[0143] According to some embodiments of the inventive concept, the ground select transistors in each cell string can be programmed to adjust their respective threshold voltages. This makes it possible to electrically isolate the ground select transistors connected to a ground select line from each other. This ensures operational reliability and increases the number of cell strings provided in each word line block.

[0144] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A three-dimensional semiconductor memory device comprising a plurality of word line blocks, the plurality of word line blocks comprising a plurality of cell strings connected in parallel between bit lines and a common source line, in, Each of the plurality of cell strings includes: a plurality of memory cell transistors stacked on a substrate in a vertical direction; a plurality of ground selection transistors connected in series between the plurality of memory cell transistors and the substrate; and a string selection transistor located between the plurality of memory cell transistors and a bit line. wherein, in each of the plurality of word line blocks, string selection transistors of the plurality of cell strings are electrically isolated from each other, and ground selection transistors located at the same level among the plurality of ground selection transistors are commonly controlled, and In each of the plurality of cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and the remaining ground selection transistors have a second threshold voltage different from the first threshold voltage.

2. The three-dimensional semiconductor memory device according to claim 1, wherein: A first ground selection transistor and a second ground selection transistor located at the same level among the plurality of ground selection transistors have a first threshold voltage and a second threshold voltage, respectively.

3. The three-dimensional semiconductor memory device according to claim 1, in, In each of the plurality of word line blocks, the plurality of cell strings includes n cell strings, Each of the plurality of cell strings includes m ground selection transistors. where m is equal to or less than n, and Wherein, m and n are both natural numbers greater than 0.

4. The three-dimensional semiconductor memory device according to claim 1, in, In each of the plurality of word line blocks, the plurality of cell strings includes six cell strings, and Each of the plurality of cell strings includes a first ground selection transistor, a second ground selection transistor, and a third ground selection transistor connected in series with each other.

5. The three-dimensional semiconductor memory device according to claim 4, wherein The plurality of cell strings include a first cell string, a second cell string, and a third cell string. In the first cell string, a first ground selection transistor has a first threshold voltage. In the second cell string, a second ground selection transistor has a first threshold voltage. In the third cell string, a third ground selection transistor has a first threshold voltage.

6. The three-dimensional semiconductor memory device according to claim 5, wherein: First, second, and third ground selection transistors of the first, second, and third cell strings are connected to first, second, and third ground selection lines, respectively.

7. The three-dimensional semiconductor memory device according to claim 5, wherein: The first, second, and third ground selection transistors of the first, second, and third cell strings are located at different respective levels from the substrate.

8. A three-dimensional semiconductor memory device comprising: substrate; A first cell string and a second cell string are commonly connected to a bit line, each of the first cell string and the second cell string comprising: A plurality of memory cell transistors are stacked on a substrate in a vertical direction; a first ground selection transistor and a second ground selection transistor connected in series between the plurality of memory cell transistors and a substrate; and a string selection transistor located between the plurality of memory cell transistors and a bit line; a first string selection line connected to a string selection transistor of a first cell string; a second string selection line connected to a string selection transistor of a second cell string; a first ground selection line commonly connected to first ground selection transistors of the first cell string and the second cell string; and A second ground selection line is commonly connected to the second ground selection transistors of the first cell string and the second cell string. Here, in each of the first cell string and the second cell string, the first ground selection transistor and the second ground selection transistor have respective threshold voltages different from each other.

9. The three-dimensional semiconductor memory device according to claim 8, in, A threshold voltage of a first ground selection transistor of the first cell string is different from a threshold voltage of a first ground selection transistor of the second cell string, and The threshold voltage of the second ground selection transistor of the first cell string is different from the threshold voltage of the second ground selection transistor of the second cell string.

10. The three-dimensional semiconductor memory device according to claim 8, wherein In the first cell string and the second cell string, memory cell transistors located at the same level from the substrate among the plurality of memory cell transistors are commonly connected to one word line.

11. The three-dimensional semiconductor memory device according to claim 8, in, The first ground selection transistors of the first cell string and the second cell string are located at a first level from the substrate, and The second ground selection transistors of the first cell string and the second cell string are located at a second level from the substrate, and the second level is higher than the first level.

12. The three-dimensional semiconductor memory device according to claim 8, in, The first ground selection line and the second ground selection line are vertically stacked on the substrate, and The first string selection line and the second string selection line are horizontally spaced apart from each other on the substrate.

13. The three-dimensional semiconductor memory device according to claim 12, in, The first cell string includes: a first vertical semiconductor pattern vertically penetrating the first string selection line, the first ground selection line, and the second ground selection line; and a first data storage pattern located between the first and second ground selection lines and the first vertical semiconductor pattern, and The second unit string includes: a second vertical semiconductor pattern vertically penetrating the second string selection line, the first ground selection line, and the second ground selection line; and The second data storage pattern is located between the first and second ground selection lines and the second vertical semiconductor pattern.

14. The three-dimensional semiconductor memory device according to claim 13, wherein: Each of the first and second data storage patterns includes a tunnel insulating layer, a charge storage layer, and a blocking insulating layer sequentially stacked on sidewalls of the first and second vertical semiconductor patterns.

15. The three-dimensional semiconductor memory device according to claim 13, wherein: Charges are trapped in a first data storage pattern between the first ground selection line and the first vertical semiconductor pattern, and charges are trapped in a second data storage pattern between the second ground selection line and the second vertical semiconductor pattern.

16. A three-dimensional semiconductor memory device comprising: substrate; A unit electrode structure includes word lines vertically stacked on a substrate, wherein the unit electrode structure includes a plurality of word line blocks, each word line block including: a plurality of ground selection electrodes vertically stacked between the unit electrode structure and the substrate; and a plurality of string selection electrodes, located on the unit electrode structure and horizontally spaced apart from each other, a plurality of vertical semiconductor patterns penetrating the cell electrode structure, the ground selection electrode, and the string selection electrode; and The data storage pattern is located between the ground selection electrode and the vertical semiconductor pattern. The plurality of ground selection electrodes include a first ground selection line and a second ground selection line, the first ground selection line is connected to the lowermost ground selection transistor of the first cell string and the lowermost ground selection transistor of the second cell string, and the second ground selection line is connected to the uppermost ground selection transistor of the first cell string and the uppermost ground selection transistor of the second cell string. wherein the uppermost ground selection transistor of the first cell string has a different threshold voltage from the uppermost ground selection transistor of the second cell string, and Herein, the lowermost ground selection transistor of the first cell string has a threshold voltage different from that of the lowermost ground selection transistor of the second cell string.

17. The three-dimensional semiconductor memory device according to claim 16, wherein: Each of the data storage patterns includes a tunnel insulating layer, a charge storage layer, and a blocking insulating layer, which are sequentially stacked on sidewalls of the vertical semiconductor patterns.

18. The three-dimensional semiconductor memory device according to claim 16, wherein: The plurality of string selection electrodes overlap the plurality of ground selection electrodes.

19. The three-dimensional semiconductor memory device according to claim 16, in, The plurality of ground selection electrodes include a first ground selection electrode and a second ground selection electrode, The plurality of string selection electrodes include a first string selection electrode and a second string selection electrode. The plurality of vertical semiconductor patterns include a first vertical semiconductor pattern and a second vertical semiconductor pattern. The data storage pattern includes a first data storage pattern and a second data storage pattern. The first vertical semiconductor pattern passes through the first string selection electrode, the first ground selection electrode and the second ground selection electrode. The first data storage pattern is located between the first ground selection electrode, the second ground selection electrode and the first vertical semiconductor pattern. wherein the second vertical semiconductor pattern penetrates the second string selection electrode, the first ground selection electrode, and the second ground selection electrode, and The second data storage pattern is located between the first ground selection electrode, the second ground selection electrode and the second vertical semiconductor pattern.

20. The three-dimensional semiconductor memory device according to claim 16, in, The plurality of string selection electrodes include a first string selection electrode of a first cell string and a second string selection electrode of a second cell string, Here, in each of the first cell string and the second cell string, the uppermost ground selection transistor and the lowermost ground selection transistor have different threshold voltages from each other.

21. A method of operating a three-dimensional semiconductor memory device including a first ground selection transistor, a second ground selection transistor, and a third ground selection transistor, the method comprising: In a first cell string of the three-dimensional semiconductor memory device, increasing a threshold voltage of a third ground selection transistor to be higher than threshold voltages of the first and second ground selection transistors; In a second cell string of the three-dimensional semiconductor memory device, increasing a threshold voltage of a second ground selection transistor to be higher than threshold voltages of a first ground selection transistor and a third ground selection transistor; and then In a third cell string of the three-dimensional semiconductor memory device, a threshold voltage of the first ground selection transistor is increased to be higher than threshold voltages of the second and third ground selection transistors, The first cell string, the second cell string, and the third cell string are connected in parallel between the bit line and the common source line of the three-dimensional semiconductor memory device, and Each of the first cell string, the second cell string, and the third cell string includes: A plurality of memory cell transistors are stacked on a substrate in a vertical direction; a first ground selection transistor, a second ground selection transistor, and a third ground selection transistor connected in series between the plurality of memory cell transistors and a substrate; and A string selection transistor is located between the plurality of memory cell transistors and a bit line.

22. The method of claim 21, further comprising: Before increasing the threshold voltage of the third ground selection transistor, the third ground selection transistor, the second ground selection transistor, and the first ground selection transistor are erased.

23. The method of claim 21, further comprising: After increasing the threshold voltage of the first ground selection transistor, electrically connecting a selected cell string among the first, second, and third cell strings to a bit line and a common source line, and electrically disconnecting unselected cell strings among the first, second, and third cell strings from the bit line and the common source line by applying a gate voltage to at least one of the first, second, and third ground selection transistors, The gate voltage is higher than a threshold voltage of at least one of the first ground selection transistor, the second ground selection transistor, and the third ground selection transistor.

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