Semiconductor device and method for manufacturing the same

Abstract

The embodiment relates to a semiconductor device and a method for manufacturing the same. The semiconductor device of the embodiment comprises: a semiconductor portion; a first insulating film disposed on the semiconductor portion; a second insulating film disposed on the semiconductor portion, in contact with the first insulating film, thicker than the first insulating film, and having a through hole formed therein; a first contact member, the lower end of which is connected to the semiconductor portion; a second contact member, the lower portion of which is disposed in the through hole and the lower end of which is connected to the semiconductor portion; and a gate electrode, which is located between the first contact member and the second contact member, and is disposed on the first insulating film and on a portion of the second insulating film other than the through hole.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2019-53157 (filing date: March 20, 2019). This application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] For example, DMOS (Double-Diffused MOSFET) is used as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) for power control. DMOS requires a reduction in on-resistance and an improvement in reliability. In DMOS, an oxide film thicker than the gate oxide film is provided between the source and the drain in order to obtain a field plate effect. As an oxide film thicker than the gate oxide film, STI (Shallow Trench Isolation) is often used from the perspective of miniaturization and manufacturing cost. Summary of the invention

[0005] Embodiments provide a semiconductor device having low on-resistance and high reliability and a method for manufacturing the same.

[0006] A semiconductor device according to an embodiment comprises: a semiconductor portion; a first insulating film disposed on the semiconductor portion; a second insulating film disposed on the semiconductor portion, in contact with the first insulating film, thicker than the first insulating film, and having a through hole formed therein; a first contact member, a lower end of which is connected to the semiconductor portion; a second contact member, a lower portion of which is disposed in the through hole and a lower end of which is connected to the semiconductor portion; and a gate electrode located between the first contact member and the second contact member, disposed on the first insulating film and on a portion of the second insulating film other than the through hole.

[0007] A semiconductor device according to another embodiment includes: a semiconductor portion; a first insulating film provided on the semiconductor portion; a second insulating film provided on the semiconductor portion, in contact with the first insulating film, and thicker than the first insulating film; and a gate electrode provided on the first insulating film and on a portion of the second insulating film. The second side surface of the second insulating film, which is opposite to the first side surface of the first insulating film and in contact with the second insulating film and separated from the second insulating film, is inclined relative to the upper surface of the second insulating film.

[0008] The manufacturing method of the semiconductor device of the embodiment comprises: the process of forming a first insulating film and a second insulating film on a semiconductor part, the second insulating film is in contact with the first insulating film and is thicker than the first insulating film; the process of forming a conductive film on the first insulating film and the second insulating film; the process of forming a groove in the conductive film by selectively removing the conductive film, and forming a gate electrode covering the side surface of the second insulating film; the process of forming a through hole in the portion of the second insulating film exposed at the bottom surface of the groove; and the process of forming a first contact connected to the semiconductor part on the outside of the second insulating film, and forming a second contact connected to the semiconductor part via the through hole.

[0009] A method for manufacturing a semiconductor device in another embodiment comprises: a process of forming an insulating component and a second insulating film made of a material different from the insulating component on a semiconductor portion; a process of forming a mask material on the insulating component and the second insulating film to expose an end portion of the second insulating film and cover a portion of the second insulating film other than the end portion; a process of isotropically etching the second insulating film using the mask material as a mask; a process of removing the mask material and the insulating component; a process of forming a first insulating film thinner than the second insulating film on the semiconductor portion; and a process of forming a gate electrode, a portion of which is arranged on the first insulating film and another portion of which is arranged on the second insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0011] Figure 2 Yes means Figure 1 A partially enlarged cross-sectional view of region A.

[0012] Figure 3A to Figure 3D It is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 4A to Figure 4D It is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 5A to Figure 5D It is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Fig. 6A as well as Figure 6B It is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 7A to Figure 7CIt is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modification of the first embodiment.

[0017] Figure 8 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0018] Fig. 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0019] Fig.10 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0020] Fig.11 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0021] Fig.12 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0022] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0023] <First embodiment>

[0024] First, the first embodiment will be described.

[0025] Figure 1 is a cross-sectional view showing the semiconductor device according to the present embodiment.

[0026] Figure 2 Yes means Figure 1 A partially enlarged cross-sectional view of region A.

[0027] like Figure 1 As shown, the semiconductor device 1 of this embodiment includes a semiconductor substrate 10. The semiconductor substrate 10 includes a semiconductor material, for example, silicon (Si), and is composed of, for example, single crystal silicon, and impurities of different types and concentrations are introduced into various parts.

[0028] Next, the internal structure of the semiconductor substrate 10 will be described.

[0029] As will be described later, the semiconductor substrate 10 includes at least a p-type substrate 11, a p － type epitaxial layer 12, p-type well 13, n-type drift layer 14, n + Type source layer 15, p + type contact layer 16 and n + Type drain layer 17.

[0030] The semiconductor substrate 10 includes a p-type substrate 11 having a p-type conductivity. － Type p － Type epitaxial layer 12. In p － On a portion of the epitaxial layer 12, a p-type well 13 having a p-type conductivity and an n-type drift layer 14 having an n-type conductivity are provided separately from each other. － A portion of the epitaxial layer 12 is interposed between the p-type well 13 and the n-type drift layer 14. The p-type well 13 and the n-type drift layer 14 may be alternately arranged along a direction parallel to the upper surface of the p-type substrate 11.

[0031] A portion of the p-type well 13 is provided with a conductive layer of n + Type n + Type source layer 15, and conductivity type p + Type p + Type contact layer 16. + Type source layer 15 and p + The n type contact layers 16 are in contact with each other. + Type source layer 15 and p + Type contact layer 16 from p － The epitaxial layer 12 is separated. + The impurity concentration of the n-type source layer 15 is higher than the impurity concentration of the n-type drift layer 14. + The impurity concentration of the p-type contact layer 16 is higher than that of the p-type well 13. A conductive layer of n is provided on a portion of the n-type drift layer 14. + Type n + Type drain layer 17. + The impurity concentration of the n-type drain layer 17 is higher than the impurity concentration of the n-type drift layer 14. In this specification, "impurity concentration" refers to the concentration of impurities that contribute to the conductivity of the semiconductor material, and in the case of containing both impurities that serve as donors and impurities that serve as acceptors, it refers to the effective concentration excluding the amount that cancels out these impurities.

[0032] Next, the structure on the semiconductor substrate 10 will be described.

[0033] A gate insulating film 21 is provided on the semiconductor substrate 10. The gate insulating film 21 is formed of, for example, silicon oxide. The gate insulating film 21 is disposed in a region directly above the portion of the n-type drift layer 14 on the p-type well 13 side, and in a region directly above the p-type well 13 side. － The region directly above the portion between the n-type drift layer 14 and the p-type well 13 in the epitaxial layer 12, the p-type well 13 in the p-type well 13, － Type epitaxial layer 12 and n + The area directly above the portion between the type source layer 15.

[0034] An insulating film 22 is provided on the semiconductor substrate 10. The insulating film 22 is formed of, for example, silicon oxide. The insulating film 22 is disposed in a region directly above a portion of the n-type drift layer 14 and in contact with the gate insulating film 21. When viewed from above, the gate insulating film 21 is disposed on the n-type drift layer 14. + The insulating film 22 is disposed between the gate insulating film 21 and the n-type source layer 15 and the insulating film 22. + type drain layer 17.

[0035] like Figure 2 As shown, the insulating film 22 is thicker than the gate insulating film 21. The upper surface 22a of the insulating film 22 is located above the upper surface 21a of the gate insulating film 21, and the lower surface 22b of the insulating film 22 is located below the lower surface 21b of the gate insulating film 21. In addition, the thickness t1 of the portion of the insulating film 22 disposed on the semiconductor substrate 10 is thicker than the thickness t2 of the portion of the insulating film 22 disposed in the semiconductor substrate 10. That is, t1>t2. The thickness t2 may be zero or, for example, several nm to several tens of nm.

[0036] n in the insulating film 22 + The side surface 22c on the side opposite to the type drain layer 17 side, that is, the gate insulating film 21 side, includes a lower portion 22d and an upper portion 22e. The lower portion 22d is a vertical surface substantially perpendicular to the upper surface of the semiconductor substrate 10, and the upper portion 22e is closer to the n-type drain layer 17 side as it goes upward. + The upper portion 22e is curved into a concave shape. Therefore, the n-type source layer 15 is inclined. + An angle α formed between the side surface 22 c on the drain layer 17 side and the upper surface 22 a is an obtuse angle.

[0037] On the other hand, the upper surface 22a of the insulating film 22 is substantially horizontal, but there is also a + The end portion of the n-type source layer 15 side, that is, the gate insulating film 21 side, is inclined upward. + The angle β formed between the side surface 22f on the source layer 15 side and the upper surface 22a is a right angle or an acute angle. Therefore, α>β.

[0038] The upper surface 22a and the lower surface 22b of the insulating film 22 are roughly parallel, and the upper surface 22a is shorter than the lower surface 22b in the direction from the gate insulating film 21 toward the insulating film 22. In addition, the side surfaces 22c and 22f are respectively surfaces connecting the upper surface 22a and the lower surface 22b. That is, the side surface 22c is inclined relative to the upper surface 22a. As described above, the side surface 22c has two surfaces, the lower part 22d and the upper part 22e. The lower part 22d is connected to the lower surface 22b, and the upper part 22e is connected to the upper surface 22a. In addition, the side surface 22c can also have more than three surfaces.

[0039] like Figure 1 As shown in FIG. 1 , a gate electrode 23 is provided on the gate insulating film 21 and the insulating film 22. The gate electrode 23 is made of a conductive material, for example, polysilicon containing impurities. + The portion on the side of the type source layer 15 is arranged on the gate insulating film 21. + The portion on the drain layer 17 side is arranged on the insulating film 22 .

[0040] DMOS is formed by various parts of the semiconductor substrate 10, the gate insulating film 21, the insulating film 22, and the gate electrode 23. Hereinafter, the region in which DMOS is formed in the semiconductor device 1 is referred to as "region 91". Elements or circuits other than DMOS may also be formed in the semiconductor device 1. In the present embodiment, for example, it is assumed that a logic circuit is formed. The region other than region 91 in the semiconductor device 1 is referred to as "region 90". In region 90, a logic circuit and STI, etc. are formed. The logic circuit is described by taking an example of a structure other than DMOS in the semiconductor device 1, and it is not necessarily necessary to provide a logic circuit in the semiconductor device 1.

[0041] The semiconductor device 1 is provided with a STI (Shallow Trench Isolation) 24. The STI 24 may be arranged so as to surround the region 91. Alternatively, the STI 24 may be arranged in a region 90 separated from the region 91. In the present embodiment, it is assumed that the STI 24 is arranged in the region 90.

[0042] STI24 is made of silicon oxide, for example, and is thicker than the gate insulating film 21. At least the lower portion of STI24 is arranged in the semiconductor substrate 10. The thickness t3 of the portion of STI24 arranged on the semiconductor substrate 10 is thinner than the thickness t4 of the portion of STI24 arranged in the semiconductor substrate 10. That is, t3<t4. The thickness t3 can be zero or, for example, a few nm to tens of nm. The upper surface 24a of STI24 is located below the upper surface 22a of the insulating film 22, and the lower surface 24b of STI24 is located below the lower surface 22b of the insulating film 22.

[0043] An interlayer insulating film 30 is provided on the semiconductor substrate 10, the gate insulating film 21, the insulating film 22, the gate electrode 23, and the STI 24. A source contact 31, a drain contact 32, and a gate contact (not shown) are provided in the interlayer insulating film 30. The lower end of the source contact 31 is connected to the n-type terminal of the semiconductor substrate 10. + The lower end of the drain contact 32 is connected to the n-type source layer 15 of the semiconductor substrate 10. + The gate contact has a lower end connected to the gate electrode 23.

[0044] Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0045] Figure 3A to Figure 6B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the present embodiment.

[0046] In the following description, a region (region 91) where a DMOS is to be formed and a region (region 90) where a logic circuit is to be formed are described.

[0047] First, if Figure 3A As shown, a p-type substrate 11 (see Figure 1 ) to form a p － Next, a thermal oxidation process is performed on the semiconductor substrate 10 having a p-type epitaxial layer 12. － A silicon oxide layer 51 is formed on the upper surface of the epitaxial layer 12. Next, a silicon nitride film 52 is formed on the silicon oxide layer 51. Next, a silicon oxide film 53 is formed.

[0048] Then, if Figure 3B As shown in FIG. 1 , a resist pattern 54 is formed on the silicon oxide film 53 by photolithography. Openings 54a and 54b are formed in the resist pattern 54. Figure 3C As shown, etching such as RIE (Reactive Ion Etching) is performed using the resist pattern 54 as a mask, thereby removing portions of the silicon oxide film 53, the silicon nitride film 52, and the silicon oxide layer 51 that are located directly below the openings 54a and 54b.

[0049] Then, if Figure 3D As shown in FIG. 1 , a resist pattern 55 is formed by photolithography. In the resist pattern 55 , an opening 55 a is formed in a region 90 .

[0050] Then, if Figure 4A As shown, the resist pattern 55 is used as a mask to perform etching such as RIE. － A recessed portion 56 is formed on the upper surface of the epitaxial layer 12. At this time, the upper layer portion of the silicon oxide film 53 is also removed in the region directly below the opening 55a. Next, the resist pattern 55 is removed.

[0051] Then, if Figure 4B As shown, silicon oxide film 57 is formed by CVD method using TEOS as a raw material. Silicon oxide film 57 is formed so as to cover both region 91 and region 90. The thickness of silicon oxide film 57 is such that recess 56 is completely buried.

[0052] Then, if Figure 4CAs shown, a planarization process such as CMP (Chemical Mechanical Polishing) is performed using the silicon nitride film 52 as a barrier layer, thereby removing a portion of the silicon oxide film 57 and the silicon oxide film 53 to expose the silicon nitride film 52 .

[0053] Then, if Figure 4D As shown in FIG. 1 , a resist pattern 58 is formed in the region 91 by photolithography. In the resist pattern 58, n + An opening 58a is formed in a predetermined region at the end of the drain layer 17. The silicon nitride film 52 and the silicon oxide film 57 are exposed at the bottom of the opening 58a. The resist pattern 58 exposes the end of the silicon oxide film 57 and covers the portion other than the end.

[0054] Then, if Figure 5A As shown in the figure, isotropic etching such as wet etching of silicon oxide is performed using the resist pattern 58 as a mask. As a result, the silicon oxide film 57 is etched starting from the portion exposed in the opening 58a of the resist pattern 58. As a result, a concave curved surface 57a is formed in the silicon oxide film 57. The curved surface 57a is inclined relative to the horizontal plane and the vertical plane. At this time, in the region 90, the upper layer of the silicon oxide film 57 remaining in the concave portion 56 is removed. As a result, in the process described later, the upper surface 24a of the STI 24 becomes lower than the upper surface 22a of the insulating film 22.

[0055] Then, if Figure 5B As shown in FIG. 1 , the resist pattern 58 and the silicon nitride film 52 are removed. As a result, the upper portion of the silicon oxide film 57 is removed from the p － The upper surface of the epitaxial layer 12 protrudes. Thus, the silicon oxide film 57 remaining in the region 91 becomes the insulating film 22, and the curved surface 57a becomes the upper portion 22e of the side surface 22c of the insulating film 22. In addition, in the region 90, the silicon oxide film 57 remaining in the recess 56 becomes the STI 24.

[0056] Then, if Figure 5C As shown, the impurities are directly and via the insulating film 22 to the p － Ions are selectively implanted into the upper layer of the n-type epitaxial layer 12. Thus, an n-type drift layer 14 and a p-type well 13 are formed.

[0057] Then, if Figure 5DAs shown in FIG. 1 , the silicon oxide layer is removed from the surface of the semiconductor substrate 10. Next, a thermal oxidation process is performed to form a gate insulating film 21 on the exposed portion of the semiconductor substrate 10. Next, by depositing polysilicon, a polysilicon film 59 is formed on the gate insulating film 21, the insulating film 22, and the STI 24. Next, a resist pattern 60 is formed on the polysilicon film 59 by photolithography. The resist pattern 60 is arranged in a predetermined region where the gate electrode 23 is to be formed.

[0058] Then, if Fig. 6A As shown, the polysilicon film 59 is patterned by etching such as RIE using the resist pattern 60 as a mask. Thus, the gate electrode 23 is formed. The portion on the source side of the gate electrode 23 is arranged on the gate insulating film 21, and the portion on the drain side is arranged on the insulating film 22. In the conventional structure, since the corners of the insulating film 22 are acute angles, the polysilicon film 59 is likely to remain at the corners of the insulating film 22 when the polysilicon film 59 is processed. The residue of the polysilicon film 59 causes defects such as leakage current. In the present embodiment, the upper portion 22e of the side 22c of the insulating film 22 that is not covered by the resist pattern 60 is inclined relative to the vertical plane, so that the polysilicon film 59 is not likely to remain on the side 22c.

[0059] Then, if Figure 6B As shown in FIG. 1 , an insulating material is deposited on the entire surface and etched back. Thus, a sidewall insulating film 65 is formed on the side surface of the gate electrode 23 on the drain side, a sidewall insulating film 66 is formed on the side surface of the gate electrode 23 on the source side, and a sidewall insulating film 67 is formed on the side surface 22c of the insulating film 22 that is not covered by the gate electrode 23. Next, impurities are selectively ion-implanted to form n + Type source layer 15, n + type drain layer 17 and p + type contact layer 16. In this way, a DMOS is formed.

[0060] Then, if Figure 1 As shown in FIG. 1 , silicon oxide is deposited by CVD method using TEOS as a raw material to form an interlayer insulating film 30 on the entire surface. Next, contact holes are formed in the interlayer insulating film 30 to form a source contact 31 and a drain contact 32. At this time, the source contact 31 reaches the region between the sidewall insulating films 66, and the drain contact 32 reaches the region between the sidewall insulating films 67. In this way, the semiconductor device 1 of this embodiment is manufactured.

[0061] Next, the effects of this embodiment will be described.

[0062] In this embodiment, an insulating film 22 thicker than the gate insulating film 21 is provided on the semiconductor substrate 10, and a portion of the gate electrode 23 on the drain side is arranged on the insulating film 22.+ Type source layer 15 and n + The electric field concentration between the type drain layers 17 is relaxed, and the withstand voltage of the DMOS is improved.

[0063] The insulating film 22 is generally disposed on the semiconductor substrate 10, and a thickness t1 of a portion of the insulating film 22 disposed on the semiconductor substrate 10 is thicker than a thickness t2 of a portion of the insulating film 22 disposed within the semiconductor substrate 10. + The drain layer 17 is n-type + The current flowing through the source layer 15 is rarely intercepted by the insulating film 22, and the on-resistance of the DMOS is low. Furthermore, since the thickness t2 is thin, the electric field is not easily concentrated at the corner of the semiconductor substrate 10 of the insulating film 22. Therefore, HCI (Hot Carrier Injection) is not easily generated, and the reliability of the DMOS is high.

[0064] Furthermore, in this embodiment, Figure 4D In the process shown in FIG. 1 , a resist pattern 58 is formed, and an opening 58a is formed in the resist pattern 58. The opening 58a is located at the n-th layer in the insulating film 22. + A predetermined region at the end of the drain layer 17 side. And, Figure 5A In the process shown in FIG. 1 , wet etching of silicon oxide is performed using the resist pattern 58 as a mask. As a result, a concave curved surface 57a is formed on the silicon oxide film 57. Figure 5B In the step shown, the upper portion 22e of the side surface 22c of the insulating film 22 is formed.

[0065] Therefore, in Fig. 6A In the process shown in FIG. 1 , when the polysilicon film 59 is patterned to form the gate electrode 23, the polysilicon film 59 is unlikely to remain on the side surface 22 c of the insulating film 22. As a result, Figure 1 In the illustrated process, when the drain contact 32 is formed, the position of the drain contact 32 can be controlled with high precision.

[0066] <Modification of the first embodiment>

[0067] Next, a modification of the first embodiment will be described.

[0068] Figure 7A to Figure 7C It is a cross-sectional view showing a method for manufacturing a semiconductor device according to this modification.

[0069] First, implement Figure 3A to Figure 4C The process shown.

[0070] Then, if Fig. 7A As shown in FIG. 1 , a resist pattern 58 b is formed by photolithography. Figure 4D ), the resist pattern 58b is formed in the region 90 in addition to the region 91. For example, the resist pattern 58b is formed on the entire surface of the semiconductor substrate 10. In the resist pattern 58b, similarly to the resist pattern 58, the n + An opening 58 a is formed in a predetermined region of the end portion on the drain layer 17 side.

[0071] Then, if Figure 7B As shown in FIG. 1 , the silicon oxide is wet-etched using the resist pattern 58b as a mask. Thus, a concave curved surface 57a is formed on the silicon oxide film 57. At this time, the silicon oxide film 57 is not etched in the region 90. Figure 5B In the illustrated process, the upper surface 24 a of the STI 24 is substantially at the same height as the upper surface 22 a of the insulating film 22 .

[0072] Then, if Figure 7C As shown, the resist pattern 58b is removed.

[0073] Next, implement Figure 5B to Figure 6B The process shown.

[0074] According to this modification, it is also possible to manufacture a semiconductor device similar to that of the first embodiment. However, this modification is different from the first embodiment in that the upper surface 24 a of the STI 24 is substantially at the same height as the upper surface 22 a of the insulating film 22 .

[0075] The structure, manufacturing method, and effects other than those described above in this modification are the same as those in the first embodiment.

[0076] <Second embodiment>

[0077] Next, a second embodiment will be described.

[0078] Figure 8 is a cross-sectional view showing the semiconductor device according to the present embodiment.

[0079] like Figure 8 As shown, the semiconductor device 2 of this embodiment is different from the semiconductor device 1 of the first embodiment (see Figure 1 as well as Figure 2 ) is different in that: the insulating film 22 is equivalent to n + A through hole 71 is formed in the portion of the region immediately above the type drain layer 17, and the drain contact 32 is connected to the n +The drain contact 32 is provided with a type drain layer 17. That is, the lower portion of the drain contact 32 is arranged in the through hole 71 of the insulating film 22. The gate electrode 23 is arranged on the gate insulating film 21 and on the portion of the insulating film 22 other than the through hole 71. In addition, a sidewall insulating film 65 is provided on the side surface on the drain side of the gate electrode 23, a sidewall insulating film 66 is provided on the side surface on the source side of the gate electrode 23, and a sidewall insulating film 67 is provided on the side surface of the through hole 71, that is, on the inner surface of the insulating film 22. In addition, in the semiconductor device 2, unlike the semiconductor device 1, the relationship between the above-mentioned angles α and β is not particularly limited. That is, the angle formed by the upper surface and the side surface of the insulating film 22 is arbitrary.

[0080] Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0081] Figures 9 to 13 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the present embodiment.

[0082] First, implement Figure 3A to Figure 4C The process shown.

[0083] Then, if Fig. 9 As shown, the silicon nitride film 52 is removed by wet etching. Thus, the insulating film 22 and the STI 24 are formed on the semiconductor substrate 10.

[0084] Then, if Fig.10 As shown, by selectively ion-implanting impurities, a p-type well 13 and an n-type drift layer 14 are formed. Next, by performing a thermal oxidation process, a gate insulating film 21 is formed on the exposed surface of the semiconductor substrate 10. Next, by depositing polysilicon, a conductive polysilicon film 59 is formed on the gate insulating film 21, the insulating film 22, and the STI 24.

[0085] Then, if Fig.11 As shown in FIG. 1 , the polysilicon film 59 is selectively removed by photolithography and RIE to form the gate electrode 23. At this time, when viewed from above, the edge of the gate electrode 23 is arranged outside the insulating film 22. As a result, the side surfaces of the insulating film 22 are all covered by the gate electrode 23. In addition, a groove 72 is formed in the portion of the polysilicon film 59 located on the insulating film 22. The insulating film 22 is exposed at the bottom surface of the groove 72. The groove 72 is, for example, formed along the same direction as the insulating film 22. Fig.11 The paper plane extends in a direction perpendicular to the paper plane. Fig.11 In the region shown, two gate electrodes 23 separated from each other are formed.

[0086] Then, if Fig.12As shown, a through hole 71 is formed in the portion of the insulating film 22 exposed at the bottom surface of the trench 72. The n-type drift layer 14 is exposed at the bottom surface of the through hole 71. When viewed from above, the through hole 71 may be in the shape of a hole such as a circle or a rectangle, or in the shape of a trench extending along the trench 72.

[0087] Then, if Fig.13 As shown in FIG. 1 , a sidewall insulating film 65 is formed on the side surface of the gate electrode 23 on the drain side, a sidewall insulating film 66 is formed on the side surface of the gate electrode 23 on the source side, and a sidewall insulating film 67 is formed on the side surface of the through hole 71. Next, a resist pattern (not shown) is formed, and ion implantation of impurities as donors is performed using the resist pattern, the gate electrode 23, the insulating film 22, and the sidewall insulating film 67 as masks. As a result, an n type drift layer 14 is formed in the upper layer portion and in the region directly below the through hole 71. + In addition, by selectively ion-implanting impurities, an n type drain layer 17 is formed. + Type source layer 15 and p + Type contact layer 16.

[0088] Then, if Figure 8 As shown in FIG. 1 , an interlayer insulating film 30 is formed on the semiconductor substrate 10. Next, a source contact 31, a drain contact 32, and a gate contact are formed. The source contact 31 is connected to the n electrode on the outside of the insulating film 22. + The lower portion of the drain contact 32 is disposed in the through hole 71 of the insulating film 22 and is connected to the n-type source layer 15 via the through hole 71. + The type drain layer 17 is formed. The gate contact is connected to the gate electrode 23. In this way, the semiconductor device 2 of this embodiment is manufactured.

[0089] Next, the effects of this embodiment will be described.

[0090] According to this embodiment, Fig.11 In the process shown in FIG. 1 , when the polysilicon film 59 is patterned to form the gate electrode 23, the side surfaces of the insulating film 22 are all covered by the gate electrode 23. Therefore, the polysilicon film 59 where the gate electrode 23 is not formed does not remain on the side surfaces of the insulating film 22. Fig.12 In the process shown, the through hole 71 is formed in the insulating film 22. Since the through hole 71 is formed after the polysilicon film 59 is patterned, the polysilicon film 59 does not remain on the side surface of the through hole 71.

[0091] Thus, when the sidewall insulating film 67 is formed on the side surface of the through hole 71 of the insulating film 22, the position of the sidewall insulating film 67 is not shifted due to the influence of the polysilicon film 59 remaining on the side surface of the insulating film 22. As a result, the drain contact 32 can be formed with high accuracy.

[0092] The structure, manufacturing method, and effects other than those described above in this embodiment are the same as those in the first embodiment.

[0093] In addition, in each of the above-mentioned embodiments and their variations, an example of forming an n-channel DMOS is shown, but it is not limited to this, and a p-channel DMOS may also be formed. In addition, the transistor formed is not limited to DMOS, and for example, all MOSFETs such as LDMOS (Laterally Diffused MOS) and DEMOS (Drain Extended Metal Oxide Semiconductor) are included. In addition, the material of the gate electrode 23 is not limited to polysilicon, but may also be metal. Furthermore, the first embodiment and its variations may also be implemented in combination with the second embodiment.

[0094] According to the embodiments described above, it is possible to realize a semiconductor device having low on-resistance and high reliability and a method for manufacturing the same.

[0095] Some embodiments of the present invention have been described, and these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: Semiconductor segment; A first insulating film is provided on the semiconductor portion; a second insulating film, provided on the semiconductor portion, in contact with the first insulating film, thicker than the first insulating film, and having a through hole; A first contact, the lower end of which is connected to the semiconductor portion; A second contact, a portion of the lower side of which is disposed in the through hole and a lower end of which is connected to the semiconductor portion; a gate electrode located between the first contact and the second contact, provided on the first insulating film, and provided on a portion of the second insulating film excluding the through hole; and A third insulating film, at least the lower portion of which is disposed within the semiconductor portion, The lower surface of the third insulating film is located below the lower surface of the second insulating film. The angle formed by the upper surface of the second insulating film and the first side surface of the second insulating film on the first insulating film side is a right angle or an acute angle, and the angle formed by the upper surface of the second insulating film and the second side surface of the second insulating film on the opposite side to the first insulating film is an obtuse angle. The second side surface connects the upper surface and the lower surface of the second insulating film. In a direction from the first insulating film toward the second insulating film, an upper surface of the second insulating film is shorter than a lower surface of the second insulating film, The thickness of a portion of the second insulating film disposed on the semiconductor portion is thicker than the thickness of a portion of the second insulating film disposed within the semiconductor portion. The second side has: a first surface connected to the upper surface; and A second surface connected to the lower surface, The semiconductor device further includes a sidewall insulating film provided on the second surface.

2. The semiconductor device according to claim 1, The semiconductor part has: A first semiconductor layer; A second semiconductor layer of the first conductivity type, provided on a portion of the first semiconductor layer; a third semiconductor layer of the second conductivity type, which is disposed on a portion of the second semiconductor layer and is connected to the first contact; and The fourth semiconductor layer of the second conductivity type is provided on another portion of the first semiconductor layer and is connected to the second contact.

3. The semiconductor device according to claim 1, The upper surface of the third insulating film is flush with the upper surface of the second insulating film, or the upper surface of the third insulating film is located below the upper surface of the second insulating film.

4. A semiconductor device comprising: Semiconductor segment; A first insulating film is provided on the semiconductor portion; a second insulating film, provided on the semiconductor portion, in contact with the first insulating film, and thicker than the first insulating film; a gate electrode provided on the first insulating film and a portion of the second insulating film; as well as A third insulating film, at least the lower portion of which is disposed within the semiconductor portion, The second side surface of the second insulating film, which is opposed to the first side surface in contact with the first insulating film and separated from the first insulating film, is inclined relative to the upper surface of the second insulating film. The lower surface of the third insulating film is located below the lower surface of the second insulating film. The angle formed by the upper surface of the second insulating film and the first side surface of the second insulating film on the first insulating film side is a right angle or an acute angle, and the angle formed by the upper surface of the second insulating film and the second side surface is an obtuse angle, The second side surface connects the upper surface and the lower surface of the second insulating film. In a direction from the first insulating film toward the second insulating film, an upper surface of the second insulating film is shorter than a lower surface of the second insulating film, The thickness of a portion of the second insulating film disposed on the semiconductor portion is thicker than the thickness of a portion of the second insulating film disposed within the semiconductor portion. The second side has: a first surface connected to the upper surface; and A second surface connected to the lower surface, The semiconductor device further includes a sidewall insulating film provided on the second surface.

5. The semiconductor device according to claim 4, The second side surface of the second insulating film is inclined in a direction away from the first side surface.

6. The semiconductor device according to claim 4 or 5, Also available: a first contact, the lower end of which is connected to the semiconductor portion; and a second contact, the lower end of which is connected to the semiconductor portion; The gate electrode is located between the first contact and the second contact; The first insulating film is located between the first contact and the second insulating film; The second insulating film is located between the second contact and the first insulating film.

7. The semiconductor device according to claim 6, The semiconductor part has: A first semiconductor layer; A second semiconductor layer of the first conductivity type, provided on a portion of the first semiconductor layer; a third semiconductor layer of the second conductivity type, which is disposed on a portion of the second semiconductor layer and is connected to the first contact; and The fourth semiconductor layer of the second conductivity type is provided on another portion of the first semiconductor layer and is connected to the second contact.

8. The semiconductor device according to claim 4, The upper surface of the third insulating film is flush with the upper surface of the second insulating film, or the upper surface of the third insulating film is located below the upper surface of the second insulating film.

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