Semiconductor element mounting substrate

Abstract

A semiconductor element mounting substrate of the present invention is a semiconductor element mounting substrate provided with a columnar terminal portion composed only of a plating layer on one surface of a metal plate on which a silver plating layer is applied as a topmost layer, and is capable of reducing cost, operation time, improving productivity, while suppressing the thickness of the plating layer as a whole of a terminal or the like including the silver plating layer to be relatively thin and significantly improving adhesion to sealing resin. A semiconductor element mounting substrate (1) is provided with a columnar terminal portion (12-1) composed only of a plating layer on one surface of a metal plate (10), the columnar terminal portion being provided with a roughened silver plating layer (11) having a group of needle-shaped protrusions as a topmost layer plating layer, the roughened silver plating layer having a crystal structure in which the ratio of crystal orientation <101> is the highest among the ratios of crystal orientations <001>, <111>, and <101>.

Description

Technical Field

[0001] The present invention relates to a substrate for mounting semiconductor devices, wherein one side of a metal plate is silver-plated as the outermost layer of plating, and the metal plate is provided as a columnar terminal portion consisting only of plating layer, and the metal plate is removed during the manufacturing of semiconductor packaging. Background Technology

[0002] It is known that a resist mask with a defined pattern is formed on one side of a conductive substrate, and a conductive metal is electrodeposited on the substrate exposed from the resist mask to form an electrode layer for connecting a metal layer for mounting a semiconductor element to an external substrate. The resist mask is then removed to form a substrate for mounting a semiconductor element. A semiconductor element is mounted on the formed substrate and wire bonded, or the semiconductor element is flip-chip mounted and then sealed with resin. The substrate is then removed to obtain a semiconductor package that exposes the other side of the electrodeposited conductive metal.

[0003] Patent Document 1 describes a method for obtaining a semiconductor element mounting substrate by electrodepositing a conductive metal beyond the formed resist mask, thereby obtaining a metal layer for mounting a semiconductor element and an electrode layer for connecting to the outside with protrusions at the upper periphery. When sealed with resin, the protrusions of the metal layer and the electrode layer are embedded in the resin and remain securely on the resin side.

[0004] Patent document 2 describes that when forming a resist mask, scattered ultraviolet light is used to form the resist mask into a trapezoidal shape, thereby forming an inverted trapezoidal shape for the metal layer or electrode layer.

[0005] Patent document 3 describes how a roughened surface is applied to the metal layer to increase the contact area with the sealing resin, thereby improving the sealing force between the metal layer and the resin and ensuring that the protruding part of the metal layer remains firmly on the resin side.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent No. 3626075

[0009] Patent Document 2: Japanese Patent No. 4508064

[0010] Patent Document 3: Japanese Patent No. 5151438 Summary of the Invention

[0011] The problem that the invention aims to solve

[0012] The method described in Patent Document 1, which involves electrodepositing a conductive metal beyond the resist mask to form a coating, suffers from several problems: the excess amount is difficult to control, resulting in coatings that cannot all have the same extension length; and if the protrusion increases, it may connect with adjacent coatings. Furthermore, if the coating becomes thinner, both the width and thickness of the protrusion decrease, leading to reduced adhesion to the resin. Additionally, the upper surface of the excess coating is spherical due to the longitudinal and transverse growth ratios, which also reduces the reliability of the bond.

[0013] Furthermore, in the method of using scattered ultraviolet light to form a trapezoidal cross-sectional shape of the opening of the resist layer as shown in Patent Document 2, when the thickness of the resist layer used is about 50 μm, the ultraviolet light is absorbed by the resist. The closer to the substrate direction, the more difficult it is for the light to attenuate. Therefore, the angle of the trapezoid in the cross-sectional shape of the opening is close to 90 degrees (i.e., a rectangle) and becomes larger, forming a common trapezoidal shape with a short top. The shape of the metal layer or electrode layer is no longer an inverted trapezoid, so the adhesion between the metal layer or electrode layer and the resin is reduced.

[0014] Furthermore, as shown in Patent Document 3, a certain degree of adhesion between the sealing resin and the lead terminal after forming a leadless package is obtained by roughening the surface of the connection terminal surface on the mounting surface of the semiconductor element. However, a noble metal plating layer for connecting the semiconductor element needs to be stacked on the roughened substrate plating layer. There is a concern that the roughened surface of the substrate plating layer may be buried by the noble metal plating layer, resulting in insufficient roughening. As a result, there is a concern that terminal detachment failure may occur.

[0015] Furthermore, as a common issue in Patent Documents 1, 2, and 3, the plating conditions used to roughen the substrate coating are typically low-speed plating, resulting in high costs due to reduced productivity in the semiconductor device mounting substrate manufacturing process – a problem that remains unresolved. In addition, precious metal plating is also a major factor contributing to high costs. On the other hand, further enhancing the adhesion with the sealing resin is also an important issue.

[0016] To further improve the adhesion between the electrode layer and the resin, it is necessary to roughen the outermost surface of the electrode layer. To improve the adhesion with the sealing resin and to further increase the adhesion area compared to the roughened state described in Patent Document 3, increasing the thickness of the electrode layer and further forming an electrode with an inverted trapezoidal cross-sectional shape that is embedded in the resin are effective. However, it is necessary to investigate the deterioration of productivity risks caused by increasing the thickness at low-speed plating and the high cost of precious metal plating. Therefore, a precious metal plating with high adhesion to the sealing resin should be selected.

[0017] However, the inventors in this case conducted repeated experiments and the results showed that, compared with the technologies disclosed in the aforementioned patent documents, there is still room to suppress the overall thickness of the coating to a thinner level and significantly improve the adhesion with the sealing resin.

[0018] The present invention was made in view of such a problem and aims to provide a semiconductor device mounting substrate, which is a semiconductor device mounting substrate having a silver plating layer as the outermost plating layer on one side of a metal plate and having a columnar terminal portion consisting only of the plating layer. This substrate can reduce costs, operating time, and increase productivity, while suppressing the overall thickness of the plating layer including the silver plating layer to a thinner thickness and significantly improving the adhesion with the sealing resin.

[0019] Methods for solving problems

[0020] To address the aforementioned issues, the semiconductor device mounting substrate of the present invention is characterized in that it is a semiconductor device mounting substrate having a columnar terminal portion consisting only of a plating layer on one side of a metal plate. The aforementioned columnar terminal portion has a roughened silver plating layer with needle-like protrusions as its outermost plating layer, and this roughened silver plating layer has properties that are conducive to crystal orientation. <001> , <111> , <101> Crystal orientation in each ratio <101> The crystal structure with the highest ratio.

[0021] Furthermore, in the semiconductor element mounting substrate of the present invention, it is preferable that the average crystal grain size of the aforementioned roughened silver plating layer is less than 0.28 μm.

[0022] Furthermore, in the semiconductor element mounting substrate of the present invention, it is preferable that the plating layer in the aforementioned columnar terminal portion that is in contact with the aforementioned metal plate is a gold plating layer.

[0023] Furthermore, in the semiconductor element mounting substrate of the present invention, the aforementioned columnar terminal portion is preferably formed by a plating layer consisting of metals stacked in any one of the following sequences (1) to (6) starting from the aforementioned metal plate side.

[0024] (1) Gold / Nickel / Silver

[0025] (2) Gold / Palladium / Nickel / Silver

[0026] (3) Gold / Palladium / Nickel / Palladium / Silver

[0027] (4) Gold / Nickel / Palladium / Silver

[0028] (5) Gold / Nickel / Palladium / Gold / Silver

[0029] (6) Gold / Palladium / Nickel / Palladium / Gold / Silver

[0030] The effects of the invention

[0031] According to the present invention, a semiconductor device mounting substrate is obtained, which is a semiconductor device mounting substrate having a silver plating layer as the outermost plating layer on one side of a metal plate and having a columnar terminal portion consisting only of the plating layer. This substrate can reduce costs, operating time, and increase productivity, while suppressing the overall thickness of the plating layer including the silver plating layer to a thinner thickness and significantly improving the adhesion with the sealing resin. Attached Figure Description

[0032] Figure 1 The figures shown are examples of a semiconductor element mounting substrate according to the first embodiment of the present invention. (a) is a top view and (b) is an explanatory diagram schematically showing the AA section of (a).

[0033] Figure 2 This is a plan view of an example of a substrate for mounting semiconductor elements arranged in multiple rows according to the first embodiment of the present invention.

[0034] Figure 3 This is an explanatory diagram showing an example of the manufacturing steps of a semiconductor element mounting substrate according to the first embodiment of the present invention.

[0035] Figure 4 This is an explanatory diagram showing an example of the manufacturing steps of a semiconductor package using a semiconductor element mounting substrate according to the first embodiment of the present invention.

[0036] Figure 5 The figures shown are examples of a semiconductor element mounting substrate according to the second embodiment of the present invention. (a) is a top view and (b) is an explanatory diagram schematically showing the BB cross section of (a).

[0037] Figure 6 This is a plan view of an example of a substrate for mounting semiconductor elements arranged in multiple rows according to the second embodiment of the present invention.

[0038] Figure 7 This is an explanatory diagram showing an example of the manufacturing steps of the semiconductor device mounting substrate according to the second embodiment of the present invention.

[0039] Figure 8 This is an explanatory diagram showing an example of the manufacturing steps of a semiconductor package using a semiconductor element mounting substrate according to the second embodiment of the present invention.

[0040] Symbol Explanation

[0041] 1, 1' - Semiconductor component mounting substrate; 2, 2' - Semiconductor package; 10 - Substrate (metal plate) for semiconductor component mounting substrate; 11 - Roughened silver plating layer; 12-1, 12-2 - Columnar terminal portion; 12a - Internal connection terminal portion; 12b - External connection terminal portion; 12c - Pad portion; 13 - External connection plating layer; 14 - Solder; 15 - Sealing resin; 16 - Die bond; 17 - Bonding wire; 20 - Semiconductor component; 31 - Plating resist mask; R1 - Resist layer. Detailed Implementation

[0042] Before describing the implementation methods, the process of deriving the present invention and the effects of the present invention will be explained.

[0043] As a strategy to improve the adhesion between the columnar terminal portion, which is composed solely of a plating layer and the resin used as a terminal in semiconductor packaging, the inventors of this case have studied the formation of a base plating layer on the upper surface of the columnar terminal portion in a manner that roughens the surface, and then stacking a noble metal plating layer thereon in a manner that follows the shape of the roughened surface. However, in order to form the roughened surface of the base plating layer into a surface with an uneven shape that can improve the adhesion with the resin even when a noble metal plating layer is stacked, it is necessary to form a thicker base plating layer. Moreover, the plating speed for roughening the base plating layer is slow, thus increasing operation time, increasing costs, and decreasing productivity.

[0044] Furthermore, as another strategy to improve adhesion to resin, the inventors investigated roughening the surface of the noble metal plating layer after forming the upper surface of the columnar terminal portion from a smooth noble metal plating layer. However, in order to form a roughened surface with an uneven shape that can improve adhesion to resin, it is necessary to form a thicker smooth noble metal plating layer before forming the roughened surface, which increases the cost of the noble metal plating layer and decreases productivity.

[0045] Next, the inventors of this case considered that in order to reduce the cost and operation time of the roughened surface used to form the surface, improve productivity, improve the adhesion with the sealing resin and reduce the overall thickness of the plating, it is necessary to smoothly stack the base plating on the structure of the columnar terminal portion of the metal plate, and form a surface-roughened silver plating on it in a way that roughens the smooth silver plating surface.

[0046] Furthermore, during repeated experiments, the inventors of this case developed a semiconductor element mounting substrate. As a semiconductor element mounting substrate, it has a columnar terminal portion consisting only of a plating layer. On the upper surface of the base plating layer, a roughened silver plating layer with needle-like protrusions is provided as the outermost plating layer without roughening the smooth silver plating surface.

[0047] It should be noted that, in this application, the needle-like protrusions in the roughened silver plating refer to an aggregate of multiple needle-like protrusions with a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface) of 1.30 to 6.00.

[0048] It has been found that if a roughened silver plating layer is formed in the form of a group of needle-shaped protrusions with such a surface area ratio, the sealing resin can easily flow into the base of each needle-shaped protrusion. When the sealing resin cures, it exerts a physical anchoring effect due to the increased contact area and the uneven shape, thus achieving good adhesion compared to the prior art.

[0049] Furthermore, the inventors of this invention conducted repeated experiments and the results clarified that the roughened silver plating with needle-like protrusions is formed by growing a crystal structure that increases the ratio of a specified crystal orientation. This crystal structure is different from the crystal structure of conventional smooth silver plating and different from the crystal structure of roughened silver plating formed by roughening the surface of smooth silver plating. Moreover, the roughened surface with needle-like protrusions formed by the large-scale growth of this crystal structure has a significantly improved adhesion to the sealing resin compared to the roughened surface formed by conventional technology, thus leading to the present invention.

[0050] The semiconductor device mounting substrate of the present invention is a semiconductor device mounting substrate having a columnar terminal portion consisting only of a plating layer on one side of a metal plate. The columnar terminal portion has a roughened silver plating layer with needle-like protrusions as the outermost plating layer, and the roughened silver plating layer has a crystal orientation. <001> , <111> , <101> Crystal orientation in each ratio <101> The crystal structure with the highest ratio.

[0051] If, as with the semiconductor element mounting substrate of the present invention, the roughened silver plating layer has a group of needle-shaped protrusions with a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating layer to the surface area of ​​the smooth surface) of 1.30 to 6.00 or less, the sealing resin can easily flow into the base of each needle-shaped protrusion. Therefore, during the curing of the sealing resin, the increased contact area and the physical anchoring effect brought about by the uneven shape can be achieved, resulting in good adhesion. It should be noted that the extension direction of each needle-shaped protrusion in the group of needle-shaped protrusions is different, including upward, oblique, and even curved needle shapes. If the needle-shaped protrusions in the group of needle-shaped protrusions extend randomly in a radial pattern, the anchoring effect on the sealing resin can be further improved.

[0052] Furthermore, if it is a semiconductor element mounting substrate like the one of the present invention, the roughened silver plating layer with needle-like protrusions on the upper surface of the base plating layer in the columnar terminal portion, as the outermost plating layer, has a crystal orientation <001> , <111> , <101> Crystal orientation in each ratio <101> The crystal structure with the highest ratio, for example, compared to a silver plating with a roughened surface composed of unevenness and roughness having a surface area ratio (here, the ratio of the surface area of ​​the silver plating to the surface area of ​​the smooth surface) of less than 1.30, and compared to a silver plating with a surface area ratio of less than 1.30 in the crystal orientation... <001> , <111> , <101> Crystal orientation in each ratio <101> The crystal structure with the highest ratio differs from previous crystal structures. Compared to roughened silver plating, which forms a roughened surface by roughening the smooth surface of the silver plating, the sealant can penetrate deeper and the adhesion to the sealant is further improved.

[0053] Furthermore, if it is configured as a semiconductor element mounting substrate like the one of the present invention, the semiconductor element mounting portion on the upper surface side of the columnar terminal portion, and the internal connection terminal portion that is electrically connected to the semiconductor element directly or through a wire, can increase the contact area with the connecting members such as solder and solder paste by utilizing the needle-shaped protrusions of the roughened silver plating layer, thereby preventing moisture intrusion. At the same time, deformation caused by thermal expansion is suppressed, and interlayer peeling between the connecting members and the plating film is suppressed.

[0054] Furthermore, if it is configured as a semiconductor element mounting substrate like the one of the present invention, it is possible to utilize a substrate having crystal orientation... <001> , <111> , <101> Crystal orientation ratio <101> The roughened silver plating with the highest crystal structure and needle-like protrusions significantly improves the adhesion to the sealing resin. As a result, it is sufficient to form a thin and smooth base plating in the columnar terminal portion, without the need to form a surface-roughened base plating.

[0055] Furthermore, it has crystal orientation <001> , <111> , <101> Crystal orientation in each ratio <101> The roughened silver plating with the highest crystal structure and needle-like protrusions can be formed by silver plating under the conditions described later, without roughening the smooth silver plating surface.

[0056] Therefore, if a substrate for mounting semiconductor elements is used as in the present invention, the cost of forming a roughened surface that improves adhesion to the resin can be minimized, and the overall thickness of the plating layer can be minimized.

[0057] Furthermore, in the semiconductor element mounting substrate of the present invention, the average crystal grain size of the roughened silver plating layer is preferably less than 0.28 μm.

[0058] If the average crystal grain size of the roughened silver coating is greater than 0.28 μm, the spacing between the crystals will widen as the silver-plated crystals grow in the height direction, making it impossible to obtain a surface area ratio of 1.30 to 6.00 (here, the ratio of the surface area of ​​the roughened silver coating to the surface area of ​​the smooth surface).

[0059] If the average crystal grain size of the roughened silver coating is less than 0.28 μm, the spacing between the crystals becomes narrower as the silver-plated crystals grow in the height direction, resulting in a surface area ratio of 1.30 to 6.00 (where 1.30 is the ratio of the surface area of ​​the roughened silver coating to the surface area of ​​the smooth surface). It should be noted that, more preferably, the average crystal grain size of the roughened silver coating is 0.15 μm to 0.25 μm.

[0060] Furthermore, in the semiconductor element mounting substrate of the present invention, it is preferable to construct a gold plating layer in which the plating layer in the columnar terminal portion is in contact with the metal plate.

[0061] Furthermore, in the semiconductor element mounting substrate of the present invention, the columnar terminal portion is preferably formed by a plating layer consisting of metals stacked in any one of the following sequences (1) to (6) starting from the metal plate side.

[0062] (1) Gold / Nickel / Silver

[0063] (2) Gold / Palladium / Nickel / Silver

[0064] (3) Gold / Palladium / Nickel / Palladium / Silver

[0065] (4) Gold / Nickel / Palladium / Silver

[0066] (5) Gold / Nickel / Palladium / Gold / Silver

[0067] (6) Gold / Palladium / Nickel / Palladium / Gold / Silver

[0068] For example, when the columnar terminal portion is constructed using a plating layer made of metals stacked in the order of gold / nickel / silver, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed on the surface of the portion corresponding to the columnar terminal portion on one side of the metal plate; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, is formed thereon; and a roughened silver plating layer of 0.2 μm to 3.0 μm, having needle-like protrusions on the surface, preferably 0.5 μm, is formed thereon.

[0069] Furthermore, for example, when the columnar terminal portion is constructed using a plating layer composed of metals stacked in the order of gold / palladium / nickel / silver, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed on the surface of the portion corresponding to the columnar terminal portion on one side of the metal plate; a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed thereon; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, is formed thereon; and a roughened silver plating layer of 0.2 μm to 3.0 μm, having needle-like protrusions on the surface, preferably 0.5 μm, is formed thereon.

[0070] Furthermore, for example, when the columnar terminal portion is constructed using a plating layer made of metals stacked in the order of gold / palladium / nickel / palladium / silver, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed on the surface of the portion corresponding to the columnar terminal portion on one side of the metal plate; a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed thereon; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, is formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, is formed thereon; and a roughened silver plating layer of 0.2 μm to 3.0 μm, preferably 0.5 μm, with needle-like protrusions on the surface, is formed thereon.

[0071] Furthermore, for example, when the columnar terminal portion is constructed using a plating layer composed of metals stacked in the order of gold / nickel / palladium / silver, as an example, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of the portion corresponding to the columnar terminal portion on one side of the metal plate; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, can be formed thereon; and a roughened silver plating layer of 0.2 μm to 3.0 μm, having needle-like protrusions on the surface, preferably 0.5 μm, can be formed thereon.

[0072] Furthermore, for example, when the columnar terminal portion is constructed using a plating layer composed of metals stacked in the order of gold / nickel / palladium / gold / silver, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed on the surface of one side of the metal plate corresponding to the columnar terminal portion; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, is formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, is formed thereon; a gold plating layer of 0.0005 μm to 0.5 μm, preferably 0.005 μm, is formed thereon; and a roughened silver plating layer of 0.2 μm to 3.0 μm, preferably 0.5 μm, with needle-like protrusions on the surface, is formed thereon.

[0073] Furthermore, for example, when the columnar terminal portion is constructed using a plating layer composed of metals stacked in the order of gold / palladium / nickel / palladium / gold / silver, it is possible to: form a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, on the surface of one side of the metal plate corresponding to the columnar terminal portion; form a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, on the surface thereon; and form a 5.0 μm plating layer thereon. A smooth crystalline nickel plating layer of 80.0 μm or less is preferably formed at 30.0 μm; a palladium plating layer of 0.005 μm or more and 1.5 μm or less is formed thereon, preferably at 0.05 μm; a gold plating layer of 0.0005 μm or more and 0.5 μm or less is formed thereon, preferably at 0.005 μm; and a roughened silver plating layer of 0.2 μm or more and 3.0 μm or less with needle-like protrusions on the surface is formed thereon, preferably at 0.5 μm.

[0074] Furthermore, in the semiconductor element mounting substrate of the present invention, the metal plate that serves as the substrate of the semiconductor element mounting substrate can be made of copper-based materials such as copper alloys, or stainless steel alloys.

[0075] In the case where the metal plate serving as the substrate of the semiconductor element mounting substrate of the present invention is made of a stainless steel alloy, the columnar terminal portion is formed by a plating layer composed of metals stacked in the order of gold / nickel / palladium / silver. In this case, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate corresponding to the columnar terminal portion; a smooth crystalline nickel plating layer of 20.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, can be formed thereon; and a roughened silver plating layer of 0.2 μm to 3.0 μm with needle-like protrusions on the surface, preferably 0.5 μm, can be formed thereon.

[0076] Furthermore, in all the examples described above, the columnar terminal portion formed by a plating layer composed of sequentially stacked metals has needle-like protrusions on its surface and exhibits crystal orientation. <001> , <111> , <101> Crystal orientation in each ratio <101> The surface area ratio of the roughened silver plating layer with the highest crystal structure (here, the ratio of the surface area of ​​the roughened silver plating layer to the surface area of ​​the smooth surface) can be 1.30 or more and 6.00 or less, preferably 3.00.

[0077] It should be noted that the semiconductor device mounting substrate of the present invention has a crystal orientation <001> , <111> , <101> Crystal orientation in each ratio <101> The roughened silver plating layer with the highest crystal structure and needle-like protrusions can be achieved using a silver plating bath composed of methanesulfonic acid-based silver plating solution, with a silver concentration of 1.0 g / L to 10 g / L, at a temperature of 55°C to 65°C and a current density of 3 A / dm³. 2 Above 20A / dm 2 The following process involves a 5-60 second plating step to achieve the desired result.

[0078] Therefore, according to the present invention, a semiconductor element mounting substrate can be obtained, which is a semiconductor element mounting substrate having a columnar terminal portion consisting only of a plating layer, wherein one side of a metal plate is silver-plated as the outermost plating layer. This reduces the cost and operation time for forming the roughened surface, improves productivity, and at the same time, suppresses the overall thickness of the plating layer including the silver plating layer to a thinner thickness, thereby significantly improving the adhesion with the sealing resin.

[0079] The following describes a semiconductor element mounting substrate and its manufacturing method using the present invention. It should be noted that, unless otherwise specified, the present invention is not limited to the following detailed description.

[0080] Implementation Method 1

[0081] Figure 1 The figures shown are examples of a semiconductor element mounting substrate according to the first embodiment of the present invention. (a) is a plan view and (b) is an explanatory diagram schematically showing the AA section of (a). Figure 2 This is a plan view showing an example of a semiconductor element mounting substrate arranged in multiple rows according to the first embodiment of the present invention. Figure 3 This is an explanatory diagram showing an example of the manufacturing steps of a semiconductor element mounting substrate according to the first embodiment of the present invention. Figure 4 This is an explanatory diagram showing an example of the manufacturing steps of a semiconductor package using a semiconductor element mounting substrate according to the first embodiment of the present invention.

[0082] like Figure 1 As shown in (a), in the semiconductor element mounting substrate 1 of this embodiment, a plurality of columnar terminal portions 12-1 extending from four directions toward the region mounting the semiconductor element are provided on one surface of a metal plate 10 made of copper-based material.

[0083] The columnar terminal portion 12-1 is composed only of platings of different metals, and as... Figure 1 As shown in (b), a roughened silver plating layer 11 with needle-like protrusions is provided as the outermost plating layer.

[0084] The roughened silver plating 11 has a group of needle-like protrusions with a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface) of 1.30 to 6.00 or less.

[0085] Furthermore, the roughened silver plating 11 has a crystal orientation <001> , <111> , <101> Crystal orientation in each ratio <101> The crystal structure with the highest ratio.

[0086] The roughened silver coating 11 has an average crystal grain size of less than 0.28 μm.

[0087] Moreover, such as Figure 1 As shown in (b), one side of the columnar terminal portion 12-1 constitutes an internal connection terminal portion 12a for connecting to a semiconductor element in a semiconductor package, while the other side constitutes an external connection terminal portion 12b for connecting to an external substrate.

[0088] Furthermore, in the columnar terminal portion 12-1, the plating layer that is in contact with the metal plate 10 is composed of a gold plating layer.

[0089] It should be noted that, regarding the columnar terminal portion 12-1, gold, palladium, nickel, and their alloys can be selected as the base plating material to form the roughened silver plating layer 11 by sequentially stacking them.

[0090] For example, the columnar terminal portion 12-1 can be constructed using a plating layer composed of metals stacked in the order of gold / nickel / silver. In this case, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm with needle-like protrusions on the surface can be formed thereon, preferably 0.5 μm.

[0091] Furthermore, for example, a plating layer composed of metals stacked in the order of gold / palladium / nickel / silver can be used to form the columnar terminal portion 12-1. In this case, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed thereon; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm with needle-like protrusions on the surface, preferably 0.5 μm, can be formed thereon.

[0092] Furthermore, for example, the columnar terminal portion 12-1 can be constructed using a plating layer composed of metals stacked in the order of gold / palladium / nickel / palladium / silver. In this case, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed thereon; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, can be formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm, preferably 0.5 μm, with needle-like protrusions on the surface, can be formed thereon.

[0093] Furthermore, for example, the columnar terminal portion 12-1 can be constructed using a plating layer composed of metals stacked in the order of gold / nickel / palladium / silver. In this case, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, can be formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm with needle-like protrusions on the surface, preferably 0.5 μm, can be formed thereon.

[0094] Furthermore, for example, the columnar terminal portion 12-1 can be constructed using a plating layer composed of metals stacked in the order of gold / nickel / palladium / gold / silver. In this case, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, can be formed thereon; a gold plating layer of 0.0005 μm to 0.5 μm, preferably 0.005 μm, can be formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm, preferably 0.5 μm, with needle-like protrusions on the surface, can be formed thereon.

[0095] Alternatively, for example, the columnar terminal portion 12-1 can be constructed using a plating made of metals stacked in the order of gold / palladium / nickel / palladium / gold / silver. In this case, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate 10 corresponding to the columnar terminal portion 12-1; a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed thereon; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, can be formed thereon; a gold plating layer of 0.0005 μm to 0.5 μm, preferably 0.005 μm, can be formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm with needle-like protrusions on the surface can be formed thereon, preferably 0.5 μm.

[0096] In addition, the metal plate 10 constituting the substrate of the semiconductor element mounting substrate 1 can be made of copper-based materials such as copper alloys or stainless steel alloys.

[0097] When the metal plate 10 is made of a stainless steel alloy, the columnar terminal portion 12-1 is formed by a plating layer composed of metals stacked in the order of gold / nickel / palladium / silver. In this case, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate 10 corresponding to the columnar terminal portion 12-1; a smooth crystalline nickel plating layer of 20.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, can be formed thereon; and a roughened silver plating layer of 0.2 μm to 3.0 μm with needle-like protrusions on the surface, preferably 0.5 μm, can be formed thereon.

[0098] Furthermore, in all the examples described above, the columnar terminal portion 12-1, formed by a plating layer of metal stacked sequentially, has needle-like protrusions on its surface and exhibits crystal orientation. <001> , <111> , <101> Crystal orientation in each ratio <101> The surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating layer 11 to the surface area of ​​the smooth surface) of the crystal structure with the highest ratio is 1.30 or more and 6.00 or less. Preferably, it is 3.00.

[0099] In addition, such as Figure 2 As shown, in the semiconductor element mounting substrate 1 of this embodiment, each semiconductor element mounting substrate 1 is arranged in multiple columns.

[0100] Next, use Figure 3 An example of the manufacturing process of the semiconductor device mounting substrate 1 in this embodiment will be described.

[0101] First, a metal plate 10 made of copper-based material is prepared as the substrate for mounting semiconductor components (see reference). Figure 3 (a)

[0102] Next, a resist layer R1 is formed on both sides of the metal plate 10 (refer to...). Figure 3 (b)

[0103] Next, the resist layer R1 on the upper surface side of the metal plate 10 is exposed and developed using a mask formed in a predetermined shape corresponding to the columnar terminal portion 12-1. Simultaneously, the entire area of ​​the resist layer R1 on the lower surface side of the metal plate 10 is exposed and developed. A plating resist mask 31 (see reference 31) is formed on the upper surface side of the metal plate 10, opening at the portion corresponding to the columnar terminal portion 12-1, and covering the entire area of ​​the lower surface side of the metal plate 10. Figure 3 (c)).

[0104] Next, using a plating resist mask 31, a roughened silver plating layer 11 with needle-like protrusions is formed on the upper surface of the metal plate 10 at the location corresponding to the columnar terminal portion 12-1 as the outermost plating layer (see reference). Figure 3 (d)

[0105] Next, the resist mask 31 for plating is removed (see reference). Figure 3 (e)).

[0106] Thus, the semiconductor element mounting substrate 1 of this embodiment is completed.

[0107] It should be noted that, regarding the formation step of the columnar terminal portion 12-1 with a roughened silver plating layer 11 having needle-like protrusions as the outermost plating layer, for example, when the columnar terminal portion 12-1 is formed by using a plating layer composed of metals stacked in the order of gold / nickel / silver, the following steps can be taken: a gold plating layer of 0.005 μm to 0.5 μm or less, preferably 0.05 μm, is formed on the surface of the metal plate 10, which serves as the substrate for the semiconductor element mounting substrate, corresponding to the portion of the columnar terminal portion 12-1; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm or less, preferably 30.0 μm, is formed thereon; and a roughened silver plating layer 11 having needle-like protrusions on the surface of 0.2 μm to 3.0 μm, preferably 0.5 μm, is formed thereon.

[0108] Furthermore, for example, when the columnar terminal portion 12-1 is constructed using a plating layer composed of metals stacked in the order of gold / palladium / nickel / silver, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed thereon; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, is formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm, having needle-like protrusions on its surface, preferably 0.5 μm, is formed thereon.

[0109] Furthermore, for example, when the columnar terminal portion 12-1 is constructed using a plating layer made of metals stacked in the order of gold / palladium / nickel / palladium / silver, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed thereon; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, is formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, is formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm, having needle-like protrusions on its surface, preferably 0.5 μm, is formed thereon.

[0110] Furthermore, for example, when the columnar terminal portion 12-1 is constructed using a plating layer made of metals stacked in the order of gold / nickel / palladium / silver, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm or less, preferably 0.05 μm, is formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm or less, preferably 30.0 μm, is formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm or less, preferably 0.05 μm, is formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm with needle-like protrusions on the surface, preferably 0.5 μm, is formed thereon.

[0111] Furthermore, for example, when the columnar terminal portion 12-1 is constructed using a plating layer made of metals stacked in the order of gold / nickel / palladium / gold / silver, the following can be achieved: a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, is formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a smooth crystalline nickel plating layer of 5.0 μm to 80.0 μm, preferably 30.0 μm, is formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, is formed thereon; a gold plating layer of 0.0005 μm to 0.5 μm, preferably 0.005 μm, is formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm, preferably 0.5 μm, with needle-like protrusions on the surface, is formed thereon.

[0112] Furthermore, for example, when the columnar terminal portion 12-1 is constructed using a plating layer made of metals stacked in the order of gold / palladium / nickel / palladium / gold / silver, it is possible to: form a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; form a palladium plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, thereon; and form a 5 μm... A smooth crystalline nickel plating layer of 0.0 μm to 80.0 μm, preferably 30.0 μm, is formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, is formed thereon; a gold plating layer of 0.0005 μm to 0.5 μm, preferably 0.005 μm, is formed thereon; and a roughened silver plating layer 11 of 0.2 μm to 3.0 μm, having needle-like protrusions on the surface, is formed thereon, preferably 0.5 μm.

[0113] It should be noted that the metal plate 10 constituting the substrate of the semiconductor element mounting substrate 1 can also be made of a stainless steel alloy. In this case, the columnar terminal portion 12-1 is formed by a plating layer composed of metals stacked in the order of gold / nickel / palladium / silver. In this case, a gold plating layer of 0.005 μm to 0.5 μm, preferably 0.05 μm, can be formed on the surface of one side of the metal plate 10 corresponding to the portion of the columnar terminal portion 12-1; a smooth crystalline nickel plating layer of 20.0 μm to 80.0 μm, preferably 30.0 μm, can be formed thereon; a palladium plating layer of 0.005 μm to 1.5 μm, preferably 0.05 μm, can be formed thereon; and a roughened silver plating layer of 0.2 μm to 3.0 μm with needle-like protrusions on the surface, preferably 0.5 μm, can be formed thereon.

[0114] At this point, in order to form a crystal orientation <001> , <111> , <101> Crystal orientation in each ratio <101> The roughened silver plating layer 11, which has the highest ratio of crystal structure and a group of needle-like protrusions with a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating layer to the surface area of ​​the smooth surface) of 1.30 to 6.00, has a silver concentration in a silver plating bath composed of a methanesulfonic acid-based silver plating solution set to a range of 1.0 g / L to 10 g / L. In particular, it is more preferable to set the silver concentration to a range of 1.5 g / L to 5.0 g / L.

[0115] If the silver concentration is less than 1.0 g / L, a sufficiently roughened silver plating film cannot be formed, and therefore this is not preferred. If the silver concentration is higher than 10 g / L, the formed roughened silver plating film will be a smooth surface, and it will be impossible to obtain needle-like silver crystals, which is also not preferred.

[0116] Next, use Figure 4 An example of the manufacturing process of a semiconductor package using the semiconductor element mounting substrate 1 of this embodiment will be described.

[0117] First, prepare to pass Figure 3 The semiconductor device mounting substrate 1 of this embodiment, manufactured according to the manufacturing steps shown (see reference), Figure 4 (a)

[0118] Next, solder 14 is printed on the semiconductor element mounting area in the internal connection terminal portion 12a on the upper surface of the columnar terminal portion 12-1 of the semiconductor element mounting substrate 1, and the semiconductor element 20 is mounted and fixed thereon, thereby electrically connecting the electrodes of the semiconductor element 20 to the internal connection terminal portion 12a of the semiconductor element mounting substrate 1 (see reference). Figure 4 (b)

[0119] Next, using a molding die, the space on the upper surface of the semiconductor component mounting substrate 1 is sealed with sealing resin 15 (see reference). Figure 4 (c)).

[0120] Next, for the metal plate 10 that serves as the substrate for the semiconductor device mounting substrate 1, if the metal plate 10 is made of a copper-based material, the metal plate 10 is removed by etching; if the metal plate 10 is made of a stainless steel-based material, the metal plate 10 is removed by tearing (see reference). Figure 4 (d)

[0121] Finally, the semiconductor packages arranged in multiple rows are monolithically assembled through processes such as cutting and stamping (see reference). Figure 4 (e)).

[0122] Thus, a semiconductor package 2 using the semiconductor element mounting substrate 1 of this embodiment is obtained (see reference). Figure 4 (f)

[0123] Implementation Method 2

[0124] Figure 5 The figures shown are examples of a semiconductor element mounting substrate according to the second embodiment of the present invention. (a) is a top view and (b) is an explanatory diagram schematically showing the BB cross section of (a). Figure 6 This is a plan view of an example of a substrate for mounting semiconductor elements arranged in multiple rows according to the second embodiment of the present invention. Figure 7 This is an explanatory diagram showing an example of the manufacturing steps of the semiconductor device mounting substrate according to the second embodiment of the present invention. Figure 8 This is an explanatory diagram showing an example of the manufacturing steps of a semiconductor package using a semiconductor element mounting substrate according to the second embodiment of the present invention.

[0125] like Figure 5 As shown in (a), the semiconductor element mounting substrate 1' of this embodiment includes a large-area columnar terminal portion 12-2 disposed at the central position, and a plurality of small-area columnar terminal portions 12-1 arranged around the four directions of the columnar terminal portion 12-2. The columnar terminal portion 12-2 forms a pad portion 12c on the upper surface on which the semiconductor element is mounted, and the columnar terminal portion 12-1 forms an internal connection terminal portion 12a on the upper surface that is electrically connected to the semiconductor element via a bonding wire.

[0126] The columnar terminal portions 12-1 and 12-2 are composed only of platings of different metals, and as... Figure 5 As shown in (b), a roughened silver plating layer 11 with needle-like protrusions is provided as the outermost plating layer.

[0127] The other components are substantially the same as those of the semiconductor element mounting substrate 1 in the first embodiment.

[0128] In addition, such as Figure 6 As shown, in the semiconductor element mounting substrate 1' of this embodiment, each semiconductor element mounting substrate 1' is arranged in multiple columns.

[0129] Next, use Figure 7 An example of the manufacturing process of the semiconductor device mounting substrate 1' of this embodiment will be described.

[0130] The manufacturing process of the semiconductor device mounting substrate 1' in this embodiment is the same as that of the semiconductor device mounting substrate 1'. Figure 3 The manufacturing process of the semiconductor device mounting substrate 1 in the first embodiment shown is largely the same, and the formation step of the roughened silver plating layer 11 with needle-like protrusions as the outermost plating layer is also largely the same as that in the semiconductor device mounting substrate 1 of the first embodiment (see reference). Figure 7 (a)~ Figure 7 (e)).

[0131] Next, use Figure 8 An example of the manufacturing process of a semiconductor package using the semiconductor element mounting substrate 1' of this embodiment will be described.

[0132] First, prepare to pass Figure 7 The semiconductor device mounting substrate 1' of this embodiment, manufactured according to the manufacturing steps shown (see reference 1), is a semiconductor device mounting substrate manufactured according to the manufacturing steps shown. Figure 8 (a)

[0133] Next, on the upper surface of the semiconductor element mounting substrate 1', the semiconductor element 20 is mounted and fixed on the pad portion 12c in the columnar terminal portion 12-2 using die bond 16. Simultaneously, the electrodes of the semiconductor element 20 are electrically connected to the internal connection terminal portion 12a of the columnar terminal portion 12-1 via bonding wire 17 (see reference). Figure 8 (b)

[0134] Next, using a molding die, the space on the upper surface of the semiconductor component mounting substrate 1' is sealed with sealing resin 15 (see reference). Figure 8 (c)).

[0135] Next, for the metal plate 10 that serves as the substrate for mounting semiconductor components, if the metal plate 10 is made of a copper-based material, it is removed by etching; if the metal plate 10 is made of a stainless steel-based material, it is removed by tearing (see reference). Figure 8 (d)

[0136] Finally, the semiconductor packages arranged in multiple rows are monolithized through cutting, stamping, and other processes (see reference). Figure 8 (e)).

[0137] Thus, a semiconductor package 2' using the semiconductor element mounting substrate 1' of this embodiment is obtained (see reference). Figure 8 (f)

[0138] Example

[0139] (Example 1)

[0140] Prepare a strip of copper material (C194 copper alloy) with a thickness of 0.15 mm and a width of 180 mm as the substrate 10 for the semiconductor device mounting substrate (refer to...). Figure 3 (a) A 50 μm thick thin film of resist is laminated on both sides of the copper material to form resist layer R1 (refer to...). Figure 3 (b)

[0141] The lamination was carried out under the following conditions: roller temperature 105℃, roller pressure 0.5MPa, and feed speed 2.5m / min. It should be noted that the photoresist used in the lamination was a negative photoresist that could be exposed to ultraviolet light.

[0142] Next, on the resist layer R1 on the upper surface side, a mask with a predetermined pattern corresponding to the columnar terminal portion 12-1 is used for exposure and development, and an ultraviolet mercury lamp is used as the light source. At the same time, the entire area of ​​the resist layer R1 on the lower surface side of the metal plate 10 is exposed and developed. A plating resist mask 31 is formed on the upper surface side of the metal plate 10, with an opening corresponding to the columnar terminal portion 12-1, and covering the entire area of ​​the lower surface side of the metal plate 10 (see reference). Figure 3 (c)).

[0143] Next, using a plating resist mask 31, the upper surface of the metal plate 10 corresponding to the internal connection terminal portion 12a is pretreated with alkali and acid (removal of surface oxide film and surface activation treatment), and then electroplating is performed as follows.

[0144] In detail, a 0.05 μm gold plating layer is first formed, and then a nickel plating bath consisting of nickel sulfamate, nickel chloride, and boric acid is applied at a current density of 2 A / dm³. 2 A 90-minute plating process was performed to form a smooth crystalline nickel plating layer of 31.0 μm.

[0145] Next, a silver plating bath with a silver concentration of 3.5 g / L, composed of a methanesulfonic acid-based silver plating solution, was used at a temperature of 60°C and a current density of 5 A / dm³. 2 A 15-second plating process is performed to form a structure with needle-like protrusions, a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface), and crystal orientation. <001> , <111> , <101> A roughened silver plating layer 11 with a thickness of 0.5 μm and a ratio and crystal grain size (average value) as shown in Table 1 is used to complete the columnar terminal portion 12-1 (refer to Table 1). Figure 3 (d)

[0146] Next, the plating resist mask 31 is removed using an alkaline solution (see reference). Figure 3 (e)) thereby obtaining the semiconductor element mounting substrate 1 of Example 1.

[0147] (Example 2)

[0148] Prepare a strip of stainless steel (SUS430) with a thickness of 0.15 mm and a width of 180 mm as substrate 10 for mounting semiconductor components (refer to...). Figure 3 In (a)), two 38 μm thick thin film resists are laminated on the upper surface of the stainless steel material, and one identical thin film resist is laminated on the lower surface, thereby forming a resist layer R1 (refer to...). Figure 3 (b)

[0149] The lamination conditions are as follows: roller temperature 105℃, roller pressure 0.5MPa, and feeding speed 2.5m / min.

[0150] Next, similarly to Example 1, on the resist layer R1 on the upper surface side, a mask with a predetermined pattern corresponding to the columnar terminal portion 12-1 is used for exposure and development using an ultraviolet mercury lamp as the light source. Simultaneously, the entire area of ​​the resist layer R1 on the lower surface side of the metal plate 10 is exposed and developed. A plating resist mask 31 (see reference 31) is formed on the upper surface side of the metal plate 10, opening at the portion corresponding to the columnar terminal portion 12-1, and covering the entire area of ​​the lower surface side of the metal plate 10. Figure 3 (c)).

[0151] Next, using a plating resist mask 31, the upper surface of the metal plate 10 corresponding to the internal connection terminal portion 12a is pretreated with alkali and acid (removal of surface oxide film and surface activation treatment), and then electroplating is performed as follows.

[0152] In detail, a 0.05 μm gold plating layer is first formed, and then a nickel plating bath consisting of nickel sulfamate, nickel chloride, and boric acid is applied at a current density of 2 A / dm³. 2 A 90-minute plating process was performed to form a smooth crystalline nickel plating layer of 31.0 μm, on which a 0.06 μm palladium plating layer was formed.

[0153] Next, a silver plating bath with a silver concentration of 3.5 g / L, composed of a methanesulfonic acid-based silver plating solution, was used at a temperature of 60°C and a current density of 5 A / dm³. 2 A 15-second plating process is performed to form a structure with needle-like protrusions, a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface), and crystal orientation. <001> , <111> , <101> A roughened silver plating layer 11 with a thickness of 0.5 μm and a ratio and crystal grain size (average value) as shown in Table 1 is used to complete the columnar terminal portion 12-1 (refer to Table 1). Figure 3 (d)

[0154] Next, the plating resist mask 31 is removed using an alkaline solution (see reference). Figure 3 (e)) thereby obtaining the semiconductor element mounting substrate 1 of Example 2.

[0155] (Example 3)

[0156] In Example 3, until the formation of the resist mask 31 for plating (refer to...) Figure 3(c) The electroplating pretreatment was carried out in largely the same manner as in Example 1. During the subsequent electroplating process, a 0.05 μm gold plating layer was formed, followed by a 0.05 μm palladium plating layer. Then, a nickel plating bath consisting of nickel sulfamate, nickel chloride, and boric acid was used at a current density of 2 A / dm³. 2 A 90-minute plating process was performed to form a smooth 30.0 μm crystalline nickel plating layer.

[0157] Next, a silver plating bath with a silver concentration of 3.5 g / L, composed of a methanesulfonic acid-based silver plating solution, was used at a temperature of 60°C and a current density of 5 A / dm³. 2 A 15-second plating process is performed to form a structure with needle-like protrusions, a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface), and crystal orientation. <001> , <111> , <101> A roughened silver plating layer 11 with a thickness of 0.5 μm and a ratio and crystal grain size (average value) as shown in Table 1 is used to complete the columnar terminal portion 12-1 (refer to Table 1). Figure 3 (d)

[0158] Next, the plating resist mask 31 is removed using an alkaline solution (see reference). Figure 3 (e)) thereby obtaining the semiconductor element mounting substrate 1 of Example 3.

[0159] (Example 4)

[0160] In Example 4, until the formation of the resist mask 31 for plating (refer to...) Figure 3 (c) The electroplating pretreatment was carried out in largely the same manner as in Example 1. During the subsequent electroplating process, a 0.06 μm gold plating layer was formed, followed by a 0.04 μm palladium plating layer. A nickel plating bath consisting of nickel sulfamate, nickel chloride, and boric acid was then applied at a current density of 2 A / dm³. 2 A 90-minute plating process was performed to form a smooth crystalline nickel plating layer of 32.0 μm, on which a 0.05 μm palladium plating layer was formed.

[0161] Next, a silver plating bath with a silver concentration of 3.5 g / L, composed of a methanesulfonic acid-based silver plating solution, was used at a temperature of 60°C and a current density of 5 A / dm³. 2 A 15-second plating process is performed to form a structure with needle-like protrusions, a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface), and crystal orientation. <001> , <111> , <101> A roughened silver plating layer 11 with a thickness of 0.5 μm and a ratio and crystal grain size (average value) as shown in Table 1 is used to complete the columnar terminal portion 12-1 (refer to Table 1). Figure 3 (d)

[0162] Next, the plating resist mask 31 is removed using an alkaline solution (see reference). Figure 3 (e)) thereby obtaining the semiconductor element mounting substrate 1 of Example 4.

[0163] (Example 5)

[0164] In Example 5, until the formation of the resist mask 31 for plating (see...) Figure 3 (c) The electroplating pretreatment was carried out in largely the same manner as in Example 1. During the subsequent electroplating process, a 0.05 μm gold plating layer was formed, on which a nickel plating bath composed of nickel sulfamate, nickel chloride, and boric acid was applied at a current density of 2 A / dm³. 2 A 90-minute plating process was performed to form a smooth crystalline nickel plating layer of 30.0 μm, on which a 0.05 μm palladium plating layer was formed.

[0165] Next, a silver plating bath with a silver concentration of 3.5 g / L, composed of a methanesulfonic acid-based silver plating solution, was used at a temperature of 60°C and a current density of 5 A / dm³. 2 A 15-second plating process is performed to form a structure with needle-like protrusions, a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface), and crystal orientation. <001> , <111> , <101> A roughened silver plating layer 11 with a thickness of 0.5 μm and a ratio and crystal grain size (average value) as shown in Table 1 is used to complete the columnar terminal portion 12-1 (refer to Table 1). Figure 3 (d)

[0166] Next, the plating resist mask 31 is removed using an alkaline solution (see reference). Figure 3 (e)) thereby obtaining the semiconductor element mounting substrate 1 of Example 5.

[0167] (Example 6)

[0168] In Example 6, until the formation of the resist mask 31 for plating (see...) Figure 3 (c) The electroplating pretreatment was carried out in largely the same manner as in Example 1. During the subsequent electroplating process, a 0.06 μm gold plating layer was formed, on which a nickel plating bath composed of nickel sulfamate, nickel chloride, and boric acid was applied at a current density of 2 A / dm³. 2 A 90-minute plating process was performed to form a smooth crystalline nickel plating layer of 32.0 μm, on which a palladium plating layer of 0.04 μm was formed, and on which a gold plating layer of 0.006 μm was formed.

[0169] Next, a silver plating bath with a silver concentration of 3.5 g / L, composed of a methanesulfonic acid-based silver plating solution, was used at a temperature of 60°C and a current density of 5 A / dm³. 2A 15-second plating process is performed to form a structure with needle-like protrusions, a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface), and crystal orientation. <001> , <111> , <101> A roughened silver plating layer 11 with a thickness of 0.5 μm and a ratio and crystal grain size (average value) as shown in Table 1 is used to complete the columnar terminal portion 12-1 (refer to Table 1). Figure 3 (d)

[0170] Next, the plating resist mask 31 is removed using an alkaline solution (see reference). Figure 3 (e)) thereby obtaining the semiconductor element mounting substrate 1 of Example 6.

[0171] (Example 7)

[0172] In Example 7, until the formation of the resist mask 31 for plating (see...) Figure 3 (c) The electroplating pretreatment was carried out in largely the same manner as in Example 1. During the subsequent electroplating process, a 0.06 μm gold plating layer was formed, followed by a 0.05 μm palladium plating layer. Then, a nickel plating bath consisting of nickel sulfamate, nickel chloride, and boric acid was used at a current density of 2 A / dm³. 2 A 90-minute plating process was performed to form a smooth crystalline nickel plating layer of 31.0 μm, on which a 0.04 μm palladium plating layer was formed, and on which a 0.006 μm gold plating layer was formed.

[0173] Next, a silver plating bath with a silver concentration of 3.5 g / L, composed of a methanesulfonic acid-based silver plating solution, was used at a temperature of 60°C and a current density of 5 A / dm³. 2 A 15-second plating process is performed to form a structure with needle-like protrusions, a surface area ratio (here, the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface), and crystal orientation. <001> , <111> , <101> A roughened silver plating layer 11 with a thickness of 0.5 μm and a ratio and crystal grain size (average value) as shown in Table 1 is used to complete the columnar terminal portion 12-1 (refer to Table 1). Figure 3 (d)

[0174] Next, the plating resist mask 31 is removed using an alkaline solution (see reference). Figure 3 (e)) thereby obtaining the semiconductor element mounting substrate 1 of Example 7.

[0175] (Comparative Example 1)

[0176] In Comparative Example 1, the process was carried out in largely the same manner as in Example 1 until the formation of the gold plating layer during the electroplating process. Next, a nickel plating bath consisting of nickel sulfamate, nickel chloride, and boric acid was used on the gold plating layer at a current density of 2 A / dm³. 2A 90-minute plating process was performed to form a 30.0 μm nickel plating layer. Next, a silver plating bath with a silver concentration of 65 g / L, composed of a cyanide-based silver plating solution, was used at a current density of 3 A / dm². 2 A silver plating layer with a smooth surface and a thickness of approximately 1.5 μm was formed by plating for 1 minute and 30 seconds, completing the columnar terminal portion. Next, the plating resist mask was removed using an alkaline solution, thereby obtaining the semiconductor device mounting substrate of Comparative Example 1.

[0177] (Comparative Example 2)

[0178] Comparative Example 2 is an example of a semiconductor device mounting substrate in which a silver plating layer with a roughened surface consisting of uneven surfaces having a surface area ratio (here, the ratio of the surface area of ​​the silver plating layer to the surface area of ​​the smooth surface) of less than 1.30 is used as the outermost plating layer to form the columnar terminal portion of the semiconductor device mounting substrate.

[0179] In Comparative Example 2, the process was carried out in largely the same manner as in Example 1 until the formation of the nickel plating layer during the electroplating process. Next, a silver plating bath with a silver concentration of 65 g / L, composed of a cyanide-based silver plating solution, was used at a current density of 3 A / dm³. 2 A 5-minute plating process was performed to form a smooth silver plating layer with a thickness of approximately 4.0 μm. Next, a 2-minute micro-etching process was carried out on the surface of the silver plating layer using a silver plating stripping solution to create a roughened surface with unevenness, thus completing the columnar terminal portion. At this point, the thickness of the silver plating layer with the roughened surface was 1.7 μm. Next, the plating resist mask was removed using an alkaline solution to obtain the semiconductor device mounting substrate of Comparative Example 2.

[0180] (Comparative Example 3)

[0181] Comparative Example 3 is an example of a semiconductor device mounting substrate in which a columnar terminal portion is formed by forming a base plating layer with a roughened surface and a silver plating layer thereon.

[0182] In Comparative Example 3, the process was largely the same as in Example 1 until the formation of the gold plating layer during the electroplating process. For the subsequent electroplating process, a nickel plating bath consisting of nickel sulfamate, nickel chloride, and boric acid was first used at a current density of 2 A / dm³. 2 A nickel plating process was performed for 97 minutes and 30 seconds to form a smooth nickel plating layer with a thickness of approximately 34.5 μm. Next, a 2-minute micro-etching process was carried out on the surface of the nickel plating layer using a nickel plating stripping solution, resulting in a roughened surface with unevenness. At this point, the thickness of the nickel plating layer with the roughened surface was 32.0 μm. Next, a silver plating bath composed of a cyanide-based silver plating solution with a silver concentration of 65 g / L was used at a current density of 3 A / dm³. 2The plating process lasts 1 minute and 30 seconds, forming a roughened surface that follows the shape of the nickel plating layer, with a surface area ratio (here, the ratio of the surface area of ​​the silver plating layer to the surface area of ​​the smooth surface), and crystal orientation. <001> , <111> , <101> A silver plating layer with a roughened surface and an uneven surface, having a thickness of approximately 1.6 μm and the ratio and average crystal size shown in Table 1, was used to complete the columnar terminal portion. Next, the plating resist mask was removed using an alkaline solution to obtain the semiconductor device mounting substrate of Comparative Example 3.

[0183] Table 1 shows the plating composition elements (material of the substrate of the semiconductor device mounting substrate, type and thickness of the plating, surface area ratio (here, the ratio of the surface area of ​​the (roughened or smoothed) silver plating to the surface area of ​​the smooth surface), crystal orientation ratio of the roughened silver plating, and crystal grain size (average value)) in each semiconductor device mounting substrate of Examples 1 to 7 and Comparative Examples 1 to 3.

[0184] It should be noted that the crystal orientation ratio is determined by analyzing the field of view observed at 10,000x magnification using a scanning electron microscope (SEM) and then by electron backscatter diffraction (ESBD). <001> , <111> , <101> The allowable angles in each direction are calculated with 15° as the tolerance. In addition, the crystal grain size is set as the area circle equivalent diameter of the grain, which is determined with an azimuth difference of 15° or more as the grain boundary.

[0185] In addition, the plating thickness of the silver plating was measured using a fluorescence X-ray analysis device (SII SFT3300), and the plating thickness of the nickel, palladium, and gold plating was measured using a fluorescence X-ray analysis device (SII SFT3300).

[0186] In addition, the surface area ratio was measured using a 3D laser microscope (OLYMPUS OLS4100).

[0187] [Table 1]

[0188]

[0189] Evaluation of resin adhesion

[0190] On the roughened silver plating layer (a smooth silver plating layer in Comparative Example 1) of each semiconductor element mounting substrate of Examples 1-7 and Comparative Examples 1-3, a cylindrical resin mold with a diameter of 2 mm was formed for evaluation. The shear strength of the resin was measured using a Dage series 4000 (manufactured by Dage Corporation) as a bonding tester to evaluate the resin adhesion.

[0191] The evaluation results of the resin adhesion of Examples 1-7 and Comparative Examples 1-3 are shown in Table 2.

[0192] [Table 2]

[0193]

[0194] It was confirmed that the shear strength of the semiconductor device mounting substrate of Comparative Example 1 was 10 MPa, which cannot be said to have sufficient resin adhesion for actual use.

[0195] As shown in Table 2, the semiconductor device mounting substrates of Examples 1 to 7 all have a shear strength 1.5 times that of the semiconductor device mounting substrate of Comparative Example 1, confirming a significant improvement in resin adhesion.

[0196] On the other hand, it was confirmed that although the shear strength of the semiconductor device mounting substrates of Comparative Examples 2 and 3 was higher and the resin adhesion was improved compared with that of the semiconductor device mounting substrate of Comparative Example 1, the shear strength was only 1.2 times that of the semiconductor device mounting substrate of Comparative Example 1, and the significant improvement in resin adhesion as in the semiconductor device mounting substrates of Examples 1 to 7 could not be obtained.

[0197] Productivity evaluation

[0198] The processing time and silver plating amount required to form the surface morphology of the outermost plating layer to a roughened surface in each of the semiconductor device mounting substrates of Examples 1-7 and Comparative Examples 2 and 3 were compared to evaluate productivity. In the productivity evaluation, the relative values ​​of the processing time and silver plating amount used in the semiconductor device mounting substrate of Comparative Example 1, where a smooth silver plating layer was formed as the outermost plating layer, were both set to 100. It should be noted that the lead frame plating process was performed while the lead frame was being transported on a production line; therefore, the evaluation value of the processing time was calculated based on the time required to form the metal plating layer requiring the longest plating time in the lead frame plating process of each example and comparative example (Examples 1-7, Comparative Examples 2 and 3: smooth nickel plating).

[0199] Table 2 shows the evaluation results of the productivity (processing time and silver plating amount required to form the surface morphology of the outermost coating layer into a roughened surface) of Examples 1-7 and Comparative Examples 2 and 3.

[0200] Comparative Example 2 is an example of a semiconductor device mounting substrate formed by micro-etching with a silver plating layer having a smooth surface and a thickness of about 4.0 μm after forming a silver plating layer with an uneven surface. The thickness of the silver plating layer with an uneven surface is 1.5 μm, which is about half the thickness of the silver plating layer with a smooth surface. As shown in Table 2, the processing time is 100 and the amount of silver used is 270. It is confirmed that the cost of the originally expensive silver has increased significantly and the productivity has deteriorated.

[0201] Comparative Example 3, the semiconductor device mounting substrate, was formed by micro-etching with a nickel plating layer of approximately 34.5 μm thickness and a smooth surface, and then a nickel plating stripping solution was used to form a roughened surface with unevenness on the silver plating layer. The thickness of the nickel plating layer with the roughened surface was 32.0 μm, as shown in Table 2. The processing time was 108 and the silver usage was 100. It was confirmed that as the processing time increased, the productivity deteriorated.

[0202] As shown in Table 2, the semiconductor device mounting substrates of Examples 1-7 all had a processing time of 100 seconds and a silver usage of 30%. Compared with the semiconductor device mounting substrate of Comparative Example 2, although the processing time was the same, the silver usage was reduced by 89%, resulting in a significant reduction in production costs. Furthermore, compared with the semiconductor device mounting substrate of Comparative Example 3, the processing time was reduced by 8% and the silver usage was reduced by 70%, resulting in a significant increase in productivity.

[0203] The preferred embodiments and examples of the present invention have been described in detail above. However, the present invention is not limited to the above embodiments and examples, and various modifications and substitutions can be made to the above embodiments and examples without departing from the scope of the present invention.

[0204] Furthermore, although the substrate material of the semiconductor device mounting substrate of the present invention is set to a copper-based material such as a copper alloy or a stainless steel alloy, it is also applicable to set the substrate material of the semiconductor device mounting substrate to a nickel alloy.

[0205] Furthermore, as long as the specified thickness does not damage the surface area ratio and crystal structure of the roughened surface with needle-like protrusions, the semiconductor device mounting substrate of the present invention may further be stacked, for example, a silver plating layer or a plating layer combining nickel, palladium and gold as a covering plating layer on the roughened silver plating layer with needle-like protrusions that is provided as the outermost plating layer.

[0206] Industry availability

[0207] The semiconductor element mounting substrate of the present invention is useful in the field of manufacturing semiconductor packages where terminals and the like are required to be formed only by plating.

Claims

1. A substrate for mounting semiconductor devices, characterized in that, A substrate for mounting semiconductor devices having columnar terminal portions consisting only of plating on one side of a metal plate. The columnar terminal portion has a roughened silver plating layer with needle-like protrusions as the outermost plating layer, and this roughened silver plating layer has a crystal orientation <001> , <111> , <101> Crystal orientation in each ratio <101> The crystal structure with the highest ratio; The metal plate has a columnar terminal portion, which requires a smooth stacking of the base plating layer, and does not form a surface-roughened silver plating layer on it in a way that roughens the smooth silver plating surface. Silver plating without roughening the surface of a smooth silver plating layer is achieved by the following conditions: using a silver plating bath composed of a methanesulfonic acid-based silver plating solution with a silver concentration of 1.0 g / L to 10 g / L, and electroplating for 5 to 60 seconds at a temperature of 55°C to 65°C and a current density of 3 A / dm² to 20 A / dm². The needle-like protrusions in the roughened silver plating refer to an aggregate of multiple needle-like protrusions with a surface area ratio of 1.30 to 6.

00. Here, the surface area ratio refers to the ratio of the surface area of ​​the roughened silver plating to the surface area of ​​the smooth surface.

2. The semiconductor element mounting substrate according to claim 1, characterized by The average crystal grain size of the roughened silver coating is less than 0.28 μm.

3. The semiconductor element mounting substrate according to claim 1 or 2, characterized by The plating layer in the columnar terminal portion that is in contact with the metal plate is a gold plating layer.

4. The semiconductor element mounting substrate according to claim 1 or 2, characterized by The columnar terminal portion is formed by a plating layer consisting of metals stacked in any of the following sequences (1) to (6) starting from the side of the metal plate. (1) Gold / Nickel / Silver (2) Gold / Palladium / Nickel / Silver (3) Gold / Palladium / Nickel / Palladium / Silver (4) Gold / Nickel / Palladium / Silver (5) Gold / Nickel / Palladium / Gold / Silver (6) Gold / Palladium / Nickel / Palladium / Gold / Silver.

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